Attachment 124145 Details for Bug 96258 – compute shader dump

compute shader dump

file_96258.txt (text/plain), 202.46 KB, created by Ilia Mirkin on 2016-05-28 13:49:36 UTC

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Creator: Ilia Mirkin

Created: 2016-05-28 13:49:36 UTC

Size: 202.46 KB

patch

obsolete

>COMP
>PROPERTY CS_FIXED_BLOCK_WIDTH 1024
>PROPERTY CS_FIXED_BLOCK_HEIGHT 1
>PROPERTY CS_FIXED_BLOCK_DEPTH 1
>DCL SV[0], THREAD_ID
>DCL SV[1], BLOCK_ID
>DCL BUFFER[16]
>DCL BUFFER[17]
>DCL BUFFER[18]
>DCL BUFFER[19]
>DCL CONST[0..5]
>DCL TEMP[0..260], LOCAL
>IMM[0] UINT32 {1024, 1, 16, 0}
>IMM[1] FLT32 {    0.0000,     0.0100,     1.0000,     0.2000}
>IMM[2] FLT32 {    1.5708,    -0.0236,     0.0813,    -0.2146}
>IMM[3] FLT32 {    0.0000,    -0.2000,    10.0000,     2.0000}
>IMM[4] INT32 {1, 0, 4, 2}
>IMM[5] FLT32 {    0.3500,     0.0000,     0.0000,     0.0000}
>IMM[6] INT32 {-1, 0, 0, 0}
>  0: UMAD TEMP[0].xyz, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz
>  1: MOV TEMP[1].x, TEMP[0].xxxx
>  2: MOV TEMP[1].x, TEMP[0].xxxx
>  3: MOD TEMP[2].x, TEMP[0].xxxx, CONST[0].xxxx
>  4: IDIV TEMP[3].x, TEMP[0].xxxx, CONST[0].xxxx
>  5: MOV TEMP[4], IMM[1].xxxx
>  6: UMUL TEMP[5].x, TEMP[0].xxxx, IMM[0].zzzz
>  7: LOAD TEMP[5], BUFFER[18], TEMP[5].xxxx
>  8: ADD TEMP[5], TEMP[5], -CONST[4]
>  9: DP4 TEMP[6].x, TEMP[5], TEMP[5]
> 10: SQRT TEMP[6].x, TEMP[6].xxxx
> 11: ADD TEMP[7].x, CONST[5].xxxx, IMM[1].yyyy
> 12: FSGE TEMP[6].x, TEMP[7].xxxx, TEMP[6].xxxx
> 13: UIF TEMP[6].xxxx :0
> 14:   MOV TEMP[6].xyz, IMM[1].xxxx
> 15:   DP4 TEMP[7].x, TEMP[5], TEMP[5]
> 16:   RSQ TEMP[7].x, TEMP[7].xxxx
> 17:   MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 18:   DP3 TEMP[7].x, TEMP[5].xyzz, IMM[1].xzxx
> 19:   MAX TEMP[7].x, TEMP[7].xxxx, IMM[1].xxxx
> 20:   FSNE TEMP[8].x, TEMP[7].xxxx, IMM[1].zzzz
> 21:   UIF TEMP[8].xxxx :0
> 22:     DP3 TEMP[8].x, TEMP[5].xyzz, TEMP[5].xyzz
> 23:     FSEQ TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx
> 24:     UIF TEMP[9].xxxx :0
> 25:       MOV TEMP[9].xyz, IMM[1].xxxx
> 26:     ELSE :0
> 27:       DP3 TEMP[10].x, IMM[1].xzxx, TEMP[5].xyzz
> 28:       RCP TEMP[8].x, TEMP[8].xxxx
> 29:       MUL TEMP[8].x, TEMP[10].xxxx, TEMP[8].xxxx
> 30:       MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[8].xxxx
> 31:       ADD TEMP[9].xyz, IMM[1].xzxx, -TEMP[5].xyzz
> 32:     ENDIF
> 33:     DP3 TEMP[5].x, TEMP[9].xyzz, TEMP[9].xyzz
> 34:     RSQ TEMP[5].x, TEMP[5].xxxx
> 35:     MUL TEMP[6].xyz, TEMP[9].xyzz, TEMP[5].xxxx
> 36:   ENDIF
> 37:   MOV TEMP[5].w, IMM[1].xxxx
> 38:   MOV TEMP[5].xyz, -TEMP[6].xyzx
> 39:   MOV TEMP[8].w, IMM[1].xxxx
> 40:   MOV TEMP[8].xyz, -TEMP[6].xyzx
> 41:   SSG TEMP[6].x, TEMP[7].xxxx
> 42:   ABS TEMP[9].x, TEMP[7].xxxx
> 43:   ADD TEMP[9].x, IMM[1].zzzz, -TEMP[9].xxxx
> 44:   SQRT TEMP[9].x, TEMP[9].xxxx
> 45:   ABS TEMP[10].x, TEMP[7].xxxx
> 46:   ABS TEMP[11].x, TEMP[7].xxxx
> 47:   ABS TEMP[12].x, TEMP[7].xxxx
> 48:   MAD TEMP[12].x, TEMP[12].xxxx, IMM[2].yyyy, IMM[2].zzzz
> 49:   MAD TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx, IMM[2].wwww
> 50:   MAD TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx, IMM[2].xxxx
> 51:   MUL TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
> 52:   ADD TEMP[9].x, IMM[2].xxxx, -TEMP[9].xxxx
> 53:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[9].xxxx
> 54:   ADD TEMP[6].x, IMM[2].xxxx, -TEMP[6].xxxx
> 55:   SIN TEMP[6].x, TEMP[6].xxxx
> 56:   MUL TEMP[6].x, IMM[1].wwww, TEMP[6].xxxx
> 57:   MUL TEMP[7].x, IMM[1].wwww, TEMP[7].xxxx
> 58:   MUL TEMP[7], TEMP[7].xxxx, TEMP[8]
> 59:   MAD TEMP[4], TEMP[6].xxxx, TEMP[5], -TEMP[7]
> 60: ELSE :0
> 61:   ADD TEMP[4], TEMP[4], IMM[3].xyxx
> 62: ENDIF
> 63: UMUL TEMP[5].x, TEMP[0].xxxx, IMM[0].zzzz
> 64: UMUL TEMP[6].x, TEMP[0].xxxx, IMM[0].zzzz
> 65: LOAD TEMP[6], BUFFER[18], TEMP[6].xxxx
> 66: MOV TEMP[7], TEMP[6]
> 67: UMUL TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz
> 68: LOAD TEMP[0], BUFFER[16], TEMP[0].xxxx
> 69: MUL TEMP[4], TEMP[4], IMM[3].zzzz
> 70: MUL TEMP[7].x, CONST[1].xxxx, CONST[1].xxxx
> 71: MAD TEMP[0], IMM[3].wwww, TEMP[6], -TEMP[0]
> 72: MAD TEMP[0], TEMP[4], TEMP[7].xxxx, TEMP[0]
> 73: STORE BUFFER[19], TEMP[5].xxxx, TEMP[0]
> 74: MEMBAR IMM[4].xxxx
> 75: BARRIER
> 76: MOV TEMP[0].x, IMM[4].yyyy
> 77: BGNLOOP :0
> 78:   ISGE TEMP[4].x, TEMP[0].xxxx, IMM[4].zzzz
> 79:   UIF TEMP[4].xxxx :0
> 80:     BRK
> 81:   ENDIF
> 82:   MOV TEMP[5].x, IMM[4].yyyy
> 83:   BGNLOOP :0
> 84:     ISGE TEMP[6].x, TEMP[5].xxxx, IMM[4].wwww
> 85:     UIF TEMP[6].xxxx :0
> 86:       BRK
> 87:     ENDIF
> 88:     MOD TEMP[7].x, TEMP[3].xxxx, IMM[4].wwww
> 89:     USEQ TEMP[8].x, TEMP[7].xxxx, TEMP[5].xxxx
> 90:     MOD TEMP[9].x, TEMP[2].xxxx, IMM[4].wwww
> 91:     USEQ TEMP[10].x, TEMP[9].xxxx, TEMP[5].xxxx
> 92:     AND TEMP[11].x, TEMP[8].xxxx, TEMP[10].xxxx
> 93:     UIF TEMP[11].xxxx :0
> 94:       UMUL TEMP[12].x, TEMP[1].xxxx, IMM[0].zzzz
> 95:       LOAD TEMP[13], BUFFER[19], TEMP[12].xxxx
> 96:       MOV TEMP[14], TEMP[13]
> 97:       MOV TEMP[15], TEMP[13]
> 98:       UADD TEMP[16].x, TEMP[1].xxxx, IMM[4].xxxx
> 99:       MOD TEMP[17].x, TEMP[16].xxxx, CONST[0].xxxx
>100:       ISLT TEMP[18].x, TEMP[2].xxxx, TEMP[17].xxxx
>101:       UIF TEMP[18].xxxx :0
>102:         UMUL TEMP[19].x, TEMP[16].xxxx, IMM[0].zzzz
>103:         LOAD TEMP[20], BUFFER[19], TEMP[19].xxxx
>104:         MOV TEMP[21], TEMP[20]
>105:         ADD TEMP[22], TEMP[13], -TEMP[20]
>106:         DP4 TEMP[23].x, TEMP[22], TEMP[22]
>107:         SQRT TEMP[24].x, TEMP[23].xxxx
>108:         ADD TEMP[25].x, CONST[2].xxxx, -TEMP[24].xxxx
>109:         MUL TEMP[26].x, IMM[5].xxxx, TEMP[25].xxxx
>110:         RCP TEMP[27].x, TEMP[24].xxxx
>111:         MUL TEMP[28].x, TEMP[26].xxxx, TEMP[27].xxxx
>112:         MUL TEMP[29], TEMP[28].xxxx, TEMP[22]
>113:         UMUL TEMP[30].x, TEMP[1].xxxx, IMM[0].zzzz
>114:         UMUL TEMP[31].x, TEMP[1].xxxx, IMM[0].zzzz
>115:         LOAD TEMP[32], BUFFER[19], TEMP[31].xxxx
>116:         ADD TEMP[33], TEMP[32], TEMP[29]
>117:         STORE BUFFER[19], TEMP[30].xxxx, TEMP[33]
>118:         UMUL TEMP[34].x, TEMP[16].xxxx, IMM[0].zzzz
>119:         UMUL TEMP[35].x, TEMP[16].xxxx, IMM[0].zzzz
>120:         LOAD TEMP[36], BUFFER[19], TEMP[35].xxxx
>121:         ADD TEMP[37], TEMP[36], -TEMP[29]
>122:         STORE BUFFER[19], TEMP[34].xxxx, TEMP[37]
>123:         MEMBAR IMM[4].xxxx
>124:       ENDIF
>125:       UADD TEMP[38].x, TEMP[1].xxxx, CONST[0].xxxx
>126:       UMUL TEMP[39].x, CONST[0].xxxx, CONST[0].xxxx
>127:       ISLT TEMP[40].x, TEMP[38].xxxx, TEMP[39].xxxx
>128:       UIF TEMP[40].xxxx :0
>129:         UMUL TEMP[41].x, TEMP[38].xxxx, IMM[0].zzzz
>130:         LOAD TEMP[42], BUFFER[19], TEMP[41].xxxx
>131:         MOV TEMP[43], TEMP[42]
>132:         ADD TEMP[44], TEMP[13], -TEMP[42]
>133:         DP4 TEMP[45].x, TEMP[44], TEMP[44]
>134:         SQRT TEMP[46].x, TEMP[45].xxxx
>135:         ADD TEMP[47].x, CONST[2].xxxx, -TEMP[46].xxxx
>136:         MUL TEMP[48].x, IMM[5].xxxx, TEMP[47].xxxx
>137:         RCP TEMP[49].x, TEMP[46].xxxx
>138:         MUL TEMP[50].x, TEMP[48].xxxx, TEMP[49].xxxx
>139:         MUL TEMP[51], TEMP[50].xxxx, TEMP[44]
>140:         UMUL TEMP[52].x, TEMP[1].xxxx, IMM[0].zzzz
>141:         UMUL TEMP[53].x, TEMP[1].xxxx, IMM[0].zzzz
>142:         LOAD TEMP[54], BUFFER[19], TEMP[53].xxxx
>143:         ADD TEMP[55], TEMP[54], TEMP[51]
>144:         STORE BUFFER[19], TEMP[52].xxxx, TEMP[55]
>145:         UMUL TEMP[56].x, TEMP[38].xxxx, IMM[0].zzzz
>146:         UMUL TEMP[57].x, TEMP[38].xxxx, IMM[0].zzzz
>147:         LOAD TEMP[58], BUFFER[19], TEMP[57].xxxx
>148:         ADD TEMP[59], TEMP[58], -TEMP[51]
>149:         STORE BUFFER[19], TEMP[56].xxxx, TEMP[59]
>150:         MEMBAR IMM[4].xxxx
>151:       ENDIF
>152:       UADD TEMP[60].x, TEMP[1].xxxx, IMM[4].xxxx
>153:       UADD TEMP[61].x, TEMP[60].xxxx, CONST[0].xxxx
>154:       UMUL TEMP[62].x, CONST[0].xxxx, CONST[0].xxxx
>155:       ISLT TEMP[63].x, TEMP[61].xxxx, TEMP[62].xxxx
>156:       MOD TEMP[64].x, TEMP[61].xxxx, CONST[0].xxxx
>157:       ISLT TEMP[65].x, TEMP[2].xxxx, TEMP[64].xxxx
>158:       AND TEMP[66].x, TEMP[63].xxxx, TEMP[65].xxxx
>159:       UIF TEMP[66].xxxx :0
>160:         UMUL TEMP[67].x, TEMP[61].xxxx, IMM[0].zzzz
>161:         LOAD TEMP[68], BUFFER[19], TEMP[67].xxxx
>162:         MOV TEMP[69], TEMP[68]
>163:         ADD TEMP[70], TEMP[21], -TEMP[68]
>164:         DP4 TEMP[71].x, TEMP[70], TEMP[70]
>165:         SQRT TEMP[72].x, TEMP[71].xxxx
>166:         ADD TEMP[73].x, CONST[2].xxxx, -TEMP[72].xxxx
>167:         MUL TEMP[74].x, IMM[5].xxxx, TEMP[73].xxxx
>168:         RCP TEMP[75].x, TEMP[72].xxxx
>169:         MUL TEMP[76].x, TEMP[74].xxxx, TEMP[75].xxxx
>170:         MUL TEMP[77], TEMP[76].xxxx, TEMP[70]
>171:         UMUL TEMP[78].x, TEMP[16].xxxx, IMM[0].zzzz
>172:         UMUL TEMP[79].x, TEMP[16].xxxx, IMM[0].zzzz
>173:         LOAD TEMP[80], BUFFER[19], TEMP[79].xxxx
>174:         ADD TEMP[81], TEMP[80], TEMP[77]
>175:         STORE BUFFER[19], TEMP[78].xxxx, TEMP[81]
>176:         UMUL TEMP[82].x, TEMP[61].xxxx, IMM[0].zzzz
>177:         UMUL TEMP[83].x, TEMP[61].xxxx, IMM[0].zzzz
>178:         LOAD TEMP[84], BUFFER[19], TEMP[83].xxxx
>179:         ADD TEMP[85], TEMP[84], -TEMP[77]
>180:         STORE BUFFER[19], TEMP[82].xxxx, TEMP[85]
>181:         MEMBAR IMM[4].xxxx
>182:         ADD TEMP[86], TEMP[43], -TEMP[68]
>183:         DP4 TEMP[87].x, TEMP[86], TEMP[86]
>184:         SQRT TEMP[88].x, TEMP[87].xxxx
>185:         ADD TEMP[89].x, CONST[2].xxxx, -TEMP[88].xxxx
>186:         MUL TEMP[90].x, IMM[5].xxxx, TEMP[89].xxxx
>187:         RCP TEMP[91].x, TEMP[88].xxxx
>188:         MUL TEMP[92].x, TEMP[90].xxxx, TEMP[91].xxxx
>189:         MUL TEMP[93], TEMP[92].xxxx, TEMP[86]
>190:         UMUL TEMP[94].x, TEMP[38].xxxx, IMM[0].zzzz
>191:         UMUL TEMP[95].x, TEMP[38].xxxx, IMM[0].zzzz
>192:         LOAD TEMP[96], BUFFER[19], TEMP[95].xxxx
>193:         ADD TEMP[97], TEMP[96], TEMP[93]
>194:         STORE BUFFER[19], TEMP[94].xxxx, TEMP[97]
>195:         UMUL TEMP[98].x, TEMP[61].xxxx, IMM[0].zzzz
>196:         UMUL TEMP[99].x, TEMP[61].xxxx, IMM[0].zzzz
>197:         LOAD TEMP[100], BUFFER[19], TEMP[99].xxxx
>198:         ADD TEMP[14], TEMP[100], -TEMP[93]
>199:         STORE BUFFER[19], TEMP[98].xxxx, TEMP[14]
>200:         MEMBAR IMM[4].xxxx
>201:         ADD TEMP[15], TEMP[13], -TEMP[68]
>202:         DP4 TEMP[101].x, TEMP[15], TEMP[15]
>203:         SQRT TEMP[102].x, TEMP[101].xxxx
>204:         ADD TEMP[103].x, CONST[3].xxxx, -TEMP[102].xxxx
>205:         MUL TEMP[104].x, IMM[5].xxxx, TEMP[103].xxxx
>206:         RCP TEMP[105].x, TEMP[102].xxxx
>207:         MUL TEMP[106].x, TEMP[104].xxxx, TEMP[105].xxxx
>208:         MUL TEMP[107], TEMP[106].xxxx, TEMP[15]
>209:         UMUL TEMP[108].x, TEMP[1].xxxx, IMM[0].zzzz
>210:         UMUL TEMP[109].x, TEMP[1].xxxx, IMM[0].zzzz
>211:         LOAD TEMP[110], BUFFER[19], TEMP[109].xxxx
>212:         ADD TEMP[111], TEMP[110], TEMP[107]
>213:         STORE BUFFER[19], TEMP[108].xxxx, TEMP[111]
>214:         UMUL TEMP[112].x, TEMP[61].xxxx, IMM[0].zzzz
>215:         UMUL TEMP[113].x, TEMP[61].xxxx, IMM[0].zzzz
>216:         LOAD TEMP[114], BUFFER[19], TEMP[113].xxxx
>217:         ADD TEMP[115], TEMP[114], -TEMP[107]
>218:         STORE BUFFER[19], TEMP[112].xxxx, TEMP[115]
>219:         ADD TEMP[116], TEMP[21], -TEMP[43]
>220:         DP4 TEMP[117].x, TEMP[116], TEMP[116]
>221:         SQRT TEMP[118].x, TEMP[117].xxxx
>222:         ADD TEMP[119].x, CONST[3].xxxx, -TEMP[118].xxxx
>223:         MUL TEMP[120].x, IMM[5].xxxx, TEMP[119].xxxx
>224:         RCP TEMP[121].x, TEMP[118].xxxx
>225:         MUL TEMP[122].x, TEMP[120].xxxx, TEMP[121].xxxx
>226:         MUL TEMP[123], TEMP[122].xxxx, TEMP[116]
>227:         UMUL TEMP[124].x, TEMP[16].xxxx, IMM[0].zzzz
>228:         UMUL TEMP[125].x, TEMP[16].xxxx, IMM[0].zzzz
>229:         LOAD TEMP[126], BUFFER[19], TEMP[125].xxxx
>230:         ADD TEMP[127], TEMP[126], TEMP[123]
>231:         STORE BUFFER[19], TEMP[124].xxxx, TEMP[127]
>232:         UMUL TEMP[128].x, TEMP[38].xxxx, IMM[0].zzzz
>233:         UMUL TEMP[129].x, TEMP[38].xxxx, IMM[0].zzzz
>234:         LOAD TEMP[130], BUFFER[19], TEMP[129].xxxx
>235:         ADD TEMP[131], TEMP[130], -TEMP[123]
>236:         STORE BUFFER[19], TEMP[128].xxxx, TEMP[131]
>237:         MEMBAR IMM[4].xxxx
>238:       ENDIF
>239:     ELSE :0
>240:       USEQ TEMP[132].x, TEMP[5].xxxx, IMM[4].xxxx
>241:       MOD TEMP[133].x, TEMP[2].xxxx, IMM[4].wwww
>242:       USEQ TEMP[134].x, TEMP[133].xxxx, IMM[4].xxxx
>243:       AND TEMP[135].x, TEMP[132].xxxx, TEMP[134].xxxx
>244:       USEQ TEMP[136].x, TEMP[3].xxxx, IMM[4].yyyy
>245:       AND TEMP[137].x, TEMP[135].xxxx, TEMP[136].xxxx
>246:       UIF TEMP[137].xxxx :0
>247:         UADD TEMP[16].x, TEMP[1].xxxx, IMM[4].xxxx
>248:         ISLT TEMP[138].x, TEMP[16].xxxx, CONST[0].xxxx
>249:         UIF TEMP[138].xxxx :0
>250:           UMUL TEMP[139].x, TEMP[1].xxxx, IMM[0].zzzz
>251:           LOAD TEMP[140], BUFFER[19], TEMP[139].xxxx
>252:           MOV TEMP[141], TEMP[140]
>253:           UMUL TEMP[142].x, TEMP[16].xxxx, IMM[0].zzzz
>254:           LOAD TEMP[143], BUFFER[19], TEMP[142].xxxx
>255:           ADD TEMP[144], TEMP[140], -TEMP[143]
>256:           DP4 TEMP[145].x, TEMP[144], TEMP[144]
>257:           SQRT TEMP[146].x, TEMP[145].xxxx
>258:           ADD TEMP[147].x, CONST[2].xxxx, -TEMP[146].xxxx
>259:           MUL TEMP[148].x, IMM[5].xxxx, TEMP[147].xxxx
>260:           RCP TEMP[149].x, TEMP[146].xxxx
>261:           MUL TEMP[150].x, TEMP[148].xxxx, TEMP[149].xxxx
>262:           MUL TEMP[151], TEMP[150].xxxx, TEMP[144]
>263:           UMUL TEMP[152].x, TEMP[1].xxxx, IMM[0].zzzz
>264:           UMUL TEMP[153].x, TEMP[1].xxxx, IMM[0].zzzz
>265:           LOAD TEMP[154], BUFFER[19], TEMP[153].xxxx
>266:           ADD TEMP[155], TEMP[154], TEMP[151]
>267:           STORE BUFFER[19], TEMP[152].xxxx, TEMP[155]
>268:           UMUL TEMP[156].x, TEMP[16].xxxx, IMM[0].zzzz
>269:           UMUL TEMP[157].x, TEMP[16].xxxx, IMM[0].zzzz
>270:           LOAD TEMP[158], BUFFER[19], TEMP[157].xxxx
>271:           ADD TEMP[159], TEMP[158], -TEMP[151]
>272:           STORE BUFFER[19], TEMP[156].xxxx, TEMP[159]
>273:           MEMBAR IMM[4].xxxx
>274:         ENDIF
>275:       ELSE :0
>276:         USEQ TEMP[160].x, TEMP[5].xxxx, IMM[4].xxxx
>277:         MOD TEMP[161].x, TEMP[3].xxxx, IMM[4].wwww
>278:         USEQ TEMP[162].x, TEMP[161].xxxx, IMM[4].xxxx
>279:         AND TEMP[163].x, TEMP[160].xxxx, TEMP[162].xxxx
>280:         USEQ TEMP[164].x, TEMP[2].xxxx, IMM[4].yyyy
>281:         AND TEMP[165].x, TEMP[163].xxxx, TEMP[164].xxxx
>282:         UIF TEMP[165].xxxx :0
>283:           UADD TEMP[38].x, TEMP[1].xxxx, CONST[0].xxxx
>284:           UMUL TEMP[166].x, CONST[0].xxxx, CONST[0].xxxx
>285:           ISLT TEMP[167].x, TEMP[38].xxxx, TEMP[166].xxxx
>286:           UIF TEMP[167].xxxx :0
>287:             UMUL TEMP[168].x, TEMP[1].xxxx, IMM[0].zzzz
>288:             LOAD TEMP[169], BUFFER[19], TEMP[168].xxxx
>289:             MOV TEMP[170], TEMP[169]
>290:             UMUL TEMP[171].x, TEMP[38].xxxx, IMM[0].zzzz
>291:             LOAD TEMP[172], BUFFER[19], TEMP[171].xxxx
>292:             ADD TEMP[173], TEMP[169], -TEMP[172]
>293:             DP4 TEMP[174].x, TEMP[173], TEMP[173]
>294:             SQRT TEMP[175].x, TEMP[174].xxxx
>295:             ADD TEMP[176].x, CONST[2].xxxx, -TEMP[175].xxxx
>296:             MUL TEMP[177].x, IMM[5].xxxx, TEMP[176].xxxx
>297:             RCP TEMP[178].x, TEMP[175].xxxx
>298:             MUL TEMP[179].x, TEMP[177].xxxx, TEMP[178].xxxx
>299:             MUL TEMP[180], TEMP[179].xxxx, TEMP[173]
>300:             UMUL TEMP[181].x, TEMP[1].xxxx, IMM[0].zzzz
>301:             UMUL TEMP[182].x, TEMP[1].xxxx, IMM[0].zzzz
>302:             LOAD TEMP[183], BUFFER[19], TEMP[182].xxxx
>303:             ADD TEMP[184], TEMP[183], TEMP[180]
>304:             STORE BUFFER[19], TEMP[181].xxxx, TEMP[184]
>305:             UMUL TEMP[185].x, TEMP[38].xxxx, IMM[0].zzzz
>306:             UMUL TEMP[69].x, TEMP[38].xxxx, IMM[0].zzzz
>307:             LOAD TEMP[186], BUFFER[19], TEMP[69].xxxx
>308:             ADD TEMP[187], TEMP[186], -TEMP[180]
>309:             STORE BUFFER[19], TEMP[185].xxxx, TEMP[187]
>310:             MEMBAR IMM[4].xxxx
>311:           ENDIF
>312:         ENDIF
>313:       ENDIF
>314:     ENDIF
>315:     BARRIER
>316:     UADD TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx
>317:   ENDLOOP :0
>318:   MOV TEMP[188].x, IMM[4].yyyy
>319:   BGNLOOP :0
>320:     ISGE TEMP[189].x, TEMP[188].xxxx, IMM[4].wwww
>321:     UIF TEMP[189].xxxx :0
>322:       BRK
>323:     ENDIF
>324:     MOD TEMP[190].x, TEMP[3].xxxx, IMM[4].wwww
>325:     USEQ TEMP[191].x, TEMP[190].xxxx, TEMP[188].xxxx
>326:     UADD TEMP[192].x, TEMP[2].xxxx, IMM[4].xxxx
>327:     MOD TEMP[193].x, TEMP[192].xxxx, IMM[4].wwww
>328:     USEQ TEMP[194].x, TEMP[193].xxxx, TEMP[188].xxxx
>329:     AND TEMP[195].x, TEMP[191].xxxx, TEMP[194].xxxx
>330:     UIF TEMP[195].xxxx :0
>331:       UMUL TEMP[196].x, TEMP[1].xxxx, IMM[0].zzzz
>332:       LOAD TEMP[197], BUFFER[19], TEMP[196].xxxx
>333:       MOV TEMP[198], TEMP[197]
>334:       UADD TEMP[199].x, TEMP[1].xxxx, IMM[4].xxxx
>335:       UADD TEMP[200].x, TEMP[1].xxxx, CONST[0].xxxx
>336:       UADD TEMP[201].x, TEMP[1].xxxx, IMM[4].xxxx
>337:       UADD TEMP[202].x, TEMP[201].xxxx, CONST[0].xxxx
>338:       UMUL TEMP[203].x, CONST[0].xxxx, CONST[0].xxxx
>339:       ISLT TEMP[204].x, TEMP[202].xxxx, TEMP[203].xxxx
>340:       MOD TEMP[205].x, TEMP[202].xxxx, CONST[0].xxxx
>341:       ISLT TEMP[206].x, TEMP[2].xxxx, TEMP[205].xxxx
>342:       AND TEMP[207].x, TEMP[204].xxxx, TEMP[206].xxxx
>343:       UIF TEMP[207].xxxx :0
>344:         UMUL TEMP[208].x, TEMP[199].xxxx, IMM[0].zzzz
>345:         LOAD TEMP[209], BUFFER[19], TEMP[208].xxxx
>346:         MOV TEMP[210], TEMP[209]
>347:         UMUL TEMP[211].x, TEMP[200].xxxx, IMM[0].zzzz
>348:         LOAD TEMP[212], BUFFER[19], TEMP[211].xxxx
>349:         MOV TEMP[213], TEMP[212]
>350:         UMUL TEMP[214].x, TEMP[202].xxxx, IMM[0].zzzz
>351:         LOAD TEMP[215], BUFFER[19], TEMP[214].xxxx
>352:         ADD TEMP[216], TEMP[197], -TEMP[215]
>353:         DP4 TEMP[217].x, TEMP[216], TEMP[216]
>354:         SQRT TEMP[218].x, TEMP[217].xxxx
>355:         ADD TEMP[219].x, CONST[3].xxxx, -TEMP[218].xxxx
>356:         MUL TEMP[220].x, IMM[5].xxxx, TEMP[219].xxxx
>357:         RCP TEMP[221].x, TEMP[218].xxxx
>358:         MUL TEMP[222].x, TEMP[220].xxxx, TEMP[221].xxxx
>359:         MUL TEMP[223], TEMP[222].xxxx, TEMP[216]
>360:         UMUL TEMP[224].x, TEMP[1].xxxx, IMM[0].zzzz
>361:         UMUL TEMP[225].x, TEMP[1].xxxx, IMM[0].zzzz
>362:         LOAD TEMP[226], BUFFER[19], TEMP[225].xxxx
>363:         ADD TEMP[227], TEMP[226], TEMP[223]
>364:         STORE BUFFER[19], TEMP[224].xxxx, TEMP[227]
>365:         UMUL TEMP[228].x, TEMP[202].xxxx, IMM[0].zzzz
>366:         UMUL TEMP[229].x, TEMP[202].xxxx, IMM[0].zzzz
>367:         LOAD TEMP[230], BUFFER[19], TEMP[229].xxxx
>368:         ADD TEMP[231], TEMP[230], -TEMP[223]
>369:         STORE BUFFER[19], TEMP[228].xxxx, TEMP[231]
>370:         ADD TEMP[232], TEMP[209], -TEMP[212]
>371:         DP4 TEMP[233].x, TEMP[232], TEMP[232]
>372:         SQRT TEMP[234].x, TEMP[233].xxxx
>373:         ADD TEMP[235].x, CONST[3].xxxx, -TEMP[234].xxxx
>374:         MUL TEMP[236].x, IMM[5].xxxx, TEMP[235].xxxx
>375:         RCP TEMP[237].x, TEMP[234].xxxx
>376:         MUL TEMP[238].x, TEMP[236].xxxx, TEMP[237].xxxx
>377:         MUL TEMP[239], TEMP[238].xxxx, TEMP[232]
>378:         UMUL TEMP[240].x, TEMP[199].xxxx, IMM[0].zzzz
>379:         UMUL TEMP[241].x, TEMP[199].xxxx, IMM[0].zzzz
>380:         LOAD TEMP[242], BUFFER[19], TEMP[241].xxxx
>381:         ADD TEMP[243], TEMP[242], TEMP[239]
>382:         STORE BUFFER[19], TEMP[240].xxxx, TEMP[243]
>383:         UMUL TEMP[244].x, TEMP[200].xxxx, IMM[0].zzzz
>384:         UMUL TEMP[245].x, TEMP[200].xxxx, IMM[0].zzzz
>385:         LOAD TEMP[246], BUFFER[19], TEMP[245].xxxx
>386:         ADD TEMP[247], TEMP[246], -TEMP[239]
>387:         STORE BUFFER[19], TEMP[244].xxxx, TEMP[247]
>388:         MEMBAR IMM[4].xxxx
>389:       ENDIF
>390:     ENDIF
>391:     BARRIER
>392:     UADD TEMP[188].x, TEMP[188].xxxx, IMM[4].xxxx
>393:   ENDLOOP :0
>394:   UMUL TEMP[248].x, TEMP[1].xxxx, IMM[0].zzzz
>395:   LOAD TEMP[249], BUFFER[19], TEMP[248].xxxx
>396:   ADD TEMP[250], TEMP[249], -CONST[4]
>397:   DP4 TEMP[251].x, TEMP[250], TEMP[250]
>398:   SQRT TEMP[252].x, TEMP[251].xxxx
>399:   ADD TEMP[253].x, CONST[5].xxxx, IMM[1].yyyy
>400:   FSLT TEMP[254].x, TEMP[252].xxxx, TEMP[253].xxxx
>401:   UIF TEMP[254].xxxx :0
>402:     UMUL TEMP[255].x, TEMP[1].xxxx, IMM[0].zzzz
>403:     DP4 TEMP[256].x, TEMP[250], TEMP[250]
>404:     RSQ TEMP[257].x, TEMP[256].xxxx
>405:     MUL TEMP[258], TEMP[250], TEMP[257].xxxx
>406:     ADD TEMP[259].x, CONST[5].xxxx, IMM[1].yyyy
>407:     MAD TEMP[260], TEMP[258], TEMP[259].xxxx, CONST[4]
>408:     STORE BUFFER[19], TEMP[255].xxxx, TEMP[260]
>409:     MEMBAR IMM[4].xxxx
>410:   ENDIF
>411:   BARRIER
>412:   UADD TEMP[0].x, TEMP[0].xxxx, IMM[4].xxxx
>413: ENDLOOP :0
>414: MOV TEMP[0].xyz, IMM[1].xxxx
>415: UADD TEMP[4].x, CONST[0].xxxx, IMM[6].xxxx
>416: ISLT TEMP[4].x, TEMP[2].xxxx, TEMP[4].xxxx
>417: UIF TEMP[4].xxxx :0
>418:   UADD TEMP[4].x, TEMP[1].xxxx, IMM[4].xxxx
>419:   UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz
>420:   LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx
>421:   UMUL TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz
>422:   LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx
>423:   ADD TEMP[4].xyz, TEMP[4], -TEMP[5]
>424:   DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
>425:   RSQ TEMP[5].x, TEMP[5].xxxx
>426:   MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>427:   UADD TEMP[5].x, CONST[0].xxxx, IMM[6].xxxx
>428:   ISLT TEMP[5].x, TEMP[3].xxxx, TEMP[5].xxxx
>429:   UIF TEMP[5].xxxx :0
>430:     UADD TEMP[5].x, TEMP[1].xxxx, CONST[0].xxxx
>431:     UMUL TEMP[5].x, TEMP[5].xxxx, IMM[0].zzzz
>432:     LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx
>433:     UMUL TEMP[6].x, TEMP[1].xxxx, IMM[0].zzzz
>434:     LOAD TEMP[6], BUFFER[19], TEMP[6].xxxx
>435:     ADD TEMP[5].xyz, TEMP[5], -TEMP[6]
>436:     DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
>437:     RSQ TEMP[6].x, TEMP[6].xxxx
>438:     MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
>439:     MUL TEMP[6].xyz, TEMP[5].zxyy, TEMP[4].yzxx
>440:     MAD TEMP[5].xyz, TEMP[5].yzxx, TEMP[4].zxyy, -TEMP[6].xyzz
>441:     DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
>442:     RSQ TEMP[6].x, TEMP[6].xxxx
>443:     MUL TEMP[0].xyz, TEMP[5].xyzz, TEMP[6].xxxx
>444:   ENDIF
>445:   ISLT TEMP[5].x, IMM[4].yyyy, TEMP[3].xxxx
>446:   UIF TEMP[5].xxxx :0
>447:     UMUL TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz
>448:     LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx
>449:     INEG TEMP[6].x, CONST[0].xxxx
>450:     UADD TEMP[6].x, TEMP[1].xxxx, TEMP[6].xxxx
>451:     UMUL TEMP[6].x, TEMP[6].xxxx, IMM[0].zzzz
>452:     LOAD TEMP[6], BUFFER[19], TEMP[6].xxxx
>453:     ADD TEMP[5].xyz, TEMP[5], -TEMP[6]
>454:     DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
>455:     RSQ TEMP[6].x, TEMP[6].xxxx
>456:     MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
>457:     MUL TEMP[6].xyz, TEMP[5].zxyy, TEMP[4].yzxx
>458:     MAD TEMP[4].xyz, TEMP[5].yzxx, TEMP[4].zxyy, -TEMP[6].xyzz
>459:     DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
>460:     RSQ TEMP[5].x, TEMP[5].xxxx
>461:     MAD TEMP[0].xyz, TEMP[4].xyzz, TEMP[5].xxxx, TEMP[0].xyzz
>462:   ENDIF
>463: ENDIF
>464: ISLT TEMP[2].x, IMM[4].yyyy, TEMP[2].xxxx
>465: UIF TEMP[2].xxxx :0
>466:   UMUL TEMP[2].x, TEMP[1].xxxx, IMM[0].zzzz
>467:   LOAD TEMP[2], BUFFER[19], TEMP[2].xxxx
>468:   UADD TEMP[4].x, TEMP[1].xxxx, IMM[6].xxxx
>469:   UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz
>470:   LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx
>471:   ADD TEMP[2].xyz, TEMP[2], -TEMP[4]
>472:   DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[2].xyzz
>473:   RSQ TEMP[4].x, TEMP[4].xxxx
>474:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[4].xxxx
>475:   UADD TEMP[4].x, CONST[0].xxxx, IMM[6].xxxx
>476:   ISLT TEMP[4].x, TEMP[3].xxxx, TEMP[4].xxxx
>477:   UIF TEMP[4].xxxx :0
>478:     UADD TEMP[4].x, TEMP[1].xxxx, CONST[0].xxxx
>479:     UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz
>480:     LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx
>481:     UMUL TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz
>482:     LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx
>483:     ADD TEMP[4].xyz, TEMP[4], -TEMP[5]
>484:     DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
>485:     RSQ TEMP[5].x, TEMP[5].xxxx
>486:     MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>487:     MUL TEMP[5].xyz, TEMP[4].zxyy, TEMP[2].yzxx
>488:     MAD TEMP[4].xyz, TEMP[4].yzxx, TEMP[2].zxyy, -TEMP[5].xyzz
>489:     DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
>490:     RSQ TEMP[5].x, TEMP[5].xxxx
>491:     MAD TEMP[0].xyz, TEMP[4].xyzz, TEMP[5].xxxx, TEMP[0].xyzz
>492:   ENDIF
>493:   ISLT TEMP[3].x, IMM[4].yyyy, TEMP[3].xxxx
>494:   UIF TEMP[3].xxxx :0
>495:     UMUL TEMP[3].x, TEMP[1].xxxx, IMM[0].zzzz
>496:     LOAD TEMP[3], BUFFER[19], TEMP[3].xxxx
>497:     INEG TEMP[4].x, CONST[0].xxxx
>498:     UADD TEMP[4].x, TEMP[1].xxxx, TEMP[4].xxxx
>499:     UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz
>500:     LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx
>501:     ADD TEMP[3].xyz, TEMP[3], -TEMP[4]
>502:     DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
>503:     RSQ TEMP[4].x, TEMP[4].xxxx
>504:     MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>505:     MUL TEMP[4].xyz, TEMP[3].zxyy, TEMP[2].yzxx
>506:     MAD TEMP[2].xyz, TEMP[3].yzxx, TEMP[2].zxyy, -TEMP[4].xyzz
>507:     DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
>508:     RSQ TEMP[3].x, TEMP[3].xxxx
>509:     MAD TEMP[0].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[0].xyzz
>510:   ENDIF
>511: ENDIF
>512: UMUL TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz
>513: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
>514: RSQ TEMP[2].x, TEMP[2].xxxx
>515: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
>516: STORE BUFFER[17].xyz, TEMP[1].xxxx, TEMP[0].xyzz
>517: MEMBAR IMM[4].xxxx
>518: END
>
>MAIN:-1 ()
>BB:0 (55 instructions) - df = { }
> -> BB:8 (tree)
> -> BB:2 (tree)
>  0: nop u32 %r3135 (0)
>  1: rdsv u32 %r2700 sv[CTAID:0] (0)
>  2: mov u32 %r2701 0x00000400 (0)
>  3: rdsv u32 %r2702 sv[TID:0] (0)
>  4: mad u32 %r2703 %r2700 %r2701 %r2702 (0)
>  5: ld  u32 %r2714 c0[0x0] (0)
>  6: mov u32 $r0 %r2703 (0)
>  7: mov u32 $r1 %r2714 (0)
>  8: call abs BUILTIN:1 (0)
>  9: mov u32 %r2715 $r1 (0)
> 10: nop - { $r0 $r2d } (0)
> 11: nop - $p0q (0)
> 12: mov u32 $r0 %r2703 (0)
> 13: mov u32 $r1 %r2714 (0)
> 14: call abs BUILTIN:1 (0)
> 15: mov u32 %r2717 $r0 (0)
> 16: nop - { $r1 $r2d } (0)
> 17: nop - $p0q (0)
> 18: shl u32 %r2727 %r2703 0x00000004 (0)
> 19: add u64 %r2731d %r2727 c7[0x320] (0)
> 20: add u32 %r2732 %r2727 0x00000004 (0)
> 21: set u8 %p2733 gt u32 %r2732 c7[0x328] (0)
> 22: not %p2733 ld  u32 %r2734 g[%r2731d+0x0] (0)
> 23: %p2733 mov u32 %r2735 0x00000000 (0)
> 24: union u32 %r2736 %r2734 %r2735 (0)
> 25: add u32 %r2741 %r2727 0x00000008 (0)
> 26: set u8 %p2742 gt u32 %r2741 c7[0x328] (0)
> 27: not %p2742 ld  u32 %r2743 g[%r2731d+0x4] (0)
> 28: %p2742 mov u32 %r2744 0x00000000 (0)
> 29: union u32 %r2745 %r2743 %r2744 (0)
> 30: add u32 %r2750 %r2727 0x0000000c (0)
> 31: set u8 %p2751 gt u32 %r2750 c7[0x328] (0)
> 32: not %p2751 ld  u32 %r2752 g[%r2731d+0x8] (0)
> 33: %p2751 mov u32 %r2753 0x00000000 (0)
> 34: union u32 %r2754 %r2752 %r2753 (0)
> 35: add u32 %r2759 %r2727 0x00000010 (0)
> 36: set u8 %p2760 gt u32 %r2759 c7[0x328] (0)
> 37: not %p2760 ld  u32 %r2761 g[%r2731d+0xc] (0)
> 38: %p2760 mov u32 %r2762 0x00000000 (0)
> 39: union u32 %r2763 %r2761 %r2762 (0)
> 40: add f32 %r2770 %r2736 neg c0[0x40] (0)
> 41: add f32 %r2773 %r2745 neg c0[0x44] (0)
> 42: add f32 %r2776 %r2754 neg c0[0x48] (0)
> 43: add f32 %r2779 %r2763 neg c0[0x4c] (0)
> 44: mul f32 %r2784 %r2770 %r2770 (0)
> 45: mad f32 %r2785 %r2773 %r2773 %r2784 (0)
> 46: mad f32 %r2786 %r2776 %r2776 %r2785 (0)
> 47: mad f32 %r2787 %r2779 %r2779 %r2786 (0)
> 48: rsq f32 %r2789 %r2787 (0)
> 49: rcp f32 %r2790 %r2789 (0)
> 50: ld  u32 %r2792 c0[0x50] (0)
> 51: add f32 %r2794 %r2792 0.010000 (0)
> 52: joinat BB:9 (0)
> 53: set u8 %p2797 ge f32 %r2794 %r2790 (0)
> 54: not %p2797 bra BB:8 (0)
>BB:2 (13 instructions) - idom = BB:0, df = { BB:9 }
> -> BB:7 (forward)
> -> BB:3 (tree)
> 55: mov u32 %r2798 0x00000000 (0)
> 56: mul f32 %r2804 %r2770 %r2770 (0)
> 57: mad f32 %r2805 %r2773 %r2773 %r2804 (0)
> 58: mad f32 %r2806 %r2776 %r2776 %r2805 (0)
> 59: mad f32 %r2807 %r2779 %r2779 %r2806 (0)
> 60: rsq f32 %r2810 abs %r2807 (0)
> 61: mul f32 %r2813 %r2770 %r2810 (0)
> 62: mul f32 %r2814 %r2773 %r2810 (0)
> 63: mul f32 %r2815 %r2776 %r2810 (0)
> 64: max f32 %r2829 %r2814 0.000000 (0)
> 65: joinat BB:7 (0)
> 66: set u8 %p2833 neu f32 %r2829 1.000000 (0)
> 67: not %p2833 bra BB:7 (0)
>BB:3 (6 instructions) - idom = BB:2, df = { BB:7 }
> -> BB:5 (tree)
> -> BB:4 (tree)
> 68: mul f32 %r2834 %r2813 %r2813 (0)
> 69: mad f32 %r2835 %r2814 %r2814 %r2834 (0)
> 70: mad f32 %r2836 %r2815 %r2815 %r2835 (0)
> 71: joinat BB:6 (0)
> 72: set u8 %p2840 eq f32 %r2836 0.000000 (0)
> 73: not %p2840 bra BB:5 (0)
>BB:4 (2 instructions) - idom = BB:3, df = { BB:6 }
> -> BB:6 (forward)
> 74: mov u32 %r2841 0x00000000 (0)
> 75: bra BB:6 (0)
>BB:5 (9 instructions) - idom = BB:3, df = { BB:6 }
> -> BB:6 (forward)
> 76: rcp f32 %r2868 %r2836 (0)
> 77: mul f32 %r2870 %r2814 %r2868 (0)
> 78: mul f32 %r2872 %r2813 %r2870 (0)
> 79: mul f32 %r2873 %r2814 %r2870 (0)
> 80: mul f32 %r2874 %r2815 %r2870 (0)
> 81: neg f32 %r2879 %r2872 (0)
> 82: add f32 %r2883 neg %r2873 1.000000 (0)
> 83: neg f32 %r2885 %r2874 (0)
> 84: bra BB:6 (0)
>BB:6 (12 instructions) - idom = BB:3, df = { BB:7 }
> -> BB:7 (forward)
> 85: phi u32 %r2847 %r2841 %r2879 (0)
> 86: phi u32 %r2848 %r2841 %r2883 (0)
> 87: phi u32 %r2849 %r2841 %r2885 (0)
> 88: join (0)
> 89: mul f32 %r2850 %r2847 %r2847 (0)
> 90: mad f32 %r2851 %r2848 %r2848 %r2850 (0)
> 91: mad f32 %r2852 %r2849 %r2849 %r2851 (0)
> 92: rsq f32 %r2855 abs %r2852 (0)
> 93: mul f32 %r2858 %r2847 %r2855 (0)
> 94: mul f32 %r2859 %r2848 %r2855 (0)
> 95: mul f32 %r2860 %r2849 %r2855 (0)
> 96: bra BB:7 (0)
>BB:7 (34 instructions) - idom = BB:2, df = { BB:9 }
> -> BB:9 (forward)
> 97: phi u32 %r2887 %r2798 %r2858 (0)
> 98: phi u32 %r2888 %r2798 %r2859 (0)
> 99: phi u32 %r2889 %r2798 %r2860 (0)
>100: join (0)
>101: set f32 %r2906 gt %r2829 0.000000 (0)
>102: set f32 %r2907 lt %r2829 0.000000 (0)
>103: sub f32 %r2908 %r2906 %r2907 (0)
>104: abs f32 %r2909 %r2829 (0)
>105: add f32 %r2912 neg abs %r2829 1.000000 (0)
>106: rsq f32 %r2914 %r2912 (0)
>107: rcp f32 %r2915 %r2914 (0)
>108: mov u32 %r2920 0xbcc19a5f (0)
>109: mov u32 %r2921 0x3da68d87 (0)
>110: mad f32 %r2922 %r2909 %r2920 %r2921 (0)
>111: mov u32 %r2924 0xbe5bc094 (0)
>112: mad f32 %r2925 %r2909 %r2922 %r2924 (0)
>113: mov u32 %r2927 0x3fc90fdb (0)
>114: mad f32 %r2928 %r2909 %r2925 %r2927 (0)
>115: mul f32 %r2930 %r2915 %r2928 (0)
>116: add f32 %r2934 neg %r2930 1.570796 (0)
>117: mul f32 %r2936 %r2908 %r2934 (0)
>118: add f32 %r2940 neg %r2936 1.570796 (0)
>119: presin f32 %r2942 %r2940 (0)
>120: sin f32 %r2943 %r2942 (0)
>121: mul f32 %r2947 %r2943 0.200000 (0)
>122: mul f32 %r2950 %r2829 0.200000 (0)
>123: mul f32 %r2952 %r2950 neg %r2887 (0)
>124: mul f32 %r2953 %r2950 neg %r2888 (0)
>125: mul f32 %r2954 %r2950 neg %r2889 (0)
>126: mad f32 %r2961 %r2947 neg %r2887 neg %r2952 (0)
>127: mad f32 %r2963 %r2947 neg %r2888 neg %r2953 (0)
>128: mad f32 %r2965 %r2947 neg %r2889 neg %r2954 (0)
>129: mov f32 %r2966 -0.000000 (0)
>130: bra BB:9 (0)
>BB:8 (3 instructions) - idom = BB:0, df = { BB:9 }
> -> BB:9 (forward)
>131: mov f32 %r6409 0.000000 (0)
>132: mov f32 %r6411 -0.200000 (0)
>133: bra BB:9 (0)
>BB:9 (71 instructions) - idom = BB:0, df = { }
> -> BB:10 (tree)
>134: phi u32 %r2968 %r2961 %r6409 (0)
>135: phi u32 %r2969 %r2963 %r6411 (0)
>136: phi u32 %r2970 %r2965 %r6409 (0)
>137: phi u32 %r2971 %r2966 %r6409 (0)
>138: join (0)
>139: shl u32 %r2973 %r2703 0x00000004 (0)
>140: add u64 %r2979d %r2973 c7[0x320] (0)
>141: add u32 %r2980 %r2973 0x00000004 (0)
>142: set u8 %p2981 gt u32 %r2980 c7[0x328] (0)
>143: not %p2981 ld  u32 %r2982 g[%r2979d+0x0] (0)
>144: %p2981 mov u32 %r2983 0x00000000 (0)
>145: union u32 %r2984 %r2982 %r2983 (0)
>146: add u32 %r2989 %r2973 0x00000008 (0)
>147: set u8 %p2990 gt u32 %r2989 c7[0x328] (0)
>148: not %p2990 ld  u32 %r2991 g[%r2979d+0x4] (0)
>149: %p2990 mov u32 %r2992 0x00000000 (0)
>150: union u32 %r2993 %r2991 %r2992 (0)
>151: add u32 %r2998 %r2973 0x0000000c (0)
>152: set u8 %p2999 gt u32 %r2998 c7[0x328] (0)
>153: not %p2999 ld  u32 %r3000 g[%r2979d+0x8] (0)
>154: %p2999 mov u32 %r3001 0x00000000 (0)
>155: union u32 %r3002 %r3000 %r3001 (0)
>156: add u32 %r3007 %r2973 0x00000010 (0)
>157: set u8 %p3008 gt u32 %r3007 c7[0x328] (0)
>158: not %p3008 ld  u32 %r3009 g[%r2979d+0xc] (0)
>159: %p3008 mov u32 %r3010 0x00000000 (0)
>160: union u32 %r3011 %r3009 %r3010 (0)
>161: add u64 %r3026d %r2973 c7[0x300] (0)
>162: set u8 %p3028 gt u32 %r2980 c7[0x308] (0)
>163: not %p3028 ld  u32 %r3029 g[%r3026d+0x0] (0)
>164: %p3028 mov u32 %r3030 0x00000000 (0)
>165: union u32 %r3031 %r3029 %r3030 (0)
>166: set u8 %p3037 gt u32 %r2989 c7[0x308] (0)
>167: not %p3037 ld  u32 %r3038 g[%r3026d+0x4] (0)
>168: %p3037 mov u32 %r3039 0x00000000 (0)
>169: union u32 %r3040 %r3038 %r3039 (0)
>170: set u8 %p3046 gt u32 %r2998 c7[0x308] (0)
>171: not %p3046 ld  u32 %r3047 g[%r3026d+0x8] (0)
>172: %p3046 mov u32 %r3048 0x00000000 (0)
>173: union u32 %r3049 %r3047 %r3048 (0)
>174: set u8 %p3055 gt u32 %r3007 c7[0x308] (0)
>175: not %p3055 ld  u32 %r3056 g[%r3026d+0xc] (0)
>176: %p3055 mov u32 %r3057 0x00000000 (0)
>177: union u32 %r3058 %r3056 %r3057 (0)
>178: mul f32 %r3064 %r2968 10.000000 (0)
>179: mul f32 %r3066 %r2969 10.000000 (0)
>180: mul f32 %r3068 %r2970 10.000000 (0)
>181: mul f32 %r3070 %r2971 10.000000 (0)
>182: ld  u32 %r3075 c0[0x10] (0)
>183: mul f32 %r3077 %r3075 c0[0x10] (0)
>184: mad f32 %r3080 %r2984 2.000000 neg %r3031 (0)
>185: mad f32 %r3083 %r2993 2.000000 neg %r3040 (0)
>186: mad f32 %r3086 %r3002 2.000000 neg %r3049 (0)
>187: mad f32 %r3089 %r3011 2.000000 neg %r3058 (0)
>188: mad f32 %r3094 %r3064 %r3077 %r3080 (0)
>189: mad f32 %r3095 %r3066 %r3077 %r3083 (0)
>190: mad f32 %r3096 %r3068 %r3077 %r3086 (0)
>191: mad f32 %r3097 %r3070 %r3077 %r3089 (0)
>192: add u64 %r3105d %r2973 c7[0x330] (0)
>193: set u8 %p3107 gt u32 %r2980 c7[0x338] (0)
>194: not %p3107 st  u32 # g[%r3105d+0x0] %r3094 (0)
>195: set u8 %p3113 gt u32 %r2989 c7[0x338] (0)
>196: not %p3113 st  u32 # g[%r3105d+0x4] %r3095 (0)
>197: set u8 %p3119 gt u32 %r2998 c7[0x338] (0)
>198: not %p3119 st  u32 # g[%r3105d+0x8] %r3096 (0)
>199: set u8 %p3125 gt u32 %r3007 c7[0x338] (0)
>200: not %p3125 st  u32 # g[%r3105d+0xc] %r3097 (0)
>201: membar (SUBOP:7) - # (0)
>202: bar u32 # 0x00000000 0x00000000 (0)
>203: mov u32 %r3126 0x00000000 (0)
>204: prebreak BB:11 (0)
>BB:10 (12 instructions) - idom = BB:9, df = { BB:10 }
> -> BB:13 (forward)
> -> BB:12 (tree)
>205: phi u32 %r3136 %r4133 %r3126 (0)
>206: phi u32 %r3137 %r4004 %r3135 (0)
>207: phi u32 %r3138 %r4005 %r3135 (0)
>208: phi u32 %r3139 %r4006 %r3135 (0)
>209: phi u32 %r3140 %r4007 %r3135 (0)
>210: phi u32 %r3141 %r4008 %r3135 (0)
>211: phi u32 %r3142 %r4009 %r3135 (0)
>212: phi u32 %r3143 %r4010 %r3135 (0)
>213: phi u32 %r3144 %r4011 %r3135 (0)
>214: precont BB:10 (0)
>215: set u8 %p3147 ge s32 %r3136 4 (0)
>216: not %p3147 bra BB:13 (0)
>BB:12 (1 instructions) - idom = BB:10, df = { }
> -> BB:11 (cross)
>217: break BB:11 (0)
>BB:13 (2 instructions) - idom = BB:10, df = { BB:10 }
> -> BB:14 (tree)
>218: mov u32 %r4001 0x00000000 (0)
>219: prebreak BB:15 (0)
>BB:14 (12 instructions) - idom = BB:13, df = { BB:10 BB:14 }
> -> BB:17 (forward)
> -> BB:16 (tree)
>220: phi u32 %r4003 %r5880 %r4001 (0)
>221: phi u32 %r4004 %r5871 %r3137 (0)
>222: phi u32 %r4005 %r5872 %r3138 (0)
>223: phi u32 %r4006 %r5873 %r3139 (0)
>224: phi u32 %r4007 %r5874 %r3140 (0)
>225: phi u32 %r4008 %r5875 %r3141 (0)
>226: phi u32 %r4009 %r5876 %r3142 (0)
>227: phi u32 %r4010 %r5877 %r3143 (0)
>228: phi u32 %r4011 %r5878 %r3144 (0)
>229: precont BB:14 (0)
>230: set u8 %p4014 ge s32 %r4003 2 (0)
>231: not %p4014 bra BB:17 (0)
>BB:16 (1 instructions) - idom = BB:14, df = { BB:10 }
> -> BB:15 (cross)
>232: break BB:15 (0)
>BB:17 (17 instructions) - idom = BB:14, df = { BB:14 }
> -> BB:25 (tree)
> -> BB:18 (tree)
>233: mov u32 %r4661 0x00000002 (0)
>234: mov u32 $r0 %r2717 (0)
>235: mov u32 $r1 %r4661 (0)
>236: call abs BUILTIN:1 (0)
>237: mov u32 %r4662 $r1 (0)
>238: nop - { $r0 $r2d } (0)
>239: nop - $p0q (0)
>240: mov u32 $r0 %r2715 (0)
>241: mov u32 $r1 %r4661 (0)
>242: call abs BUILTIN:1 (0)
>243: mov u32 %r4665 $r1 (0)
>244: nop - { $r0 $r2d } (0)
>245: nop - $p0q (0)
>246: set u8 %p6420 eq u32 %r4662 %r4003 (0)
>247: joinat BB:35 (0)
>248: set and u8 %p4668 eq u32 %r4665 %r4003 %p6420 (0)
>249: not %p4668 bra BB:25 (0)
>BB:18 (33 instructions) - idom = BB:17, df = { BB:35 }
> -> BB:20 (forward)
> -> BB:19 (tree)
>250: shl u32 %r4670 %r2703 0x00000004 (0)
>251: add u64 %r4674d %r4670 c7[0x330] (0)
>252: add u32 %r4675 %r4670 0x00000004 (0)
>253: set u8 %p4676 gt u32 %r4675 c7[0x338] (0)
>254: not %p4676 ld  u32 %r4677 g[%r4674d+0x0] (0)
>255: %p4676 mov u32 %r4678 0x00000000 (0)
>256: union u32 %r4679 %r4677 %r4678 (0)
>257: add u32 %r4684 %r4670 0x00000008 (0)
>258: set u8 %p4685 gt u32 %r4684 c7[0x338] (0)
>259: not %p4685 ld  u32 %r4686 g[%r4674d+0x4] (0)
>260: %p4685 mov u32 %r4687 0x00000000 (0)
>261: union u32 %r4688 %r4686 %r4687 (0)
>262: add u32 %r4693 %r4670 0x0000000c (0)
>263: set u8 %p4694 gt u32 %r4693 c7[0x338] (0)
>264: not %p4694 ld  u32 %r4695 g[%r4674d+0x8] (0)
>265: %p4694 mov u32 %r4696 0x00000000 (0)
>266: union u32 %r4697 %r4695 %r4696 (0)
>267: add u32 %r4702 %r4670 0x00000010 (0)
>268: set u8 %p4703 gt u32 %r4702 c7[0x338] (0)
>269: not %p4703 ld  u32 %r4704 g[%r4674d+0xc] (0)
>270: %p4703 mov u32 %r4705 0x00000000 (0)
>271: union u32 %r4706 %r4704 %r4705 (0)
>272: add u32 %r4716 %r2703 0x00000001 (0)
>273: ld  u32 %r4717 c0[0x0] (0)
>274: mov u32 $r0 %r4716 (0)
>275: mov u32 $r1 %r4717 (0)
>276: call abs BUILTIN:1 (0)
>277: mov u32 %r4718 $r1 (0)
>278: nop - { $r0 $r2d } (0)
>279: nop - $p0q (0)
>280: joinat BB:20 (0)
>281: set u8 %p4720 lt s32 %r2715 %r4718 (0)
>282: not %p4720 bra BB:20 (0)
>BB:19 (90 instructions) - idom = BB:18, df = { BB:20 }
> -> BB:20 (forward)
>283: shl u32 %r6433 %r2703 0x00000004 (0)
>284: add u32 %r4722 %r6433 0x00000010 (0)
>285: add u64 %r4726d %r4722 c7[0x330] (0)
>286: add u32 %r4727 %r4722 0x00000004 (0)
>287: set u8 %p4728 gt u32 %r4727 c7[0x338] (0)
>288: not %p4728 ld  u32 %r4729 g[%r4726d+0x0] (0)
>289: %p4728 mov u32 %r4730 0x00000000 (0)
>290: union u32 %r4731 %r4729 %r4730 (0)
>291: add u32 %r4736 %r4722 0x00000008 (0)
>292: set u8 %p4737 gt u32 %r4736 c7[0x338] (0)
>293: not %p4737 ld  u32 %r4738 g[%r4726d+0x4] (0)
>294: %p4737 mov u32 %r4739 0x00000000 (0)
>295: union u32 %r4740 %r4738 %r4739 (0)
>296: add u32 %r4745 %r4722 0x0000000c (0)
>297: set u8 %p4746 gt u32 %r4745 c7[0x338] (0)
>298: not %p4746 ld  u32 %r4747 g[%r4726d+0x8] (0)
>299: %p4746 mov u32 %r4748 0x00000000 (0)
>300: union u32 %r4749 %r4747 %r4748 (0)
>301: add u32 %r4754 %r4722 0x00000010 (0)
>302: set u8 %p4755 gt u32 %r4754 c7[0x338] (0)
>303: not %p4755 ld  u32 %r4756 g[%r4726d+0xc] (0)
>304: %p4755 mov u32 %r4757 0x00000000 (0)
>305: union u32 %r4758 %r4756 %r4757 (0)
>306: add f32 %r4764 %r4679 neg %r4731 (0)
>307: add f32 %r4766 %r4688 neg %r4740 (0)
>308: add f32 %r4768 %r4697 neg %r4749 (0)
>309: add f32 %r4770 %r4706 neg %r4758 (0)
>310: mul f32 %r4771 %r4764 %r4764 (0)
>311: mad f32 %r4772 %r4766 %r4766 %r4771 (0)
>312: mad f32 %r4773 %r4768 %r4768 %r4772 (0)
>313: mad f32 %r4774 %r4770 %r4770 %r4773 (0)
>314: rsq f32 %r4776 %r4774 (0)
>315: rcp f32 %r4777 %r4776 (0)
>316: add f32 %r4780 neg %r4777 c0[0x20] (0)
>317: mul f32 %r4782 %r4780 0.350000 (0)
>318: mul f32 %r4784 %r4782 %r4776 (0)
>319: mul f32 %r4785 %r4784 %r4764 (0)
>320: mul f32 %r4786 %r4784 %r4766 (0)
>321: mul f32 %r4787 %r4784 %r4768 (0)
>322: mul f32 %r4788 %r4784 %r4770 (0)
>323: add u64 %r4796d %r6433 c7[0x330] (0)
>324: add u32 %r4797 %r6433 0x00000004 (0)
>325: set u8 %p4798 gt u32 %r4797 c7[0x338] (0)
>326: not %p4798 ld  u32 %r4799 g[%r4796d+0x0] (0)
>327: %p4798 mov u32 %r4800 0x00000000 (0)
>328: union u32 %r4801 %r4799 %r4800 (0)
>329: add u32 %r4806 %r6433 0x00000008 (0)
>330: set u8 %p4807 gt u32 %r4806 c7[0x338] (0)
>331: not %p4807 ld  u32 %r4808 g[%r4796d+0x4] (0)
>332: %p4807 mov u32 %r4809 0x00000000 (0)
>333: union u32 %r4810 %r4808 %r4809 (0)
>334: add u32 %r4815 %r6433 0x0000000c (0)
>335: set u8 %p4816 gt u32 %r4815 c7[0x338] (0)
>336: not %p4816 ld  u32 %r4817 g[%r4796d+0x8] (0)
>337: %p4816 mov u32 %r4818 0x00000000 (0)
>338: union u32 %r4819 %r4817 %r4818 (0)
>339: set u8 %p4825 gt u32 %r4722 c7[0x338] (0)
>340: not %p4825 ld  u32 %r4826 g[%r4796d+0xc] (0)
>341: %p4825 mov u32 %r4827 0x00000000 (0)
>342: union u32 %r4828 %r4826 %r4827 (0)
>343: add f32 %r4829 %r4801 %r4785 (0)
>344: add f32 %r4830 %r4810 %r4786 (0)
>345: add f32 %r4831 %r4819 %r4787 (0)
>346: add f32 %r4832 %r4828 %r4788 (0)
>347: not %p4798 st  u32 # g[%r4796d+0x0] %r4829 (0)
>348: not %p4807 st  u32 # g[%r4796d+0x4] %r4830 (0)
>349: not %p4816 st  u32 # g[%r4796d+0x8] %r4831 (0)
>350: not %p4825 st  u32 # g[%r4796d+0xc] %r4832 (0)
>351: not %p4728 ld  u32 %r4867 g[%r4726d+0x0] (0)
>352: %p4728 mov u32 %r4868 0x00000000 (0)
>353: union u32 %r4869 %r4867 %r4868 (0)
>354: not %p4737 ld  u32 %r4876 g[%r4726d+0x4] (0)
>355: %p4737 mov u32 %r4877 0x00000000 (0)
>356: union u32 %r4878 %r4876 %r4877 (0)
>357: not %p4746 ld  u32 %r4885 g[%r4726d+0x8] (0)
>358: %p4746 mov u32 %r4886 0x00000000 (0)
>359: union u32 %r4887 %r4885 %r4886 (0)
>360: not %p4755 ld  u32 %r4894 g[%r4726d+0xc] (0)
>361: %p4755 mov u32 %r4895 0x00000000 (0)
>362: union u32 %r4896 %r4894 %r4895 (0)
>363: add f32 %r4898 %r4869 neg %r4785 (0)
>364: add f32 %r4900 %r4878 neg %r4786 (0)
>365: add f32 %r4902 %r4887 neg %r4787 (0)
>366: add f32 %r4904 %r4896 neg %r4788 (0)
>367: not %p4728 st  u32 # g[%r4726d+0x0] %r4898 (0)
>368: not %p4737 st  u32 # g[%r4726d+0x4] %r4900 (0)
>369: not %p4746 st  u32 # g[%r4726d+0x8] %r4902 (0)
>370: not %p4755 st  u32 # g[%r4726d+0xc] %r4904 (0)
>371: membar (SUBOP:7) - # (0)
>372: bra BB:20 (0)
>BB:20 (11 instructions) - idom = BB:18, df = { BB:35 }
> -> BB:22 (forward)
> -> BB:21 (tree)
>373: phi u32 %r4929 %r4004 %r4731 (0)
>374: phi u32 %r4930 %r4005 %r4740 (0)
>375: phi u32 %r4931 %r4006 %r4749 (0)
>376: phi u32 %r4932 %r4007 %r4758 (0)
>377: join (0)
>378: ld  u32 %r4933 c0[0x0] (0)
>379: add u32 %r4934 %r2703 c0[0x0] (0)
>380: mul u32 %r4937 %r4933 c0[0x0] (0)
>381: joinat BB:22 (0)
>382: set u8 %p4939 lt s32 %r4934 %r4937 (0)
>383: not %p4939 bra BB:22 (0)
>BB:21 (91 instructions) - idom = BB:20, df = { BB:22 }
> -> BB:22 (forward)
>384: shl u32 %r4941 %r4934 0x00000004 (0)
>385: add u64 %r4945d %r4941 c7[0x330] (0)
>386: add u32 %r4946 %r4941 0x00000004 (0)
>387: set u8 %p4947 gt u32 %r4946 c7[0x338] (0)
>388: not %p4947 ld  u32 %r4948 g[%r4945d+0x0] (0)
>389: %p4947 mov u32 %r4949 0x00000000 (0)
>390: union u32 %r4950 %r4948 %r4949 (0)
>391: add u32 %r4955 %r4941 0x00000008 (0)
>392: set u8 %p4956 gt u32 %r4955 c7[0x338] (0)
>393: not %p4956 ld  u32 %r4957 g[%r4945d+0x4] (0)
>394: %p4956 mov u32 %r4958 0x00000000 (0)
>395: union u32 %r4959 %r4957 %r4958 (0)
>396: add u32 %r4964 %r4941 0x0000000c (0)
>397: set u8 %p4965 gt u32 %r4964 c7[0x338] (0)
>398: not %p4965 ld  u32 %r4966 g[%r4945d+0x8] (0)
>399: %p4965 mov u32 %r4967 0x00000000 (0)
>400: union u32 %r4968 %r4966 %r4967 (0)
>401: add u32 %r4973 %r4941 0x00000010 (0)
>402: set u8 %p4974 gt u32 %r4973 c7[0x338] (0)
>403: not %p4974 ld  u32 %r4975 g[%r4945d+0xc] (0)
>404: %p4974 mov u32 %r4976 0x00000000 (0)
>405: union u32 %r4977 %r4975 %r4976 (0)
>406: add f32 %r4983 %r4679 neg %r4950 (0)
>407: add f32 %r4985 %r4688 neg %r4959 (0)
>408: add f32 %r4987 %r4697 neg %r4968 (0)
>409: add f32 %r4989 %r4706 neg %r4977 (0)
>410: mul f32 %r4990 %r4983 %r4983 (0)
>411: mad f32 %r4991 %r4985 %r4985 %r4990 (0)
>412: mad f32 %r4992 %r4987 %r4987 %r4991 (0)
>413: mad f32 %r4993 %r4989 %r4989 %r4992 (0)
>414: rsq f32 %r4995 %r4993 (0)
>415: rcp f32 %r4996 %r4995 (0)
>416: add f32 %r4999 neg %r4996 c0[0x20] (0)
>417: mul f32 %r5001 %r4999 0.350000 (0)
>418: mul f32 %r5003 %r5001 %r4995 (0)
>419: mul f32 %r5004 %r5003 %r4983 (0)
>420: mul f32 %r5005 %r5003 %r4985 (0)
>421: mul f32 %r5006 %r5003 %r4987 (0)
>422: mul f32 %r5007 %r5003 %r4989 (0)
>423: shl u32 %r5009 %r2703 0x00000004 (0)
>424: add u64 %r5015d %r5009 c7[0x330] (0)
>425: add u32 %r5016 %r5009 0x00000004 (0)
>426: set u8 %p5017 gt u32 %r5016 c7[0x338] (0)
>427: not %p5017 ld  u32 %r5018 g[%r5015d+0x0] (0)
>428: %p5017 mov u32 %r5019 0x00000000 (0)
>429: union u32 %r5020 %r5018 %r5019 (0)
>430: add u32 %r5025 %r5009 0x00000008 (0)
>431: set u8 %p5026 gt u32 %r5025 c7[0x338] (0)
>432: not %p5026 ld  u32 %r5027 g[%r5015d+0x4] (0)
>433: %p5026 mov u32 %r5028 0x00000000 (0)
>434: union u32 %r5029 %r5027 %r5028 (0)
>435: add u32 %r5034 %r5009 0x0000000c (0)
>436: set u8 %p5035 gt u32 %r5034 c7[0x338] (0)
>437: not %p5035 ld  u32 %r5036 g[%r5015d+0x8] (0)
>438: %p5035 mov u32 %r5037 0x00000000 (0)
>439: union u32 %r5038 %r5036 %r5037 (0)
>440: add u32 %r5043 %r5009 0x00000010 (0)
>441: set u8 %p5044 gt u32 %r5043 c7[0x338] (0)
>442: not %p5044 ld  u32 %r5045 g[%r5015d+0xc] (0)
>443: %p5044 mov u32 %r5046 0x00000000 (0)
>444: union u32 %r5047 %r5045 %r5046 (0)
>445: add f32 %r5048 %r5020 %r5004 (0)
>446: add f32 %r5049 %r5029 %r5005 (0)
>447: add f32 %r5050 %r5038 %r5006 (0)
>448: add f32 %r5051 %r5047 %r5007 (0)
>449: not %p5017 st  u32 # g[%r5015d+0x0] %r5048 (0)
>450: not %p5026 st  u32 # g[%r5015d+0x4] %r5049 (0)
>451: not %p5035 st  u32 # g[%r5015d+0x8] %r5050 (0)
>452: not %p5044 st  u32 # g[%r5015d+0xc] %r5051 (0)
>453: not %p4947 ld  u32 %r5086 g[%r4945d+0x0] (0)
>454: %p4947 mov u32 %r5087 0x00000000 (0)
>455: union u32 %r5088 %r5086 %r5087 (0)
>456: not %p4956 ld  u32 %r5095 g[%r4945d+0x4] (0)
>457: %p4956 mov u32 %r5096 0x00000000 (0)
>458: union u32 %r5097 %r5095 %r5096 (0)
>459: not %p4965 ld  u32 %r5104 g[%r4945d+0x8] (0)
>460: %p4965 mov u32 %r5105 0x00000000 (0)
>461: union u32 %r5106 %r5104 %r5105 (0)
>462: not %p4974 ld  u32 %r5113 g[%r4945d+0xc] (0)
>463: %p4974 mov u32 %r5114 0x00000000 (0)
>464: union u32 %r5115 %r5113 %r5114 (0)
>465: add f32 %r5117 %r5088 neg %r5004 (0)
>466: add f32 %r5119 %r5097 neg %r5005 (0)
>467: add f32 %r5121 %r5106 neg %r5006 (0)
>468: add f32 %r5123 %r5115 neg %r5007 (0)
>469: not %p4947 st  u32 # g[%r4945d+0x0] %r5117 (0)
>470: not %p4956 st  u32 # g[%r4945d+0x4] %r5119 (0)
>471: not %p4965 st  u32 # g[%r4945d+0x8] %r5121 (0)
>472: not %p4974 st  u32 # g[%r4945d+0xc] %r5123 (0)
>473: membar (SUBOP:7) - # (0)
>474: bra BB:22 (0)
>BB:22 (19 instructions) - idom = BB:20, df = { BB:35 }
> -> BB:24 (forward)
> -> BB:23 (tree)
>475: phi u32 %r5148 %r4008 %r4950 (0)
>476: phi u32 %r5149 %r4009 %r4959 (0)
>477: phi u32 %r5150 %r4010 %r4968 (0)
>478: phi u32 %r5151 %r4011 %r4977 (0)
>479: join (0)
>480: add u32 %r5153 %r2703 0x00000001 (0)
>481: ld  u32 %r5154 c0[0x0] (0)
>482: add u32 %r5155 %r5153 c0[0x0] (0)
>483: mul u32 %r5158 %r5154 c0[0x0] (0)
>484: mov u32 $r0 %r5155 (0)
>485: mov u32 $r1 %r5154 (0)
>486: call abs BUILTIN:1 (0)
>487: mov u32 %r5161 $r1 (0)
>488: nop - { $r0 $r2d } (0)
>489: nop - $p0q (0)
>490: set u8 %p6425 lt s32 %r5155 %r5158 (0)
>491: joinat BB:24 (0)
>492: set and u8 %p5164 lt s32 %r2715 %r5161 %p6425 (0)
>493: not %p5164 bra BB:24 (0)
>BB:23 (283 instructions) - idom = BB:22, df = { BB:24 }
> -> BB:24 (forward)
>494: shl u32 %r5166 %r5155 0x00000004 (0)
>495: add u64 %r5170d %r5166 c7[0x330] (0)
>496: add u32 %r5171 %r5166 0x00000004 (0)
>497: set u8 %p5172 gt u32 %r5171 c7[0x338] (0)
>498: not %p5172 ld  u32 %r5173 g[%r5170d+0x0] (0)
>499: %p5172 mov u32 %r5174 0x00000000 (0)
>500: union u32 %r5175 %r5173 %r5174 (0)
>501: add u32 %r5180 %r5166 0x00000008 (0)
>502: set u8 %p5181 gt u32 %r5180 c7[0x338] (0)
>503: not %p5181 ld  u32 %r5182 g[%r5170d+0x4] (0)
>504: %p5181 mov u32 %r5183 0x00000000 (0)
>505: union u32 %r5184 %r5182 %r5183 (0)
>506: add u32 %r5189 %r5166 0x0000000c (0)
>507: set u8 %p5190 gt u32 %r5189 c7[0x338] (0)
>508: not %p5190 ld  u32 %r5191 g[%r5170d+0x8] (0)
>509: %p5190 mov u32 %r5192 0x00000000 (0)
>510: union u32 %r5193 %r5191 %r5192 (0)
>511: add u32 %r5198 %r5166 0x00000010 (0)
>512: set u8 %p5199 gt u32 %r5198 c7[0x338] (0)
>513: not %p5199 ld  u32 %r5200 g[%r5170d+0xc] (0)
>514: %p5199 mov u32 %r5201 0x00000000 (0)
>515: union u32 %r5202 %r5200 %r5201 (0)
>516: add f32 %r5208 %r4929 neg %r5175 (0)
>517: add f32 %r5210 %r4930 neg %r5184 (0)
>518: add f32 %r5212 %r4931 neg %r5193 (0)
>519: add f32 %r5214 %r4932 neg %r5202 (0)
>520: mul f32 %r5215 %r5208 %r5208 (0)
>521: mad f32 %r5216 %r5210 %r5210 %r5215 (0)
>522: mad f32 %r5217 %r5212 %r5212 %r5216 (0)
>523: mad f32 %r5218 %r5214 %r5214 %r5217 (0)
>524: rsq f32 %r5220 %r5218 (0)
>525: rcp f32 %r5221 %r5220 (0)
>526: add f32 %r5224 neg %r5221 c0[0x20] (0)
>527: mul f32 %r5226 %r5224 0.350000 (0)
>528: mul f32 %r5228 %r5226 %r5220 (0)
>529: mul f32 %r5229 %r5228 %r5208 (0)
>530: mul f32 %r5230 %r5228 %r5210 (0)
>531: mul f32 %r5231 %r5228 %r5212 (0)
>532: mul f32 %r5232 %r5228 %r5214 (0)
>533: shl u32 %r6431 %r2703 0x00000004 (0)
>534: add u32 %r5234 %r6431 0x00000010 (0)
>535: add u64 %r5240d %r5234 c7[0x330] (0)
>536: add u32 %r5241 %r5234 0x00000004 (0)
>537: set u8 %p5242 gt u32 %r5241 c7[0x338] (0)
>538: not %p5242 ld  u32 %r5243 g[%r5240d+0x0] (0)
>539: %p5242 mov u32 %r5244 0x00000000 (0)
>540: union u32 %r5245 %r5243 %r5244 (0)
>541: add u32 %r5250 %r5234 0x00000008 (0)
>542: set u8 %p5251 gt u32 %r5250 c7[0x338] (0)
>543: not %p5251 ld  u32 %r5252 g[%r5240d+0x4] (0)
>544: %p5251 mov u32 %r5253 0x00000000 (0)
>545: union u32 %r5254 %r5252 %r5253 (0)
>546: add u32 %r5259 %r5234 0x0000000c (0)
>547: set u8 %p5260 gt u32 %r5259 c7[0x338] (0)
>548: not %p5260 ld  u32 %r5261 g[%r5240d+0x8] (0)
>549: %p5260 mov u32 %r5262 0x00000000 (0)
>550: union u32 %r5263 %r5261 %r5262 (0)
>551: add u32 %r5268 %r5234 0x00000010 (0)
>552: set u8 %p5269 gt u32 %r5268 c7[0x338] (0)
>553: not %p5269 ld  u32 %r5270 g[%r5240d+0xc] (0)
>554: %p5269 mov u32 %r5271 0x00000000 (0)
>555: union u32 %r5272 %r5270 %r5271 (0)
>556: add f32 %r5273 %r5245 %r5229 (0)
>557: add f32 %r5274 %r5254 %r5230 (0)
>558: add f32 %r5275 %r5263 %r5231 (0)
>559: add f32 %r5276 %r5272 %r5232 (0)
>560: not %p5242 st  u32 # g[%r5240d+0x0] %r5273 (0)
>561: not %p5251 st  u32 # g[%r5240d+0x4] %r5274 (0)
>562: not %p5260 st  u32 # g[%r5240d+0x8] %r5275 (0)
>563: not %p5269 st  u32 # g[%r5240d+0xc] %r5276 (0)
>564: not %p5172 ld  u32 %r5311 g[%r5170d+0x0] (0)
>565: %p5172 mov u32 %r5312 0x00000000 (0)
>566: union u32 %r5313 %r5311 %r5312 (0)
>567: not %p5181 ld  u32 %r5320 g[%r5170d+0x4] (0)
>568: %p5181 mov u32 %r5321 0x00000000 (0)
>569: union u32 %r5322 %r5320 %r5321 (0)
>570: not %p5190 ld  u32 %r5329 g[%r5170d+0x8] (0)
>571: %p5190 mov u32 %r5330 0x00000000 (0)
>572: union u32 %r5331 %r5329 %r5330 (0)
>573: not %p5199 ld  u32 %r5338 g[%r5170d+0xc] (0)
>574: %p5199 mov u32 %r5339 0x00000000 (0)
>575: union u32 %r5340 %r5338 %r5339 (0)
>576: add f32 %r5342 %r5313 neg %r5229 (0)
>577: add f32 %r5344 %r5322 neg %r5230 (0)
>578: add f32 %r5346 %r5331 neg %r5231 (0)
>579: add f32 %r5348 %r5340 neg %r5232 (0)
>580: not %p5172 st  u32 # g[%r5170d+0x0] %r5342 (0)
>581: not %p5181 st  u32 # g[%r5170d+0x4] %r5344 (0)
>582: not %p5190 st  u32 # g[%r5170d+0x8] %r5346 (0)
>583: not %p5199 st  u32 # g[%r5170d+0xc] %r5348 (0)
>584: membar (SUBOP:7) - # (0)
>585: add f32 %r5374 %r5148 neg %r5175 (0)
>586: add f32 %r5376 %r5149 neg %r5184 (0)
>587: add f32 %r5378 %r5150 neg %r5193 (0)
>588: add f32 %r5380 %r5151 neg %r5202 (0)
>589: mul f32 %r5381 %r5374 %r5374 (0)
>590: mad f32 %r5382 %r5376 %r5376 %r5381 (0)
>591: mad f32 %r5383 %r5378 %r5378 %r5382 (0)
>592: mad f32 %r5384 %r5380 %r5380 %r5383 (0)
>593: rsq f32 %r5386 %r5384 (0)
>594: rcp f32 %r5387 %r5386 (0)
>595: add f32 %r5390 neg %r5387 c0[0x20] (0)
>596: mul f32 %r5392 %r5390 0.350000 (0)
>597: mul f32 %r5394 %r5392 %r5386 (0)
>598: mul f32 %r5395 %r5394 %r5374 (0)
>599: mul f32 %r5396 %r5394 %r5376 (0)
>600: mul f32 %r5397 %r5394 %r5378 (0)
>601: mul f32 %r5398 %r5394 %r5380 (0)
>602: shl u32 %r5400 %r4934 0x00000004 (0)
>603: add u64 %r5406d %r5400 c7[0x330] (0)
>604: add u32 %r5407 %r5400 0x00000004 (0)
>605: set u8 %p5408 gt u32 %r5407 c7[0x338] (0)
>606: not %p5408 ld  u32 %r5409 g[%r5406d+0x0] (0)
>607: %p5408 mov u32 %r5410 0x00000000 (0)
>608: union u32 %r5411 %r5409 %r5410 (0)
>609: add u32 %r5416 %r5400 0x00000008 (0)
>610: set u8 %p5417 gt u32 %r5416 c7[0x338] (0)
>611: not %p5417 ld  u32 %r5418 g[%r5406d+0x4] (0)
>612: %p5417 mov u32 %r5419 0x00000000 (0)
>613: union u32 %r5420 %r5418 %r5419 (0)
>614: add u32 %r5425 %r5400 0x0000000c (0)
>615: set u8 %p5426 gt u32 %r5425 c7[0x338] (0)
>616: not %p5426 ld  u32 %r5427 g[%r5406d+0x8] (0)
>617: %p5426 mov u32 %r5428 0x00000000 (0)
>618: union u32 %r5429 %r5427 %r5428 (0)
>619: add u32 %r5434 %r5400 0x00000010 (0)
>620: set u8 %p5435 gt u32 %r5434 c7[0x338] (0)
>621: not %p5435 ld  u32 %r5436 g[%r5406d+0xc] (0)
>622: %p5435 mov u32 %r5437 0x00000000 (0)
>623: union u32 %r5438 %r5436 %r5437 (0)
>624: add f32 %r5439 %r5411 %r5395 (0)
>625: add f32 %r5440 %r5420 %r5396 (0)
>626: add f32 %r5441 %r5429 %r5397 (0)
>627: add f32 %r5442 %r5438 %r5398 (0)
>628: not %p5408 st  u32 # g[%r5406d+0x0] %r5439 (0)
>629: not %p5417 st  u32 # g[%r5406d+0x4] %r5440 (0)
>630: not %p5426 st  u32 # g[%r5406d+0x8] %r5441 (0)
>631: not %p5435 st  u32 # g[%r5406d+0xc] %r5442 (0)
>632: not %p5172 ld  u32 %r5477 g[%r5170d+0x0] (0)
>633: %p5172 mov u32 %r5478 0x00000000 (0)
>634: union u32 %r5479 %r5477 %r5478 (0)
>635: not %p5181 ld  u32 %r5486 g[%r5170d+0x4] (0)
>636: %p5181 mov u32 %r5487 0x00000000 (0)
>637: union u32 %r5488 %r5486 %r5487 (0)
>638: not %p5190 ld  u32 %r5495 g[%r5170d+0x8] (0)
>639: %p5190 mov u32 %r5496 0x00000000 (0)
>640: union u32 %r5497 %r5495 %r5496 (0)
>641: not %p5199 ld  u32 %r5504 g[%r5170d+0xc] (0)
>642: %p5199 mov u32 %r5505 0x00000000 (0)
>643: union u32 %r5506 %r5504 %r5505 (0)
>644: add f32 %r5508 %r5479 neg %r5395 (0)
>645: add f32 %r5510 %r5488 neg %r5396 (0)
>646: add f32 %r5512 %r5497 neg %r5397 (0)
>647: add f32 %r5514 %r5506 neg %r5398 (0)
>648: not %p5172 st  u32 # g[%r5170d+0x0] %r5508 (0)
>649: not %p5181 st  u32 # g[%r5170d+0x4] %r5510 (0)
>650: not %p5190 st  u32 # g[%r5170d+0x8] %r5512 (0)
>651: not %p5199 st  u32 # g[%r5170d+0xc] %r5514 (0)
>652: membar (SUBOP:7) - # (0)
>653: add f32 %r5540 %r4679 neg %r5175 (0)
>654: add f32 %r5542 %r4688 neg %r5184 (0)
>655: add f32 %r5544 %r4697 neg %r5193 (0)
>656: add f32 %r5546 %r4706 neg %r5202 (0)
>657: mul f32 %r5547 %r5540 %r5540 (0)
>658: mad f32 %r5548 %r5542 %r5542 %r5547 (0)
>659: mad f32 %r5549 %r5544 %r5544 %r5548 (0)
>660: mad f32 %r5550 %r5546 %r5546 %r5549 (0)
>661: rsq f32 %r5552 %r5550 (0)
>662: rcp f32 %r5553 %r5552 (0)
>663: add f32 %r5556 neg %r5553 c0[0x30] (0)
>664: mul f32 %r5558 %r5556 0.350000 (0)
>665: mul f32 %r5560 %r5558 %r5552 (0)
>666: mul f32 %r5561 %r5560 %r5540 (0)
>667: mul f32 %r5562 %r5560 %r5542 (0)
>668: mul f32 %r5563 %r5560 %r5544 (0)
>669: mul f32 %r5564 %r5560 %r5546 (0)
>670: add u64 %r5572d %r6431 c7[0x330] (0)
>671: add u32 %r5573 %r6431 0x00000004 (0)
>672: set u8 %p5574 gt u32 %r5573 c7[0x338] (0)
>673: not %p5574 ld  u32 %r5575 g[%r5572d+0x0] (0)
>674: %p5574 mov u32 %r5576 0x00000000 (0)
>675: union u32 %r5577 %r5575 %r5576 (0)
>676: add u32 %r5582 %r6431 0x00000008 (0)
>677: set u8 %p5583 gt u32 %r5582 c7[0x338] (0)
>678: not %p5583 ld  u32 %r5584 g[%r5572d+0x4] (0)
>679: %p5583 mov u32 %r5585 0x00000000 (0)
>680: union u32 %r5586 %r5584 %r5585 (0)
>681: add u32 %r5591 %r6431 0x0000000c (0)
>682: set u8 %p5592 gt u32 %r5591 c7[0x338] (0)
>683: not %p5592 ld  u32 %r5593 g[%r5572d+0x8] (0)
>684: %p5592 mov u32 %r5594 0x00000000 (0)
>685: union u32 %r5595 %r5593 %r5594 (0)
>686: set u8 %p5601 gt u32 %r5234 c7[0x338] (0)
>687: not %p5601 ld  u32 %r5602 g[%r5572d+0xc] (0)
>688: %p5601 mov u32 %r5603 0x00000000 (0)
>689: union u32 %r5604 %r5602 %r5603 (0)
>690: add f32 %r5605 %r5577 %r5561 (0)
>691: add f32 %r5606 %r5586 %r5562 (0)
>692: add f32 %r5607 %r5595 %r5563 (0)
>693: add f32 %r5608 %r5604 %r5564 (0)
>694: not %p5574 st  u32 # g[%r5572d+0x0] %r5605 (0)
>695: not %p5583 st  u32 # g[%r5572d+0x4] %r5606 (0)
>696: not %p5592 st  u32 # g[%r5572d+0x8] %r5607 (0)
>697: not %p5601 st  u32 # g[%r5572d+0xc] %r5608 (0)
>698: not %p5172 ld  u32 %r5643 g[%r5170d+0x0] (0)
>699: %p5172 mov u32 %r5644 0x00000000 (0)
>700: union u32 %r5645 %r5643 %r5644 (0)
>701: not %p5181 ld  u32 %r5652 g[%r5170d+0x4] (0)
>702: %p5181 mov u32 %r5653 0x00000000 (0)
>703: union u32 %r5654 %r5652 %r5653 (0)
>704: not %p5190 ld  u32 %r5661 g[%r5170d+0x8] (0)
>705: %p5190 mov u32 %r5662 0x00000000 (0)
>706: union u32 %r5663 %r5661 %r5662 (0)
>707: not %p5199 ld  u32 %r5670 g[%r5170d+0xc] (0)
>708: %p5199 mov u32 %r5671 0x00000000 (0)
>709: union u32 %r5672 %r5670 %r5671 (0)
>710: add f32 %r5674 %r5645 neg %r5561 (0)
>711: add f32 %r5676 %r5654 neg %r5562 (0)
>712: add f32 %r5678 %r5663 neg %r5563 (0)
>713: add f32 %r5680 %r5672 neg %r5564 (0)
>714: not %p5172 st  u32 # g[%r5170d+0x0] %r5674 (0)
>715: not %p5181 st  u32 # g[%r5170d+0x4] %r5676 (0)
>716: not %p5190 st  u32 # g[%r5170d+0x8] %r5678 (0)
>717: not %p5199 st  u32 # g[%r5170d+0xc] %r5680 (0)
>718: add f32 %r5706 %r4929 neg %r5148 (0)
>719: add f32 %r5708 %r4930 neg %r5149 (0)
>720: add f32 %r5710 %r4931 neg %r5150 (0)
>721: add f32 %r5712 %r4932 neg %r5151 (0)
>722: mul f32 %r5713 %r5706 %r5706 (0)
>723: mad f32 %r5714 %r5708 %r5708 %r5713 (0)
>724: mad f32 %r5715 %r5710 %r5710 %r5714 (0)
>725: mad f32 %r5716 %r5712 %r5712 %r5715 (0)
>726: rsq f32 %r5718 %r5716 (0)
>727: rcp f32 %r5719 %r5718 (0)
>728: add f32 %r5722 neg %r5719 c0[0x30] (0)
>729: mul f32 %r5724 %r5722 0.350000 (0)
>730: mul f32 %r5726 %r5724 %r5718 (0)
>731: mul f32 %r5727 %r5726 %r5706 (0)
>732: mul f32 %r5728 %r5726 %r5708 (0)
>733: mul f32 %r5729 %r5726 %r5710 (0)
>734: mul f32 %r5730 %r5726 %r5712 (0)
>735: not %p5242 ld  u32 %r5741 g[%r5240d+0x0] (0)
>736: %p5242 mov u32 %r5742 0x00000000 (0)
>737: union u32 %r5743 %r5741 %r5742 (0)
>738: not %p5251 ld  u32 %r5750 g[%r5240d+0x4] (0)
>739: %p5251 mov u32 %r5751 0x00000000 (0)
>740: union u32 %r5752 %r5750 %r5751 (0)
>741: not %p5260 ld  u32 %r5759 g[%r5240d+0x8] (0)
>742: %p5260 mov u32 %r5760 0x00000000 (0)
>743: union u32 %r5761 %r5759 %r5760 (0)
>744: not %p5269 ld  u32 %r5768 g[%r5240d+0xc] (0)
>745: %p5269 mov u32 %r5769 0x00000000 (0)
>746: union u32 %r5770 %r5768 %r5769 (0)
>747: add f32 %r5771 %r5743 %r5727 (0)
>748: add f32 %r5772 %r5752 %r5728 (0)
>749: add f32 %r5773 %r5761 %r5729 (0)
>750: add f32 %r5774 %r5770 %r5730 (0)
>751: not %p5242 st  u32 # g[%r5240d+0x0] %r5771 (0)
>752: not %p5251 st  u32 # g[%r5240d+0x4] %r5772 (0)
>753: not %p5260 st  u32 # g[%r5240d+0x8] %r5773 (0)
>754: not %p5269 st  u32 # g[%r5240d+0xc] %r5774 (0)
>755: not %p5408 ld  u32 %r5809 g[%r5406d+0x0] (0)
>756: %p5408 mov u32 %r5810 0x00000000 (0)
>757: union u32 %r5811 %r5809 %r5810 (0)
>758: not %p5417 ld  u32 %r5818 g[%r5406d+0x4] (0)
>759: %p5417 mov u32 %r5819 0x00000000 (0)
>760: union u32 %r5820 %r5818 %r5819 (0)
>761: not %p5426 ld  u32 %r5827 g[%r5406d+0x8] (0)
>762: %p5426 mov u32 %r5828 0x00000000 (0)
>763: union u32 %r5829 %r5827 %r5828 (0)
>764: not %p5435 ld  u32 %r5836 g[%r5406d+0xc] (0)
>765: %p5435 mov u32 %r5837 0x00000000 (0)
>766: union u32 %r5838 %r5836 %r5837 (0)
>767: add f32 %r5840 %r5811 neg %r5727 (0)
>768: add f32 %r5842 %r5820 neg %r5728 (0)
>769: add f32 %r5844 %r5829 neg %r5729 (0)
>770: add f32 %r5846 %r5838 neg %r5730 (0)
>771: not %p5408 st  u32 # g[%r5406d+0x0] %r5840 (0)
>772: not %p5417 st  u32 # g[%r5406d+0x4] %r5842 (0)
>773: not %p5426 st  u32 # g[%r5406d+0x8] %r5844 (0)
>774: not %p5435 st  u32 # g[%r5406d+0xc] %r5846 (0)
>775: membar (SUBOP:7) - # (0)
>776: bra BB:24 (0)
>BB:24 (2 instructions) - idom = BB:22, df = { BB:35 }
> -> BB:35 (forward)
>777: join (0)
>778: bra BB:35 (0)
>BB:25 (12 instructions) - idom = BB:17, df = { BB:35 }
> -> BB:29 (tree)
> -> BB:26 (tree)
>779: mov u32 %r5884 0x00000002 (0)
>780: mov u32 $r0 %r2715 (0)
>781: mov u32 $r1 %r5884 (0)
>782: call abs BUILTIN:1 (0)
>783: mov u32 %r5885 $r1 (0)
>784: nop - { $r0 $r2d } (0)
>785: nop - $p0q (0)
>786: set u8 %p6421 eq u32 %r4003 0x00000001 (0)
>787: set and u8 %p6422 eq u32 %r5885 0x00000001 %p6421 (0)
>788: joinat BB:34 (0)
>789: set and u8 %p5892 eq u32 %r2717 0x00000000 %p6422 (0)
>790: not %p5892 bra BB:29 (0)
>BB:26 (4 instructions) - idom = BB:25, df = { BB:34 }
> -> BB:28 (forward)
> -> BB:27 (tree)
>791: add u32 %r5894 %r2703 0x00000001 (0)
>792: joinat BB:28 (0)
>793: set u8 %p5897 lt s32 %r5894 c0[0x0] (0)
>794: not %p5897 bra BB:28 (0)
>BB:27 (102 instructions) - idom = BB:26, df = { BB:28 }
> -> BB:28 (forward)
>795: shl u32 %r5899 %r2703 0x00000004 (0)
>796: add u64 %r5903d %r5899 c7[0x330] (0)
>797: add u32 %r5904 %r5899 0x00000004 (0)
>798: set u8 %p5905 gt u32 %r5904 c7[0x338] (0)
>799: not %p5905 ld  u32 %r5906 g[%r5903d+0x0] (0)
>800: %p5905 mov u32 %r5907 0x00000000 (0)
>801: union u32 %r5908 %r5906 %r5907 (0)
>802: add u32 %r5913 %r5899 0x00000008 (0)
>803: set u8 %p5914 gt u32 %r5913 c7[0x338] (0)
>804: not %p5914 ld  u32 %r5915 g[%r5903d+0x4] (0)
>805: %p5914 mov u32 %r5916 0x00000000 (0)
>806: union u32 %r5917 %r5915 %r5916 (0)
>807: add u32 %r5922 %r5899 0x0000000c (0)
>808: set u8 %p5923 gt u32 %r5922 c7[0x338] (0)
>809: not %p5923 ld  u32 %r5924 g[%r5903d+0x8] (0)
>810: %p5923 mov u32 %r5925 0x00000000 (0)
>811: union u32 %r5926 %r5924 %r5925 (0)
>812: add u32 %r5931 %r5899 0x00000010 (0)
>813: set u8 %p5932 gt u32 %r5931 c7[0x338] (0)
>814: not %p5932 ld  u32 %r5933 g[%r5903d+0xc] (0)
>815: %p5932 mov u32 %r5934 0x00000000 (0)
>816: union u32 %r5935 %r5933 %r5934 (0)
>817: add u64 %r5945d %r5931 c7[0x330] (0)
>818: add u32 %r5946 %r5931 0x00000004 (0)
>819: set u8 %p5947 gt u32 %r5946 c7[0x338] (0)
>820: not %p5947 ld  u32 %r5948 g[%r5945d+0x0] (0)
>821: %p5947 mov u32 %r5949 0x00000000 (0)
>822: union u32 %r5950 %r5948 %r5949 (0)
>823: add u32 %r5955 %r5931 0x00000008 (0)
>824: set u8 %p5956 gt u32 %r5955 c7[0x338] (0)
>825: not %p5956 ld  u32 %r5957 g[%r5945d+0x4] (0)
>826: %p5956 mov u32 %r5958 0x00000000 (0)
>827: union u32 %r5959 %r5957 %r5958 (0)
>828: add u32 %r5964 %r5931 0x0000000c (0)
>829: set u8 %p5965 gt u32 %r5964 c7[0x338] (0)
>830: not %p5965 ld  u32 %r5966 g[%r5945d+0x8] (0)
>831: %p5965 mov u32 %r5967 0x00000000 (0)
>832: union u32 %r5968 %r5966 %r5967 (0)
>833: add u32 %r5973 %r5931 0x00000010 (0)
>834: set u8 %p5974 gt u32 %r5973 c7[0x338] (0)
>835: not %p5974 ld  u32 %r5975 g[%r5945d+0xc] (0)
>836: %p5974 mov u32 %r5976 0x00000000 (0)
>837: union u32 %r5977 %r5975 %r5976 (0)
>838: add f32 %r5979 %r5908 neg %r5950 (0)
>839: add f32 %r5981 %r5917 neg %r5959 (0)
>840: add f32 %r5983 %r5926 neg %r5968 (0)
>841: add f32 %r5985 %r5935 neg %r5977 (0)
>842: mul f32 %r5986 %r5979 %r5979 (0)
>843: mad f32 %r5987 %r5981 %r5981 %r5986 (0)
>844: mad f32 %r5988 %r5983 %r5983 %r5987 (0)
>845: mad f32 %r5989 %r5985 %r5985 %r5988 (0)
>846: rsq f32 %r5991 %r5989 (0)
>847: rcp f32 %r5992 %r5991 (0)
>848: add f32 %r5995 neg %r5992 c0[0x20] (0)
>849: mul f32 %r5997 %r5995 0.350000 (0)
>850: mul f32 %r5999 %r5997 %r5991 (0)
>851: mul f32 %r6000 %r5999 %r5979 (0)
>852: mul f32 %r6001 %r5999 %r5981 (0)
>853: mul f32 %r6002 %r5999 %r5983 (0)
>854: mul f32 %r6003 %r5999 %r5985 (0)
>855: not %p5905 ld  u32 %r6014 g[%r5903d+0x0] (0)
>856: %p5905 mov u32 %r6015 0x00000000 (0)
>857: union u32 %r6016 %r6014 %r6015 (0)
>858: not %p5914 ld  u32 %r6023 g[%r5903d+0x4] (0)
>859: %p5914 mov u32 %r6024 0x00000000 (0)
>860: union u32 %r6025 %r6023 %r6024 (0)
>861: not %p5923 ld  u32 %r6032 g[%r5903d+0x8] (0)
>862: %p5923 mov u32 %r6033 0x00000000 (0)
>863: union u32 %r6034 %r6032 %r6033 (0)
>864: not %p5932 ld  u32 %r6041 g[%r5903d+0xc] (0)
>865: %p5932 mov u32 %r6042 0x00000000 (0)
>866: union u32 %r6043 %r6041 %r6042 (0)
>867: add f32 %r6044 %r6016 %r6000 (0)
>868: add f32 %r6045 %r6025 %r6001 (0)
>869: add f32 %r6046 %r6034 %r6002 (0)
>870: add f32 %r6047 %r6043 %r6003 (0)
>871: not %p5905 st  u32 # g[%r5903d+0x0] %r6044 (0)
>872: not %p5914 st  u32 # g[%r5903d+0x4] %r6045 (0)
>873: not %p5923 st  u32 # g[%r5903d+0x8] %r6046 (0)
>874: not %p5932 st  u32 # g[%r5903d+0xc] %r6047 (0)
>875: not %p5947 ld  u32 %r6082 g[%r5945d+0x0] (0)
>876: %p5947 mov u32 %r6083 0x00000000 (0)
>877: union u32 %r6084 %r6082 %r6083 (0)
>878: not %p5956 ld  u32 %r6091 g[%r5945d+0x4] (0)
>879: %p5956 mov u32 %r6092 0x00000000 (0)
>880: union u32 %r6093 %r6091 %r6092 (0)
>881: not %p5965 ld  u32 %r6100 g[%r5945d+0x8] (0)
>882: %p5965 mov u32 %r6101 0x00000000 (0)
>883: union u32 %r6102 %r6100 %r6101 (0)
>884: not %p5974 ld  u32 %r6109 g[%r5945d+0xc] (0)
>885: %p5974 mov u32 %r6110 0x00000000 (0)
>886: union u32 %r6111 %r6109 %r6110 (0)
>887: add f32 %r6113 %r6084 neg %r6000 (0)
>888: add f32 %r6115 %r6093 neg %r6001 (0)
>889: add f32 %r6117 %r6102 neg %r6002 (0)
>890: add f32 %r6119 %r6111 neg %r6003 (0)
>891: not %p5947 st  u32 # g[%r5945d+0x0] %r6113 (0)
>892: not %p5956 st  u32 # g[%r5945d+0x4] %r6115 (0)
>893: not %p5965 st  u32 # g[%r5945d+0x8] %r6117 (0)
>894: not %p5974 st  u32 # g[%r5945d+0xc] %r6119 (0)
>895: membar (SUBOP:7) - # (0)
>896: bra BB:28 (0)
>BB:28 (2 instructions) - idom = BB:26, df = { BB:34 }
> -> BB:34 (forward)
>897: join (0)
>898: bra BB:34 (0)
>BB:29 (12 instructions) - idom = BB:25, df = { BB:34 }
> -> BB:33 (forward)
> -> BB:30 (tree)
>899: mov u32 %r6146 0x00000002 (0)
>900: mov u32 $r0 %r2717 (0)
>901: mov u32 $r1 %r6146 (0)
>902: call abs BUILTIN:1 (0)
>903: mov u32 %r6147 $r1 (0)
>904: nop - { $r0 $r2d } (0)
>905: nop - $p0q (0)
>906: set u8 %p6423 eq u32 %r4003 0x00000001 (0)
>907: set and u8 %p6424 eq u32 %r6147 0x00000001 %p6423 (0)
>908: joinat BB:33 (0)
>909: set and u8 %p6154 eq u32 %r2715 0x00000000 %p6424 (0)
>910: not %p6154 bra BB:33 (0)
>BB:30 (6 instructions) - idom = BB:29, df = { BB:33 }
> -> BB:32 (forward)
> -> BB:31 (tree)
>911: ld  u32 %r6155 c0[0x0] (0)
>912: add u32 %r6156 %r2703 c0[0x0] (0)
>913: mul u32 %r6159 %r6155 c0[0x0] (0)
>914: joinat BB:32 (0)
>915: set u8 %p6161 lt s32 %r6156 %r6159 (0)
>916: not %p6161 bra BB:32 (0)
>BB:31 (103 instructions) - idom = BB:30, df = { BB:32 }
> -> BB:32 (forward)
>917: shl u32 %r6163 %r2703 0x00000004 (0)
>918: add u64 %r6167d %r6163 c7[0x330] (0)
>919: add u32 %r6168 %r6163 0x00000004 (0)
>920: set u8 %p6169 gt u32 %r6168 c7[0x338] (0)
>921: not %p6169 ld  u32 %r6170 g[%r6167d+0x0] (0)
>922: %p6169 mov u32 %r6171 0x00000000 (0)
>923: union u32 %r6172 %r6170 %r6171 (0)
>924: add u32 %r6177 %r6163 0x00000008 (0)
>925: set u8 %p6178 gt u32 %r6177 c7[0x338] (0)
>926: not %p6178 ld  u32 %r6179 g[%r6167d+0x4] (0)
>927: %p6178 mov u32 %r6180 0x00000000 (0)
>928: union u32 %r6181 %r6179 %r6180 (0)
>929: add u32 %r6186 %r6163 0x0000000c (0)
>930: set u8 %p6187 gt u32 %r6186 c7[0x338] (0)
>931: not %p6187 ld  u32 %r6188 g[%r6167d+0x8] (0)
>932: %p6187 mov u32 %r6189 0x00000000 (0)
>933: union u32 %r6190 %r6188 %r6189 (0)
>934: add u32 %r6195 %r6163 0x00000010 (0)
>935: set u8 %p6196 gt u32 %r6195 c7[0x338] (0)
>936: not %p6196 ld  u32 %r6197 g[%r6167d+0xc] (0)
>937: %p6196 mov u32 %r6198 0x00000000 (0)
>938: union u32 %r6199 %r6197 %r6198 (0)
>939: shl u32 %r6205 %r6156 0x00000004 (0)
>940: add u64 %r6209d %r6205 c7[0x330] (0)
>941: add u32 %r6210 %r6205 0x00000004 (0)
>942: set u8 %p6211 gt u32 %r6210 c7[0x338] (0)
>943: not %p6211 ld  u32 %r6212 g[%r6209d+0x0] (0)
>944: %p6211 mov u32 %r6213 0x00000000 (0)
>945: union u32 %r6214 %r6212 %r6213 (0)
>946: add u32 %r6219 %r6205 0x00000008 (0)
>947: set u8 %p6220 gt u32 %r6219 c7[0x338] (0)
>948: not %p6220 ld  u32 %r6221 g[%r6209d+0x4] (0)
>949: %p6220 mov u32 %r6222 0x00000000 (0)
>950: union u32 %r6223 %r6221 %r6222 (0)
>951: add u32 %r6228 %r6205 0x0000000c (0)
>952: set u8 %p6229 gt u32 %r6228 c7[0x338] (0)
>953: not %p6229 ld  u32 %r6230 g[%r6209d+0x8] (0)
>954: %p6229 mov u32 %r6231 0x00000000 (0)
>955: union u32 %r6232 %r6230 %r6231 (0)
>956: add u32 %r6237 %r6205 0x00000010 (0)
>957: set u8 %p6238 gt u32 %r6237 c7[0x338] (0)
>958: not %p6238 ld  u32 %r6239 g[%r6209d+0xc] (0)
>959: %p6238 mov u32 %r6240 0x00000000 (0)
>960: union u32 %r6241 %r6239 %r6240 (0)
>961: add f32 %r6243 %r6172 neg %r6214 (0)
>962: add f32 %r6245 %r6181 neg %r6223 (0)
>963: add f32 %r6247 %r6190 neg %r6232 (0)
>964: add f32 %r6249 %r6199 neg %r6241 (0)
>965: mul f32 %r6250 %r6243 %r6243 (0)
>966: mad f32 %r6251 %r6245 %r6245 %r6250 (0)
>967: mad f32 %r6252 %r6247 %r6247 %r6251 (0)
>968: mad f32 %r6253 %r6249 %r6249 %r6252 (0)
>969: rsq f32 %r6255 %r6253 (0)
>970: rcp f32 %r6256 %r6255 (0)
>971: add f32 %r6259 neg %r6256 c0[0x20] (0)
>972: mul f32 %r6261 %r6259 0.350000 (0)
>973: mul f32 %r6263 %r6261 %r6255 (0)
>974: mul f32 %r6264 %r6263 %r6243 (0)
>975: mul f32 %r6265 %r6263 %r6245 (0)
>976: mul f32 %r6266 %r6263 %r6247 (0)
>977: mul f32 %r6267 %r6263 %r6249 (0)
>978: not %p6169 ld  u32 %r6278 g[%r6167d+0x0] (0)
>979: %p6169 mov u32 %r6279 0x00000000 (0)
>980: union u32 %r6280 %r6278 %r6279 (0)
>981: not %p6178 ld  u32 %r6287 g[%r6167d+0x4] (0)
>982: %p6178 mov u32 %r6288 0x00000000 (0)
>983: union u32 %r6289 %r6287 %r6288 (0)
>984: not %p6187 ld  u32 %r6296 g[%r6167d+0x8] (0)
>985: %p6187 mov u32 %r6297 0x00000000 (0)
>986: union u32 %r6298 %r6296 %r6297 (0)
>987: not %p6196 ld  u32 %r6305 g[%r6167d+0xc] (0)
>988: %p6196 mov u32 %r6306 0x00000000 (0)
>989: union u32 %r6307 %r6305 %r6306 (0)
>990: add f32 %r6308 %r6280 %r6264 (0)
>991: add f32 %r6309 %r6289 %r6265 (0)
>992: add f32 %r6310 %r6298 %r6266 (0)
>993: add f32 %r6311 %r6307 %r6267 (0)
>994: not %p6169 st  u32 # g[%r6167d+0x0] %r6308 (0)
>995: not %p6178 st  u32 # g[%r6167d+0x4] %r6309 (0)
>996: not %p6187 st  u32 # g[%r6167d+0x8] %r6310 (0)
>997: not %p6196 st  u32 # g[%r6167d+0xc] %r6311 (0)
>998: not %p6211 ld  u32 %r6346 g[%r6209d+0x0] (0)
>999: %p6211 mov u32 %r6347 0x00000000 (0)
>1000: union u32 %r6348 %r6346 %r6347 (0)
>1001: not %p6220 ld  u32 %r6355 g[%r6209d+0x4] (0)
>1002: %p6220 mov u32 %r6356 0x00000000 (0)
>1003: union u32 %r6357 %r6355 %r6356 (0)
>1004: not %p6229 ld  u32 %r6364 g[%r6209d+0x8] (0)
>1005: %p6229 mov u32 %r6365 0x00000000 (0)
>1006: union u32 %r6366 %r6364 %r6365 (0)
>1007: not %p6238 ld  u32 %r6373 g[%r6209d+0xc] (0)
>1008: %p6238 mov u32 %r6374 0x00000000 (0)
>1009: union u32 %r6375 %r6373 %r6374 (0)
>1010: add f32 %r6377 %r6348 neg %r6264 (0)
>1011: add f32 %r6379 %r6357 neg %r6265 (0)
>1012: add f32 %r6381 %r6366 neg %r6266 (0)
>1013: add f32 %r6383 %r6375 neg %r6267 (0)
>1014: not %p6211 st  u32 # g[%r6209d+0x0] %r6377 (0)
>1015: not %p6220 st  u32 # g[%r6209d+0x4] %r6379 (0)
>1016: not %p6229 st  u32 # g[%r6209d+0x8] %r6381 (0)
>1017: not %p6238 st  u32 # g[%r6209d+0xc] %r6383 (0)
>1018: membar (SUBOP:7) - # (0)
>1019: bra BB:32 (0)
>BB:32 (2 instructions) - idom = BB:30, df = { BB:33 }
> -> BB:33 (forward)
>1020: join (0)
>1021: bra BB:33 (0)
>BB:33 (2 instructions) - idom = BB:29, df = { BB:34 }
> -> BB:34 (forward)
>1022: join (0)
>1023: bra BB:34 (0)
>BB:34 (2 instructions) - idom = BB:25, df = { BB:35 }
> -> BB:35 (forward)
>1024: join (0)
>1025: bra BB:35 (0)
>BB:35 (12 instructions) - idom = BB:17, df = { BB:14 }
> -> BB:14 (back)
>1026: phi u32 %r5871 %r4929 %r4004 (0)
>1027: phi u32 %r5872 %r4930 %r4005 (0)
>1028: phi u32 %r5873 %r4931 %r4006 (0)
>1029: phi u32 %r5874 %r4932 %r4007 (0)
>1030: phi u32 %r5875 %r5148 %r4008 (0)
>1031: phi u32 %r5876 %r5149 %r4009 (0)
>1032: phi u32 %r5877 %r5150 %r4010 (0)
>1033: phi u32 %r5878 %r5151 %r4011 (0)
>1034: join (0)
>1035: bar u32 # 0x00000000 0x00000000 (0)
>1036: add u32 %r5880 %r4003 0x00000001 (0)
>1037: cont BB:14 (0)
>BB:15 (2 instructions) - idom = BB:16, df = { BB:10 }
> -> BB:36 (tree)
>1038: mov u32 %r4015 0x00000000 (0)
>1039: prebreak BB:37 (0)
>BB:36 (4 instructions) - idom = BB:15, df = { BB:10 BB:36 }
> -> BB:39 (forward)
> -> BB:38 (tree)
>1040: phi u32 %r4017 %r4659 %r4015 (0)
>1041: precont BB:36 (0)
>1042: set u8 %p4020 ge s32 %r4017 2 (0)
>1043: not %p4020 bra BB:39 (0)
>BB:38 (1 instructions) - idom = BB:36, df = { BB:10 }
> -> BB:37 (cross)
>1044: break BB:37 (0)
>BB:39 (18 instructions) - idom = BB:36, df = { BB:36 }
> -> BB:43 (forward)
> -> BB:40 (tree)
>1045: mov u32 %r4135 0x00000002 (0)
>1046: mov u32 $r0 %r2717 (0)
>1047: mov u32 $r1 %r4135 (0)
>1048: call abs BUILTIN:1 (0)
>1049: mov u32 %r4136 $r1 (0)
>1050: nop - { $r0 $r2d } (0)
>1051: nop - $p0q (0)
>1052: add u32 %r4139 %r2715 0x00000001 (0)
>1053: mov u32 $r0 %r4139 (0)
>1054: mov u32 $r1 %r4135 (0)
>1055: call abs BUILTIN:1 (0)
>1056: mov u32 %r4141 $r1 (0)
>1057: nop - { $r0 $r2d } (0)
>1058: nop - $p0q (0)
>1059: set u8 %p6426 eq u32 %r4136 %r4017 (0)
>1060: joinat BB:43 (0)
>1061: set and u8 %p4144 eq u32 %r4141 %r4017 %p6426 (0)
>1062: not %p4144 bra BB:43 (0)
>BB:40 (37 instructions) - idom = BB:39, df = { BB:43 }
> -> BB:42 (forward)
> -> BB:41 (tree)
>1063: shl u32 %r4146 %r2703 0x00000004 (0)
>1064: add u64 %r4150d %r4146 c7[0x330] (0)
>1065: add u32 %r4151 %r4146 0x00000004 (0)
>1066: set u8 %p4152 gt u32 %r4151 c7[0x338] (0)
>1067: not %p4152 ld  u32 %r4153 g[%r4150d+0x0] (0)
>1068: %p4152 mov u32 %r4154 0x00000000 (0)
>1069: union u32 %r4155 %r4153 %r4154 (0)
>1070: add u32 %r4160 %r4146 0x00000008 (0)
>1071: set u8 %p4161 gt u32 %r4160 c7[0x338] (0)
>1072: not %p4161 ld  u32 %r4162 g[%r4150d+0x4] (0)
>1073: %p4161 mov u32 %r4163 0x00000000 (0)
>1074: union u32 %r4164 %r4162 %r4163 (0)
>1075: add u32 %r4169 %r4146 0x0000000c (0)
>1076: set u8 %p4170 gt u32 %r4169 c7[0x338] (0)
>1077: not %p4170 ld  u32 %r4171 g[%r4150d+0x8] (0)
>1078: %p4170 mov u32 %r4172 0x00000000 (0)
>1079: union u32 %r4173 %r4171 %r4172 (0)
>1080: add u32 %r4178 %r4146 0x00000010 (0)
>1081: set u8 %p4179 gt u32 %r4178 c7[0x338] (0)
>1082: not %p4179 ld  u32 %r4180 g[%r4150d+0xc] (0)
>1083: %p4179 mov u32 %r4181 0x00000000 (0)
>1084: union u32 %r4182 %r4180 %r4181 (0)
>1085: add u32 %r4188 %r2703 0x00000001 (0)
>1086: ld  u32 %r4189 c0[0x0] (0)
>1087: add u32 %r4190 %r2703 c0[0x0] (0)
>1088: add u32 %r4194 %r4188 c0[0x0] (0)
>1089: mul u32 %r4197 %r4189 c0[0x0] (0)
>1090: mov u32 $r0 %r4194 (0)
>1091: mov u32 $r1 %r4189 (0)
>1092: call abs BUILTIN:1 (0)
>1093: mov u32 %r4200 $r1 (0)
>1094: nop - { $r0 $r2d } (0)
>1095: nop - $p0q (0)
>1096: set u8 %p6427 lt s32 %r4194 %r4197 (0)
>1097: joinat BB:42 (0)
>1098: set and u8 %p4203 lt s32 %r2715 %r4200 %p6427 (0)
>1099: not %p4203 bra BB:42 (0)
>BB:41 (191 instructions) - idom = BB:40, df = { BB:42 }
> -> BB:42 (forward)
>1100: shl u32 %r6435 %r2703 0x00000004 (0)
>1101: add u32 %r4205 %r6435 0x00000010 (0)
>1102: add u64 %r4209d %r4205 c7[0x330] (0)
>1103: add u32 %r4210 %r4205 0x00000004 (0)
>1104: set u8 %p4211 gt u32 %r4210 c7[0x338] (0)
>1105: not %p4211 ld  u32 %r4212 g[%r4209d+0x0] (0)
>1106: %p4211 mov u32 %r4213 0x00000000 (0)
>1107: union u32 %r4214 %r4212 %r4213 (0)
>1108: add u32 %r4219 %r4205 0x00000008 (0)
>1109: set u8 %p4220 gt u32 %r4219 c7[0x338] (0)
>1110: not %p4220 ld  u32 %r4221 g[%r4209d+0x4] (0)
>1111: %p4220 mov u32 %r4222 0x00000000 (0)
>1112: union u32 %r4223 %r4221 %r4222 (0)
>1113: add u32 %r4228 %r4205 0x0000000c (0)
>1114: set u8 %p4229 gt u32 %r4228 c7[0x338] (0)
>1115: not %p4229 ld  u32 %r4230 g[%r4209d+0x8] (0)
>1116: %p4229 mov u32 %r4231 0x00000000 (0)
>1117: union u32 %r4232 %r4230 %r4231 (0)
>1118: add u32 %r4237 %r4205 0x00000010 (0)
>1119: set u8 %p4238 gt u32 %r4237 c7[0x338] (0)
>1120: not %p4238 ld  u32 %r4239 g[%r4209d+0xc] (0)
>1121: %p4238 mov u32 %r4240 0x00000000 (0)
>1122: union u32 %r4241 %r4239 %r4240 (0)
>1123: shl u32 %r4247 %r4190 0x00000004 (0)
>1124: add u64 %r4251d %r4247 c7[0x330] (0)
>1125: add u32 %r4252 %r4247 0x00000004 (0)
>1126: set u8 %p4253 gt u32 %r4252 c7[0x338] (0)
>1127: not %p4253 ld  u32 %r4254 g[%r4251d+0x0] (0)
>1128: %p4253 mov u32 %r4255 0x00000000 (0)
>1129: union u32 %r4256 %r4254 %r4255 (0)
>1130: add u32 %r4261 %r4247 0x00000008 (0)
>1131: set u8 %p4262 gt u32 %r4261 c7[0x338] (0)
>1132: not %p4262 ld  u32 %r4263 g[%r4251d+0x4] (0)
>1133: %p4262 mov u32 %r4264 0x00000000 (0)
>1134: union u32 %r4265 %r4263 %r4264 (0)
>1135: add u32 %r4270 %r4247 0x0000000c (0)
>1136: set u8 %p4271 gt u32 %r4270 c7[0x338] (0)
>1137: not %p4271 ld  u32 %r4272 g[%r4251d+0x8] (0)
>1138: %p4271 mov u32 %r4273 0x00000000 (0)
>1139: union u32 %r4274 %r4272 %r4273 (0)
>1140: add u32 %r4279 %r4247 0x00000010 (0)
>1141: set u8 %p4280 gt u32 %r4279 c7[0x338] (0)
>1142: not %p4280 ld  u32 %r4281 g[%r4251d+0xc] (0)
>1143: %p4280 mov u32 %r4282 0x00000000 (0)
>1144: union u32 %r4283 %r4281 %r4282 (0)
>1145: shl u32 %r4289 %r4194 0x00000004 (0)
>1146: add u64 %r4293d %r4289 c7[0x330] (0)
>1147: add u32 %r4294 %r4289 0x00000004 (0)
>1148: set u8 %p4295 gt u32 %r4294 c7[0x338] (0)
>1149: not %p4295 ld  u32 %r4296 g[%r4293d+0x0] (0)
>1150: %p4295 mov u32 %r4297 0x00000000 (0)
>1151: union u32 %r4298 %r4296 %r4297 (0)
>1152: add u32 %r4303 %r4289 0x00000008 (0)
>1153: set u8 %p4304 gt u32 %r4303 c7[0x338] (0)
>1154: not %p4304 ld  u32 %r4305 g[%r4293d+0x4] (0)
>1155: %p4304 mov u32 %r4306 0x00000000 (0)
>1156: union u32 %r4307 %r4305 %r4306 (0)
>1157: add u32 %r4312 %r4289 0x0000000c (0)
>1158: set u8 %p4313 gt u32 %r4312 c7[0x338] (0)
>1159: not %p4313 ld  u32 %r4314 g[%r4293d+0x8] (0)
>1160: %p4313 mov u32 %r4315 0x00000000 (0)
>1161: union u32 %r4316 %r4314 %r4315 (0)
>1162: add u32 %r4321 %r4289 0x00000010 (0)
>1163: set u8 %p4322 gt u32 %r4321 c7[0x338] (0)
>1164: not %p4322 ld  u32 %r4323 g[%r4293d+0xc] (0)
>1165: %p4322 mov u32 %r4324 0x00000000 (0)
>1166: union u32 %r4325 %r4323 %r4324 (0)
>1167: add f32 %r4327 %r4155 neg %r4298 (0)
>1168: add f32 %r4329 %r4164 neg %r4307 (0)
>1169: add f32 %r4331 %r4173 neg %r4316 (0)
>1170: add f32 %r4333 %r4182 neg %r4325 (0)
>1171: mul f32 %r4334 %r4327 %r4327 (0)
>1172: mad f32 %r4335 %r4329 %r4329 %r4334 (0)
>1173: mad f32 %r4336 %r4331 %r4331 %r4335 (0)
>1174: mad f32 %r4337 %r4333 %r4333 %r4336 (0)
>1175: rsq f32 %r4339 %r4337 (0)
>1176: rcp f32 %r4340 %r4339 (0)
>1177: add f32 %r4343 neg %r4340 c0[0x30] (0)
>1178: mul f32 %r4345 %r4343 0.350000 (0)
>1179: mul f32 %r4347 %r4345 %r4339 (0)
>1180: mul f32 %r4348 %r4347 %r4327 (0)
>1181: mul f32 %r4349 %r4347 %r4329 (0)
>1182: mul f32 %r4350 %r4347 %r4331 (0)
>1183: mul f32 %r4351 %r4347 %r4333 (0)
>1184: add u64 %r4359d %r6435 c7[0x330] (0)
>1185: add u32 %r4360 %r6435 0x00000004 (0)
>1186: set u8 %p4361 gt u32 %r4360 c7[0x338] (0)
>1187: not %p4361 ld  u32 %r4362 g[%r4359d+0x0] (0)
>1188: %p4361 mov u32 %r4363 0x00000000 (0)
>1189: union u32 %r4364 %r4362 %r4363 (0)
>1190: add u32 %r4369 %r6435 0x00000008 (0)
>1191: set u8 %p4370 gt u32 %r4369 c7[0x338] (0)
>1192: not %p4370 ld  u32 %r4371 g[%r4359d+0x4] (0)
>1193: %p4370 mov u32 %r4372 0x00000000 (0)
>1194: union u32 %r4373 %r4371 %r4372 (0)
>1195: add u32 %r4378 %r6435 0x0000000c (0)
>1196: set u8 %p4379 gt u32 %r4378 c7[0x338] (0)
>1197: not %p4379 ld  u32 %r4380 g[%r4359d+0x8] (0)
>1198: %p4379 mov u32 %r4381 0x00000000 (0)
>1199: union u32 %r4382 %r4380 %r4381 (0)
>1200: set u8 %p4388 gt u32 %r4205 c7[0x338] (0)
>1201: not %p4388 ld  u32 %r4389 g[%r4359d+0xc] (0)
>1202: %p4388 mov u32 %r4390 0x00000000 (0)
>1203: union u32 %r4391 %r4389 %r4390 (0)
>1204: add f32 %r4392 %r4364 %r4348 (0)
>1205: add f32 %r4393 %r4373 %r4349 (0)
>1206: add f32 %r4394 %r4382 %r4350 (0)
>1207: add f32 %r4395 %r4391 %r4351 (0)
>1208: not %p4361 st  u32 # g[%r4359d+0x0] %r4392 (0)
>1209: not %p4370 st  u32 # g[%r4359d+0x4] %r4393 (0)
>1210: not %p4379 st  u32 # g[%r4359d+0x8] %r4394 (0)
>1211: not %p4388 st  u32 # g[%r4359d+0xc] %r4395 (0)
>1212: not %p4295 ld  u32 %r4430 g[%r4293d+0x0] (0)
>1213: %p4295 mov u32 %r4431 0x00000000 (0)
>1214: union u32 %r4432 %r4430 %r4431 (0)
>1215: not %p4304 ld  u32 %r4439 g[%r4293d+0x4] (0)
>1216: %p4304 mov u32 %r4440 0x00000000 (0)
>1217: union u32 %r4441 %r4439 %r4440 (0)
>1218: not %p4313 ld  u32 %r4448 g[%r4293d+0x8] (0)
>1219: %p4313 mov u32 %r4449 0x00000000 (0)
>1220: union u32 %r4450 %r4448 %r4449 (0)
>1221: not %p4322 ld  u32 %r4457 g[%r4293d+0xc] (0)
>1222: %p4322 mov u32 %r4458 0x00000000 (0)
>1223: union u32 %r4459 %r4457 %r4458 (0)
>1224: add f32 %r4461 %r4432 neg %r4348 (0)
>1225: add f32 %r4463 %r4441 neg %r4349 (0)
>1226: add f32 %r4465 %r4450 neg %r4350 (0)
>1227: add f32 %r4467 %r4459 neg %r4351 (0)
>1228: not %p4295 st  u32 # g[%r4293d+0x0] %r4461 (0)
>1229: not %p4304 st  u32 # g[%r4293d+0x4] %r4463 (0)
>1230: not %p4313 st  u32 # g[%r4293d+0x8] %r4465 (0)
>1231: not %p4322 st  u32 # g[%r4293d+0xc] %r4467 (0)
>1232: add f32 %r4493 %r4214 neg %r4256 (0)
>1233: add f32 %r4495 %r4223 neg %r4265 (0)
>1234: add f32 %r4497 %r4232 neg %r4274 (0)
>1235: add f32 %r4499 %r4241 neg %r4283 (0)
>1236: mul f32 %r4500 %r4493 %r4493 (0)
>1237: mad f32 %r4501 %r4495 %r4495 %r4500 (0)
>1238: mad f32 %r4502 %r4497 %r4497 %r4501 (0)
>1239: mad f32 %r4503 %r4499 %r4499 %r4502 (0)
>1240: rsq f32 %r4505 %r4503 (0)
>1241: rcp f32 %r4506 %r4505 (0)
>1242: add f32 %r4509 neg %r4506 c0[0x30] (0)
>1243: mul f32 %r4511 %r4509 0.350000 (0)
>1244: mul f32 %r4513 %r4511 %r4505 (0)
>1245: mul f32 %r4514 %r4513 %r4493 (0)
>1246: mul f32 %r4515 %r4513 %r4495 (0)
>1247: mul f32 %r4516 %r4513 %r4497 (0)
>1248: mul f32 %r4517 %r4513 %r4499 (0)
>1249: not %p4211 ld  u32 %r4528 g[%r4209d+0x0] (0)
>1250: %p4211 mov u32 %r4529 0x00000000 (0)
>1251: union u32 %r4530 %r4528 %r4529 (0)
>1252: not %p4220 ld  u32 %r4537 g[%r4209d+0x4] (0)
>1253: %p4220 mov u32 %r4538 0x00000000 (0)
>1254: union u32 %r4539 %r4537 %r4538 (0)
>1255: not %p4229 ld  u32 %r4546 g[%r4209d+0x8] (0)
>1256: %p4229 mov u32 %r4547 0x00000000 (0)
>1257: union u32 %r4548 %r4546 %r4547 (0)
>1258: not %p4238 ld  u32 %r4555 g[%r4209d+0xc] (0)
>1259: %p4238 mov u32 %r4556 0x00000000 (0)
>1260: union u32 %r4557 %r4555 %r4556 (0)
>1261: add f32 %r4558 %r4530 %r4514 (0)
>1262: add f32 %r4559 %r4539 %r4515 (0)
>1263: add f32 %r4560 %r4548 %r4516 (0)
>1264: add f32 %r4561 %r4557 %r4517 (0)
>1265: not %p4211 st  u32 # g[%r4209d+0x0] %r4558 (0)
>1266: not %p4220 st  u32 # g[%r4209d+0x4] %r4559 (0)
>1267: not %p4229 st  u32 # g[%r4209d+0x8] %r4560 (0)
>1268: not %p4238 st  u32 # g[%r4209d+0xc] %r4561 (0)
>1269: not %p4253 ld  u32 %r4596 g[%r4251d+0x0] (0)
>1270: %p4253 mov u32 %r4597 0x00000000 (0)
>1271: union u32 %r4598 %r4596 %r4597 (0)
>1272: not %p4262 ld  u32 %r4605 g[%r4251d+0x4] (0)
>1273: %p4262 mov u32 %r4606 0x00000000 (0)
>1274: union u32 %r4607 %r4605 %r4606 (0)
>1275: not %p4271 ld  u32 %r4614 g[%r4251d+0x8] (0)
>1276: %p4271 mov u32 %r4615 0x00000000 (0)
>1277: union u32 %r4616 %r4614 %r4615 (0)
>1278: not %p4280 ld  u32 %r4623 g[%r4251d+0xc] (0)
>1279: %p4280 mov u32 %r4624 0x00000000 (0)
>1280: union u32 %r4625 %r4623 %r4624 (0)
>1281: add f32 %r4627 %r4598 neg %r4514 (0)
>1282: add f32 %r4629 %r4607 neg %r4515 (0)
>1283: add f32 %r4631 %r4616 neg %r4516 (0)
>1284: add f32 %r4633 %r4625 neg %r4517 (0)
>1285: not %p4253 st  u32 # g[%r4251d+0x0] %r4627 (0)
>1286: not %p4262 st  u32 # g[%r4251d+0x4] %r4629 (0)
>1287: not %p4271 st  u32 # g[%r4251d+0x8] %r4631 (0)
>1288: not %p4280 st  u32 # g[%r4251d+0xc] %r4633 (0)
>1289: membar (SUBOP:7) - # (0)
>1290: bra BB:42 (0)
>BB:42 (2 instructions) - idom = BB:40, df = { BB:43 }
> -> BB:43 (forward)
>1291: join (0)
>1292: bra BB:43 (0)
>BB:43 (4 instructions) - idom = BB:39, df = { BB:36 }
> -> BB:36 (back)
>1293: join (0)
>1294: bar u32 # 0x00000000 0x00000000 (0)
>1295: add u32 %r4659 %r4017 0x00000001 (0)
>1296: cont BB:36 (0)
>BB:11 (6 instructions) - idom = BB:12, df = { }
> -> BB:51 (forward)
> -> BB:46 (tree)
>1297: mov u32 %r3148 0x00000000 (0)
>1298: ld  u32 %r3154 c0[0x0] (0)
>1299: add u32 %r3156 %r3154 0xffffffff (0)
>1300: joinat BB:51 (0)
>1301: set u8 %p3159 lt s32 %r2715 %r3156 (0)
>1302: not %p3159 bra BB:51 (0)
>BB:46 (49 instructions) - idom = BB:11, df = { BB:51 }
> -> BB:48 (forward)
> -> BB:47 (tree)
>1303: shl u32 %r6439 %r2703 0x00000004 (0)
>1304: add u32 %r3163 %r6439 0x00000010 (0)
>1305: add u64 %r3168d %r3163 c7[0x330] (0)
>1306: add u32 %r3169 %r3163 0x00000004 (0)
>1307: set u8 %p3170 gt u32 %r3169 c7[0x338] (0)
>1308: not %p3170 ld  u32 %r3171 g[%r3168d+0x0] (0)
>1309: %p3170 mov u32 %r3172 0x00000000 (0)
>1310: union u32 %r3173 %r3171 %r3172 (0)
>1311: add u32 %r3178 %r3163 0x00000008 (0)
>1312: set u8 %p3179 gt u32 %r3178 c7[0x338] (0)
>1313: not %p3179 ld  u32 %r3180 g[%r3168d+0x4] (0)
>1314: %p3179 mov u32 %r3181 0x00000000 (0)
>1315: union u32 %r3182 %r3180 %r3181 (0)
>1316: add u32 %r3187 %r3163 0x0000000c (0)
>1317: set u8 %p3188 gt u32 %r3187 c7[0x338] (0)
>1318: not %p3188 ld  u32 %r3189 g[%r3168d+0x8] (0)
>1319: %p3188 mov u32 %r3190 0x00000000 (0)
>1320: union u32 %r3191 %r3189 %r3190 (0)
>1321: add u64 %r3210d %r6439 c7[0x330] (0)
>1322: add u32 %r3211 %r6439 0x00000004 (0)
>1323: set u8 %p3212 gt u32 %r3211 c7[0x338] (0)
>1324: not %p3212 ld  u32 %r3213 g[%r3210d+0x0] (0)
>1325: %p3212 mov u32 %r3214 0x00000000 (0)
>1326: union u32 %r3215 %r3213 %r3214 (0)
>1327: add u32 %r3220 %r6439 0x00000008 (0)
>1328: set u8 %p3221 gt u32 %r3220 c7[0x338] (0)
>1329: not %p3221 ld  u32 %r3222 g[%r3210d+0x4] (0)
>1330: %p3221 mov u32 %r3223 0x00000000 (0)
>1331: union u32 %r3224 %r3222 %r3223 (0)
>1332: add u32 %r3229 %r6439 0x0000000c (0)
>1333: set u8 %p3230 gt u32 %r3229 c7[0x338] (0)
>1334: not %p3230 ld  u32 %r3231 g[%r3210d+0x8] (0)
>1335: %p3230 mov u32 %r3232 0x00000000 (0)
>1336: union u32 %r3233 %r3231 %r3232 (0)
>1337: add f32 %r3248 %r3173 neg %r3215 (0)
>1338: add f32 %r3250 %r3182 neg %r3224 (0)
>1339: add f32 %r3252 %r3191 neg %r3233 (0)
>1340: mul f32 %r3256 %r3248 %r3248 (0)
>1341: mad f32 %r3257 %r3250 %r3250 %r3256 (0)
>1342: mad f32 %r3258 %r3252 %r3252 %r3257 (0)
>1343: rsq f32 %r3261 abs %r3258 (0)
>1344: mul f32 %r3264 %r3248 %r3261 (0)
>1345: mul f32 %r3265 %r3250 %r3261 (0)
>1346: mul f32 %r3266 %r3252 %r3261 (0)
>1347: ld  u32 %r3270 c0[0x0] (0)
>1348: add u32 %r3272 %r3270 0xffffffff (0)
>1349: joinat BB:48 (0)
>1350: set u8 %p3275 lt s32 %r2717 %r3272 (0)
>1351: not %p3275 bra BB:48 (0)
>BB:47 (59 instructions) - idom = BB:46, df = { BB:48 }
> -> BB:48 (forward)
>1352: add u32 %r3277 %r2703 c0[0x0] (0)
>1353: shl u32 %r3279 %r3277 0x00000004 (0)
>1354: add u64 %r3284d %r3279 c7[0x330] (0)
>1355: add u32 %r3285 %r3279 0x00000004 (0)
>1356: set u8 %p3286 gt u32 %r3285 c7[0x338] (0)
>1357: not %p3286 ld  u32 %r3287 g[%r3284d+0x0] (0)
>1358: %p3286 mov u32 %r3288 0x00000000 (0)
>1359: union u32 %r3289 %r3287 %r3288 (0)
>1360: add u32 %r3294 %r3279 0x00000008 (0)
>1361: set u8 %p3295 gt u32 %r3294 c7[0x338] (0)
>1362: not %p3295 ld  u32 %r3296 g[%r3284d+0x4] (0)
>1363: %p3295 mov u32 %r3297 0x00000000 (0)
>1364: union u32 %r3298 %r3296 %r3297 (0)
>1365: add u32 %r3303 %r3279 0x0000000c (0)
>1366: set u8 %p3304 gt u32 %r3303 c7[0x338] (0)
>1367: not %p3304 ld  u32 %r3305 g[%r3284d+0x8] (0)
>1368: %p3304 mov u32 %r3306 0x00000000 (0)
>1369: union u32 %r3307 %r3305 %r3306 (0)
>1370: shl u32 %r3322 %r2703 0x00000004 (0)
>1371: add u64 %r3326d %r3322 c7[0x330] (0)
>1372: add u32 %r3327 %r3322 0x00000004 (0)
>1373: set u8 %p3328 gt u32 %r3327 c7[0x338] (0)
>1374: not %p3328 ld  u32 %r3329 g[%r3326d+0x0] (0)
>1375: %p3328 mov u32 %r3330 0x00000000 (0)
>1376: union u32 %r3331 %r3329 %r3330 (0)
>1377: add u32 %r3336 %r3322 0x00000008 (0)
>1378: set u8 %p3337 gt u32 %r3336 c7[0x338] (0)
>1379: not %p3337 ld  u32 %r3338 g[%r3326d+0x4] (0)
>1380: %p3337 mov u32 %r3339 0x00000000 (0)
>1381: union u32 %r3340 %r3338 %r3339 (0)
>1382: add u32 %r3345 %r3322 0x0000000c (0)
>1383: set u8 %p3346 gt u32 %r3345 c7[0x338] (0)
>1384: not %p3346 ld  u32 %r3347 g[%r3326d+0x8] (0)
>1385: %p3346 mov u32 %r3348 0x00000000 (0)
>1386: union u32 %r3349 %r3347 %r3348 (0)
>1387: add f32 %r3364 %r3289 neg %r3331 (0)
>1388: add f32 %r3366 %r3298 neg %r3340 (0)
>1389: add f32 %r3368 %r3307 neg %r3349 (0)
>1390: mul f32 %r3372 %r3364 %r3364 (0)
>1391: mad f32 %r3373 %r3366 %r3366 %r3372 (0)
>1392: mad f32 %r3374 %r3368 %r3368 %r3373 (0)
>1393: rsq f32 %r3377 abs %r3374 (0)
>1394: mul f32 %r3380 %r3364 %r3377 (0)
>1395: mul f32 %r3381 %r3366 %r3377 (0)
>1396: mul f32 %r3382 %r3368 %r3377 (0)
>1397: mul f32 %r3386 %r3382 %r3265 (0)
>1398: mul f32 %r3387 %r3380 %r3266 (0)
>1399: mul f32 %r3388 %r3381 %r3264 (0)
>1400: mad f32 %r3390 %r3381 %r3266 neg %r3386 (0)
>1401: mad f32 %r3392 %r3382 %r3264 neg %r3387 (0)
>1402: mad f32 %r3394 %r3380 %r3265 neg %r3388 (0)
>1403: mul f32 %r3398 %r3390 %r3390 (0)
>1404: mad f32 %r3399 %r3392 %r3392 %r3398 (0)
>1405: mad f32 %r3400 %r3394 %r3394 %r3399 (0)
>1406: rsq f32 %r3403 abs %r3400 (0)
>1407: mul f32 %r3406 %r3390 %r3403 (0)
>1408: mul f32 %r3407 %r3392 %r3403 (0)
>1409: mul f32 %r3408 %r3394 %r3403 (0)
>1410: bra BB:48 (0)
>BB:48 (7 instructions) - idom = BB:46, df = { BB:51 }
> -> BB:50 (forward)
> -> BB:49 (tree)
>1411: phi u32 %r3409 %r3148 %r3406 (0)
>1412: phi u32 %r3410 %r3148 %r3407 (0)
>1413: phi u32 %r3411 %r3148 %r3408 (0)
>1414: join (0)
>1415: joinat BB:50 (0)
>1416: set u8 %p3414 lt s32 0 %r2717 (0)
>1417: not %p3414 bra BB:50 (0)
>BB:49 (59 instructions) - idom = BB:48, df = { BB:50 }
> -> BB:50 (forward)
>1418: shl u32 %r3416 %r2703 0x00000004 (0)
>1419: add u64 %r3420d %r3416 c7[0x330] (0)
>1420: add u32 %r3421 %r3416 0x00000004 (0)
>1421: set u8 %p3422 gt u32 %r3421 c7[0x338] (0)
>1422: not %p3422 ld  u32 %r3423 g[%r3420d+0x0] (0)
>1423: %p3422 mov u32 %r3424 0x00000000 (0)
>1424: union u32 %r3425 %r3423 %r3424 (0)
>1425: add u32 %r3430 %r3416 0x00000008 (0)
>1426: set u8 %p3431 gt u32 %r3430 c7[0x338] (0)
>1427: not %p3431 ld  u32 %r3432 g[%r3420d+0x4] (0)
>1428: %p3431 mov u32 %r3433 0x00000000 (0)
>1429: union u32 %r3434 %r3432 %r3433 (0)
>1430: add u32 %r3439 %r3416 0x0000000c (0)
>1431: set u8 %p3440 gt u32 %r3439 c7[0x338] (0)
>1432: not %p3440 ld  u32 %r3441 g[%r3420d+0x8] (0)
>1433: %p3440 mov u32 %r3442 0x00000000 (0)
>1434: union u32 %r3443 %r3441 %r3442 (0)
>1435: add u32 %r3459 %r2703 neg c0[0x0] (0)
>1436: shl u32 %r3462 %r3459 0x00000004 (0)
>1437: add u64 %r3467d %r3462 c7[0x330] (0)
>1438: add u32 %r3468 %r3462 0x00000004 (0)
>1439: set u8 %p3469 gt u32 %r3468 c7[0x338] (0)
>1440: not %p3469 ld  u32 %r3470 g[%r3467d+0x0] (0)
>1441: %p3469 mov u32 %r3471 0x00000000 (0)
>1442: union u32 %r3472 %r3470 %r3471 (0)
>1443: add u32 %r3477 %r3462 0x00000008 (0)
>1444: set u8 %p3478 gt u32 %r3477 c7[0x338] (0)
>1445: not %p3478 ld  u32 %r3479 g[%r3467d+0x4] (0)
>1446: %p3478 mov u32 %r3480 0x00000000 (0)
>1447: union u32 %r3481 %r3479 %r3480 (0)
>1448: add u32 %r3486 %r3462 0x0000000c (0)
>1449: set u8 %p3487 gt u32 %r3486 c7[0x338] (0)
>1450: not %p3487 ld  u32 %r3488 g[%r3467d+0x8] (0)
>1451: %p3487 mov u32 %r3489 0x00000000 (0)
>1452: union u32 %r3490 %r3488 %r3489 (0)
>1453: add f32 %r3505 %r3425 neg %r3472 (0)
>1454: add f32 %r3507 %r3434 neg %r3481 (0)
>1455: add f32 %r3509 %r3443 neg %r3490 (0)
>1456: mul f32 %r3513 %r3505 %r3505 (0)
>1457: mad f32 %r3514 %r3507 %r3507 %r3513 (0)
>1458: mad f32 %r3515 %r3509 %r3509 %r3514 (0)
>1459: rsq f32 %r3518 abs %r3515 (0)
>1460: mul f32 %r3521 %r3505 %r3518 (0)
>1461: mul f32 %r3522 %r3507 %r3518 (0)
>1462: mul f32 %r3523 %r3509 %r3518 (0)
>1463: mul f32 %r3527 %r3523 %r3265 (0)
>1464: mul f32 %r3528 %r3521 %r3266 (0)
>1465: mul f32 %r3529 %r3522 %r3264 (0)
>1466: mad f32 %r3531 %r3522 %r3266 neg %r3527 (0)
>1467: mad f32 %r3533 %r3523 %r3264 neg %r3528 (0)
>1468: mad f32 %r3535 %r3521 %r3265 neg %r3529 (0)
>1469: mul f32 %r3539 %r3531 %r3531 (0)
>1470: mad f32 %r3540 %r3533 %r3533 %r3539 (0)
>1471: mad f32 %r3541 %r3535 %r3535 %r3540 (0)
>1472: rsq f32 %r3544 abs %r3541 (0)
>1473: mad f32 %r3547 %r3531 %r3544 %r3409 (0)
>1474: mad f32 %r3548 %r3533 %r3544 %r3410 (0)
>1475: mad f32 %r3549 %r3535 %r3544 %r3411 (0)
>1476: bra BB:50 (0)
>BB:50 (5 instructions) - idom = BB:48, df = { BB:51 }
> -> BB:51 (forward)
>1477: phi u32 %r3553 %r3409 %r3547 (0)
>1478: phi u32 %r3554 %r3410 %r3548 (0)
>1479: phi u32 %r3555 %r3411 %r3549 (0)
>1480: join (0)
>1481: bra BB:51 (0)
>BB:51 (7 instructions) - idom = BB:11, df = { }
> -> BB:57 (forward)
> -> BB:52 (tree)
>1482: phi u32 %r3556 %r3148 %r3553 (0)
>1483: phi u32 %r3557 %r3148 %r3554 (0)
>1484: phi u32 %r3558 %r3148 %r3555 (0)
>1485: join (0)
>1486: joinat BB:57 (0)
>1487: set u8 %p3562 lt s32 0 %r2715 (0)
>1488: not %p3562 bra BB:57 (0)
>BB:52 (49 instructions) - idom = BB:51, df = { BB:57 }
> -> BB:54 (forward)
> -> BB:53 (tree)
>1489: shl u32 %r3564 %r2703 0x00000004 (0)
>1490: add u64 %r3568d %r3564 c7[0x330] (0)
>1491: add u32 %r3569 %r3564 0x00000004 (0)
>1492: set u8 %p3570 gt u32 %r3569 c7[0x338] (0)
>1493: not %p3570 ld  u32 %r3571 g[%r3568d+0x0] (0)
>1494: %p3570 mov u32 %r3572 0x00000000 (0)
>1495: union u32 %r3573 %r3571 %r3572 (0)
>1496: add u32 %r3578 %r3564 0x00000008 (0)
>1497: set u8 %p3579 gt u32 %r3578 c7[0x338] (0)
>1498: not %p3579 ld  u32 %r3580 g[%r3568d+0x4] (0)
>1499: %p3579 mov u32 %r3581 0x00000000 (0)
>1500: union u32 %r3582 %r3580 %r3581 (0)
>1501: add u32 %r3587 %r3564 0x0000000c (0)
>1502: set u8 %p3588 gt u32 %r3587 c7[0x338] (0)
>1503: not %p3588 ld  u32 %r3589 g[%r3568d+0x8] (0)
>1504: %p3588 mov u32 %r3590 0x00000000 (0)
>1505: union u32 %r3591 %r3589 %r3590 (0)
>1506: add u32 %r3608 %r3564 0xfffffff0 (0)
>1507: add u64 %r3613d %r3608 c7[0x330] (0)
>1508: add u32 %r3614 %r3608 0x00000004 (0)
>1509: set u8 %p3615 gt u32 %r3614 c7[0x338] (0)
>1510: not %p3615 ld  u32 %r3616 g[%r3613d+0x0] (0)
>1511: %p3615 mov u32 %r3617 0x00000000 (0)
>1512: union u32 %r3618 %r3616 %r3617 (0)
>1513: add u32 %r3623 %r3608 0x00000008 (0)
>1514: set u8 %p3624 gt u32 %r3623 c7[0x338] (0)
>1515: not %p3624 ld  u32 %r3625 g[%r3613d+0x4] (0)
>1516: %p3624 mov u32 %r3626 0x00000000 (0)
>1517: union u32 %r3627 %r3625 %r3626 (0)
>1518: add u32 %r3632 %r3608 0x0000000c (0)
>1519: set u8 %p3633 gt u32 %r3632 c7[0x338] (0)
>1520: not %p3633 ld  u32 %r3634 g[%r3613d+0x8] (0)
>1521: %p3633 mov u32 %r3635 0x00000000 (0)
>1522: union u32 %r3636 %r3634 %r3635 (0)
>1523: add f32 %r3651 %r3573 neg %r3618 (0)
>1524: add f32 %r3653 %r3582 neg %r3627 (0)
>1525: add f32 %r3655 %r3591 neg %r3636 (0)
>1526: mul f32 %r3659 %r3651 %r3651 (0)
>1527: mad f32 %r3660 %r3653 %r3653 %r3659 (0)
>1528: mad f32 %r3661 %r3655 %r3655 %r3660 (0)
>1529: rsq f32 %r3664 abs %r3661 (0)
>1530: mul f32 %r3667 %r3651 %r3664 (0)
>1531: mul f32 %r3668 %r3653 %r3664 (0)
>1532: mul f32 %r3669 %r3655 %r3664 (0)
>1533: ld  u32 %r3673 c0[0x0] (0)
>1534: add u32 %r3675 %r3673 0xffffffff (0)
>1535: joinat BB:54 (0)
>1536: set u8 %p3678 lt s32 %r2717 %r3675 (0)
>1537: not %p3678 bra BB:54 (0)
>BB:53 (59 instructions) - idom = BB:52, df = { BB:54 }
> -> BB:54 (forward)
>1538: add u32 %r3680 %r2703 c0[0x0] (0)
>1539: shl u32 %r3682 %r3680 0x00000004 (0)
>1540: add u64 %r3687d %r3682 c7[0x330] (0)
>1541: add u32 %r3688 %r3682 0x00000004 (0)
>1542: set u8 %p3689 gt u32 %r3688 c7[0x338] (0)
>1543: not %p3689 ld  u32 %r3690 g[%r3687d+0x0] (0)
>1544: %p3689 mov u32 %r3691 0x00000000 (0)
>1545: union u32 %r3692 %r3690 %r3691 (0)
>1546: add u32 %r3697 %r3682 0x00000008 (0)
>1547: set u8 %p3698 gt u32 %r3697 c7[0x338] (0)
>1548: not %p3698 ld  u32 %r3699 g[%r3687d+0x4] (0)
>1549: %p3698 mov u32 %r3700 0x00000000 (0)
>1550: union u32 %r3701 %r3699 %r3700 (0)
>1551: add u32 %r3706 %r3682 0x0000000c (0)
>1552: set u8 %p3707 gt u32 %r3706 c7[0x338] (0)
>1553: not %p3707 ld  u32 %r3708 g[%r3687d+0x8] (0)
>1554: %p3707 mov u32 %r3709 0x00000000 (0)
>1555: union u32 %r3710 %r3708 %r3709 (0)
>1556: shl u32 %r3725 %r2703 0x00000004 (0)
>1557: add u64 %r3729d %r3725 c7[0x330] (0)
>1558: add u32 %r3730 %r3725 0x00000004 (0)
>1559: set u8 %p3731 gt u32 %r3730 c7[0x338] (0)
>1560: not %p3731 ld  u32 %r3732 g[%r3729d+0x0] (0)
>1561: %p3731 mov u32 %r3733 0x00000000 (0)
>1562: union u32 %r3734 %r3732 %r3733 (0)
>1563: add u32 %r3739 %r3725 0x00000008 (0)
>1564: set u8 %p3740 gt u32 %r3739 c7[0x338] (0)
>1565: not %p3740 ld  u32 %r3741 g[%r3729d+0x4] (0)
>1566: %p3740 mov u32 %r3742 0x00000000 (0)
>1567: union u32 %r3743 %r3741 %r3742 (0)
>1568: add u32 %r3748 %r3725 0x0000000c (0)
>1569: set u8 %p3749 gt u32 %r3748 c7[0x338] (0)
>1570: not %p3749 ld  u32 %r3750 g[%r3729d+0x8] (0)
>1571: %p3749 mov u32 %r3751 0x00000000 (0)
>1572: union u32 %r3752 %r3750 %r3751 (0)
>1573: add f32 %r3767 %r3692 neg %r3734 (0)
>1574: add f32 %r3769 %r3701 neg %r3743 (0)
>1575: add f32 %r3771 %r3710 neg %r3752 (0)
>1576: mul f32 %r3775 %r3767 %r3767 (0)
>1577: mad f32 %r3776 %r3769 %r3769 %r3775 (0)
>1578: mad f32 %r3777 %r3771 %r3771 %r3776 (0)
>1579: rsq f32 %r3780 abs %r3777 (0)
>1580: mul f32 %r3783 %r3767 %r3780 (0)
>1581: mul f32 %r3784 %r3769 %r3780 (0)
>1582: mul f32 %r3785 %r3771 %r3780 (0)
>1583: mul f32 %r3789 %r3785 %r3668 (0)
>1584: mul f32 %r3790 %r3783 %r3669 (0)
>1585: mul f32 %r3791 %r3784 %r3667 (0)
>1586: mad f32 %r3793 %r3784 %r3669 neg %r3789 (0)
>1587: mad f32 %r3795 %r3785 %r3667 neg %r3790 (0)
>1588: mad f32 %r3797 %r3783 %r3668 neg %r3791 (0)
>1589: mul f32 %r3801 %r3793 %r3793 (0)
>1590: mad f32 %r3802 %r3795 %r3795 %r3801 (0)
>1591: mad f32 %r3803 %r3797 %r3797 %r3802 (0)
>1592: rsq f32 %r3806 abs %r3803 (0)
>1593: mad f32 %r3809 %r3793 %r3806 %r3556 (0)
>1594: mad f32 %r3810 %r3795 %r3806 %r3557 (0)
>1595: mad f32 %r3811 %r3797 %r3806 %r3558 (0)
>1596: bra BB:54 (0)
>BB:54 (7 instructions) - idom = BB:52, df = { BB:57 }
> -> BB:56 (forward)
> -> BB:55 (tree)
>1597: phi u32 %r3815 %r3556 %r3809 (0)
>1598: phi u32 %r3816 %r3557 %r3810 (0)
>1599: phi u32 %r3817 %r3558 %r3811 (0)
>1600: join (0)
>1601: joinat BB:56 (0)
>1602: set u8 %p3821 lt s32 0 %r2717 (0)
>1603: not %p3821 bra BB:56 (0)
>BB:55 (59 instructions) - idom = BB:54, df = { BB:56 }
> -> BB:56 (forward)
>1604: shl u32 %r3823 %r2703 0x00000004 (0)
>1605: add u64 %r3827d %r3823 c7[0x330] (0)
>1606: add u32 %r3828 %r3823 0x00000004 (0)
>1607: set u8 %p3829 gt u32 %r3828 c7[0x338] (0)
>1608: not %p3829 ld  u32 %r3830 g[%r3827d+0x0] (0)
>1609: %p3829 mov u32 %r3831 0x00000000 (0)
>1610: union u32 %r3832 %r3830 %r3831 (0)
>1611: add u32 %r3837 %r3823 0x00000008 (0)
>1612: set u8 %p3838 gt u32 %r3837 c7[0x338] (0)
>1613: not %p3838 ld  u32 %r3839 g[%r3827d+0x4] (0)
>1614: %p3838 mov u32 %r3840 0x00000000 (0)
>1615: union u32 %r3841 %r3839 %r3840 (0)
>1616: add u32 %r3846 %r3823 0x0000000c (0)
>1617: set u8 %p3847 gt u32 %r3846 c7[0x338] (0)
>1618: not %p3847 ld  u32 %r3848 g[%r3827d+0x8] (0)
>1619: %p3847 mov u32 %r3849 0x00000000 (0)
>1620: union u32 %r3850 %r3848 %r3849 (0)
>1621: add u32 %r3866 %r2703 neg c0[0x0] (0)
>1622: shl u32 %r3869 %r3866 0x00000004 (0)
>1623: add u64 %r3874d %r3869 c7[0x330] (0)
>1624: add u32 %r3875 %r3869 0x00000004 (0)
>1625: set u8 %p3876 gt u32 %r3875 c7[0x338] (0)
>1626: not %p3876 ld  u32 %r3877 g[%r3874d+0x0] (0)
>1627: %p3876 mov u32 %r3878 0x00000000 (0)
>1628: union u32 %r3879 %r3877 %r3878 (0)
>1629: add u32 %r3884 %r3869 0x00000008 (0)
>1630: set u8 %p3885 gt u32 %r3884 c7[0x338] (0)
>1631: not %p3885 ld  u32 %r3886 g[%r3874d+0x4] (0)
>1632: %p3885 mov u32 %r3887 0x00000000 (0)
>1633: union u32 %r3888 %r3886 %r3887 (0)
>1634: add u32 %r3893 %r3869 0x0000000c (0)
>1635: set u8 %p3894 gt u32 %r3893 c7[0x338] (0)
>1636: not %p3894 ld  u32 %r3895 g[%r3874d+0x8] (0)
>1637: %p3894 mov u32 %r3896 0x00000000 (0)
>1638: union u32 %r3897 %r3895 %r3896 (0)
>1639: add f32 %r3912 %r3832 neg %r3879 (0)
>1640: add f32 %r3914 %r3841 neg %r3888 (0)
>1641: add f32 %r3916 %r3850 neg %r3897 (0)
>1642: mul f32 %r3920 %r3912 %r3912 (0)
>1643: mad f32 %r3921 %r3914 %r3914 %r3920 (0)
>1644: mad f32 %r3922 %r3916 %r3916 %r3921 (0)
>1645: rsq f32 %r3925 abs %r3922 (0)
>1646: mul f32 %r3928 %r3912 %r3925 (0)
>1647: mul f32 %r3929 %r3914 %r3925 (0)
>1648: mul f32 %r3930 %r3916 %r3925 (0)
>1649: mul f32 %r3934 %r3930 %r3668 (0)
>1650: mul f32 %r3935 %r3928 %r3669 (0)
>1651: mul f32 %r3936 %r3929 %r3667 (0)
>1652: mad f32 %r3938 %r3929 %r3669 neg %r3934 (0)
>1653: mad f32 %r3940 %r3930 %r3667 neg %r3935 (0)
>1654: mad f32 %r3942 %r3928 %r3668 neg %r3936 (0)
>1655: mul f32 %r3946 %r3938 %r3938 (0)
>1656: mad f32 %r3947 %r3940 %r3940 %r3946 (0)
>1657: mad f32 %r3948 %r3942 %r3942 %r3947 (0)
>1658: rsq f32 %r3951 abs %r3948 (0)
>1659: mad f32 %r3954 %r3938 %r3951 %r3815 (0)
>1660: mad f32 %r3955 %r3940 %r3951 %r3816 (0)
>1661: mad f32 %r3956 %r3942 %r3951 %r3817 (0)
>1662: bra BB:56 (0)
>BB:56 (5 instructions) - idom = BB:54, df = { BB:57 }
> -> BB:57 (forward)
>1663: phi u32 %r3960 %r3815 %r3954 (0)
>1664: phi u32 %r3961 %r3816 %r3955 (0)
>1665: phi u32 %r3962 %r3817 %r3956 (0)
>1666: join (0)
>1667: bra BB:57 (0)
>BB:57 (23 instructions) - idom = BB:51, df = { }
> -> BB:1 (tree)
>1668: phi u32 %r3963 %r3556 %r3960 (0)
>1669: phi u32 %r3964 %r3557 %r3961 (0)
>1670: phi u32 %r3965 %r3558 %r3962 (0)
>1671: join (0)
>1672: shl u32 %r3967 %r2703 0x00000004 (0)
>1673: mul f32 %r3969 %r3963 %r3963 (0)
>1674: mad f32 %r3970 %r3964 %r3964 %r3969 (0)
>1675: mad f32 %r3971 %r3965 %r3965 %r3970 (0)
>1676: rsq f32 %r3974 abs %r3971 (0)
>1677: mul f32 %r3977 %r3963 %r3974 (0)
>1678: mul f32 %r3978 %r3964 %r3974 (0)
>1679: mul f32 %r3979 %r3965 %r3974 (0)
>1680: add u64 %r3986d %r3967 c7[0x310] (0)
>1681: add u32 %r3987 %r3967 0x00000004 (0)
>1682: set u8 %p3988 gt u32 %r3987 c7[0x318] (0)
>1683: not %p3988 st  u32 # g[%r3986d+0x0] %r3977 (0)
>1684: add u32 %r3993 %r3967 0x00000008 (0)
>1685: set u8 %p3994 gt u32 %r3993 c7[0x318] (0)
>1686: not %p3994 st  u32 # g[%r3986d+0x4] %r3978 (0)
>1687: add u32 %r3999 %r3967 0x0000000c (0)
>1688: set u8 %p4000 gt u32 %r3999 c7[0x318] (0)
>1689: not %p4000 st  u32 # g[%r3986d+0x8] %r3979 (0)
>1690: membar (SUBOP:7) - # (0)
>BB:1 (1 instructions) - idom = BB:57, df = { }
>1691: exit - # (0)
>BB:37 (37 instructions) - idom = BB:38, df = { BB:10 }
> -> BB:45 (forward)
> -> BB:44 (tree)
>1692: shl u32 %r4022 %r2703 0x00000004 (0)
>1693: add u64 %r4026d %r4022 c7[0x330] (0)
>1694: add u32 %r4027 %r4022 0x00000004 (0)
>1695: set u8 %p4028 gt u32 %r4027 c7[0x338] (0)
>1696: not %p4028 ld  u32 %r4029 g[%r4026d+0x0] (0)
>1697: %p4028 mov u32 %r4030 0x00000000 (0)
>1698: union u32 %r4031 %r4029 %r4030 (0)
>1699: add u32 %r4036 %r4022 0x00000008 (0)
>1700: set u8 %p4037 gt u32 %r4036 c7[0x338] (0)
>1701: not %p4037 ld  u32 %r4038 g[%r4026d+0x4] (0)
>1702: %p4037 mov u32 %r4039 0x00000000 (0)
>1703: union u32 %r4040 %r4038 %r4039 (0)
>1704: add u32 %r4045 %r4022 0x0000000c (0)
>1705: set u8 %p4046 gt u32 %r4045 c7[0x338] (0)
>1706: not %p4046 ld  u32 %r4047 g[%r4026d+0x8] (0)
>1707: %p4046 mov u32 %r4048 0x00000000 (0)
>1708: union u32 %r4049 %r4047 %r4048 (0)
>1709: add u32 %r4054 %r4022 0x00000010 (0)
>1710: set u8 %p4055 gt u32 %r4054 c7[0x338] (0)
>1711: not %p4055 ld  u32 %r4056 g[%r4026d+0xc] (0)
>1712: %p4055 mov u32 %r4057 0x00000000 (0)
>1713: union u32 %r4058 %r4056 %r4057 (0)
>1714: add f32 %r4061 %r4031 neg c0[0x40] (0)
>1715: add f32 %r4064 %r4040 neg c0[0x44] (0)
>1716: add f32 %r4067 %r4049 neg c0[0x48] (0)
>1717: add f32 %r4070 %r4058 neg c0[0x4c] (0)
>1718: mul f32 %r4071 %r4061 %r4061 (0)
>1719: mad f32 %r4072 %r4064 %r4064 %r4071 (0)
>1720: mad f32 %r4073 %r4067 %r4067 %r4072 (0)
>1721: mad f32 %r4074 %r4070 %r4070 %r4073 (0)
>1722: rsq f32 %r4076 %r4074 (0)
>1723: rcp f32 %r4077 %r4076 (0)
>1724: ld  u32 %r4078 c0[0x50] (0)
>1725: add f32 %r4080 %r4078 0.010000 (0)
>1726: joinat BB:45 (0)
>1727: set u8 %p4082 lt f32 %r4077 %r4080 (0)
>1728: not %p4082 bra BB:45 (0)
>BB:44 (31 instructions) - idom = BB:37, df = { BB:45 }
> -> BB:45 (forward)
>1729: shl u32 %r4084 %r2703 0x00000004 (0)
>1730: mul f32 %r4085 %r4061 %r4061 (0)
>1731: mad f32 %r4086 %r4064 %r4064 %r4085 (0)
>1732: mad f32 %r4087 %r4067 %r4067 %r4086 (0)
>1733: mad f32 %r4088 %r4070 %r4070 %r4087 (0)
>1734: rsq f32 %r4091 abs %r4088 (0)
>1735: mul f32 %r4093 %r4061 %r4091 (0)
>1736: mul f32 %r4094 %r4064 %r4091 (0)
>1737: mul f32 %r4095 %r4067 %r4091 (0)
>1738: mul f32 %r4096 %r4070 %r4091 (0)
>1739: ld  u32 %r4097 c0[0x50] (0)
>1740: add f32 %r4099 %r4097 0.010000 (0)
>1741: mad f32 %r4101 %r4093 %r4099 c0[0x40] (0)
>1742: mad f32 %r4103 %r4094 %r4099 c0[0x44] (0)
>1743: mad f32 %r4105 %r4095 %r4099 c0[0x48] (0)
>1744: mad f32 %r4107 %r4096 %r4099 c0[0x4c] (0)
>1745: add u64 %r4111d %r4084 c7[0x330] (0)
>1746: add u32 %r4112 %r4084 0x00000004 (0)
>1747: set u8 %p4113 gt u32 %r4112 c7[0x338] (0)
>1748: not %p4113 st  u32 # g[%r4111d+0x0] %r4101 (0)
>1749: add u32 %r4118 %r4084 0x00000008 (0)
>1750: set u8 %p4119 gt u32 %r4118 c7[0x338] (0)
>1751: not %p4119 st  u32 # g[%r4111d+0x4] %r4103 (0)
>1752: add u32 %r4124 %r4084 0x0000000c (0)
>1753: set u8 %p4125 gt u32 %r4124 c7[0x338] (0)
>1754: not %p4125 st  u32 # g[%r4111d+0x8] %r4105 (0)
>1755: add u32 %r4130 %r4084 0x00000010 (0)
>1756: set u8 %p4131 gt u32 %r4130 c7[0x338] (0)
>1757: not %p4131 st  u32 # g[%r4111d+0xc] %r4107 (0)
>1758: membar (SUBOP:7) - # (0)
>1759: bra BB:45 (0)
>BB:45 (4 instructions) - idom = BB:37, df = { BB:10 }
> -> BB:10 (back)
>1760: join (0)
>1761: bar u32 # 0x00000000 0x00000000 (0)
>1762: add u32 %r4133 %r3136 0x00000001 (0)
>1763: cont BB:10 (0)
>
>MAIN:-1 ()
>BB:0 (47 instructions) - df = { }
> -> BB:8 (tree)
> -> BB:2 (tree)
>  0: rdsv u32 $r0 sv[CTAID:0] (8)
>  1: mov u32 $r1 0x00000400 (8)
>  2: rdsv u32 $r2 sv[TID:0] (8)
>  3: mad u32 $r8 $r0 $r1 $r2 (8)
>  4: ld  u32 $r4 c0[0x0] (8)
>  5: mov u32 $r0 $r8 (8)
>  6: mov u32 $r1 $r4 (8)
>  7: call abs BUILTIN:1 (8)
>  8: mov u32 $r10 $r1 (8)
>  9: mov u32 $r0 $r8 (8)
> 10: mov u32 $r1 $r4 (8)
> 11: call abs BUILTIN:1 (8)
> 12: mov u32 $r9 $r0 (8)
> 13: shl u32 $r2 $r8 0x00000004 (8)
> 14: add u32 { $r0 $c0 } $r2 c7[0x320] (8)
> 15: add u32 $r1 $r255 c7[0x324] $c0 (8)
> 16: add u32 $r3 $r2 0x00000004 (8)
> 17: set u8 $p0 gt u32 $r3 c7[0x328] (8)
> 18: not $p0 ld  u32 $r3 g[$r0d+0x0] (8)
> 19: $p0 mov u32 $r3 0x00000000 (8)
> 20: add u32 $r4 $r2 0x00000008 (8)
> 21: set u8 $p0 gt u32 $r4 c7[0x328] (8)
> 22: not $p0 ld  u32 $r4 g[$r0d+0x4] (8)
> 23: $p0 mov u32 $r4 0x00000000 (8)
> 24: add u32 $r5 $r2 0x0000000c (8)
> 25: set u8 $p0 gt u32 $r5 c7[0x328] (8)
> 26: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
> 27: $p0 mov u32 $r5 0x00000000 (8)
> 28: add u32 $r2 $r2 0x00000010 (8)
> 29: set u8 $p0 gt u32 $r2 c7[0x328] (8)
> 30: not $p0 ld  u32 $r0 g[$r0d+0xc] (8)
> 31: $p0 mov u32 $r0 0x00000000 (8)
> 32: add f32 $r1 $r3 neg c0[0x40] (8)
> 33: add f32 $r2 $r4 neg c0[0x44] (8)
> 34: add f32 $r3 $r5 neg c0[0x48] (8)
> 35: add f32 $r0 $r0 neg c0[0x4c] (8)
> 36: mul f32 $r4 $r1 $r1 (8)
> 37: mad f32 $r4 $r2 $r2 $r4 (8)
> 38: mad f32 $r4 $r3 $r3 $r4 (8)
> 39: mad f32 $r4 $r0 $r0 $r4 (8)
> 40: rsq f32 $r4 $r4 (8)
> 41: rcp f32 $r4 $r4 (8)
> 42: ld  u32 $r5 c0[0x50] (8)
> 43: add f32 $r5 $r5 0.010000 (8)
> 44: joinat BB:9 (8)
> 45: set u8 $p0 ge f32 $r5 $r4 (8)
> 46: not $p0 bra BB:8 (8)
>BB:2 (13 instructions) - idom = BB:0, df = { BB:9 }
> -> BB:73 (tree)
> -> BB:3 (tree)
> 47: mov u32 $r5 0x00000000 (8)
> 48: mul f32 $r4 $r1 $r1 (8)
> 49: mad f32 $r4 $r2 $r2 $r4 (8)
> 50: mad f32 $r4 $r3 $r3 $r4 (8)
> 51: mad f32 $r0 $r0 $r0 $r4 (8)
> 52: rsq f32 $r0 abs $r0 (8)
> 53: mul f32 $r1 $r1 $r0 (8)
> 54: mul f32 $r2 $r2 $r0 (8)
> 55: mul f32 $r0 $r3 $r0 (8)
> 56: max f32 $r3 $r2 $r255 (8)
> 57: joinat BB:7 (8)
> 58: set u8 $p0 neu f32 $r3 1.000000 (8)
> 59: not $p0 bra BB:73 (8)
>BB:3 (4 instructions) - idom = BB:2, df = { BB:7 }
> -> BB:5 (tree)
> -> BB:4 (tree)
> 60: mul f32 $r4 $r1 $r1 (8)
> 61: mad f32 $r4 $r2 $r2 $r4 (8)
> 62: mad f32 $r4 $r0 $r0 $r4 (8)
> 63: set u8 $p0 eq f32 $r4 $r255 (8)
>BB:4 (3 instructions) - idom = BB:3, df = { BB:6 }
> -> BB:6 (forward)
> 64: $p0 mov u32 $r2 0x00000000 (8)
> 65: $p0 mov u32 $r0 $r2 (8)
> 66: $p0 mov u32 $r1 $r2 (8)
>BB:5 (8 instructions) - idom = BB:3, df = { BB:6 }
> -> BB:6 (forward)
> 67: not $p0 rcp f32 $r4 $r4 (8)
> 68: not $p0 mul f32 $r4 $r2 $r4 (8)
> 69: not $p0 mul f32 $r1 $r1 $r4 (8)
> 70: not $p0 mul f32 $r2 $r2 $r4 (8)
> 71: not $p0 mul f32 $r4 $r0 $r4 (8)
> 72: not $p0 neg f32 $r0 $r1 (8)
> 73: not $p0 add f32 $r1 neg $r2 1.000000 (8)
> 74: not $p0 neg f32 $r2 $r4 (8)
>BB:6 (7 instructions) - idom = BB:3, df = { BB:7 }
> -> BB:7 (forward)
> 75: mul f32 $r4 $r0 $r0 (8)
> 76: mad f32 $r4 $r1 $r1 $r4 (8)
> 77: mad f32 $r4 $r2 $r2 $r4 (8)
> 78: rsq f32 $r4 abs $r4 (8)
> 79: mul f32 $r0 $r0 $r4 (8)
> 80: mul f32 $r1 $r1 $r4 (8)
> 81: join mul f32 $r5 $r2 $r4 (8)
>BB:73 (2 instructions) - df = { }
> -> BB:7 (forward)
> 82: mov u32 $r0 $r5 (8)
> 83: join mov u32 $r1 $r5 (8)
>BB:7 (29 instructions) - idom = BB:2, df = { BB:9 }
> -> BB:9 (forward)
> 84: set f32 $r2 gt $r3 $r255 (8)
> 85: set f32 $r4 lt $r3 $r255 (8)
> 86: sub f32 $r2 $r2 $r4 (8)
> 87: abs f32 $r4 $r3 (8)
> 88: add f32 $r6 neg abs $r3 1.000000 (8)
> 89: rsq f32 $r6 $r6 (8)
> 90: rcp f32 $r6 $r6 (8)
> 91: mov u32 $r7 0xbcc19a5f (8)
> 92: mov u32 $r12 0x3da68d87 (8)
> 93: mad f32 $r7 $r4 $r7 $r12 (8)
> 94: mov u32 $r12 0xbe5bc094 (8)
> 95: mad f32 $r7 $r4 $r7 $r12 (8)
> 96: mov u32 $r12 0x3fc90fdb (8)
> 97: mad f32 $r4 $r4 $r7 $r12 (8)
> 98: mul f32 $r4 $r6 $r4 (8)
> 99: add f32 $r4 neg $r4 1.570796 (8)
>100: mul f32 $r2 $r2 $r4 (8)
>101: add f32 $r2 neg $r2 1.570796 (8)
>102: presin f32 $r2 $r2 (8)
>103: sin f32 $r2 $r2 (8)
>104: mul f32 $r2 $r2 0.200000 (8)
>105: mul f32 $r3 $r3 0.200000 (8)
>106: mul f32 $r4 $r3 neg $r0 (8)
>107: mul f32 $r6 $r3 neg $r1 (8)
>108: mul f32 $r3 $r3 neg $r5 (8)
>109: mad f32 $r4 $r2 neg $r0 neg $r4 (8)
>110: mad f32 $r6 $r2 neg $r1 neg $r6 (8)
>111: mad f32 $r2 $r2 neg $r5 neg $r3 (8)
>112: join mov f32 $r3 -0.000000 (8)
>BB:8 (4 instructions) - idom = BB:0, df = { BB:9 }
> -> BB:9 (forward)
>113: mov f32 $r3 0.000000 (8)
>114: mov f32 $r6 -0.200000 (8)
>115: mov u32 $r4 $r3 (8)
>116: join mov u32 $r2 $r3 (8)
>BB:9 (68 instructions) - idom = BB:0, df = { }
> -> BB:10 (tree)
>117: shl u32 $r5 $r8 0x00000004 (8)
>118: add u32 { $r0 $c0 } $r5 c7[0x320] (8)
>119: add u32 $r1 $r255 c7[0x324] $c0 (8)
>120: add u32 $r7 $r5 0x00000004 (8)
>121: set u8 $p0 gt u32 $r7 c7[0x328] (8)
>122: not $p0 ld  u32 $r12 g[$r0d+0x0] (8)
>123: $p0 mov u32 $r12 0x00000000 (8)
>124: add u32 $r13 $r5 0x00000008 (8)
>125: set u8 $p0 gt u32 $r13 c7[0x328] (8)
>126: not $p0 ld  u32 $r14 g[$r0d+0x4] (8)
>127: $p0 mov u32 $r14 0x00000000 (8)
>128: add u32 $r15 $r5 0x0000000c (8)
>129: set u8 $p0 gt u32 $r15 c7[0x328] (8)
>130: not $p0 ld  u32 $r16 g[$r0d+0x8] (8)
>131: $p0 mov u32 $r16 0x00000000 (8)
>132: add u32 $r17 $r5 0x00000010 (8)
>133: set u8 $p0 gt u32 $r17 c7[0x328] (8)
>134: not $p0 ld  u32 $r18 g[$r0d+0xc] (8)
>135: $p0 mov u32 $r18 0x00000000 (8)
>136: add u32 { $r0 $c0 } $r5 c7[0x300] (8)
>137: add u32 $r1 $r255 c7[0x304] $c0 (8)
>138: set u8 $p0 gt u32 $r7 c7[0x308] (8)
>139: not $p0 ld  u32 $r19 g[$r0d+0x0] (8)
>140: $p0 mov u32 $r19 0x00000000 (8)
>141: set u8 $p0 gt u32 $r13 c7[0x308] (8)
>142: not $p0 ld  u32 $r20 g[$r0d+0x4] (8)
>143: $p0 mov u32 $r20 0x00000000 (8)
>144: set u8 $p0 gt u32 $r15 c7[0x308] (8)
>145: not $p0 ld  u32 $r21 g[$r0d+0x8] (8)
>146: $p0 mov u32 $r21 0x00000000 (8)
>147: set u8 $p0 gt u32 $r17 c7[0x308] (8)
>148: not $p0 ld  u32 $r0 g[$r0d+0xc] (8)
>149: $p0 mov u32 $r0 0x00000000 (8)
>150: mul f32 $r1 $r4 10.000000 (8)
>151: mul f32 $r4 $r6 10.000000 (8)
>152: mul f32 $r2 $r2 10.000000 (8)
>153: mul f32 $r3 $r3 10.000000 (8)
>154: ld  u32 $r6 c0[0x10] (8)
>155: mul f32 $r6 $r6 c0[0x10] (8)
>156: mad f32 $r12 $r12 2.000000 neg $r19 (8)
>157: mad f32 $r14 $r14 2.000000 neg $r20 (8)
>158: mad f32 $r16 $r16 2.000000 neg $r21 (8)
>159: mad f32 $r0 $r18 2.000000 neg $r0 (8)
>160: mad f32 $r12 $r1 $r6 $r12 (8)
>161: mad f32 $r4 $r4 $r6 $r14 (8)
>162: mad f32 $r2 $r2 $r6 $r16 (8)
>163: mad f32 $r3 $r3 $r6 $r0 (8)
>164: add u32 { $r0 $c0 } $r5 c7[0x330] (8)
>165: add u32 $r1 $r255 c7[0x334] $c0 (8)
>166: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>167: not $p0 st  u32 # g[$r0d+0x0] $r12 (8)
>168: set u8 $p0 gt u32 $r13 c7[0x338] (8)
>169: not $p0 st  u32 # g[$r0d+0x4] $r4 (8)
>170: set u8 $p0 gt u32 $r15 c7[0x338] (8)
>171: not $p0 st  u32 # g[$r0d+0x8] $r2 (8)
>172: set u8 $p0 gt u32 $r17 c7[0x338] (8)
>173: not $p0 st  u32 # g[$r0d+0xc] $r3 (8)
>174: membar (SUBOP:7) - # (8)
>175: bar u32 # $r255 $r255 (8)
>176: mov u32 $r12 0x00000000 (8)
>177: prebreak BB:11 (8)
>178: mov u32 $r13 $r11 (8)
>179: mov u32 $r14 $r11 (8)
>180: mov u32 $r15 $r11 (8)
>181: mov u32 $r16 $r11 (8)
>182: mov u32 $r17 $r11 (8)
>183: mov u32 $r18 $r11 (8)
>184: mov u32 $r19 $r11 (8)
>BB:10 (1 instructions) - idom = BB:9, df = { BB:10 }
> -> BB:13 (forward)
> -> BB:12 (tree)
>185: set u8 $p0 ge s32 $r12 4 (8)
>BB:12 (1 instructions) - idom = BB:10, df = { }
> -> BB:11 (cross)
>186: $p0 break BB:11 (8)
>BB:13 (2 instructions) - idom = BB:10, df = { BB:10 }
> -> BB:14 (tree)
>187: mov u32 $r20 0x00000000 (8)
>188: prebreak BB:15 (8)
>BB:14 (1 instructions) - idom = BB:13, df = { BB:10 BB:14 }
> -> BB:17 (forward)
> -> BB:16 (tree)
>189: set u8 $p0 ge s32 $r20 2 (8)
>BB:16 (1 instructions) - idom = BB:14, df = { BB:10 }
> -> BB:15 (cross)
>190: $p0 break BB:15 (8)
>BB:17 (12 instructions) - idom = BB:14, df = { BB:14 }
> -> BB:25 (tree)
> -> BB:18 (tree)
>191: mov u32 $r4 0x00000002 (8)
>192: mov u32 $r0 $r9 (8)
>193: mov u32 $r1 $r4 (8)
>194: call abs BUILTIN:1 (8)
>195: mov u32 $r5 $r1 (8)
>196: mov u32 $r0 $r10 (8)
>197: mov u32 $r1 $r4 (8)
>198: call abs BUILTIN:1 (8)
>199: set u8 $p0 eq u32 $r5 $r20 (8)
>200: joinat BB:35 (8)
>201: set and u8 $p0 eq u32 $r1 $r20 $p0 (8)
>202: not $p0 bra BB:25 (8)
>BB:18 (25 instructions) - idom = BB:17, df = { BB:35 }
> -> BB:61 (tree)
> -> BB:19 (tree)
>203: shl u32 $r2 $r8 0x00000004 (8)
>204: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>205: add u32 $r1 $r255 c7[0x334] $c0 (8)
>206: add u32 $r3 $r2 0x00000004 (8)
>207: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>208: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>209: $p0 mov u32 $r6 0x00000000 (8)
>210: add u32 $r3 $r2 0x00000008 (8)
>211: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>212: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>213: $p0 mov u32 $r7 0x00000000 (8)
>214: add u32 $r3 $r2 0x0000000c (8)
>215: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>216: not $p0 ld  u32 $r21 g[$r0d+0x8] (8)
>217: $p0 mov u32 $r21 0x00000000 (8)
>218: add u32 $r2 $r2 0x00000010 (8)
>219: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>220: not $p0 ld  u32 $r22 g[$r0d+0xc] (8)
>221: $p0 mov u32 $r22 0x00000000 (8)
>222: add u32 $r0 $r8 0x00000001 (8)
>223: ld  u32 $r1 c0[0x0] (8)
>224: call abs BUILTIN:1 (8)
>225: joinat BB:20 (8)
>226: set u8 $p0 lt s32 $r10 $r1 (8)
>227: not $p0 join BB:20 (8)
>BB:19 (84 instructions) - idom = BB:18, df = { BB:20 }
> -> BB:20 (forward)
>228: shl u32 $r28 $r8 0x00000004 (8)
>229: add u32 $r4 $r28 0x00000010 (8)
>230: add u32 { $r0 $c0 } $r4 c7[0x330] (8)
>231: add u32 $r1 $r255 c7[0x334] $c0 (8)
>232: add u32 $r2 $r4 0x00000004 (8)
>233: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>234: cvt u8 $r29 $p0 (8)
>235: cvt u8 $p0 $r29 (8)
>236: not $p0 ld  u32 $r5 g[$r0d+0x0] (8)
>237: $p0 mov u32 $r5 0x00000000 (8)
>238: add u32 $r2 $r4 0x00000008 (8)
>239: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>240: not $p0 ld  u32 $r14 g[$r0d+0x4] (8)
>241: $p0 mov u32 $r14 0x00000000 (8)
>242: add u32 $r2 $r4 0x0000000c (8)
>243: set u8 $p1 gt u32 $r2 c7[0x338] (8)
>244: not $p1 ld  u32 $r15 g[$r0d+0x8] (8)
>245: $p1 mov u32 $r15 0x00000000 (8)
>246: add u32 $r2 $r4 0x00000010 (8)
>247: set u8 $p2 gt u32 $r2 c7[0x338] (8)
>248: not $p2 ld  u32 $r16 g[$r0d+0xc] (8)
>249: $p2 mov u32 $r16 0x00000000 (8)
>250: add f32 $r2 $r6 neg $r5 (8)
>251: add f32 $r3 $r7 neg $r14 (8)
>252: add f32 $r13 $r21 neg $r15 (8)
>253: add f32 $r23 $r22 neg $r16 (8)
>254: mul f32 $r24 $r2 $r2 (8)
>255: mad f32 $r24 $r3 $r3 $r24 (8)
>256: mad f32 $r24 $r13 $r13 $r24 (8)
>257: mad f32 $r24 $r23 $r23 $r24 (8)
>258: rsq f32 $r24 $r24 (8)
>259: rcp f32 $r25 $r24 (8)
>260: add f32 $r25 neg $r25 c0[0x20] (8)
>261: mul f32 $r25 $r25 0.350000 (8)
>262: mul f32 $r24 $r25 $r24 (8)
>263: mul f32 $r25 $r24 $r2 (8)
>264: mul f32 $r26 $r24 $r3 (8)
>265: mul f32 $r13 $r24 $r13 (8)
>266: mul f32 $r23 $r24 $r23 (8)
>267: add u32 { $r2 $c0 } $r28 c7[0x330] (8)
>268: add u32 $r3 $r255 c7[0x334] $c0 (8)
>269: add u32 $r24 $r28 0x00000004 (8)
>270: set u8 $p3 gt u32 $r24 c7[0x338] (8)
>271: not $p3 ld  u32 $r24 g[$r2d+0x0] (8)
>272: $p3 mov u32 $r24 0x00000000 (8)
>273: add u32 $r27 $r28 0x00000008 (8)
>274: set u8 $p4 gt u32 $r27 c7[0x338] (8)
>275: not $p4 ld  u32 $r27 g[$r2d+0x4] (8)
>276: $p4 mov u32 $r27 0x00000000 (8)
>277: add u32 $r28 $r28 0x0000000c (8)
>278: set u8 $p5 gt u32 $r28 c7[0x338] (8)
>279: not $p5 ld  u32 $r28 g[$r2d+0x8] (8)
>280: $p5 mov u32 $r28 0x00000000 (8)
>281: set u8 $p6 gt u32 $r4 c7[0x338] (8)
>282: not $p6 ld  u32 $r4 g[$r2d+0xc] (8)
>283: $p6 mov u32 $r4 0x00000000 (8)
>284: add f32 $r24 $r24 $r25 (8)
>285: add f32 $r27 $r27 $r26 (8)
>286: add f32 $r28 $r28 $r13 (8)
>287: add f32 $r4 $r4 $r23 (8)
>288: not $p3 st  u32 # g[$r2d+0x0] $r24 (8)
>289: not $p4 st  u32 # g[$r2d+0x4] $r27 (8)
>290: not $p5 st  u32 # g[$r2d+0x8] $r28 (8)
>291: not $p6 st  u32 # g[$r2d+0xc] $r4 (8)
>292: cvt u8 $p3 $r29 (8)
>293: not $p3 ld  u32 $r2 g[$r0d+0x0] (8)
>294: $p3 mov u32 $r2 0x00000000 (8)
>295: not $p0 ld  u32 $r3 g[$r0d+0x4] (8)
>296: $p0 mov u32 $r3 0x00000000 (8)
>297: not $p1 ld  u32 $r4 g[$r0d+0x8] (8)
>298: $p1 mov u32 $r4 0x00000000 (8)
>299: not $p2 ld  u32 $r24 g[$r0d+0xc] (8)
>300: $p2 mov u32 $r24 0x00000000 (8)
>301: add f32 $r2 $r2 neg $r25 (8)
>302: add f32 $r3 $r3 neg $r26 (8)
>303: add f32 $r4 $r4 neg $r13 (8)
>304: add f32 $r13 $r24 neg $r23 (8)
>305: cvt u8 $p3 $r29 (8)
>306: not $p3 st  u32 # g[$r0d+0x0] $r2 (8)
>307: not $p0 st  u32 # g[$r0d+0x4] $r3 (8)
>308: not $p1 st  u32 # g[$r0d+0x8] $r4 (8)
>309: not $p2 st  u32 # g[$r0d+0xc] $r13 (8)
>310: membar (SUBOP:7) - # (8)
>311: join mov u32 $r13 $r5 (8)
>BB:61 (0 instructions) - df = { }
> -> BB:20 (forward)
>BB:20 (6 instructions) - idom = BB:18, df = { BB:35 }
> -> BB:62 (tree)
> -> BB:21 (tree)
>312: ld  u32 $r0 c0[0x0] (8)
>313: add u32 $r4 $r8 c0[0x0] (8)
>314: mul u32 $r0 $r0 c0[0x0] (8)
>315: joinat BB:22 (8)
>316: set u8 $p0 lt s32 $r4 $r0 (8)
>317: not $p0 join BB:22 (8)
>BB:21 (87 instructions) - idom = BB:20, df = { BB:22 }
> -> BB:22 (forward)
>318: shl u32 $r2 $r4 0x00000004 (8)
>319: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>320: add u32 $r1 $r255 c7[0x334] $c0 (8)
>321: add u32 $r3 $r2 0x00000004 (8)
>322: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>323: cvt u8 $r30 $p0 (8)
>324: cvt u8 $p0 $r30 (8)
>325: not $p0 ld  u32 $r5 g[$r0d+0x0] (8)
>326: $p0 mov u32 $r5 0x00000000 (8)
>327: add u32 $r3 $r2 0x00000008 (8)
>328: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>329: not $p0 ld  u32 $r11 g[$r0d+0x4] (8)
>330: $p0 mov u32 $r11 0x00000000 (8)
>331: add u32 $r3 $r2 0x0000000c (8)
>332: set u8 $p1 gt u32 $r3 c7[0x338] (8)
>333: not $p1 ld  u32 $r19 g[$r0d+0x8] (8)
>334: $p1 mov u32 $r19 0x00000000 (8)
>335: add u32 $r2 $r2 0x00000010 (8)
>336: set u8 $p2 gt u32 $r2 c7[0x338] (8)
>337: not $p2 ld  u32 $r23 g[$r0d+0xc] (8)
>338: $p2 mov u32 $r23 0x00000000 (8)
>339: add f32 $r2 $r6 neg $r5 (8)
>340: add f32 $r3 $r7 neg $r11 (8)
>341: add f32 $r17 $r21 neg $r19 (8)
>342: add f32 $r18 $r22 neg $r23 (8)
>343: mul f32 $r24 $r2 $r2 (8)
>344: mad f32 $r24 $r3 $r3 $r24 (8)
>345: mad f32 $r24 $r17 $r17 $r24 (8)
>346: mad f32 $r24 $r18 $r18 $r24 (8)
>347: rsq f32 $r24 $r24 (8)
>348: rcp f32 $r25 $r24 (8)
>349: add f32 $r25 neg $r25 c0[0x20] (8)
>350: mul f32 $r25 $r25 0.350000 (8)
>351: mul f32 $r24 $r25 $r24 (8)
>352: mul f32 $r25 $r24 $r2 (8)
>353: mul f32 $r26 $r24 $r3 (8)
>354: mul f32 $r17 $r24 $r17 (8)
>355: mul f32 $r18 $r24 $r18 (8)
>356: shl u32 $r24 $r8 0x00000004 (8)
>357: add u32 { $r2 $c0 } $r24 c7[0x330] (8)
>358: add u32 $r3 $r255 c7[0x334] $c0 (8)
>359: add u32 $r27 $r24 0x00000004 (8)
>360: set u8 $p3 gt u32 $r27 c7[0x338] (8)
>361: not $p3 ld  u32 $r27 g[$r2d+0x0] (8)
>362: $p3 mov u32 $r27 0x00000000 (8)
>363: add u32 $r28 $r24 0x00000008 (8)
>364: set u8 $p4 gt u32 $r28 c7[0x338] (8)
>365: not $p4 ld  u32 $r28 g[$r2d+0x4] (8)
>366: $p4 mov u32 $r28 0x00000000 (8)
>367: add u32 $r29 $r24 0x0000000c (8)
>368: set u8 $p5 gt u32 $r29 c7[0x338] (8)
>369: not $p5 ld  u32 $r29 g[$r2d+0x8] (8)
>370: $p5 mov u32 $r29 0x00000000 (8)
>371: add u32 $r24 $r24 0x00000010 (8)
>372: set u8 $p6 gt u32 $r24 c7[0x338] (8)
>373: not $p6 ld  u32 $r24 g[$r2d+0xc] (8)
>374: $p6 mov u32 $r24 0x00000000 (8)
>375: add f32 $r27 $r27 $r25 (8)
>376: add f32 $r28 $r28 $r26 (8)
>377: add f32 $r29 $r29 $r17 (8)
>378: add f32 $r24 $r24 $r18 (8)
>379: not $p3 st  u32 # g[$r2d+0x0] $r27 (8)
>380: not $p4 st  u32 # g[$r2d+0x4] $r28 (8)
>381: not $p5 st  u32 # g[$r2d+0x8] $r29 (8)
>382: not $p6 st  u32 # g[$r2d+0xc] $r24 (8)
>383: cvt u8 $p3 $r30 (8)
>384: not $p3 ld  u32 $r2 g[$r0d+0x0] (8)
>385: $p3 mov u32 $r2 0x00000000 (8)
>386: not $p0 ld  u32 $r3 g[$r0d+0x4] (8)
>387: $p0 mov u32 $r3 0x00000000 (8)
>388: not $p1 ld  u32 $r24 g[$r0d+0x8] (8)
>389: $p1 mov u32 $r24 0x00000000 (8)
>390: not $p2 ld  u32 $r27 g[$r0d+0xc] (8)
>391: $p2 mov u32 $r27 0x00000000 (8)
>392: add f32 $r2 $r2 neg $r25 (8)
>393: add f32 $r3 $r3 neg $r26 (8)
>394: add f32 $r17 $r24 neg $r17 (8)
>395: add f32 $r18 $r27 neg $r18 (8)
>396: cvt u8 $p3 $r30 (8)
>397: not $p3 st  u32 # g[$r0d+0x0] $r2 (8)
>398: not $p0 st  u32 # g[$r0d+0x4] $r3 (8)
>399: not $p1 st  u32 # g[$r0d+0x8] $r17 (8)
>400: not $p2 st  u32 # g[$r0d+0xc] $r18 (8)
>401: membar (SUBOP:7) - # (8)
>402: mov u32 $r17 $r5 (8)
>403: mov u32 $r18 $r11 (8)
>404: join mov u32 $r11 $r23 (8)
>BB:62 (0 instructions) - df = { }
> -> BB:22 (forward)
>BB:22 (10 instructions) - idom = BB:20, df = { BB:35 }
> -> BB:63 (tree)
> -> BB:23 (tree)
>405: add u32 $r0 $r8 0x00000001 (8)
>406: ld  u32 $r1 c0[0x0] (8)
>407: add u32 $r5 $r0 c0[0x0] (8)
>408: mul u32 $r23 $r1 c0[0x0] (8)
>409: mov u32 $r0 $r5 (8)
>410: call abs BUILTIN:1 (8)
>411: set u8 $p0 lt s32 $r5 $r23 (8)
>412: joinat BB:24 (8)
>413: set and u8 $p0 lt s32 $r10 $r1 $p0 (8)
>414: not $p0 join BB:24 (8)
>BB:23 (296 instructions) - idom = BB:22, df = { BB:24 }
> -> BB:24 (forward)
>415: shl u32 $r2 $r5 0x00000004 (8)
>416: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>417: add u32 $r1 $r255 c7[0x334] $c0 (8)
>418: add u32 $r3 $r2 0x00000004 (8)
>419: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>420: not $p0 ld  u32 $r23 g[$r0d+0x0] (8)
>421: $p0 mov u32 $r23 0x00000000 (8)
>422: add u32 $r3 $r2 0x00000008 (8)
>423: set u8 $p1 gt u32 $r3 c7[0x338] (8)
>424: not $p1 ld  u32 $r24 g[$r0d+0x4] (8)
>425: $p1 mov u32 $r24 0x00000000 (8)
>426: add u32 $r3 $r2 0x0000000c (8)
>427: set u8 $p2 gt u32 $r3 c7[0x338] (8)
>428: not $p2 ld  u32 $r25 g[$r0d+0x8] (8)
>429: $p2 mov u32 $r25 0x00000000 (8)
>430: add u32 $r2 $r2 0x00000010 (8)
>431: set u8 $p3 gt u32 $r2 c7[0x338] (8)
>432: not $p3 ld  u32 $r26 g[$r0d+0xc] (8)
>433: $p3 mov u32 $r26 0x00000000 (8)
>434: add f32 $r2 $r13 neg $r23 (8)
>435: add f32 $r3 $r14 neg $r24 (8)
>436: add f32 $r5 $r15 neg $r25 (8)
>437: add f32 $r27 $r16 neg $r26 (8)
>438: mul f32 $r28 $r2 $r2 (8)
>439: mad f32 $r28 $r3 $r3 $r28 (8)
>440: mad f32 $r28 $r5 $r5 $r28 (8)
>441: mad f32 $r28 $r27 $r27 $r28 (8)
>442: rsq f32 $r28 $r28 (8)
>443: rcp f32 $r29 $r28 (8)
>444: add f32 $r29 neg $r29 c0[0x20] (8)
>445: mul f32 $r29 $r29 0.350000 (8)
>446: mul f32 $r28 $r29 $r28 (8)
>447: mul f32 $r29 $r28 $r2 (8)
>448: mul f32 $r30 $r28 $r3 (8)
>449: mul f32 $r5 $r28 $r5 (8)
>450: mul f32 $r27 $r28 $r27 (8)
>451: shl u32 $r36 $r8 0x00000004 (8)
>452: add u32 $r28 $r36 0x00000010 (8)
>453: add u32 { $r2 $c0 } $r28 c7[0x330] (8)
>454: add u32 $r3 $r255 c7[0x334] $c0 (8)
>455: add u32 $r31 $r28 0x00000004 (8)
>456: set u8 $p4 gt u32 $r31 c7[0x338] (8)
>457: cvt u8 $r44 $p4 (8)
>458: cvt u8 $p4 $r44 (8)
>459: not $p4 ld  u32 $r31 g[$r2d+0x0] (8)
>460: $p4 mov u32 $r31 0x00000000 (8)
>461: add u32 $r32 $r28 0x00000008 (8)
>462: set u8 $p4 gt u32 $r32 c7[0x338] (8)
>463: cvt u8 $r43 $p4 (8)
>464: cvt u8 $p4 $r43 (8)
>465: not $p4 ld  u32 $r32 g[$r2d+0x4] (8)
>466: $p4 mov u32 $r32 0x00000000 (8)
>467: add u32 $r33 $r28 0x0000000c (8)
>468: set u8 $p4 gt u32 $r33 c7[0x338] (8)
>469: cvt u8 $r42 $p4 (8)
>470: cvt u8 $p4 $r42 (8)
>471: not $p4 ld  u32 $r33 g[$r2d+0x8] (8)
>472: $p4 mov u32 $r33 0x00000000 (8)
>473: add u32 $r34 $r28 0x00000010 (8)
>474: set u8 $p4 gt u32 $r34 c7[0x338] (8)
>475: cvt u8 $r41 $p4 (8)
>476: cvt u8 $p4 $r41 (8)
>477: not $p4 ld  u32 $r34 g[$r2d+0xc] (8)
>478: $p4 mov u32 $r34 0x00000000 (8)
>479: add f32 $r31 $r31 $r29 (8)
>480: add f32 $r32 $r32 $r30 (8)
>481: add f32 $r33 $r33 $r5 (8)
>482: add f32 $r34 $r34 $r27 (8)
>483: cvt u8 $p4 $r44 (8)
>484: not $p4 st  u32 # g[$r2d+0x0] $r31 (8)
>485: cvt u8 $p4 $r43 (8)
>486: not $p4 st  u32 # g[$r2d+0x4] $r32 (8)
>487: cvt u8 $p4 $r42 (8)
>488: not $p4 st  u32 # g[$r2d+0x8] $r33 (8)
>489: cvt u8 $p4 $r41 (8)
>490: not $p4 st  u32 # g[$r2d+0xc] $r34 (8)
>491: not $p0 ld  u32 $r31 g[$r0d+0x0] (8)
>492: $p0 mov u32 $r31 0x00000000 (8)
>493: not $p1 ld  u32 $r32 g[$r0d+0x4] (8)
>494: $p1 mov u32 $r32 0x00000000 (8)
>495: not $p2 ld  u32 $r33 g[$r0d+0x8] (8)
>496: $p2 mov u32 $r33 0x00000000 (8)
>497: not $p3 ld  u32 $r34 g[$r0d+0xc] (8)
>498: $p3 mov u32 $r34 0x00000000 (8)
>499: add f32 $r29 $r31 neg $r29 (8)
>500: add f32 $r30 $r32 neg $r30 (8)
>501: add f32 $r5 $r33 neg $r5 (8)
>502: add f32 $r27 $r34 neg $r27 (8)
>503: not $p0 st  u32 # g[$r0d+0x0] $r29 (8)
>504: not $p1 st  u32 # g[$r0d+0x4] $r30 (8)
>505: not $p2 st  u32 # g[$r0d+0x8] $r5 (8)
>506: not $p3 st  u32 # g[$r0d+0xc] $r27 (8)
>507: membar (SUBOP:7) - # (8)
>508: add f32 $r5 $r17 neg $r23 (8)
>509: add f32 $r27 $r18 neg $r24 (8)
>510: add f32 $r29 $r19 neg $r25 (8)
>511: add f32 $r30 $r11 neg $r26 (8)
>512: mul f32 $r31 $r5 $r5 (8)
>513: mad f32 $r31 $r27 $r27 $r31 (8)
>514: mad f32 $r31 $r29 $r29 $r31 (8)
>515: mad f32 $r31 $r30 $r30 $r31 (8)
>516: rsq f32 $r31 $r31 (8)
>517: rcp f32 $r32 $r31 (8)
>518: add f32 $r32 neg $r32 c0[0x20] (8)
>519: mul f32 $r32 $r32 0.350000 (8)
>520: mul f32 $r31 $r32 $r31 (8)
>521: mul f32 $r32 $r31 $r5 (8)
>522: mul f32 $r27 $r31 $r27 (8)
>523: mul f32 $r29 $r31 $r29 (8)
>524: mul f32 $r30 $r31 $r30 (8)
>525: shl u32 $r31 $r4 0x00000004 (8)
>526: add u32 { $r4 $c0 } $r31 c7[0x330] (8)
>527: add u32 $r5 $r255 c7[0x334] $c0 (8)
>528: add u32 $r33 $r31 0x00000004 (8)
>529: set u8 $p4 gt u32 $r33 c7[0x338] (8)
>530: cvt u8 $r40 $p4 (8)
>531: cvt u8 $p4 $r40 (8)
>532: not $p4 ld  u32 $r33 g[$r4d+0x0] (8)
>533: $p4 mov u32 $r33 0x00000000 (8)
>534: add u32 $r34 $r31 0x00000008 (8)
>535: set u8 $p4 gt u32 $r34 c7[0x338] (8)
>536: cvt u8 $r39 $p4 (8)
>537: cvt u8 $p4 $r39 (8)
>538: not $p4 ld  u32 $r34 g[$r4d+0x4] (8)
>539: $p4 mov u32 $r34 0x00000000 (8)
>540: add u32 $r35 $r31 0x0000000c (8)
>541: set u8 $p4 gt u32 $r35 c7[0x338] (8)
>542: cvt u8 $r38 $p4 (8)
>543: cvt u8 $p4 $r38 (8)
>544: not $p4 ld  u32 $r35 g[$r4d+0x8] (8)
>545: $p4 mov u32 $r35 0x00000000 (8)
>546: add u32 $r31 $r31 0x00000010 (8)
>547: set u8 $p4 gt u32 $r31 c7[0x338] (8)
>548: cvt u8 $r37 $p4 (8)
>549: cvt u8 $p4 $r37 (8)
>550: not $p4 ld  u32 $r31 g[$r4d+0xc] (8)
>551: $p4 mov u32 $r31 0x00000000 (8)
>552: add f32 $r33 $r33 $r32 (8)
>553: add f32 $r34 $r34 $r27 (8)
>554: add f32 $r35 $r35 $r29 (8)
>555: add f32 $r31 $r31 $r30 (8)
>556: cvt u8 $p4 $r40 (8)
>557: not $p4 st  u32 # g[$r4d+0x0] $r33 (8)
>558: cvt u8 $p4 $r39 (8)
>559: not $p4 st  u32 # g[$r4d+0x4] $r34 (8)
>560: cvt u8 $p4 $r38 (8)
>561: not $p4 st  u32 # g[$r4d+0x8] $r35 (8)
>562: cvt u8 $p4 $r37 (8)
>563: not $p4 st  u32 # g[$r4d+0xc] $r31 (8)
>564: not $p0 ld  u32 $r31 g[$r0d+0x0] (8)
>565: $p0 mov u32 $r31 0x00000000 (8)
>566: not $p1 ld  u32 $r33 g[$r0d+0x4] (8)
>567: $p1 mov u32 $r33 0x00000000 (8)
>568: not $p2 ld  u32 $r34 g[$r0d+0x8] (8)
>569: $p2 mov u32 $r34 0x00000000 (8)
>570: not $p3 ld  u32 $r35 g[$r0d+0xc] (8)
>571: $p3 mov u32 $r35 0x00000000 (8)
>572: add f32 $r31 $r31 neg $r32 (8)
>573: add f32 $r27 $r33 neg $r27 (8)
>574: add f32 $r29 $r34 neg $r29 (8)
>575: add f32 $r30 $r35 neg $r30 (8)
>576: not $p0 st  u32 # g[$r0d+0x0] $r31 (8)
>577: not $p1 st  u32 # g[$r0d+0x4] $r27 (8)
>578: not $p2 st  u32 # g[$r0d+0x8] $r29 (8)
>579: not $p3 st  u32 # g[$r0d+0xc] $r30 (8)
>580: membar (SUBOP:7) - # (8)
>581: add f32 $r6 $r6 neg $r23 (8)
>582: add f32 $r7 $r7 neg $r24 (8)
>583: add f32 $r21 $r21 neg $r25 (8)
>584: add f32 $r22 $r22 neg $r26 (8)
>585: mul f32 $r23 $r6 $r6 (8)
>586: mad f32 $r23 $r7 $r7 $r23 (8)
>587: mad f32 $r23 $r21 $r21 $r23 (8)
>588: mad f32 $r23 $r22 $r22 $r23 (8)
>589: rsq f32 $r23 $r23 (8)
>590: rcp f32 $r24 $r23 (8)
>591: add f32 $r24 neg $r24 c0[0x30] (8)
>592: mul f32 $r24 $r24 0.350000 (8)
>593: mul f32 $r23 $r24 $r23 (8)
>594: mul f32 $r24 $r23 $r6 (8)
>595: mul f32 $r25 $r23 $r7 (8)
>596: mul f32 $r21 $r23 $r21 (8)
>597: mul f32 $r22 $r23 $r22 (8)
>598: add u32 { $r6 $c0 } $r36 c7[0x330] (8)
>599: add u32 $r7 $r255 c7[0x334] $c0 (8)
>600: add u32 $r23 $r36 0x00000004 (8)
>601: set u8 $p4 gt u32 $r23 c7[0x338] (8)
>602: cvt u8 $r29 $p4 (8)
>603: cvt u8 $p4 $r29 (8)
>604: not $p4 ld  u32 $r23 g[$r6d+0x0] (8)
>605: $p4 mov u32 $r23 0x00000000 (8)
>606: add u32 $r26 $r36 0x00000008 (8)
>607: set u8 $p4 gt u32 $r26 c7[0x338] (8)
>608: cvt u8 $r30 $p4 (8)
>609: cvt u8 $p4 $r30 (8)
>610: not $p4 ld  u32 $r26 g[$r6d+0x4] (8)
>611: $p4 mov u32 $r26 0x00000000 (8)
>612: add u32 $r27 $r36 0x0000000c (8)
>613: set u8 $p4 gt u32 $r27 c7[0x338] (8)
>614: not $p4 ld  u32 $r27 g[$r6d+0x8] (8)
>615: $p4 mov u32 $r27 0x00000000 (8)
>616: set u8 $p5 gt u32 $r28 c7[0x338] (8)
>617: not $p5 ld  u32 $r28 g[$r6d+0xc] (8)
>618: $p5 mov u32 $r28 0x00000000 (8)
>619: add f32 $r23 $r23 $r24 (8)
>620: add f32 $r26 $r26 $r25 (8)
>621: add f32 $r27 $r27 $r21 (8)
>622: add f32 $r28 $r28 $r22 (8)
>623: cvt u8 $p6 $r29 (8)
>624: not $p6 st  u32 # g[$r6d+0x0] $r23 (8)
>625: cvt u8 $p6 $r30 (8)
>626: not $p6 st  u32 # g[$r6d+0x4] $r26 (8)
>627: not $p4 st  u32 # g[$r6d+0x8] $r27 (8)
>628: not $p5 st  u32 # g[$r6d+0xc] $r28 (8)
>629: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>630: $p0 mov u32 $r6 0x00000000 (8)
>631: not $p1 ld  u32 $r7 g[$r0d+0x4] (8)
>632: $p1 mov u32 $r7 0x00000000 (8)
>633: not $p2 ld  u32 $r23 g[$r0d+0x8] (8)
>634: $p2 mov u32 $r23 0x00000000 (8)
>635: not $p3 ld  u32 $r26 g[$r0d+0xc] (8)
>636: $p3 mov u32 $r26 0x00000000 (8)
>637: add f32 $r6 $r6 neg $r24 (8)
>638: add f32 $r7 $r7 neg $r25 (8)
>639: add f32 $r21 $r23 neg $r21 (8)
>640: add f32 $r22 $r26 neg $r22 (8)
>641: not $p0 st  u32 # g[$r0d+0x0] $r6 (8)
>642: not $p1 st  u32 # g[$r0d+0x4] $r7 (8)
>643: not $p2 st  u32 # g[$r0d+0x8] $r21 (8)
>644: not $p3 st  u32 # g[$r0d+0xc] $r22 (8)
>645: add f32 $r0 $r13 neg $r17 (8)
>646: add f32 $r1 $r14 neg $r18 (8)
>647: add f32 $r6 $r15 neg $r19 (8)
>648: add f32 $r7 $r16 neg $r11 (8)
>649: mul f32 $r21 $r0 $r0 (8)
>650: mad f32 $r21 $r1 $r1 $r21 (8)
>651: mad f32 $r21 $r6 $r6 $r21 (8)
>652: mad f32 $r21 $r7 $r7 $r21 (8)
>653: rsq f32 $r21 $r21 (8)
>654: rcp f32 $r22 $r21 (8)
>655: add f32 $r22 neg $r22 c0[0x30] (8)
>656: mul f32 $r22 $r22 0.350000 (8)
>657: mul f32 $r21 $r22 $r21 (8)
>658: mul f32 $r0 $r21 $r0 (8)
>659: mul f32 $r1 $r21 $r1 (8)
>660: mul f32 $r6 $r21 $r6 (8)
>661: mul f32 $r7 $r21 $r7 (8)
>662: cvt u8 $p0 $r44 (8)
>663: not $p0 ld  u32 $r21 g[$r2d+0x0] (8)
>664: $p0 mov u32 $r21 0x00000000 (8)
>665: cvt u8 $p0 $r43 (8)
>666: not $p0 ld  u32 $r22 g[$r2d+0x4] (8)
>667: $p0 mov u32 $r22 0x00000000 (8)
>668: cvt u8 $p0 $r42 (8)
>669: not $p0 ld  u32 $r23 g[$r2d+0x8] (8)
>670: $p0 mov u32 $r23 0x00000000 (8)
>671: cvt u8 $p0 $r41 (8)
>672: not $p0 ld  u32 $r24 g[$r2d+0xc] (8)
>673: $p0 mov u32 $r24 0x00000000 (8)
>674: add f32 $r21 $r21 $r0 (8)
>675: add f32 $r22 $r22 $r1 (8)
>676: add f32 $r23 $r23 $r6 (8)
>677: add f32 $r24 $r24 $r7 (8)
>678: cvt u8 $p0 $r44 (8)
>679: not $p0 st  u32 # g[$r2d+0x0] $r21 (8)
>680: cvt u8 $p0 $r43 (8)
>681: not $p0 st  u32 # g[$r2d+0x4] $r22 (8)
>682: cvt u8 $p0 $r42 (8)
>683: not $p0 st  u32 # g[$r2d+0x8] $r23 (8)
>684: cvt u8 $p0 $r41 (8)
>685: not $p0 st  u32 # g[$r2d+0xc] $r24 (8)
>686: cvt u8 $p0 $r40 (8)
>687: not $p0 ld  u32 $r2 g[$r4d+0x0] (8)
>688: $p0 mov u32 $r2 0x00000000 (8)
>689: cvt u8 $p0 $r39 (8)
>690: not $p0 ld  u32 $r3 g[$r4d+0x4] (8)
>691: $p0 mov u32 $r3 0x00000000 (8)
>692: cvt u8 $p0 $r38 (8)
>693: not $p0 ld  u32 $r21 g[$r4d+0x8] (8)
>694: $p0 mov u32 $r21 0x00000000 (8)
>695: cvt u8 $p0 $r37 (8)
>696: not $p0 ld  u32 $r22 g[$r4d+0xc] (8)
>697: $p0 mov u32 $r22 0x00000000 (8)
>698: add f32 $r0 $r2 neg $r0 (8)
>699: add f32 $r1 $r3 neg $r1 (8)
>700: add f32 $r2 $r21 neg $r6 (8)
>701: add f32 $r3 $r22 neg $r7 (8)
>702: cvt u8 $p0 $r40 (8)
>703: not $p0 st  u32 # g[$r4d+0x0] $r0 (8)
>704: cvt u8 $p0 $r39 (8)
>705: not $p0 st  u32 # g[$r4d+0x4] $r1 (8)
>706: cvt u8 $p0 $r38 (8)
>707: not $p0 st  u32 # g[$r4d+0x8] $r2 (8)
>708: cvt u8 $p0 $r37 (8)
>709: not $p0 st  u32 # g[$r4d+0xc] $r3 (8)
>710: join membar (SUBOP:7) - # (8)
>BB:63 (0 instructions) - df = { }
> -> BB:24 (forward)
>BB:24 (1 instructions) - idom = BB:22, df = { BB:35 }
> -> BB:35 (forward)
>711: join BB:35 (8)
>BB:25 (8 instructions) - idom = BB:17, df = { BB:35 }
> -> BB:29 (tree)
> -> BB:26 (tree)
>712: mov u32 $r1 0x00000002 (8)
>713: mov u32 $r0 $r10 (8)
>714: call abs BUILTIN:1 (8)
>715: set u8 $p0 eq u32 $r20 0x00000001 (8)
>716: set and u8 $p0 eq u32 $r1 0x00000001 $p0 (8)
>717: joinat BB:34 (8)
>718: set and u8 $p0 eq u32 $r9 $r255 $p0 (8)
>719: not $p0 bra BB:29 (8)
>BB:26 (4 instructions) - idom = BB:25, df = { BB:34 }
> -> BB:60 (tree)
> -> BB:27 (tree)
>720: add u32 $r0 $r8 0x00000001 (8)
>721: joinat BB:28 (8)
>722: set u8 $p0 lt s32 $r0 c0[0x0] (8)
>723: not $p0 join BB:28 (8)
>BB:27 (95 instructions) - idom = BB:26, df = { BB:28 }
> -> BB:28 (forward)
>724: shl u32 $r2 $r8 0x00000004 (8)
>725: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>726: add u32 $r1 $r255 c7[0x334] $c0 (8)
>727: add u32 $r3 $r2 0x00000004 (8)
>728: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>729: cvt u8 $r25 $p0 (8)
>730: cvt u8 $p0 $r25 (8)
>731: not $p0 ld  u32 $r4 g[$r0d+0x0] (8)
>732: $p0 mov u32 $r4 0x00000000 (8)
>733: add u32 $r3 $r2 0x00000008 (8)
>734: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>735: not $p0 ld  u32 $r5 g[$r0d+0x4] (8)
>736: $p0 mov u32 $r5 0x00000000 (8)
>737: add u32 $r3 $r2 0x0000000c (8)
>738: set u8 $p1 gt u32 $r3 c7[0x338] (8)
>739: not $p1 ld  u32 $r6 g[$r0d+0x8] (8)
>740: $p1 mov u32 $r6 0x00000000 (8)
>741: add u32 $r7 $r2 0x00000010 (8)
>742: set u8 $p2 gt u32 $r7 c7[0x338] (8)
>743: not $p2 ld  u32 $r21 g[$r0d+0xc] (8)
>744: $p2 mov u32 $r21 0x00000000 (8)
>745: add u32 { $r2 $c0 } $r7 c7[0x330] (8)
>746: add u32 $r3 $r255 c7[0x334] $c0 (8)
>747: add u32 $r22 $r7 0x00000004 (8)
>748: set u8 $p3 gt u32 $r22 c7[0x338] (8)
>749: cvt u8 $r26 $p3 (8)
>750: cvt u8 $p3 $r26 (8)
>751: not $p3 ld  u32 $r22 g[$r2d+0x0] (8)
>752: $p3 mov u32 $r22 0x00000000 (8)
>753: add u32 $r23 $r7 0x00000008 (8)
>754: set u8 $p3 gt u32 $r23 c7[0x338] (8)
>755: not $p3 ld  u32 $r23 g[$r2d+0x4] (8)
>756: $p3 mov u32 $r23 0x00000000 (8)
>757: add u32 $r24 $r7 0x0000000c (8)
>758: set u8 $p4 gt u32 $r24 c7[0x338] (8)
>759: not $p4 ld  u32 $r24 g[$r2d+0x8] (8)
>760: $p4 mov u32 $r24 0x00000000 (8)
>761: add u32 $r7 $r7 0x00000010 (8)
>762: set u8 $p5 gt u32 $r7 c7[0x338] (8)
>763: not $p5 ld  u32 $r7 g[$r2d+0xc] (8)
>764: $p5 mov u32 $r7 0x00000000 (8)
>765: add f32 $r4 $r4 neg $r22 (8)
>766: add f32 $r5 $r5 neg $r23 (8)
>767: add f32 $r6 $r6 neg $r24 (8)
>768: add f32 $r7 $r21 neg $r7 (8)
>769: mul f32 $r21 $r4 $r4 (8)
>770: mad f32 $r21 $r5 $r5 $r21 (8)
>771: mad f32 $r21 $r6 $r6 $r21 (8)
>772: mad f32 $r21 $r7 $r7 $r21 (8)
>773: rsq f32 $r21 $r21 (8)
>774: rcp f32 $r22 $r21 (8)
>775: add f32 $r22 neg $r22 c0[0x20] (8)
>776: mul f32 $r22 $r22 0.350000 (8)
>777: mul f32 $r21 $r22 $r21 (8)
>778: mul f32 $r4 $r21 $r4 (8)
>779: mul f32 $r5 $r21 $r5 (8)
>780: mul f32 $r6 $r21 $r6 (8)
>781: mul f32 $r7 $r21 $r7 (8)
>782: cvt u8 $p6 $r25 (8)
>783: not $p6 ld  u32 $r21 g[$r0d+0x0] (8)
>784: $p6 mov u32 $r21 0x00000000 (8)
>785: not $p0 ld  u32 $r22 g[$r0d+0x4] (8)
>786: $p0 mov u32 $r22 0x00000000 (8)
>787: not $p1 ld  u32 $r23 g[$r0d+0x8] (8)
>788: $p1 mov u32 $r23 0x00000000 (8)
>789: not $p2 ld  u32 $r24 g[$r0d+0xc] (8)
>790: $p2 mov u32 $r24 0x00000000 (8)
>791: add f32 $r21 $r21 $r4 (8)
>792: add f32 $r22 $r22 $r5 (8)
>793: add f32 $r23 $r23 $r6 (8)
>794: add f32 $r24 $r24 $r7 (8)
>795: cvt u8 $p6 $r25 (8)
>796: not $p6 st  u32 # g[$r0d+0x0] $r21 (8)
>797: not $p0 st  u32 # g[$r0d+0x4] $r22 (8)
>798: not $p1 st  u32 # g[$r0d+0x8] $r23 (8)
>799: not $p2 st  u32 # g[$r0d+0xc] $r24 (8)
>800: cvt u8 $p0 $r26 (8)
>801: not $p0 ld  u32 $r0 g[$r2d+0x0] (8)
>802: $p0 mov u32 $r0 0x00000000 (8)
>803: not $p3 ld  u32 $r1 g[$r2d+0x4] (8)
>804: $p3 mov u32 $r1 0x00000000 (8)
>805: not $p4 ld  u32 $r21 g[$r2d+0x8] (8)
>806: $p4 mov u32 $r21 0x00000000 (8)
>807: not $p5 ld  u32 $r22 g[$r2d+0xc] (8)
>808: $p5 mov u32 $r22 0x00000000 (8)
>809: add f32 $r0 $r0 neg $r4 (8)
>810: add f32 $r1 $r1 neg $r5 (8)
>811: add f32 $r4 $r21 neg $r6 (8)
>812: add f32 $r5 $r22 neg $r7 (8)
>813: cvt u8 $p0 $r26 (8)
>814: not $p0 st  u32 # g[$r2d+0x0] $r0 (8)
>815: not $p3 st  u32 # g[$r2d+0x4] $r1 (8)
>816: not $p4 st  u32 # g[$r2d+0x8] $r4 (8)
>817: not $p5 st  u32 # g[$r2d+0xc] $r5 (8)
>818: join membar (SUBOP:7) - # (8)
>BB:60 (0 instructions) - df = { }
> -> BB:28 (forward)
>BB:28 (1 instructions) - idom = BB:26, df = { BB:34 }
> -> BB:34 (forward)
>819: join BB:34 (8)
>BB:29 (8 instructions) - idom = BB:25, df = { BB:34 }
> -> BB:58 (tree)
> -> BB:30 (tree)
>820: mov u32 $r1 0x00000002 (8)
>821: mov u32 $r0 $r9 (8)
>822: call abs BUILTIN:1 (8)
>823: set u8 $p0 eq u32 $r20 0x00000001 (8)
>824: set and u8 $p0 eq u32 $r1 0x00000001 $p0 (8)
>825: joinat BB:33 (8)
>826: set and u8 $p0 eq u32 $r10 $r255 $p0 (8)
>827: not $p0 join BB:33 (8)
>BB:30 (6 instructions) - idom = BB:29, df = { BB:33 }
> -> BB:59 (tree)
> -> BB:31 (tree)
>828: ld  u32 $r0 c0[0x0] (8)
>829: add u32 $r2 $r8 c0[0x0] (8)
>830: mul u32 $r0 $r0 c0[0x0] (8)
>831: joinat BB:32 (8)
>832: set u8 $p0 lt s32 $r2 $r0 (8)
>833: not $p0 join BB:32 (8)
>BB:31 (96 instructions) - idom = BB:30, df = { BB:32 }
> -> BB:32 (forward)
>834: shl u32 $r3 $r8 0x00000004 (8)
>835: add u32 { $r0 $c0 } $r3 c7[0x330] (8)
>836: add u32 $r1 $r255 c7[0x334] $c0 (8)
>837: add u32 $r4 $r3 0x00000004 (8)
>838: set u8 $p0 gt u32 $r4 c7[0x338] (8)
>839: cvt u8 $r25 $p0 (8)
>840: cvt u8 $p0 $r25 (8)
>841: not $p0 ld  u32 $r4 g[$r0d+0x0] (8)
>842: $p0 mov u32 $r4 0x00000000 (8)
>843: add u32 $r5 $r3 0x00000008 (8)
>844: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>845: not $p0 ld  u32 $r5 g[$r0d+0x4] (8)
>846: $p0 mov u32 $r5 0x00000000 (8)
>847: add u32 $r6 $r3 0x0000000c (8)
>848: set u8 $p1 gt u32 $r6 c7[0x338] (8)
>849: not $p1 ld  u32 $r6 g[$r0d+0x8] (8)
>850: $p1 mov u32 $r6 0x00000000 (8)
>851: add u32 $r3 $r3 0x00000010 (8)
>852: set u8 $p2 gt u32 $r3 c7[0x338] (8)
>853: not $p2 ld  u32 $r7 g[$r0d+0xc] (8)
>854: $p2 mov u32 $r7 0x00000000 (8)
>855: shl u32 $r21 $r2 0x00000004 (8)
>856: add u32 { $r2 $c0 } $r21 c7[0x330] (8)
>857: add u32 $r3 $r255 c7[0x334] $c0 (8)
>858: add u32 $r22 $r21 0x00000004 (8)
>859: set u8 $p3 gt u32 $r22 c7[0x338] (8)
>860: cvt u8 $r26 $p3 (8)
>861: cvt u8 $p3 $r26 (8)
>862: not $p3 ld  u32 $r22 g[$r2d+0x0] (8)
>863: $p3 mov u32 $r22 0x00000000 (8)
>864: add u32 $r23 $r21 0x00000008 (8)
>865: set u8 $p3 gt u32 $r23 c7[0x338] (8)
>866: not $p3 ld  u32 $r23 g[$r2d+0x4] (8)
>867: $p3 mov u32 $r23 0x00000000 (8)
>868: add u32 $r24 $r21 0x0000000c (8)
>869: set u8 $p4 gt u32 $r24 c7[0x338] (8)
>870: not $p4 ld  u32 $r24 g[$r2d+0x8] (8)
>871: $p4 mov u32 $r24 0x00000000 (8)
>872: add u32 $r21 $r21 0x00000010 (8)
>873: set u8 $p5 gt u32 $r21 c7[0x338] (8)
>874: not $p5 ld  u32 $r21 g[$r2d+0xc] (8)
>875: $p5 mov u32 $r21 0x00000000 (8)
>876: add f32 $r4 $r4 neg $r22 (8)
>877: add f32 $r5 $r5 neg $r23 (8)
>878: add f32 $r6 $r6 neg $r24 (8)
>879: add f32 $r7 $r7 neg $r21 (8)
>880: mul f32 $r21 $r4 $r4 (8)
>881: mad f32 $r21 $r5 $r5 $r21 (8)
>882: mad f32 $r21 $r6 $r6 $r21 (8)
>883: mad f32 $r21 $r7 $r7 $r21 (8)
>884: rsq f32 $r21 $r21 (8)
>885: rcp f32 $r22 $r21 (8)
>886: add f32 $r22 neg $r22 c0[0x20] (8)
>887: mul f32 $r22 $r22 0.350000 (8)
>888: mul f32 $r21 $r22 $r21 (8)
>889: mul f32 $r4 $r21 $r4 (8)
>890: mul f32 $r5 $r21 $r5 (8)
>891: mul f32 $r6 $r21 $r6 (8)
>892: mul f32 $r7 $r21 $r7 (8)
>893: cvt u8 $p6 $r25 (8)
>894: not $p6 ld  u32 $r21 g[$r0d+0x0] (8)
>895: $p6 mov u32 $r21 0x00000000 (8)
>896: not $p0 ld  u32 $r22 g[$r0d+0x4] (8)
>897: $p0 mov u32 $r22 0x00000000 (8)
>898: not $p1 ld  u32 $r23 g[$r0d+0x8] (8)
>899: $p1 mov u32 $r23 0x00000000 (8)
>900: not $p2 ld  u32 $r24 g[$r0d+0xc] (8)
>901: $p2 mov u32 $r24 0x00000000 (8)
>902: add f32 $r21 $r21 $r4 (8)
>903: add f32 $r22 $r22 $r5 (8)
>904: add f32 $r23 $r23 $r6 (8)
>905: add f32 $r24 $r24 $r7 (8)
>906: cvt u8 $p6 $r25 (8)
>907: not $p6 st  u32 # g[$r0d+0x0] $r21 (8)
>908: not $p0 st  u32 # g[$r0d+0x4] $r22 (8)
>909: not $p1 st  u32 # g[$r0d+0x8] $r23 (8)
>910: not $p2 st  u32 # g[$r0d+0xc] $r24 (8)
>911: cvt u8 $p0 $r26 (8)
>912: not $p0 ld  u32 $r0 g[$r2d+0x0] (8)
>913: $p0 mov u32 $r0 0x00000000 (8)
>914: not $p3 ld  u32 $r1 g[$r2d+0x4] (8)
>915: $p3 mov u32 $r1 0x00000000 (8)
>916: not $p4 ld  u32 $r21 g[$r2d+0x8] (8)
>917: $p4 mov u32 $r21 0x00000000 (8)
>918: not $p5 ld  u32 $r22 g[$r2d+0xc] (8)
>919: $p5 mov u32 $r22 0x00000000 (8)
>920: add f32 $r0 $r0 neg $r4 (8)
>921: add f32 $r1 $r1 neg $r5 (8)
>922: add f32 $r4 $r21 neg $r6 (8)
>923: add f32 $r5 $r22 neg $r7 (8)
>924: cvt u8 $p0 $r26 (8)
>925: not $p0 st  u32 # g[$r2d+0x0] $r0 (8)
>926: not $p3 st  u32 # g[$r2d+0x4] $r1 (8)
>927: not $p4 st  u32 # g[$r2d+0x8] $r4 (8)
>928: not $p5 st  u32 # g[$r2d+0xc] $r5 (8)
>929: join membar (SUBOP:7) - # (8)
>BB:59 (0 instructions) - df = { }
> -> BB:32 (forward)
>BB:32 (1 instructions) - idom = BB:30, df = { BB:33 }
> -> BB:33 (forward)
>930: join BB:33 (8)
>BB:58 (0 instructions) - df = { }
> -> BB:33 (forward)
>BB:33 (1 instructions) - idom = BB:29, df = { BB:34 }
> -> BB:34 (forward)
>931: join BB:34 (8)
>BB:34 (1 instructions) - idom = BB:25, df = { BB:35 }
> -> BB:35 (forward)
>932: join BB:35 (8)
>BB:35 (3 instructions) - idom = BB:17, df = { BB:14 }
> -> BB:14 (back)
>933: bar u32 # $r255 $r255 (8)
>934: add u32 $r20 $r20 0x00000001 (8)
>935: bra BB:14 (8)
>BB:15 (2 instructions) - idom = BB:16, df = { BB:10 }
> -> BB:36 (tree)
>936: mov u32 $r20 0x00000000 (8)
>937: prebreak BB:37 (8)
>BB:36 (1 instructions) - idom = BB:15, df = { BB:10 BB:36 }
> -> BB:39 (forward)
> -> BB:38 (tree)
>938: set u8 $p0 ge s32 $r20 2 (8)
>BB:38 (1 instructions) - idom = BB:36, df = { BB:10 }
> -> BB:37 (cross)
>939: $p0 break BB:37 (8)
>BB:39 (12 instructions) - idom = BB:36, df = { BB:36 }
> -> BB:64 (tree)
> -> BB:40 (tree)
>940: mov u32 $r4 0x00000002 (8)
>941: mov u32 $r0 $r9 (8)
>942: mov u32 $r1 $r4 (8)
>943: call abs BUILTIN:1 (8)
>944: mov u32 $r5 $r1 (8)
>945: add u32 $r0 $r10 0x00000001 (8)
>946: mov u32 $r1 $r4 (8)
>947: call abs BUILTIN:1 (8)
>948: set u8 $p0 eq u32 $r5 $r20 (8)
>949: joinat BB:43 (8)
>950: set and u8 $p0 eq u32 $r1 $r20 $p0 (8)
>951: not $p0 join BB:43 (8)
>BB:40 (30 instructions) - idom = BB:39, df = { BB:43 }
> -> BB:65 (tree)
> -> BB:41 (tree)
>952: shl u32 $r2 $r8 0x00000004 (8)
>953: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>954: add u32 $r1 $r255 c7[0x334] $c0 (8)
>955: add u32 $r3 $r2 0x00000004 (8)
>956: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>957: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>958: $p0 mov u32 $r6 0x00000000 (8)
>959: add u32 $r3 $r2 0x00000008 (8)
>960: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>961: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>962: $p0 mov u32 $r7 0x00000000 (8)
>963: add u32 $r3 $r2 0x0000000c (8)
>964: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>965: not $p0 ld  u32 $r21 g[$r0d+0x8] (8)
>966: $p0 mov u32 $r21 0x00000000 (8)
>967: add u32 $r2 $r2 0x00000010 (8)
>968: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>969: not $p0 ld  u32 $r22 g[$r0d+0xc] (8)
>970: $p0 mov u32 $r22 0x00000000 (8)
>971: add u32 $r0 $r8 0x00000001 (8)
>972: ld  u32 $r1 c0[0x0] (8)
>973: add u32 $r4 $r8 c0[0x0] (8)
>974: add u32 $r5 $r0 c0[0x0] (8)
>975: mul u32 $r23 $r1 c0[0x0] (8)
>976: mov u32 $r0 $r5 (8)
>977: call abs BUILTIN:1 (8)
>978: set u8 $p0 lt s32 $r5 $r23 (8)
>979: joinat BB:42 (8)
>980: set and u8 $p0 lt s32 $r10 $r1 $p0 (8)
>981: not $p0 join BB:42 (8)
>BB:41 (202 instructions) - idom = BB:40, df = { BB:42 }
> -> BB:42 (forward)
>982: shl u32 $r36 $r8 0x00000004 (8)
>983: add u32 $r23 $r36 0x00000010 (8)
>984: add u32 { $r0 $c0 } $r23 c7[0x330] (8)
>985: add u32 $r1 $r255 c7[0x334] $c0 (8)
>986: add u32 $r2 $r23 0x00000004 (8)
>987: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>988: cvt u8 $r45 $p0 (8)
>989: cvt u8 $p0 $r45 (8)
>990: not $p0 ld  u32 $r24 g[$r0d+0x0] (8)
>991: $p0 mov u32 $r24 0x00000000 (8)
>992: add u32 $r2 $r23 0x00000008 (8)
>993: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>994: cvt u8 $r43 $p0 (8)
>995: cvt u8 $p0 $r43 (8)
>996: not $p0 ld  u32 $r25 g[$r0d+0x4] (8)
>997: $p0 mov u32 $r25 0x00000000 (8)
>998: add u32 $r2 $r23 0x0000000c (8)
>999: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1000: cvt u8 $r41 $p0 (8)
>1001: cvt u8 $p0 $r41 (8)
>1002: not $p0 ld  u32 $r26 g[$r0d+0x8] (8)
>1003: $p0 mov u32 $r26 0x00000000 (8)
>1004: add u32 $r2 $r23 0x00000010 (8)
>1005: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1006: cvt u8 $r39 $p0 (8)
>1007: cvt u8 $p0 $r39 (8)
>1008: not $p0 ld  u32 $r27 g[$r0d+0xc] (8)
>1009: $p0 mov u32 $r27 0x00000000 (8)
>1010: shl u32 $r4 $r4 0x00000004 (8)
>1011: add u32 { $r2 $c0 } $r4 c7[0x330] (8)
>1012: add u32 $r3 $r255 c7[0x334] $c0 (8)
>1013: add u32 $r28 $r4 0x00000004 (8)
>1014: set u8 $p0 gt u32 $r28 c7[0x338] (8)
>1015: cvt u8 $r44 $p0 (8)
>1016: cvt u8 $p0 $r44 (8)
>1017: not $p0 ld  u32 $r28 g[$r2d+0x0] (8)
>1018: $p0 mov u32 $r28 0x00000000 (8)
>1019: add u32 $r29 $r4 0x00000008 (8)
>1020: set u8 $p0 gt u32 $r29 c7[0x338] (8)
>1021: cvt u8 $r42 $p0 (8)
>1022: cvt u8 $p0 $r42 (8)
>1023: not $p0 ld  u32 $r29 g[$r2d+0x4] (8)
>1024: $p0 mov u32 $r29 0x00000000 (8)
>1025: add u32 $r30 $r4 0x0000000c (8)
>1026: set u8 $p0 gt u32 $r30 c7[0x338] (8)
>1027: cvt u8 $r40 $p0 (8)
>1028: cvt u8 $p0 $r40 (8)
>1029: not $p0 ld  u32 $r30 g[$r2d+0x8] (8)
>1030: $p0 mov u32 $r30 0x00000000 (8)
>1031: add u32 $r4 $r4 0x00000010 (8)
>1032: set u8 $p0 gt u32 $r4 c7[0x338] (8)
>1033: cvt u8 $r38 $p0 (8)
>1034: cvt u8 $p0 $r38 (8)
>1035: not $p0 ld  u32 $r31 g[$r2d+0xc] (8)
>1036: $p0 mov u32 $r31 0x00000000 (8)
>1037: shl u32 $r32 $r5 0x00000004 (8)
>1038: add u32 { $r4 $c0 } $r32 c7[0x330] (8)
>1039: add u32 $r5 $r255 c7[0x334] $c0 (8)
>1040: add u32 $r33 $r32 0x00000004 (8)
>1041: set u8 $p0 gt u32 $r33 c7[0x338] (8)
>1042: cvt u8 $r37 $p0 (8)
>1043: cvt u8 $p0 $r37 (8)
>1044: not $p0 ld  u32 $r33 g[$r4d+0x0] (8)
>1045: $p0 mov u32 $r33 0x00000000 (8)
>1046: add u32 $r34 $r32 0x00000008 (8)
>1047: set u8 $p0 gt u32 $r34 c7[0x338] (8)
>1048: not $p0 ld  u32 $r34 g[$r4d+0x4] (8)
>1049: $p0 mov u32 $r34 0x00000000 (8)
>1050: add u32 $r35 $r32 0x0000000c (8)
>1051: set u8 $p1 gt u32 $r35 c7[0x338] (8)
>1052: not $p1 ld  u32 $r35 g[$r4d+0x8] (8)
>1053: $p1 mov u32 $r35 0x00000000 (8)
>1054: add u32 $r32 $r32 0x00000010 (8)
>1055: set u8 $p2 gt u32 $r32 c7[0x338] (8)
>1056: not $p2 ld  u32 $r32 g[$r4d+0xc] (8)
>1057: $p2 mov u32 $r32 0x00000000 (8)
>1058: add f32 $r6 $r6 neg $r33 (8)
>1059: add f32 $r7 $r7 neg $r34 (8)
>1060: add f32 $r21 $r21 neg $r35 (8)
>1061: add f32 $r22 $r22 neg $r32 (8)
>1062: mul f32 $r32 $r6 $r6 (8)
>1063: mad f32 $r32 $r7 $r7 $r32 (8)
>1064: mad f32 $r32 $r21 $r21 $r32 (8)
>1065: mad f32 $r32 $r22 $r22 $r32 (8)
>1066: rsq f32 $r32 $r32 (8)
>1067: rcp f32 $r33 $r32 (8)
>1068: add f32 $r33 neg $r33 c0[0x30] (8)
>1069: mul f32 $r33 $r33 0.350000 (8)
>1070: mul f32 $r32 $r33 $r32 (8)
>1071: mul f32 $r33 $r32 $r6 (8)
>1072: mul f32 $r34 $r32 $r7 (8)
>1073: mul f32 $r21 $r32 $r21 (8)
>1074: mul f32 $r22 $r32 $r22 (8)
>1075: add u32 { $r6 $c0 } $r36 c7[0x330] (8)
>1076: add u32 $r7 $r255 c7[0x334] $c0 (8)
>1077: add u32 $r32 $r36 0x00000004 (8)
>1078: set u8 $p3 gt u32 $r32 c7[0x338] (8)
>1079: not $p3 ld  u32 $r32 g[$r6d+0x0] (8)
>1080: $p3 mov u32 $r32 0x00000000 (8)
>1081: add u32 $r35 $r36 0x00000008 (8)
>1082: set u8 $p4 gt u32 $r35 c7[0x338] (8)
>1083: not $p4 ld  u32 $r35 g[$r6d+0x4] (8)
>1084: $p4 mov u32 $r35 0x00000000 (8)
>1085: add u32 $r36 $r36 0x0000000c (8)
>1086: set u8 $p5 gt u32 $r36 c7[0x338] (8)
>1087: not $p5 ld  u32 $r36 g[$r6d+0x8] (8)
>1088: $p5 mov u32 $r36 0x00000000 (8)
>1089: set u8 $p6 gt u32 $r23 c7[0x338] (8)
>1090: not $p6 ld  u32 $r23 g[$r6d+0xc] (8)
>1091: $p6 mov u32 $r23 0x00000000 (8)
>1092: add f32 $r32 $r32 $r33 (8)
>1093: add f32 $r35 $r35 $r34 (8)
>1094: add f32 $r36 $r36 $r21 (8)
>1095: add f32 $r23 $r23 $r22 (8)
>1096: not $p3 st  u32 # g[$r6d+0x0] $r32 (8)
>1097: not $p4 st  u32 # g[$r6d+0x4] $r35 (8)
>1098: not $p5 st  u32 # g[$r6d+0x8] $r36 (8)
>1099: not $p6 st  u32 # g[$r6d+0xc] $r23 (8)
>1100: cvt u8 $p3 $r37 (8)
>1101: not $p3 ld  u32 $r6 g[$r4d+0x0] (8)
>1102: $p3 mov u32 $r6 0x00000000 (8)
>1103: not $p0 ld  u32 $r7 g[$r4d+0x4] (8)
>1104: $p0 mov u32 $r7 0x00000000 (8)
>1105: not $p1 ld  u32 $r23 g[$r4d+0x8] (8)
>1106: $p1 mov u32 $r23 0x00000000 (8)
>1107: not $p2 ld  u32 $r32 g[$r4d+0xc] (8)
>1108: $p2 mov u32 $r32 0x00000000 (8)
>1109: add f32 $r6 $r6 neg $r33 (8)
>1110: add f32 $r7 $r7 neg $r34 (8)
>1111: add f32 $r21 $r23 neg $r21 (8)
>1112: add f32 $r22 $r32 neg $r22 (8)
>1113: cvt u8 $p3 $r37 (8)
>1114: not $p3 st  u32 # g[$r4d+0x0] $r6 (8)
>1115: not $p0 st  u32 # g[$r4d+0x4] $r7 (8)
>1116: not $p1 st  u32 # g[$r4d+0x8] $r21 (8)
>1117: not $p2 st  u32 # g[$r4d+0xc] $r22 (8)
>1118: add f32 $r4 $r24 neg $r28 (8)
>1119: add f32 $r5 $r25 neg $r29 (8)
>1120: add f32 $r6 $r26 neg $r30 (8)
>1121: add f32 $r7 $r27 neg $r31 (8)
>1122: mul f32 $r21 $r4 $r4 (8)
>1123: mad f32 $r21 $r5 $r5 $r21 (8)
>1124: mad f32 $r21 $r6 $r6 $r21 (8)
>1125: mad f32 $r21 $r7 $r7 $r21 (8)
>1126: rsq f32 $r21 $r21 (8)
>1127: rcp f32 $r22 $r21 (8)
>1128: add f32 $r22 neg $r22 c0[0x30] (8)
>1129: mul f32 $r22 $r22 0.350000 (8)
>1130: mul f32 $r21 $r22 $r21 (8)
>1131: mul f32 $r4 $r21 $r4 (8)
>1132: mul f32 $r5 $r21 $r5 (8)
>1133: mul f32 $r6 $r21 $r6 (8)
>1134: mul f32 $r7 $r21 $r7 (8)
>1135: cvt u8 $p0 $r45 (8)
>1136: not $p0 ld  u32 $r21 g[$r0d+0x0] (8)
>1137: $p0 mov u32 $r21 0x00000000 (8)
>1138: cvt u8 $p0 $r43 (8)
>1139: not $p0 ld  u32 $r22 g[$r0d+0x4] (8)
>1140: $p0 mov u32 $r22 0x00000000 (8)
>1141: cvt u8 $p0 $r41 (8)
>1142: not $p0 ld  u32 $r23 g[$r0d+0x8] (8)
>1143: $p0 mov u32 $r23 0x00000000 (8)
>1144: cvt u8 $p0 $r39 (8)
>1145: not $p0 ld  u32 $r24 g[$r0d+0xc] (8)
>1146: $p0 mov u32 $r24 0x00000000 (8)
>1147: add f32 $r21 $r21 $r4 (8)
>1148: add f32 $r22 $r22 $r5 (8)
>1149: add f32 $r23 $r23 $r6 (8)
>1150: add f32 $r24 $r24 $r7 (8)
>1151: cvt u8 $p0 $r45 (8)
>1152: not $p0 st  u32 # g[$r0d+0x0] $r21 (8)
>1153: cvt u8 $p0 $r43 (8)
>1154: not $p0 st  u32 # g[$r0d+0x4] $r22 (8)
>1155: cvt u8 $p0 $r41 (8)
>1156: not $p0 st  u32 # g[$r0d+0x8] $r23 (8)
>1157: cvt u8 $p0 $r39 (8)
>1158: not $p0 st  u32 # g[$r0d+0xc] $r24 (8)
>1159: cvt u8 $p0 $r44 (8)
>1160: not $p0 ld  u32 $r0 g[$r2d+0x0] (8)
>1161: $p0 mov u32 $r0 0x00000000 (8)
>1162: cvt u8 $p0 $r42 (8)
>1163: not $p0 ld  u32 $r1 g[$r2d+0x4] (8)
>1164: $p0 mov u32 $r1 0x00000000 (8)
>1165: cvt u8 $p0 $r40 (8)
>1166: not $p0 ld  u32 $r21 g[$r2d+0x8] (8)
>1167: $p0 mov u32 $r21 0x00000000 (8)
>1168: cvt u8 $p0 $r38 (8)
>1169: not $p0 ld  u32 $r22 g[$r2d+0xc] (8)
>1170: $p0 mov u32 $r22 0x00000000 (8)
>1171: add f32 $r0 $r0 neg $r4 (8)
>1172: add f32 $r1 $r1 neg $r5 (8)
>1173: add f32 $r4 $r21 neg $r6 (8)
>1174: add f32 $r5 $r22 neg $r7 (8)
>1175: cvt u8 $p0 $r44 (8)
>1176: not $p0 st  u32 # g[$r2d+0x0] $r0 (8)
>1177: cvt u8 $p0 $r42 (8)
>1178: not $p0 st  u32 # g[$r2d+0x4] $r1 (8)
>1179: cvt u8 $p0 $r40 (8)
>1180: not $p0 st  u32 # g[$r2d+0x8] $r4 (8)
>1181: cvt u8 $p0 $r38 (8)
>1182: not $p0 st  u32 # g[$r2d+0xc] $r5 (8)
>1183: join membar (SUBOP:7) - # (8)
>BB:65 (0 instructions) - df = { }
> -> BB:42 (forward)
>BB:42 (1 instructions) - idom = BB:40, df = { BB:43 }
> -> BB:43 (forward)
>1184: join BB:43 (8)
>BB:64 (0 instructions) - df = { }
> -> BB:43 (forward)
>BB:43 (3 instructions) - idom = BB:39, df = { BB:36 }
> -> BB:36 (back)
>1185: bar u32 # $r255 $r255 (8)
>1186: add u32 $r20 $r20 0x00000001 (8)
>1187: bra BB:36 (8)
>BB:11 (6 instructions) - idom = BB:12, df = { }
> -> BB:67 (tree)
> -> BB:46 (tree)
>1188: mov u32 $r16 0x00000000 (8)
>1189: ld  u32 $r0 c0[0x0] (8)
>1190: add u32 $r0 $r0 0xffffffff (8)
>1191: joinat BB:51 (8)
>1192: set u8 $p0 lt s32 $r10 $r0 (8)
>1193: not $p0 bra BB:67 (8)
>BB:46 (45 instructions) - idom = BB:11, df = { BB:51 }
> -> BB:71 (tree)
> -> BB:47 (tree)
>1194: shl u32 $r7 $r8 0x00000004 (8)
>1195: add u32 $r2 $r7 0x00000010 (8)
>1196: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>1197: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1198: add u32 $r3 $r2 0x00000004 (8)
>1199: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>1200: not $p0 ld  u32 $r3 g[$r0d+0x0] (8)
>1201: $p0 mov u32 $r3 0x00000000 (8)
>1202: add u32 $r4 $r2 0x00000008 (8)
>1203: set u8 $p0 gt u32 $r4 c7[0x338] (8)
>1204: not $p0 ld  u32 $r4 g[$r0d+0x4] (8)
>1205: $p0 mov u32 $r4 0x00000000 (8)
>1206: add u32 $r2 $r2 0x0000000c (8)
>1207: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1208: not $p0 ld  u32 $r2 g[$r0d+0x8] (8)
>1209: $p0 mov u32 $r2 0x00000000 (8)
>1210: add u32 { $r0 $c0 } $r7 c7[0x330] (8)
>1211: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1212: add u32 $r5 $r7 0x00000004 (8)
>1213: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1214: not $p0 ld  u32 $r5 g[$r0d+0x0] (8)
>1215: $p0 mov u32 $r5 0x00000000 (8)
>1216: add u32 $r6 $r7 0x00000008 (8)
>1217: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1218: not $p0 ld  u32 $r6 g[$r0d+0x4] (8)
>1219: $p0 mov u32 $r6 0x00000000 (8)
>1220: add u32 $r7 $r7 0x0000000c (8)
>1221: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1222: not $p0 ld  u32 $r0 g[$r0d+0x8] (8)
>1223: $p0 mov u32 $r0 0x00000000 (8)
>1224: add f32 $r1 $r3 neg $r5 (8)
>1225: add f32 $r3 $r4 neg $r6 (8)
>1226: add f32 $r0 $r2 neg $r0 (8)
>1227: mul f32 $r2 $r1 $r1 (8)
>1228: mad f32 $r2 $r3 $r3 $r2 (8)
>1229: mad f32 $r2 $r0 $r0 $r2 (8)
>1230: rsq f32 $r2 abs $r2 (8)
>1231: mul f32 $r4 $r1 $r2 (8)
>1232: mul f32 $r3 $r3 $r2 (8)
>1233: mul f32 $r2 $r0 $r2 (8)
>1234: ld  u32 $r0 c0[0x0] (8)
>1235: add u32 $r0 $r0 0xffffffff (8)
>1236: joinat BB:48 (8)
>1237: set u8 $p0 lt s32 $r9 $r0 (8)
>1238: not $p0 bra BB:71 (8)
>BB:47 (54 instructions) - idom = BB:46, df = { BB:48 }
> -> BB:48 (forward)
>1239: add u32 $r0 $r8 c0[0x0] (8)
>1240: shl u32 $r5 $r0 0x00000004 (8)
>1241: add u32 { $r0 $c0 } $r5 c7[0x330] (8)
>1242: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1243: add u32 $r6 $r5 0x00000004 (8)
>1244: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1245: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>1246: $p0 mov u32 $r6 0x00000000 (8)
>1247: add u32 $r7 $r5 0x00000008 (8)
>1248: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1249: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>1250: $p0 mov u32 $r7 0x00000000 (8)
>1251: add u32 $r5 $r5 0x0000000c (8)
>1252: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1253: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
>1254: $p0 mov u32 $r5 0x00000000 (8)
>1255: shl u32 $r11 $r8 0x00000004 (8)
>1256: add u32 { $r0 $c0 } $r11 c7[0x330] (8)
>1257: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1258: add u32 $r12 $r11 0x00000004 (8)
>1259: set u8 $p0 gt u32 $r12 c7[0x338] (8)
>1260: not $p0 ld  u32 $r12 g[$r0d+0x0] (8)
>1261: $p0 mov u32 $r12 0x00000000 (8)
>1262: add u32 $r13 $r11 0x00000008 (8)
>1263: set u8 $p0 gt u32 $r13 c7[0x338] (8)
>1264: not $p0 ld  u32 $r13 g[$r0d+0x4] (8)
>1265: $p0 mov u32 $r13 0x00000000 (8)
>1266: add u32 $r11 $r11 0x0000000c (8)
>1267: set u8 $p0 gt u32 $r11 c7[0x338] (8)
>1268: not $p0 ld  u32 $r0 g[$r0d+0x8] (8)
>1269: $p0 mov u32 $r0 0x00000000 (8)
>1270: add f32 $r1 $r6 neg $r12 (8)
>1271: add f32 $r6 $r7 neg $r13 (8)
>1272: add f32 $r0 $r5 neg $r0 (8)
>1273: mul f32 $r5 $r1 $r1 (8)
>1274: mad f32 $r5 $r6 $r6 $r5 (8)
>1275: mad f32 $r5 $r0 $r0 $r5 (8)
>1276: rsq f32 $r5 abs $r5 (8)
>1277: mul f32 $r1 $r1 $r5 (8)
>1278: mul f32 $r6 $r6 $r5 (8)
>1279: mul f32 $r0 $r0 $r5 (8)
>1280: mul f32 $r5 $r0 $r3 (8)
>1281: mul f32 $r7 $r1 $r2 (8)
>1282: mul f32 $r11 $r6 $r4 (8)
>1283: mad f32 $r5 $r6 $r2 neg $r5 (8)
>1284: mad f32 $r0 $r0 $r4 neg $r7 (8)
>1285: mad f32 $r1 $r1 $r3 neg $r11 (8)
>1286: mul f32 $r6 $r5 $r5 (8)
>1287: mad f32 $r6 $r0 $r0 $r6 (8)
>1288: mad f32 $r6 $r1 $r1 $r6 (8)
>1289: rsq f32 $r6 abs $r6 (8)
>1290: mul f32 $r14 $r5 $r6 (8)
>1291: mul f32 $r15 $r0 $r6 (8)
>1292: join mul f32 $r16 $r1 $r6 (8)
>BB:71 (2 instructions) - df = { }
> -> BB:48 (forward)
>1293: mov u32 $r14 $r16 (8)
>1294: join mov u32 $r15 $r16 (8)
>BB:48 (3 instructions) - idom = BB:46, df = { BB:51 }
> -> BB:72 (tree)
> -> BB:49 (tree)
>1295: joinat BB:50 (8)
>1296: set u8 $p0 lt s32 $r255 $r9 (8)
>1297: not $p0 join BB:50 (8)
>BB:49 (54 instructions) - idom = BB:48, df = { BB:50 }
> -> BB:50 (forward)
>1298: shl u32 $r5 $r8 0x00000004 (8)
>1299: add u32 { $r0 $c0 } $r5 c7[0x330] (8)
>1300: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1301: add u32 $r6 $r5 0x00000004 (8)
>1302: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1303: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>1304: $p0 mov u32 $r6 0x00000000 (8)
>1305: add u32 $r7 $r5 0x00000008 (8)
>1306: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1307: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>1308: $p0 mov u32 $r7 0x00000000 (8)
>1309: add u32 $r5 $r5 0x0000000c (8)
>1310: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1311: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
>1312: $p0 mov u32 $r5 0x00000000 (8)
>1313: add u32 $r0 $r8 neg c0[0x0] (8)
>1314: shl u32 $r11 $r0 0x00000004 (8)
>1315: add u32 { $r0 $c0 } $r11 c7[0x330] (8)
>1316: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1317: add u32 $r12 $r11 0x00000004 (8)
>1318: set u8 $p0 gt u32 $r12 c7[0x338] (8)
>1319: not $p0 ld  u32 $r12 g[$r0d+0x0] (8)
>1320: $p0 mov u32 $r12 0x00000000 (8)
>1321: add u32 $r13 $r11 0x00000008 (8)
>1322: set u8 $p0 gt u32 $r13 c7[0x338] (8)
>1323: not $p0 ld  u32 $r13 g[$r0d+0x4] (8)
>1324: $p0 mov u32 $r13 0x00000000 (8)
>1325: add u32 $r11 $r11 0x0000000c (8)
>1326: set u8 $p0 gt u32 $r11 c7[0x338] (8)
>1327: not $p0 ld  u32 $r0 g[$r0d+0x8] (8)
>1328: $p0 mov u32 $r0 0x00000000 (8)
>1329: add f32 $r1 $r6 neg $r12 (8)
>1330: add f32 $r6 $r7 neg $r13 (8)
>1331: add f32 $r0 $r5 neg $r0 (8)
>1332: mul f32 $r5 $r1 $r1 (8)
>1333: mad f32 $r5 $r6 $r6 $r5 (8)
>1334: mad f32 $r5 $r0 $r0 $r5 (8)
>1335: rsq f32 $r5 abs $r5 (8)
>1336: mul f32 $r1 $r1 $r5 (8)
>1337: mul f32 $r6 $r6 $r5 (8)
>1338: mul f32 $r0 $r0 $r5 (8)
>1339: mul f32 $r5 $r0 $r3 (8)
>1340: mul f32 $r7 $r1 $r2 (8)
>1341: mul f32 $r11 $r6 $r4 (8)
>1342: mad f32 $r2 $r6 $r2 neg $r5 (8)
>1343: mad f32 $r0 $r0 $r4 neg $r7 (8)
>1344: mad f32 $r1 $r1 $r3 neg $r11 (8)
>1345: mul f32 $r3 $r2 $r2 (8)
>1346: mad f32 $r3 $r0 $r0 $r3 (8)
>1347: mad f32 $r3 $r1 $r1 $r3 (8)
>1348: rsq f32 $r3 abs $r3 (8)
>1349: mad f32 $r14 $r2 $r3 $r14 (8)
>1350: mad f32 $r15 $r0 $r3 $r15 (8)
>1351: join mad f32 $r16 $r1 $r3 $r16 (8)
>BB:72 (0 instructions) - df = { }
> -> BB:50 (forward)
>BB:50 (1 instructions) - idom = BB:48, df = { BB:51 }
> -> BB:51 (forward)
>1352: join BB:51 (8)
>BB:67 (2 instructions) - df = { }
> -> BB:51 (forward)
>1353: mov u32 $r14 $r16 (8)
>1354: join mov u32 $r15 $r16 (8)
>BB:51 (3 instructions) - idom = BB:11, df = { }
> -> BB:68 (tree)
> -> BB:52 (tree)
>1355: joinat BB:57 (8)
>1356: set u8 $p0 lt s32 $r255 $r10 (8)
>1357: not $p0 join BB:57 (8)
>BB:52 (45 instructions) - idom = BB:51, df = { BB:57 }
> -> BB:69 (tree)
> -> BB:53 (tree)
>1358: shl u32 $r2 $r8 0x00000004 (8)
>1359: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>1360: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1361: add u32 $r3 $r2 0x00000004 (8)
>1362: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>1363: not $p0 ld  u32 $r3 g[$r0d+0x0] (8)
>1364: $p0 mov u32 $r3 0x00000000 (8)
>1365: add u32 $r4 $r2 0x00000008 (8)
>1366: set u8 $p0 gt u32 $r4 c7[0x338] (8)
>1367: not $p0 ld  u32 $r4 g[$r0d+0x4] (8)
>1368: $p0 mov u32 $r4 0x00000000 (8)
>1369: add u32 $r5 $r2 0x0000000c (8)
>1370: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1371: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
>1372: $p0 mov u32 $r5 0x00000000 (8)
>1373: add u32 $r2 $r2 0xfffffff0 (8)
>1374: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>1375: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1376: add u32 $r6 $r2 0x00000004 (8)
>1377: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1378: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>1379: $p0 mov u32 $r6 0x00000000 (8)
>1380: add u32 $r7 $r2 0x00000008 (8)
>1381: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1382: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>1383: $p0 mov u32 $r7 0x00000000 (8)
>1384: add u32 $r2 $r2 0x0000000c (8)
>1385: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1386: not $p0 ld  u32 $r0 g[$r0d+0x8] (8)
>1387: $p0 mov u32 $r0 0x00000000 (8)
>1388: add f32 $r1 $r3 neg $r6 (8)
>1389: add f32 $r2 $r4 neg $r7 (8)
>1390: add f32 $r0 $r5 neg $r0 (8)
>1391: mul f32 $r3 $r1 $r1 (8)
>1392: mad f32 $r3 $r2 $r2 $r3 (8)
>1393: mad f32 $r3 $r0 $r0 $r3 (8)
>1394: rsq f32 $r3 abs $r3 (8)
>1395: mul f32 $r4 $r1 $r3 (8)
>1396: mul f32 $r2 $r2 $r3 (8)
>1397: mul f32 $r3 $r0 $r3 (8)
>1398: ld  u32 $r0 c0[0x0] (8)
>1399: add u32 $r0 $r0 0xffffffff (8)
>1400: joinat BB:54 (8)
>1401: set u8 $p0 lt s32 $r9 $r0 (8)
>1402: not $p0 join BB:54 (8)
>BB:53 (54 instructions) - idom = BB:52, df = { BB:54 }
> -> BB:54 (forward)
>1403: add u32 $r0 $r8 c0[0x0] (8)
>1404: shl u32 $r5 $r0 0x00000004 (8)
>1405: add u32 { $r0 $c0 } $r5 c7[0x330] (8)
>1406: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1407: add u32 $r6 $r5 0x00000004 (8)
>1408: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1409: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>1410: $p0 mov u32 $r6 0x00000000 (8)
>1411: add u32 $r7 $r5 0x00000008 (8)
>1412: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1413: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>1414: $p0 mov u32 $r7 0x00000000 (8)
>1415: add u32 $r5 $r5 0x0000000c (8)
>1416: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1417: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
>1418: $p0 mov u32 $r5 0x00000000 (8)
>1419: shl u32 $r10 $r8 0x00000004 (8)
>1420: add u32 { $r0 $c0 } $r10 c7[0x330] (8)
>1421: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1422: add u32 $r11 $r10 0x00000004 (8)
>1423: set u8 $p0 gt u32 $r11 c7[0x338] (8)
>1424: not $p0 ld  u32 $r11 g[$r0d+0x0] (8)
>1425: $p0 mov u32 $r11 0x00000000 (8)
>1426: add u32 $r12 $r10 0x00000008 (8)
>1427: set u8 $p0 gt u32 $r12 c7[0x338] (8)
>1428: not $p0 ld  u32 $r12 g[$r0d+0x4] (8)
>1429: $p0 mov u32 $r12 0x00000000 (8)
>1430: add u32 $r10 $r10 0x0000000c (8)
>1431: set u8 $p0 gt u32 $r10 c7[0x338] (8)
>1432: not $p0 ld  u32 $r0 g[$r0d+0x8] (8)
>1433: $p0 mov u32 $r0 0x00000000 (8)
>1434: add f32 $r1 $r6 neg $r11 (8)
>1435: add f32 $r6 $r7 neg $r12 (8)
>1436: add f32 $r0 $r5 neg $r0 (8)
>1437: mul f32 $r5 $r1 $r1 (8)
>1438: mad f32 $r5 $r6 $r6 $r5 (8)
>1439: mad f32 $r5 $r0 $r0 $r5 (8)
>1440: rsq f32 $r5 abs $r5 (8)
>1441: mul f32 $r1 $r1 $r5 (8)
>1442: mul f32 $r6 $r6 $r5 (8)
>1443: mul f32 $r0 $r0 $r5 (8)
>1444: mul f32 $r5 $r0 $r2 (8)
>1445: mul f32 $r7 $r1 $r3 (8)
>1446: mul f32 $r10 $r6 $r4 (8)
>1447: mad f32 $r5 $r6 $r3 neg $r5 (8)
>1448: mad f32 $r0 $r0 $r4 neg $r7 (8)
>1449: mad f32 $r1 $r1 $r2 neg $r10 (8)
>1450: mul f32 $r6 $r5 $r5 (8)
>1451: mad f32 $r6 $r0 $r0 $r6 (8)
>1452: mad f32 $r6 $r1 $r1 $r6 (8)
>1453: rsq f32 $r6 abs $r6 (8)
>1454: mad f32 $r14 $r5 $r6 $r14 (8)
>1455: mad f32 $r15 $r0 $r6 $r15 (8)
>1456: join mad f32 $r16 $r1 $r6 $r16 (8)
>BB:69 (0 instructions) - df = { }
> -> BB:54 (forward)
>BB:54 (3 instructions) - idom = BB:52, df = { BB:57 }
> -> BB:70 (tree)
> -> BB:55 (tree)
>1457: joinat BB:56 (8)
>1458: set u8 $p0 lt s32 $r255 $r9 (8)
>1459: not $p0 join BB:56 (8)
>BB:55 (54 instructions) - idom = BB:54, df = { BB:56 }
> -> BB:56 (forward)
>1460: shl u32 $r5 $r8 0x00000004 (8)
>1461: add u32 { $r0 $c0 } $r5 c7[0x330] (8)
>1462: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1463: add u32 $r6 $r5 0x00000004 (8)
>1464: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1465: not $p0 ld  u32 $r6 g[$r0d+0x0] (8)
>1466: $p0 mov u32 $r6 0x00000000 (8)
>1467: add u32 $r7 $r5 0x00000008 (8)
>1468: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1469: not $p0 ld  u32 $r7 g[$r0d+0x4] (8)
>1470: $p0 mov u32 $r7 0x00000000 (8)
>1471: add u32 $r5 $r5 0x0000000c (8)
>1472: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1473: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
>1474: $p0 mov u32 $r5 0x00000000 (8)
>1475: add u32 $r0 $r8 neg c0[0x0] (8)
>1476: shl u32 $r9 $r0 0x00000004 (8)
>1477: add u32 { $r0 $c0 } $r9 c7[0x330] (8)
>1478: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1479: add u32 $r10 $r9 0x00000004 (8)
>1480: set u8 $p0 gt u32 $r10 c7[0x338] (8)
>1481: not $p0 ld  u32 $r10 g[$r0d+0x0] (8)
>1482: $p0 mov u32 $r10 0x00000000 (8)
>1483: add u32 $r11 $r9 0x00000008 (8)
>1484: set u8 $p0 gt u32 $r11 c7[0x338] (8)
>1485: not $p0 ld  u32 $r11 g[$r0d+0x4] (8)
>1486: $p0 mov u32 $r11 0x00000000 (8)
>1487: add u32 $r9 $r9 0x0000000c (8)
>1488: set u8 $p0 gt u32 $r9 c7[0x338] (8)
>1489: not $p0 ld  u32 $r0 g[$r0d+0x8] (8)
>1490: $p0 mov u32 $r0 0x00000000 (8)
>1491: add f32 $r1 $r6 neg $r10 (8)
>1492: add f32 $r6 $r7 neg $r11 (8)
>1493: add f32 $r0 $r5 neg $r0 (8)
>1494: mul f32 $r5 $r1 $r1 (8)
>1495: mad f32 $r5 $r6 $r6 $r5 (8)
>1496: mad f32 $r5 $r0 $r0 $r5 (8)
>1497: rsq f32 $r5 abs $r5 (8)
>1498: mul f32 $r1 $r1 $r5 (8)
>1499: mul f32 $r6 $r6 $r5 (8)
>1500: mul f32 $r0 $r0 $r5 (8)
>1501: mul f32 $r5 $r0 $r2 (8)
>1502: mul f32 $r7 $r1 $r3 (8)
>1503: mul f32 $r9 $r6 $r4 (8)
>1504: mad f32 $r3 $r6 $r3 neg $r5 (8)
>1505: mad f32 $r0 $r0 $r4 neg $r7 (8)
>1506: mad f32 $r1 $r1 $r2 neg $r9 (8)
>1507: mul f32 $r2 $r3 $r3 (8)
>1508: mad f32 $r2 $r0 $r0 $r2 (8)
>1509: mad f32 $r2 $r1 $r1 $r2 (8)
>1510: rsq f32 $r2 abs $r2 (8)
>1511: mad f32 $r14 $r3 $r2 $r14 (8)
>1512: mad f32 $r15 $r0 $r2 $r15 (8)
>1513: join mad f32 $r16 $r1 $r2 $r16 (8)
>BB:70 (0 instructions) - df = { }
> -> BB:56 (forward)
>BB:56 (1 instructions) - idom = BB:54, df = { BB:57 }
> -> BB:57 (forward)
>1514: join BB:57 (8)
>BB:68 (0 instructions) - df = { }
> -> BB:57 (forward)
>BB:57 (20 instructions) - idom = BB:51, df = { }
> -> BB:1 (tree)
>1515: shl u32 $r2 $r8 0x00000004 (8)
>1516: mul f32 $r0 $r14 $r14 (8)
>1517: mad f32 $r0 $r15 $r15 $r0 (8)
>1518: mad f32 $r0 $r16 $r16 $r0 (8)
>1519: rsq f32 $r0 abs $r0 (8)
>1520: mul f32 $r3 $r14 $r0 (8)
>1521: mul f32 $r4 $r15 $r0 (8)
>1522: mul f32 $r5 $r16 $r0 (8)
>1523: add u32 { $r0 $c0 } $r2 c7[0x310] (8)
>1524: add u32 $r1 $r255 c7[0x314] $c0 (8)
>1525: add u32 $r6 $r2 0x00000004 (8)
>1526: set u8 $p0 gt u32 $r6 c7[0x318] (8)
>1527: not $p0 st  u32 # g[$r0d+0x0] $r3 (8)
>1528: add u32 $r3 $r2 0x00000008 (8)
>1529: set u8 $p0 gt u32 $r3 c7[0x318] (8)
>1530: not $p0 st  u32 # g[$r0d+0x4] $r4 (8)
>1531: add u32 $r2 $r2 0x0000000c (8)
>1532: set u8 $p0 gt u32 $r2 c7[0x318] (8)
>1533: not $p0 st  u32 # g[$r0d+0x8] $r5 (8)
>1534: membar (SUBOP:7) - # (8)
>BB:1 (1 instructions) - idom = BB:57, df = { }
>1535: exit - # (8)
>BB:37 (34 instructions) - idom = BB:38, df = { BB:10 }
> -> BB:66 (tree)
> -> BB:44 (tree)
>1536: shl u32 $r2 $r8 0x00000004 (8)
>1537: add u32 { $r0 $c0 } $r2 c7[0x330] (8)
>1538: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1539: add u32 $r3 $r2 0x00000004 (8)
>1540: set u8 $p0 gt u32 $r3 c7[0x338] (8)
>1541: not $p0 ld  u32 $r3 g[$r0d+0x0] (8)
>1542: $p0 mov u32 $r3 0x00000000 (8)
>1543: add u32 $r4 $r2 0x00000008 (8)
>1544: set u8 $p0 gt u32 $r4 c7[0x338] (8)
>1545: not $p0 ld  u32 $r4 g[$r0d+0x4] (8)
>1546: $p0 mov u32 $r4 0x00000000 (8)
>1547: add u32 $r5 $r2 0x0000000c (8)
>1548: set u8 $p0 gt u32 $r5 c7[0x338] (8)
>1549: not $p0 ld  u32 $r5 g[$r0d+0x8] (8)
>1550: $p0 mov u32 $r5 0x00000000 (8)
>1551: add u32 $r2 $r2 0x00000010 (8)
>1552: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1553: not $p0 ld  u32 $r0 g[$r0d+0xc] (8)
>1554: $p0 mov u32 $r0 0x00000000 (8)
>1555: add f32 $r1 $r3 neg c0[0x40] (8)
>1556: add f32 $r2 $r4 neg c0[0x44] (8)
>1557: add f32 $r3 $r5 neg c0[0x48] (8)
>1558: add f32 $r0 $r0 neg c0[0x4c] (8)
>1559: mul f32 $r4 $r1 $r1 (8)
>1560: mad f32 $r4 $r2 $r2 $r4 (8)
>1561: mad f32 $r4 $r3 $r3 $r4 (8)
>1562: mad f32 $r4 $r0 $r0 $r4 (8)
>1563: rsq f32 $r4 $r4 (8)
>1564: rcp f32 $r4 $r4 (8)
>1565: ld  u32 $r5 c0[0x50] (8)
>1566: add f32 $r5 $r5 0.010000 (8)
>1567: joinat BB:45 (8)
>1568: set u8 $p0 lt f32 $r4 $r5 (8)
>1569: not $p0 join BB:45 (8)
>BB:44 (31 instructions) - idom = BB:37, df = { BB:45 }
> -> BB:45 (forward)
>1570: shl u32 $r4 $r8 0x00000004 (8)
>1571: mul f32 $r5 $r1 $r1 (8)
>1572: mad f32 $r5 $r2 $r2 $r5 (8)
>1573: mad f32 $r5 $r3 $r3 $r5 (8)
>1574: mad f32 $r5 $r0 $r0 $r5 (8)
>1575: rsq f32 $r5 abs $r5 (8)
>1576: mul f32 $r1 $r1 $r5 (8)
>1577: mul f32 $r2 $r2 $r5 (8)
>1578: mul f32 $r3 $r3 $r5 (8)
>1579: mul f32 $r0 $r0 $r5 (8)
>1580: ld  u32 $r5 c0[0x50] (8)
>1581: add f32 $r5 $r5 0.010000 (8)
>1582: mad f32 $r6 $r1 $r5 c0[0x40] (8)
>1583: mad f32 $r2 $r2 $r5 c0[0x44] (8)
>1584: mad f32 $r3 $r3 $r5 c0[0x48] (8)
>1585: mad f32 $r5 $r0 $r5 c0[0x4c] (8)
>1586: add u32 { $r0 $c0 } $r4 c7[0x330] (8)
>1587: add u32 $r1 $r255 c7[0x334] $c0 (8)
>1588: add u32 $r7 $r4 0x00000004 (8)
>1589: set u8 $p0 gt u32 $r7 c7[0x338] (8)
>1590: not $p0 st  u32 # g[$r0d+0x0] $r6 (8)
>1591: add u32 $r6 $r4 0x00000008 (8)
>1592: set u8 $p0 gt u32 $r6 c7[0x338] (8)
>1593: not $p0 st  u32 # g[$r0d+0x4] $r2 (8)
>1594: add u32 $r2 $r4 0x0000000c (8)
>1595: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1596: not $p0 st  u32 # g[$r0d+0x8] $r3 (8)
>1597: add u32 $r2 $r4 0x00000010 (8)
>1598: set u8 $p0 gt u32 $r2 c7[0x338] (8)
>1599: not $p0 st  u32 # g[$r0d+0xc] $r5 (8)
>1600: join membar (SUBOP:7) - # (8)
>BB:66 (0 instructions) - df = { }
> -> BB:45 (forward)
>BB:45 (3 instructions) - idom = BB:37, df = { BB:10 }
> -> BB:10 (back)
>1601: bar u32 # $r255 $r255 (8)
>1602: add u32 $r12 $r12 0x00000001 (8)
>1603: bra BB:10 (8)
>3708: message: shader compiler issue 1: type: 5, local: 0, gpr: 46, inst: 1604, bytes: 14672
>shader binary code (0x3950 bytes):
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>8010a0a0 0810a010 001c000e cc000c00 029c0c0e 84020000 019c0412 e3400000 
>019c080a e3400000 019c000e e3400000 001c0002 64c03c00 ff9c0001 407fffff 
>a000b0a0 0810b0a0 00000000 14800001 001c241e db181c00 00603c02 85800000 
>001c2002 60800000 021c0015 c2400000 661c1402 608400e0 669ffc06 608040e0 
>8010b0a0 0810b0a0 021c1419 c0800000 671c181e 5b401ce0 00200018 c4800000 
>0003c01a 74000000 041c141d c0800000 671c1c1e 5b401ce0 0220001c c4800000 
>10b0a080 08b0a080 0003c01e 74000000 061c1415 c0800000 671c141e 5b401ce0 
>04200014 c4800000 0003c016 74000000 021c2029 c2400000 661c2802 608400e0 
>10b0a010 08b0a080 669ffc06 608040e0 021c282d c0800000 671c2c1e 5b401ce0 
>0020002c c4800000 0003c02e 74000000 041c2831 c0800000 671c301e 5b401ce0 
>b0a08010 08108010 02200030 c4800000 0003c032 74000000 061c2829 c0800000 
>671c281e 5b401ce0 04200000 c4800000 0003c002 74000000 059c1806 e2c10000 
>a0a0809c 0810a0a0 061c1c1a e2c10000 001c1402 e2c10000 009c0416 e3400000 
>031c1816 cc001400 001c0016 cc001400 029c1416 84020000 029c0406 e3400000 
>8010a080 0880109c 029c181a e3400000 029c0002 e3400000 011c0016 e3400000 
>019c041e e3400000 021c182a e3400000 019c1816 cc101400 021c0002 cc101c00 
>a0a0a09c 088010a0 011c0406 cc102800 029c141a e3400000 001c001a cc001800 
>009c041a cc001800 029c181a 84020000 031c143a cc003800 031c003e cc003c00 
>00b08000 0810b0a0 035c0442 cc004000 00000000 14800001 049ffc1e db181c00 
>00603c02 85800000 021c2015 c2400000 661c1402 608400e0 669ffc06 608040e0 
>8010b0a0 0810b0a0 021c1419 c0800000 671c181e 5b401ce0 00200018 c4800000 
>0003c01a 74000000 041c141d c0800000 671c1c1e 5b401ce0 0220001c c4800000 
>10b0a080 08a0a080 0003c01e 74000000 061c1415 c0800000 671c141e 5b401ce0 
>04200014 c4800000 0003c016 74000000 001c2002 60880000 021c0025 c2400000 
>b0a010b0 08a08010 661c2402 608400e0 669ffc06 608040e0 021c2429 c0800000 
>671c281e 5b401ce0 00200028 c4800000 0003c02a 74000000 041c242d c0800000 
>a08010b0 088010b0 671c2c1e 5b401ce0 0220002c c4800000 0003c02e 74000000 
>061c2425 c0800000 671c241e 5b401ce0 04200000 c4800000 0003c002 74000000 
>a0809c10 08a0a0a0 051c1806 e2c10000 059c1c1a e2c10000 001c1402 e2c10000 
>009c0416 e3400000 031c1816 cc001400 001c0016 cc001400 029c1416 84020000 
>10a08010 08109c80 029c0406 e3400000 029c181a e3400000 029c0002 e3400000 
>011c0016 e3400000 019c041e e3400000 021c1826 e3400000 019c180e cc101400 
>a0a09c80 0810a0a0 021c0002 cc101c00 011c0406 cc102400 019c0c0a e3400000 
>001c000a cc000800 009c040a cc000800 029c080a 84020000 011c0c3a cc003800 
>10000080 08a0a0a0 011c003e cc003c00 015c0442 cc004000 005c3c02 85800000 
>021c2009 c2400000 071c3802 e3400000 079c3c02 cc000000 081c4002 cc000000 
>108010a0 08a010b0 029c0002 84020000 001c380e e3400000 001c3c12 e3400000 
>001c4016 e3400000 621c0802 608400e0 629ffc06 608040e0 021c0819 c0800000 
>b0a010b0 08b0a010 631c181e 5b401ce0 0020000c e4800000 041c080d c0800000 
>631c0c1e 5b401ce0 02200010 e4800000 061c0809 c0800000 631c081e 5b401ce0 
>a0b88010 08a010b0 04200014 e4800000 001c0402 7cc00000 001c003c 18000000 
>021c2009 c2400000 661c0802 608400e0 669ffc06 608040e0 021c080d c0800000 
>a08010b0 088010b0 671c0c1e 5b401ce0 0020000c c4800000 0003c00e 74000000 
>041c0811 c0800000 671c101e 5b401ce0 02200010 c4800000 0003c012 74000000 
>8010b0a0 0810b0a0 061c0815 c0800000 671c141e 5b401ce0 04200014 c4800000 
>0003c016 74000000 081c0809 c0800000 671c081e 5b401ce0 06200000 c4800000 
>98801080 08a0a080 0003c002 74000000 081c0c06 62c10000 089c100a 62c10000 
>091c140e 62c10000 099c0002 62c10000 009c0412 e3400000 011c0812 cc001000 
>10a0a0a0 08a010a0 019c0c12 cc001000 001c0012 cc001000 029c1012 84000000 
>021c1012 84000000 0a1c0016 64c03c00 851c1414 401e11eb 98000000 14800000 
>a01000b0 08a0a0a0 029c101e dd881c00 00603c02 85800000 021c2011 c2400000 
>009c0416 e3400000 011c0816 cc001400 019c0c16 cc001400 001c0016 cc001400 
>108010a0 08a0a080 029c1416 84020000 029c0406 e3400000 029c080a e3400000 
>029c0c0e e3400000 029c0002 e3400000 0a1c0016 64c03c00 851c1414 401e11eb 
>80108010 08a010b0 081c041a 8c001400 089c080a 8c001400 091c0c0e 8c001400 
>099c0016 8c001400 661c1002 608400e0 669ffc06 608040e0 021c101d c0800000 
>b0a010b0 08b0a010 671c1c1e 5b401ce0 00200018 e4800000 041c1019 c0800000 
>671c181e 5b401ce0 02200008 e4800000 061c1009 c0800000 671c081e 5b401ce0 
>10b0a010 08801000 0420000c e4800000 081c1009 c0800000 671c081e 5b401ce0 
>06200014 e4800000 005c0402 7cc00000 7f9ffc02 85401c00 009c3031 c0800000 
>0000009c 08000000 a81c003c 12007fe6 
>COMPUTE LAUNCH DESCRIPTOR:
>...
>[1c]: 0xbc000000
>[20]: 0x000fbe00
>...
>[2c]: 0x44014000
>[30]: 0x00000001
>[34]: 0x00010001
>...
>[48]: 0x04000000
>[4c]: 0x00010001
>[50]: 0x20000081
>...
>[74]: 0x003d0000
>[78]: 0x80000000
>...
>[ac]: 0x003e2800
>[b0]: 0x04000000
>[b4]: 0x08000000
>[b8]: 0x2e000000
>[bc]: 0x30000800
>...
>entry = 0xfbe00
>grid dimensions = 1x1x1
>block dimensions = 1024x1x1
>s[] size: 0x0
>l[] size: -0x0 / +0x0
>stack size: 0x800
>barrier count: 1
>$r count: 46
>cache split: 16K_SHARED_48K_L1
>CB[0]: address = 0x3d0000, size 0x10000
>CB[7]: address = 0x3e2800, size 0x800
>HDR[00] = 0x00020461
>HDR[04] = 0x00000000
>HDR[08] = 0x00000000
>HDR[0c] = 0x00000000
>HDR[10] = 0x000ff000
>HDR[14] = 0x00000000
>HDR[18] = 0x0000007f
>HDR[1c] = 0x00000000
>HDR[20] = 0x00000000
>HDR[24] = 0x00000000
>HDR[28] = 0x00000000
>HDR[2c] = 0x00000000
>HDR[30] = 0x00000000
>HDR[34] = 0x000ff000
>HDR[38] = 0x00000000
>HDR[3c] = 0x00000000
>HDR[40] = 0x00000000
>HDR[44] = 0x00000000
>HDR[48] = 0x00000000
>HDR[4c] = 0x00000000
>shader binary code (0x128 bytes):
>108010dc 0880109c 401ffc02 7ecffc00 001c0012 63408000 009c0016 63408000 
>011c001a 63408000 019c0002 63408000 021c0412 4d001000 029c0416 4d001400 
>80109c10 08109c10 031c041a 4d001800 039c0402 4d000000 041c0806 4d001000 
>049c0816 4d001400 051c081a 4d001800 059c0802 4d000000 061c0c12 4d000400 
>dc801080 089c8010 069c0c16 4d001400 071c0c1a 4d001800 079c0c1e 4d000000 
>481ffc02 7ec7fc00 081c000a 63408000 089c000e 63408000 091c0002 63408000 
>dc108010 089c8010 0a1c040a 4d000800 0a9c040e 4d000c00 0b1c0422 4d000000 
>4c1ffc26 7ec3fc00 0c1c2402 4d000800 0c9c2406 4d000c00 0d1c240a 4d002000 
>39010c8c 08000001 401ffc02 7f07fc00 441ffc0a 7f03fc00 381ffc12 7f0ffc00 
>001c003c 18000000 
>HDR[00] = 0x00021462
>HDR[04] = 0x00000000
>HDR[08] = 0x00000000
>HDR[0c] = 0x00000000
>HDR[10] = 0x00000000
>HDR[14] = 0x80000000
>HDR[18] = 0x0000002a
>HDR[1c] = 0x00000000
>HDR[20] = 0x00000000
>HDR[24] = 0x00000000
>HDR[28] = 0x00000000
>HDR[2c] = 0x00000000
>HDR[30] = 0x00000000
>HDR[34] = 0x00000000
>HDR[38] = 0x00000000
>HDR[3c] = 0x00000000
>HDR[40] = 0x00000000
>HDR[44] = 0x00000000
>HDR[48] = 0x0000000f
>HDR[4c] = 0x00000000
>shader binary code (0xc0 bytes):
>10b8a0b8 08b810b8 7f9ffc02 7483fc3e 021c0002 84000000 001ffc06 74a3fc40 
>009c040a e3408000 001ffc0e 74a3fc42 019c0c0a cd000800 001ffc02 74a3fc44 
>8010a0a0 08a0a09c 001c000a cd000800 029c080a 84020000 011c0406 e3408000 
>011c0c0e e3408000 011c0002 e3408000 001c0406 63408000 009c0c06 4d000400 
>8010a0a0 08b88010 011c0002 4d000400 001c280e e5508000 021c0c02 63408000 
>029c0c06 63408000 031c0c0a 63408000 039c0c0e 63408000 001c003c 18000000 
>COMPUTE LAUNCH DESCRIPTOR:
>...
>[1c]: 0xbc000000
>[20]: 0x000fbe00
>...
>[2c]: 0x44014000
>[30]: 0x00000001
>[34]: 0x00010001
>...
>[48]: 0x04000000
>[4c]: 0x00010001
>[50]: 0x20000081
>...
>[74]: 0x003d0000
>[78]: 0x80000000
>...
>[ac]: 0x003e2800
>[b0]: 0x04000000
>[b4]: 0x08000000
>[b8]: 0x2e000000
>[bc]: 0x30000800
>...
>entry = 0xfbe00
>grid dimensions = 1x1x1
>block dimensions = 1024x1x1
>s[] size: 0x0
>l[] size: -0x0 / +0x0
>stack size: 0x800
>barrier count: 1
>$r count: 46
>cache split: 16K_SHARED_48K_L1
>CB[0]: address = 0x3d0000, size 0x10000
>CB[7]: address = 0x3e2800, size 0x800

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Attachments on bug 96258: 124145 | 124146 | 124147

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