Attachment 124243 Details for Bug 86763 – dmesg_bsw

dmesg_bsw

bug_8763_dmesg (text/plain), 250.49 KB, created by Elio on 2016-06-01 19:38:18 UTC

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Creator: Elio

Created: 2016-06-01 19:38:18 UTC

Size: 250.49 KB

patch

obsolete

>[    9.014782] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[    9.029048] iwlwifi 0000:02:00.0 wlp2s0: renamed from wlan0
>[    9.102457] audit: type=1400 audit(1464773301.822:2): apparmor="STATUS" operation="profile_load" name="/usr/bin/ubuntu-core-launcher" pid=553 comm="apparmor_parser"
>[    9.107718] audit: type=1400 audit(1464773301.826:3): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=550 comm="apparmor_parser"
>[    9.107733] audit: type=1400 audit(1464773301.826:4): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=550 comm="apparmor_parser"
>[    9.107741] audit: type=1400 audit(1464773301.826:5): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-helper" pid=550 comm="apparmor_parser"
>[    9.107749] audit: type=1400 audit(1464773301.826:6): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=550 comm="apparmor_parser"
>[    9.108849] audit: type=1400 audit(1464773301.826:7): apparmor="STATUS" operation="profile_load" name="/usr/lib/lightdm/lightdm-guest-session" pid=549 comm="apparmor_parser"
>[    9.108863] audit: type=1400 audit(1464773301.826:8): apparmor="STATUS" operation="profile_load" name="chromium" pid=549 comm="apparmor_parser"
>[    9.111962] audit: type=1400 audit(1464773301.830:9): apparmor="STATUS" operation="profile_load" name="/usr/sbin/cups-browsed" pid=555 comm="apparmor_parser"
>[    9.112018] audit: type=1400 audit(1464773301.830:10): apparmor="STATUS" operation="profile_load" name="webbrowser-app" pid=554 comm="apparmor_parser"
>[    9.279821] calling  bnep_init+0x0/0x92 [bnep] @ 634
>[    9.279834] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
>[    9.279836] Bluetooth: BNEP filters: protocol multicast
>[    9.279850] Bluetooth: BNEP socket layer initialized
>[    9.279855] initcall bnep_init+0x0/0x92 [bnep] returned 0 after 20 usecs
>[    9.336823] [drm:i915_gem_open] 
>[    9.336995] [drm:i915_gem_open] 
>[    9.337082] [drm:i915_gem_open] 
>[    9.337149] [drm:i915_gem_open] 
>[    9.337210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1]
>[    9.337214] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
>[    9.341798] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    9.341804] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    9.343747] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    9.343758] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    9.344164] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    9.344168] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    9.344356] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    9.344374] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected
>[    9.344406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[    9.344414] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[    9.344866] [drm:intel_dp_get_dpcd] DPCD: 11 0a c4 01 01 00 01 00 02 02 06 00 00 00 00
>[    9.345168] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[    9.345173] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[    9.345176] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[    9.345179] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[    9.345879] [drm:drm_edid_to_eld] ELD monitor ASUS PB287Q
>[    9.345887] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 600, latency present 0 0, video latency 0 0, audio latency 0 0
>[    9.345889] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    9.345962] [drm:drm_mode_debug_printmodeline] Modeline 111:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[    9.345965] [drm:drm_mode_prune_invalid] Not using 3840x2160 mode: CLOCK_HIGH
>[    9.345973] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] probed modes :
>[    9.345977] [drm:drm_mode_debug_printmodeline] Modeline 59:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[    9.345983] [drm:drm_mode_debug_printmodeline] Modeline 61:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[    9.345987] [drm:drm_mode_debug_printmodeline] Modeline 60:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[    9.345991] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[    9.345994] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    9.345998] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    9.346002] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    9.346006] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    9.346012] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    9.346016] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    9.346020] [drm:drm_mode_debug_printmodeline] Modeline 68:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    9.346024] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    9.346027] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    9.346031] [drm:drm_mode_debug_printmodeline] Modeline 67:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    9.346036] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    9.346042] [drm:drm_mode_debug_printmodeline] Modeline 69:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    9.346046] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    9.346049] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    9.346053] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    9.346057] [drm:drm_mode_debug_printmodeline] Modeline 98:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    9.346061] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    9.346065] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    9.346071] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    9.346075] [drm:drm_mode_debug_printmodeline] Modeline 108:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    9.346078] [drm:drm_mode_debug_printmodeline] Modeline 96:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    9.346082] [drm:drm_mode_debug_printmodeline] Modeline 82:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    9.346086] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    9.346090] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    9.346093] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    9.346097] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    9.346101] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    9.346104] [drm:drm_mode_debug_printmodeline] Modeline 103:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    9.346108] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    9.346112] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    9.346116] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[    9.346119] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    9.346123] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    9.346127] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    9.346130] [drm:drm_mode_debug_printmodeline] Modeline 77:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    9.346198] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-2]
>[    9.346203] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[    9.473654] [drm:intel_hdmi_detect] HDMI live status down
>[    9.473671] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-2] disconnected
>[    9.473704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:49:DP-2]
>[    9.473708] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[    9.473717] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:49:DP-2] disconnected
>[    9.473724] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-3]
>[    9.473726] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-3]
>[    9.477640] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 w(1)
>[    9.477646] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK on first message, retry
>[    9.477864] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 w(1)
>[    9.477871] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[    9.481679] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0040 w(1)
>[    9.481686] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK on first message, retry
>[    9.482214] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0040 w(1)
>[    9.482228] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-3] disconnected
>[    9.482258] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-3]
>[    9.482263] [drm:intel_dp_detect] [CONNECTOR:53:DP-3]
>[    9.482784] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 01 00 03 01 81 00 00 00 00 00 00 00
>[    9.483165] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[    9.483174] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[    9.483177] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[    9.483180] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[    9.484013] [drm:intel_dp_probe_oui] Sink OUI: 000000
>[    9.484362] [drm:intel_dp_probe_oui] Branch OUI: 0080e1
>[    9.484774] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    9.484792] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-3] probed modes :
>[    9.484797] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    9.484801] [drm:drm_mode_debug_printmodeline] Modeline 89:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[    9.484805] [drm:drm_mode_debug_printmodeline] Modeline 102:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    9.484808] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    9.484812] [drm:drm_mode_debug_printmodeline] Modeline 87:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    9.484816] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    9.484820] [drm:drm_mode_debug_printmodeline] Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    9.484823] [drm:drm_mode_debug_printmodeline] Modeline 109:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    9.484827] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    9.484831] [drm:drm_mode_debug_printmodeline] Modeline 91:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    9.484835] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    9.484838] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    9.625388] IPv6: ADDRCONF(NETDEV_UP): wlp2s0: link is not ready
>[    9.625569] iwlwifi 0000:02:00.0: L1 Disabled - LTR Enabled
>[    9.625885] iwlwifi 0000:02:00.0: L1 Disabled - LTR Enabled
>[    9.710325] [drm:i915_gem_open] 
>[    9.744162] [drm:i915_gem_open] 
>[    9.746366] [drm:i915_gem_open] 
>[    9.748967] [drm:drm_mode_addfb2] [FB:54]
>[    9.749385] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    9.749391] [drm:i915_pages_create_for_stolen] offset=0x1000, size=16384
>[    9.750006] [drm:internal_framebuffer_create] could not create framebuffer
>[    9.750028] [drm:internal_framebuffer_create] could not create framebuffer
>[    9.750055] [drm:drm_mode_addfb2] [FB:54]
>[    9.770772] iwlwifi 0000:02:00.0: L1 Disabled - LTR Enabled
>[    9.771046] iwlwifi 0000:02:00.0: L1 Disabled - LTR Enabled
>[    9.823619] [drm:drm_mode_addfb2] [FB:54]
>[    9.855429] IPv6: ADDRCONF(NETDEV_UP): wlp2s0: link is not ready
>[    9.868866] IPv6: ADDRCONF(NETDEV_UP): eno1: link is not ready
>[    9.912352] r8169 0000:01:00.0 eno1: link down
>[    9.912354] r8169 0000:01:00.0 eno1: link down
>[    9.912444] IPv6: ADDRCONF(NETDEV_UP): eno1: link is not ready
>[   10.008788] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   10.008805] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   10.013460] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   10.029036] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   10.029116] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[   10.029125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[   10.029167] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   10.029968] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   10.116254] IPv6: ADDRCONF(NETDEV_UP): wlp2s0: link is not ready
>[   10.300399] [drm:i915_gem_open] 
>[   10.448102] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   10.448116] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   10.448173] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   10.448181] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   10.635263] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   10.635273] [drm:i915_pages_create_for_stolen] offset=0x5000, size=16384
>[   11.055582] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   11.055603] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   11.056069] [drm:intel_dp_get_dpcd] DPCD: 11 0a c4 01 01 00 01 00 02 02 06 00 00 00 00
>[   11.056393] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[   11.056399] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   11.056402] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   11.056404] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   11.056921] [drm:drm_edid_to_eld] ELD monitor ASUS PB287Q
>[   11.056928] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 600, latency present 0 0, video latency 0 0, audio latency 0 0
>[   11.056930] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[   11.057048] [drm:drm_mode_debug_printmodeline] Modeline 110:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   11.057052] [drm:drm_mode_prune_invalid] Not using 3840x2160 mode: CLOCK_HIGH
>[   11.057061] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] probed modes :
>[   11.057065] [drm:drm_mode_debug_printmodeline] Modeline 59:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[   11.057069] [drm:drm_mode_debug_printmodeline] Modeline 61:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[   11.057073] [drm:drm_mode_debug_printmodeline] Modeline 60:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[   11.057076] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   11.057080] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   11.057084] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   11.057088] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   11.057092] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   11.057095] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   11.057099] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   11.057103] [drm:drm_mode_debug_printmodeline] Modeline 68:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   11.057107] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   11.057110] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   11.057114] [drm:drm_mode_debug_printmodeline] Modeline 67:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   11.057118] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   11.057122] [drm:drm_mode_debug_printmodeline] Modeline 69:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   11.057125] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   11.057129] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   11.057133] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   11.057137] [drm:drm_mode_debug_printmodeline] Modeline 98:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[   11.057140] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   11.057144] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   11.057148] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   11.057152] [drm:drm_mode_debug_printmodeline] Modeline 108:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   11.057155] [drm:drm_mode_debug_printmodeline] Modeline 96:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   11.057159] [drm:drm_mode_debug_printmodeline] Modeline 82:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   11.057163] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   11.057167] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   11.057170] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   11.057174] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   11.057178] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   11.057181] [drm:drm_mode_debug_printmodeline] Modeline 103:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   11.057185] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   11.057189] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   11.057192] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   11.057196] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   11.057200] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   11.057204] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   11.057207] [drm:drm_mode_debug_printmodeline] Modeline 77:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   11.058695] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:49:DP-2]
>[   11.058702] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[   11.058717] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:49:DP-2] disconnected
>[   11.058731] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-3]
>[   11.058737] [drm:intel_dp_detect] [CONNECTOR:53:DP-3]
>[   11.059217] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 01 00 03 01 81 00 00 00 00 00 00 00
>[   11.059654] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[   11.059661] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   11.059664] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   11.059667] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   11.060629] [drm:intel_dp_probe_oui] Sink OUI: 000000
>[   11.060970] [drm:intel_dp_probe_oui] Branch OUI: 0080e1
>[   11.061353] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   11.061368] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-3] probed modes :
>[   11.061373] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   11.061377] [drm:drm_mode_debug_printmodeline] Modeline 89:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   11.061380] [drm:drm_mode_debug_printmodeline] Modeline 102:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   11.061384] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   11.061388] [drm:drm_mode_debug_printmodeline] Modeline 87:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   11.061392] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   11.061395] [drm:drm_mode_debug_printmodeline] Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   11.061399] [drm:drm_mode_debug_printmodeline] Modeline 109:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   11.061403] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   11.061407] [drm:drm_mode_debug_printmodeline] Modeline 91:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   11.061411] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   11.061414] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   11.061493] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1]
>[   11.061497] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
>[   11.062398] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   11.062402] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   11.062567] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   11.062572] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   11.062727] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   11.062729] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   11.062893] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   11.062898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected
>[   11.062918] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-2]
>[   11.062920] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[   11.189882] [drm:intel_hdmi_detect] HDMI live status down
>[   11.189897] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-2] disconnected
>[   11.189949] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-3]
>[   11.189953] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-3]
>[   11.190172] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 w(1)
>[   11.190178] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK on first message, retry
>[   11.190672] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 w(1)
>[   11.190679] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[   11.191424] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0040 w(1)
>[   11.191443] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK on first message, retry
>[   11.191935] [drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0040 w(1)
>[   11.191951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-3] disconnected
>[   11.380982] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   11.380995] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   11.381037] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   11.381046] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   11.420354] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.420438] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.420443] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.423462] [drm:drm_mode_addfb2] [FB:55]
>[   11.424248] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   11.424260] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   11.425937] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   11.425945] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   11.430893] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   11.430899] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   11.435951] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   11.435960] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   11.440901] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   11.440910] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   11.446441] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[   11.446465] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[   11.462507] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.462520] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.469898] [drm:drm_mode_addfb2] [FB:58]
>[   11.470153] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[   11.470163] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[   11.470896] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[   11.470901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[   11.480633] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   11.480648] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   11.480704] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   11.480715] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   11.481892] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.481900] [drm:internal_framebuffer_create] could not create framebuffer
>[   11.484457] [drm:drm_mode_addfb2] [FB:119]
>[   11.484563] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   11.484573] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   11.484592] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[   11.484602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[   11.486762] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[   11.486769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[   11.550893] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   11.550905] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   12.169125] calling  rfcomm_init+0x0/0xd9 [rfcomm] @ 984
>[   12.172812] Bluetooth: RFCOMM TTY layer initialized
>[   12.172836] Bluetooth: RFCOMM socket layer initialized
>[   12.172849] Bluetooth: RFCOMM ver 1.11
>[   12.172871] initcall rfcomm_init+0x0/0xd9 [rfcomm] returned 0 after 3633 usecs
>[   13.118628] r8169 0000:01:00.0 eno1: link up
>[   13.118652] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready
>[   16.569577] random: nonblocking pool is initialized
>[   17.926791] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   17.962739] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   17.962755] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=511, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   17.962828] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   17.980470] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   17.980485] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=511, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   17.980744] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   17.996005] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   17.996014] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   17.996045] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   17.996715] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[   17.996722] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  120.412784] [drm:i915_gem_open] 
>[  120.413236] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  120.413243] [drm:i915_pages_create_for_stolen] offset=0x9000, size=16384
>[  120.414510] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  120.414514] [drm:i915_pages_create_for_stolen] offset=0xd000, size=16384
>[  120.415072] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  120.415076] [drm:i915_pages_create_for_stolen] offset=0x11000, size=16384
>[  120.415351] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  120.415355] [drm:i915_pages_create_for_stolen] offset=0x15000, size=16384
>[  133.125072] kms_plane: executing
>[  133.125310] [drm:i915_gem_open] 
>[  133.125663] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  133.125676] [drm:i915_pages_create_for_stolen] offset=0x19000, size=16384
>[  133.126874] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  133.126885] [drm:i915_pages_create_for_stolen] offset=0x1d000, size=16384
>[  133.127850] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  133.127861] [drm:i915_pages_create_for_stolen] offset=0x21000, size=16384
>[  133.128151] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  133.128163] [drm:i915_pages_create_for_stolen] offset=0x25000, size=16384
>[  133.129657] [drm:i915_gem_open] 
>[  133.132370] kms_plane: starting subtest plane-position-covered-pipe-A-plane-1
>[  133.132580] [drm:drm_mode_addfb2] [FB:121]
>[  133.177317] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  133.177329] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  133.231489] [drm:pipe_crc_set_source] collecting CRCs for pipe A, DP-B
>[  133.299352] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  133.332259] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  133.332348] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  133.332412] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  133.364633] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  133.364973] [drm:intel_disable_pipe] disabling pipe A
>[  133.397715] [drm:intel_dp_link_down] 
>[  133.427610] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  133.436721] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  133.436757] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  133.441486] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  133.449115] [drm:intel_disable_pipe] disabling pipe C
>[  133.465337] [drm:intel_dp_link_down] 
>[  133.486280] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  133.506990] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz
>[  133.507021] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  133.507045] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  133.507060] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  133.507074] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  133.507088] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  133.507102] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  133.507113] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  133.507128] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  133.507141] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  133.507155] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  133.507168] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  133.507339] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x256007ff)
>[  133.644604] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  133.644626] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  133.646533] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  133.688170] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  133.688191] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  133.731290] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  133.731311] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  133.733102] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  133.776803] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  133.776824] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  133.821072] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  133.821093] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  133.865451] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  133.865473] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  133.910026] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  133.910047] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  133.912693] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  133.913036] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  133.913055] [drm:intel_enable_pipe] enabling pipe C
>[  133.913092] [drm:intel_psr_enable] PSR not supported by this panel
>[  133.930310] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  133.939237] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  133.948579] [drm:verify_crtc_state] [CRTC:26]
>[  133.948624] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  133.948644] [drm:verify_crtc_state] [CRTC:36]
>[  133.985642] [drm:drm_mode_addfb2] [FB:111]
>[  134.026077] [drm:drm_mode_addfb2] [FB:121]
>[  134.026813] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  134.026821] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  134.026843] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  134.026846] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  134.026851] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  134.026860] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  134.026863] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  134.026867] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  134.026871] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880274f5c800 for pipe A
>[  134.026874] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  134.026876] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  134.026879] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  134.026882] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  134.026885] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  134.026887] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  134.026888] [drm:intel_dump_pipe_config] requested mode:
>[  134.026893] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  134.026895] [drm:intel_dump_pipe_config] adjusted mode:
>[  134.026898] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  134.026902] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  134.026904] [drm:intel_dump_pipe_config] port clock: 270000
>[  134.026906] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  134.026909] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  134.026911] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  134.026913] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  134.026915] [drm:intel_dump_pipe_config] ips: 0
>[  134.026917] [drm:intel_dump_pipe_config] double wide: 0
>[  134.026920] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  134.026922] [drm:intel_dump_pipe_config] planes on this crtc
>[  134.026925] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0
>[  134.026928] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  134.026931] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0
>[  134.026933] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0
>[  134.026943] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  134.027643] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  134.045535] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  134.054429] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  134.063610] [drm:intel_disable_pipe] disabling pipe C
>[  134.081678] [drm:intel_dp_link_down] 
>[  134.102354] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  134.122137] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz
>[  134.122167] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  134.122192] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  134.122204] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  134.122218] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  134.122232] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  134.122246] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  134.122257] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  134.122272] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  134.122286] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  134.122299] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  134.122341] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  134.344449] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.344470] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  134.345267] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  134.429853] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.429873] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.431107] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  134.431338] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  134.431360] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  134.431406] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  134.431645] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  134.431674] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  134.431685] [drm:intel_enable_pipe] enabling pipe A
>[  134.431720] [drm:intel_psr_enable] PSR not supported by this panel
>[  134.431810] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  134.569045] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.569066] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.572245] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  134.614253] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.614274] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.658188] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.658210] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  134.660434] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  134.704350] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  134.704371] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.748442] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.748463] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.792368] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  134.792389] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.835602] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  134.835623] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  134.837994] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  134.842783] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  134.842820] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  134.842834] [drm:intel_enable_pipe] enabling pipe C
>[  134.842874] [drm:intel_psr_enable] PSR not supported by this panel
>[  134.865444] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  134.865478] [drm:verify_crtc_state] [CRTC:26]
>[  134.876855] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  134.876884] [drm:verify_crtc_state] [CRTC:36]
>[  134.888873] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  134.898772] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 256 / 511 / 511
>[  134.898808] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  134.965670] [drm:pipe_crc_set_source] collecting CRCs for pipe A, DP-B
>[  135.033488] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  135.065511] [drm:pipe_crc_set_source] collecting CRCs for pipe A, DP-B
>[  135.133567] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  135.176362] kms_plane: starting subtest plane-position-hole-pipe-A-plane-1
>[  135.182949] kms_plane: starting subtest plane-position-hole-dpms-pipe-A-plane-1
>[  135.187679] kms_plane: starting subtest plane-panning-top-left-pipe-A-plane-1
>[  135.191986] kms_plane: starting subtest plane-panning-bottom-right-pipe-A-plane-1
>[  135.195022] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-A-plane-1
>[  135.198085] kms_plane: starting subtest plane-position-covered-pipe-A-plane-2
>[  135.201171] kms_plane: starting subtest plane-position-hole-pipe-A-plane-2
>[  135.203995] kms_plane: starting subtest plane-position-hole-dpms-pipe-A-plane-2
>[  135.206215] kms_plane: starting subtest plane-panning-top-left-pipe-A-plane-2
>[  135.208418] kms_plane: starting subtest plane-panning-bottom-right-pipe-A-plane-2
>[  135.210604] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-A-plane-2
>[  135.212892] kms_plane: starting subtest plane-position-covered-pipe-A-plane-3
>[  135.215187] kms_plane: starting subtest plane-position-hole-pipe-A-plane-3
>[  135.217171] kms_plane: starting subtest plane-position-hole-dpms-pipe-A-plane-3
>[  135.219091] kms_plane: starting subtest plane-panning-top-left-pipe-A-plane-3
>[  135.221027] kms_plane: starting subtest plane-panning-bottom-right-pipe-A-plane-3
>[  135.222922] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-A-plane-3
>[  135.224883] kms_plane: starting subtest plane-position-covered-pipe-B-plane-1
>[  135.224979] [drm:drm_mode_addfb2] [FB:122]
>[  135.262642] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  135.262654] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  135.262681] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  135.262684] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  135.262689] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  135.262699] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  135.262701] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  135.262705] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  135.262710] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880274f5c800 for pipe B
>[  135.262712] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  135.262715] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  135.262717] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  135.262720] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  135.262723] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  135.262725] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  135.262727] [drm:intel_dump_pipe_config] requested mode:
>[  135.262731] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  135.262733] [drm:intel_dump_pipe_config] adjusted mode:
>[  135.262737] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  135.262741] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  135.262743] [drm:intel_dump_pipe_config] port clock: 270000
>[  135.262745] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  135.262747] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  135.262750] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  135.262752] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  135.262754] [drm:intel_dump_pipe_config] ips: 0
>[  135.262756] [drm:intel_dump_pipe_config] double wide: 0
>[  135.262758] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x0, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  135.262760] [drm:intel_dump_pipe_config] planes on this crtc
>[  135.262763] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  135.262766] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  135.262769] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  135.262772] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  135.262776] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  135.263649] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  135.265370] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  135.265598] [drm:intel_disable_pipe] disabling pipe A
>[  135.300061] [drm:intel_dp_link_down] 
>[  135.331477] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  135.342453] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  135.342490] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  135.347015] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  135.347047] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  135.347059] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  135.347074] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  135.347088] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  135.347102] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  135.347114] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  135.347128] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  135.347253] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  135.347273] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  135.347317] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x356007ff)
>[  135.356132] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x3d6007ff)
>[  135.577291] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  135.577312] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  135.578107] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  135.662793] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  135.662814] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  135.746471] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  135.746493] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  135.747768] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  135.747985] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  135.748005] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  135.748019] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  135.748714] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x2d6007ff)
>[  135.761985] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  135.762023] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  135.762037] [drm:intel_enable_pipe] enabling pipe B
>[  135.762074] [drm:intel_psr_enable] PSR not supported by this panel
>[  135.795787] [drm:verify_crtc_state] [CRTC:26]
>[  135.795827] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  135.795846] [drm:verify_crtc_state] [CRTC:31]
>[  135.829287] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  135.897167] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  135.930076] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  135.930163] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  135.930226] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  135.962438] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  135.962810] [drm:intel_disable_pipe] disabling pipe B
>[  135.995541] [drm:intel_dp_link_down] 
>[  136.027452] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  136.038513] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  136.038550] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  136.043349] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  136.060156] [drm:intel_disable_pipe] disabling pipe C
>[  136.078478] [drm:intel_dp_link_down] 
>[  136.098278] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  136.118055] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz
>[  136.118085] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  136.118109] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  136.118125] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  136.118139] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  136.118152] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  136.118166] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  136.118178] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  136.118192] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  136.118205] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  136.118219] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  136.118232] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  136.118277] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x256007ff)
>[  136.255448] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  136.255469] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.257341] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  136.299199] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  136.299221] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.342948] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  136.342969] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  136.344783] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  136.388808] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  136.388830] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.433031] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  136.433052] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.477500] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  136.477521] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.521854] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  136.521874] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.523940] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  136.524285] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  136.524302] [drm:intel_enable_pipe] enabling pipe C
>[  136.524341] [drm:intel_psr_enable] PSR not supported by this panel
>[  136.541379] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  136.551006] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  136.560324] [drm:verify_crtc_state] [CRTC:31]
>[  136.560367] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  136.560388] [drm:verify_crtc_state] [CRTC:36]
>[  136.599407] [drm:drm_mode_addfb2] [FB:122]
>[  136.640747] [drm:drm_mode_addfb2] [FB:123]
>[  136.641456] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  136.641463] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  136.641486] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  136.641489] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  136.641494] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  136.641503] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  136.641505] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  136.641509] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  136.641513] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880272f06000 for pipe B
>[  136.641516] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  136.641518] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  136.641521] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  136.641524] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  136.641527] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  136.641529] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  136.641530] [drm:intel_dump_pipe_config] requested mode:
>[  136.641535] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  136.641537] [drm:intel_dump_pipe_config] adjusted mode:
>[  136.641540] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  136.641544] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  136.641546] [drm:intel_dump_pipe_config] port clock: 270000
>[  136.641548] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  136.641550] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  136.641553] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  136.641555] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  136.641557] [drm:intel_dump_pipe_config] ips: 0
>[  136.641559] [drm:intel_dump_pipe_config] double wide: 0
>[  136.641562] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  136.641564] [drm:intel_dump_pipe_config] planes on this crtc
>[  136.641567] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  136.641570] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  136.641573] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  136.641575] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  136.641584] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  136.642438] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  136.658474] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  136.667848] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  136.675116] [drm:intel_disable_pipe] disabling pipe C
>[  136.692597] [drm:intel_dp_link_down] 
>[  136.714355] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  136.734766] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz
>[  136.734797] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  136.734822] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  136.734834] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  136.734848] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  136.734862] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  136.734876] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  136.734888] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  136.734903] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  136.734917] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  136.734930] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  136.734973] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x150007ff)
>[  136.744300] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0007ff)
>[  136.966651] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  136.966672] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  136.967517] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  137.052070] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.052092] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  137.137292] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.137314] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.221248] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.221269] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  137.222511] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  137.222727] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  137.222747] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  137.222762] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  137.223685] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x0d0007ff)
>[  137.232617] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  137.232654] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  137.232667] [drm:intel_enable_pipe] enabling pipe B
>[  137.232702] [drm:intel_psr_enable] PSR not supported by this panel
>[  137.232793] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  137.369837] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.369858] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.372913] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  137.414885] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.414907] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.458638] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.458659] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  137.460352] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  137.504204] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  137.504226] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.548263] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.548284] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.592507] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  137.592529] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.636895] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  137.636916] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  137.639231] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  137.643628] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  137.643665] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  137.643679] [drm:intel_enable_pipe] enabling pipe C
>[  137.643720] [drm:intel_psr_enable] PSR not supported by this panel
>[  137.666737] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  137.666772] [drm:verify_crtc_state] [CRTC:31]
>[  137.677551] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  137.677579] [drm:verify_crtc_state] [CRTC:36]
>[  137.689456] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  137.699751] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 256 / 511 / 511
>[  137.699787] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  137.766487] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  137.834534] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  137.866645] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  137.934447] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  137.976327] kms_plane: starting subtest plane-position-hole-pipe-B-plane-1
>[  137.982493] kms_plane: starting subtest plane-position-hole-dpms-pipe-B-plane-1
>[  137.987225] kms_plane: starting subtest plane-panning-top-left-pipe-B-plane-1
>[  137.991691] kms_plane: starting subtest plane-panning-bottom-right-pipe-B-plane-1
>[  137.994695] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-plane-1
>[  137.997757] kms_plane: starting subtest plane-position-covered-pipe-B-plane-2
>[  138.000813] kms_plane: starting subtest plane-position-hole-pipe-B-plane-2
>[  138.003737] kms_plane: starting subtest plane-position-hole-dpms-pipe-B-plane-2
>[  138.005922] kms_plane: starting subtest plane-panning-top-left-pipe-B-plane-2
>[  138.008152] kms_plane: starting subtest plane-panning-bottom-right-pipe-B-plane-2
>[  138.010383] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-plane-2
>[  138.012616] kms_plane: starting subtest plane-position-covered-pipe-B-plane-3
>[  138.014786] kms_plane: starting subtest plane-position-hole-pipe-B-plane-3
>[  138.016791] kms_plane: starting subtest plane-position-hole-dpms-pipe-B-plane-3
>[  138.018761] kms_plane: starting subtest plane-panning-top-left-pipe-B-plane-3
>[  138.020766] kms_plane: starting subtest plane-panning-bottom-right-pipe-B-plane-3
>[  138.022700] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-plane-3
>[  138.024630] kms_plane: starting subtest plane-position-covered-pipe-C-plane-1
>[  138.024730] [drm:drm_mode_addfb2] [FB:124]
>[  138.062404] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  138.062416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  138.094116] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  138.128133] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  138.144761] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  138.144835] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  138.144881] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  138.161220] [drm:intel_disable_pipe] disabling pipe C
>[  138.177424] [drm:intel_dp_link_down] 
>[  138.198387] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  138.207546] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  138.207582] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  138.211452] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  138.211485] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  138.211499] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  138.211514] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  138.211528] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  138.211542] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  138.211566] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  138.211601] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  138.211633] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  138.211647] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  138.211661] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  138.211684] [drm:intel_power_well_disable] disabling dpio-common-d
>[  138.220492] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  138.229849] [drm:verify_crtc_state] [CRTC:36]
>[  138.256379] [drm:drm_mode_addfb2] [FB:120]
>[  138.296965] [drm:drm_mode_addfb2] [FB:124]
>[  138.297514] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  138.297522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  138.297545] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  138.297548] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  138.297552] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  138.297556] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  138.297558] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  138.297562] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  138.297567] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880272f04000 for pipe C
>[  138.297569] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  138.297571] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  138.297574] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  138.297577] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  138.297580] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  138.297582] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  138.297584] [drm:intel_dump_pipe_config] requested mode:
>[  138.297588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  138.297590] [drm:intel_dump_pipe_config] adjusted mode:
>[  138.297594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  138.297597] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  138.297599] [drm:intel_dump_pipe_config] port clock: 270000
>[  138.297601] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  138.297604] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  138.297606] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  138.297609] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  138.297611] [drm:intel_dump_pipe_config] ips: 0
>[  138.297612] [drm:intel_dump_pipe_config] double wide: 0
>[  138.297615] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  138.297617] [drm:intel_dump_pipe_config] planes on this crtc
>[  138.297620] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  138.297624] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  138.297627] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  138.297630] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  138.297634] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  138.298699] [drm:intel_power_well_enable] enabling dpio-common-d
>[  138.317144] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  138.326502] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  138.326536] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  138.326549] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  138.326564] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  138.326578] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  138.326592] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  138.326604] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  138.326619] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  138.326633] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  138.326647] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  138.326686] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  138.464633] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  138.464654] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.468204] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  138.509327] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  138.509349] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.553783] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  138.553805] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.555843] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  138.598240] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  138.598261] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.642858] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  138.642879] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.687312] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  138.687334] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.729853] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  138.729875] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  138.732118] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  138.736920] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  138.736955] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  138.736970] [drm:intel_enable_pipe] enabling pipe C
>[  138.737010] [drm:intel_psr_enable] PSR not supported by this panel
>[  138.754029] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  138.754062] [drm:verify_crtc_state] [CRTC:36]
>[  138.765424] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  138.770771] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  138.770808] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  138.804159] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  138.838076] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  138.854100] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  138.888079] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  138.904425] [drm:drm_mode_addfb2] [FB:126]
>[  138.924238] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  138.924258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  138.937412] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  138.970704] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  138.970741] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  138.987474] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  139.021628] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  139.038599] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  139.038674] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  139.038721] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  139.054274] [drm:intel_disable_pipe] disabling pipe C
>[  139.070470] [drm:intel_dp_link_down] 
>[  139.090057] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  139.100932] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  139.100968] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  139.105647] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  139.105682] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  139.105695] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  139.105709] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  139.105724] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  139.105738] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  139.105753] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  139.105768] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  139.105782] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  139.105795] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  139.105808] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  139.105831] [drm:intel_power_well_disable] disabling dpio-common-d
>[  139.114658] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  139.123851] [drm:verify_crtc_state] [CRTC:36]
>[  139.133085] [drm:drm_mode_addfb2] [FB:126]
>[  139.154512] [drm:drm_mode_addfb2] [FB:127]
>[  139.155649] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  139.155665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  139.155705] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  139.155712] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  139.155721] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  139.155730] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  139.155736] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  139.155743] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  139.155753] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880079a40000 for pipe C
>[  139.155759] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  139.155764] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  139.155771] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  139.155779] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  139.155786] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  139.155791] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  139.155795] [drm:intel_dump_pipe_config] requested mode:
>[  139.155806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  139.155810] [drm:intel_dump_pipe_config] adjusted mode:
>[  139.155820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  139.155828] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  139.155833] [drm:intel_dump_pipe_config] port clock: 270000
>[  139.155839] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  139.155844] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  139.155850] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  139.155856] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  139.155861] [drm:intel_dump_pipe_config] ips: 0
>[  139.155866] [drm:intel_dump_pipe_config] double wide: 0
>[  139.155872] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  139.155877] [drm:intel_dump_pipe_config] planes on this crtc
>[  139.155885] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  139.155892] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  139.155899] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  139.155907] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  139.155915] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  139.156298] [drm:intel_power_well_enable] enabling dpio-common-d
>[  139.174452] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  139.183639] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  139.183673] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  139.183686] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  139.183700] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  139.183715] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  139.183729] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  139.183741] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  139.183756] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  139.183770] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  139.183784] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  139.183823] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  139.321872] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  139.321894] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  139.325469] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  139.367385] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  139.367407] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  139.411540] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  139.411562] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  139.413426] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  139.457564] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  139.457585] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  139.502187] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  139.502209] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  139.546243] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  139.546264] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  139.590280] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  139.590301] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  139.592593] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  139.597621] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  139.597658] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  139.597672] [drm:intel_enable_pipe] enabling pipe C
>[  139.597712] [drm:intel_psr_enable] PSR not supported by this panel
>[  139.615006] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  139.615039] [drm:verify_crtc_state] [CRTC:36]
>[  139.627356] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  139.631477] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  139.631518] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  139.664913] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  139.698835] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  139.714856] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  139.748895] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  139.765107] kms_plane: starting subtest plane-position-hole-pipe-C-plane-1
>[  139.765460] [drm:drm_mode_addfb2] [FB:128]
>[  139.816272] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  139.816284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  139.831543] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  139.864794] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  139.864825] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  139.881564] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  139.915917] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  139.932532] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  139.932608] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  139.932654] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  139.948491] [drm:intel_disable_pipe] disabling pipe C
>[  139.964783] [drm:intel_dp_link_down] 
>[  139.986210] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  139.997206] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  139.997242] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  140.001915] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  140.001949] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  140.001962] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  140.001977] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  140.001991] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  140.002005] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  140.002020] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  140.002035] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  140.002049] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  140.002062] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  140.002076] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  140.002098] [drm:intel_power_well_disable] disabling dpio-common-d
>[  140.010490] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  140.019987] [drm:verify_crtc_state] [CRTC:36]
>[  140.045617] [drm:drm_mode_addfb2] [FB:128]
>[  140.085743] [drm:drm_mode_addfb2] [FB:129]
>[  140.086241] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  140.086248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  140.086271] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  140.086274] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  140.086279] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  140.086283] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  140.086285] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  140.086289] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  140.086293] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880272f03000 for pipe C
>[  140.086296] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  140.086298] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  140.086301] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  140.086304] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  140.086307] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  140.086309] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  140.086310] [drm:intel_dump_pipe_config] requested mode:
>[  140.086315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  140.086317] [drm:intel_dump_pipe_config] adjusted mode:
>[  140.086320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  140.086324] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  140.086326] [drm:intel_dump_pipe_config] port clock: 270000
>[  140.086328] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  140.086330] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  140.086333] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  140.086336] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  140.086337] [drm:intel_dump_pipe_config] ips: 0
>[  140.086339] [drm:intel_dump_pipe_config] double wide: 0
>[  140.086342] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  140.086344] [drm:intel_dump_pipe_config] planes on this crtc
>[  140.086347] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  140.086351] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  140.086354] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  140.086357] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  140.086360] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  140.087023] [drm:intel_power_well_enable] enabling dpio-common-d
>[  140.103240] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  140.112087] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  140.112127] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  140.112131] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  140.112137] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  140.112142] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  140.112147] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  140.112151] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  140.112157] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  140.112162] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  140.112167] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  140.112185] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  140.252936] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  140.252958] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  140.256466] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  140.298677] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  140.298700] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  140.342857] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  140.342879] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  140.344759] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  140.388189] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  140.388210] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  140.432399] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  140.432420] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  140.476409] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  140.476430] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  140.521046] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  140.521067] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  140.523712] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  140.528147] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  140.528180] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  140.528194] [drm:intel_enable_pipe] enabling pipe C
>[  140.528233] [drm:intel_psr_enable] PSR not supported by this panel
>[  140.545343] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  140.545375] [drm:verify_crtc_state] [CRTC:36]
>[  140.557495] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  140.561889] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  140.561927] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  140.595353] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  140.629281] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  140.645318] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  140.679313] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  140.695669] [drm:drm_mode_addfb2] [FB:130]
>[  140.715857] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  140.715877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  140.728643] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  140.761935] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  140.761972] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  140.778833] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  140.812637] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  140.829563] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  140.829636] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  140.829683] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  140.845513] [drm:intel_disable_pipe] disabling pipe C
>[  140.863107] [drm:intel_dp_link_down] 
>[  140.886223] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  140.898214] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  140.898250] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  140.902906] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  140.902941] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  140.902954] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  140.902969] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  140.902983] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  140.902997] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  140.903013] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  140.903028] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  140.903155] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  140.903171] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  140.903184] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  140.903207] [drm:intel_power_well_disable] disabling dpio-common-d
>[  140.912217] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  140.921542] [drm:verify_crtc_state] [CRTC:36]
>[  140.930782] [drm:drm_mode_addfb2] [FB:130]
>[  140.947292] [drm:drm_mode_addfb2] [FB:131]
>[  140.947881] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  140.947892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  140.947922] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  140.947926] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  140.947933] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  140.947939] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  140.947942] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  140.947948] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  140.947954] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880272f01800 for pipe C
>[  140.947957] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  140.947961] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  140.947965] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  140.947970] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  140.947974] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  140.947978] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  140.947981] [drm:intel_dump_pipe_config] requested mode:
>[  140.947987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  140.947990] [drm:intel_dump_pipe_config] adjusted mode:
>[  140.947996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  140.948001] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  140.948005] [drm:intel_dump_pipe_config] port clock: 270000
>[  140.948008] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  140.948012] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  140.948016] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  140.948020] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  140.948023] [drm:intel_dump_pipe_config] ips: 0
>[  140.948026] [drm:intel_dump_pipe_config] double wide: 0
>[  140.948030] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  140.948033] [drm:intel_dump_pipe_config] planes on this crtc
>[  140.948038] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  140.948043] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  140.948047] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  140.948052] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  140.948057] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  140.948506] [drm:intel_power_well_enable] enabling dpio-common-d
>[  140.967258] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  140.976376] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  140.976410] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  140.976423] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  140.976437] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  140.976451] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  140.976466] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  140.976478] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  140.976492] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  140.976506] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  140.976519] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  140.976559] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  141.117414] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  141.117436] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  141.120570] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  141.162679] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  141.162701] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  141.206410] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  141.206432] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  141.208126] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  141.252278] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  141.252299] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  141.296047] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  141.296068] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  141.339145] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  141.339166] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  141.383197] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  141.383219] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  141.385709] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  141.390002] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  141.390040] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  141.390054] [drm:intel_enable_pipe] enabling pipe C
>[  141.390094] [drm:intel_psr_enable] PSR not supported by this panel
>[  141.407250] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  141.407283] [drm:verify_crtc_state] [CRTC:36]
>[  141.419276] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  141.423643] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  141.423679] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  141.457250] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  141.491185] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  141.507204] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  141.541175] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  141.557436] kms_plane: starting subtest plane-position-hole-dpms-pipe-C-plane-1
>[  141.557861] [drm:drm_mode_addfb2] [FB:132]
>[  141.608426] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  141.608438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  141.623841] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  141.657127] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  141.657154] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  141.673904] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  141.708052] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  141.724528] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  141.724602] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  141.724647] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  141.740697] [drm:intel_disable_pipe] disabling pipe C
>[  141.756915] [drm:intel_dp_link_down] 
>[  141.778127] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  141.788773] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  141.788810] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  141.793487] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  141.793522] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  141.793535] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  141.793549] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  141.793563] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  141.793578] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  141.793593] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  141.793608] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  141.793622] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  141.793636] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  141.793649] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  141.793672] [drm:intel_power_well_disable] disabling dpio-common-d
>[  141.802725] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  141.812042] [drm:verify_crtc_state] [CRTC:36]
>[  141.837503] [drm:drm_mode_addfb2] [FB:132]
>[  141.877666] [drm:drm_mode_addfb2] [FB:133]
>[  141.878231] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  141.878240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  141.878264] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  141.878267] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  141.878271] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  141.878275] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  141.878277] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  141.878281] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  141.878286] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880272f00000 for pipe C
>[  141.878288] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  141.878290] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  141.878293] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  141.878296] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  141.878299] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  141.878301] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  141.878303] [drm:intel_dump_pipe_config] requested mode:
>[  141.878307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  141.878309] [drm:intel_dump_pipe_config] adjusted mode:
>[  141.878313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  141.878316] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  141.878319] [drm:intel_dump_pipe_config] port clock: 270000
>[  141.878321] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  141.878323] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  141.878325] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  141.878328] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  141.878330] [drm:intel_dump_pipe_config] ips: 0
>[  141.878332] [drm:intel_dump_pipe_config] double wide: 0
>[  141.878334] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  141.878336] [drm:intel_dump_pipe_config] planes on this crtc
>[  141.878340] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  141.878343] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  141.878346] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  141.878349] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  141.878352] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  141.879285] [drm:intel_power_well_enable] enabling dpio-common-d
>[  141.897521] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  141.906562] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  141.906595] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  141.906608] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  141.906623] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  141.906637] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  141.906652] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  141.906664] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  141.906678] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  141.906692] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  141.906706] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  141.906746] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  142.047409] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.047429] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.050801] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  142.092946] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.092969] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.135416] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.135437] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  142.137574] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  142.181864] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  142.181885] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.225850] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.225871] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.269519] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  142.269540] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.313363] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.313384] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.316115] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  142.321224] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  142.321260] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  142.321274] [drm:intel_enable_pipe] enabling pipe C
>[  142.321314] [drm:intel_psr_enable] PSR not supported by this panel
>[  142.338544] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  142.338578] [drm:verify_crtc_state] [CRTC:36]
>[  142.350754] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  142.355329] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  142.355366] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  142.388677] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  142.439261] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  142.455328] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  142.455349] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  142.455371] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  142.455388] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  142.455399] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  142.455415] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  142.455434] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880079a41000 for pipe C
>[  142.455445] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  142.455455] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  142.455469] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  142.455484] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  142.455498] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  142.455509] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  142.455518] [drm:intel_dump_pipe_config] requested mode:
>[  142.455538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  142.455547] [drm:intel_dump_pipe_config] adjusted mode:
>[  142.455565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  142.455583] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  142.455593] [drm:intel_dump_pipe_config] port clock: 270000
>[  142.455603] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  142.455615] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  142.455627] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  142.455639] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  142.455648] [drm:intel_dump_pipe_config] ips: 0
>[  142.455658] [drm:intel_dump_pipe_config] double wide: 0
>[  142.455671] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  142.455680] [drm:intel_dump_pipe_config] planes on this crtc
>[  142.455695] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 enabled
>[  142.455708] [drm:intel_dump_pipe_config] 	FB:132, fb = 3840x2160 format = 0x34325258
>[  142.455724] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
>[  142.455739] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  142.455752] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 enabled
>[  142.455764] [drm:intel_dump_pipe_config] 	FB:133, fb = 64x64 format = 0x34325258
>[  142.455779] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (132, 132) 64x64
>[  142.455794] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  142.455809] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  142.455872] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  142.472564] [drm:intel_disable_pipe] disabling pipe C
>[  142.488999] [drm:intel_dp_link_down] 
>[  142.510242] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  142.521742] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  142.521779] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  142.526106] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  142.526141] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  142.526155] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  142.526169] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  142.526184] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  142.526198] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  142.526210] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  142.526225] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  142.526239] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  142.526253] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  142.526276] [drm:intel_power_well_disable] disabling dpio-common-d
>[  142.535341] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  142.544448] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  142.544477] [drm:verify_crtc_state] [CRTC:36]
>[  142.544632] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  142.544647] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  142.544666] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  142.544682] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  142.544694] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  142.544709] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  142.544728] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880079a44000 for pipe C
>[  142.544738] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  142.544749] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  142.544763] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  142.544778] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  142.544792] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  142.544802] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  142.544811] [drm:intel_dump_pipe_config] requested mode:
>[  142.544831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  142.544841] [drm:intel_dump_pipe_config] adjusted mode:
>[  142.544859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  142.544876] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  142.544887] [drm:intel_dump_pipe_config] port clock: 270000
>[  142.544897] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  142.544908] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  142.544920] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  142.544932] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  142.544942] [drm:intel_dump_pipe_config] ips: 0
>[  142.544951] [drm:intel_dump_pipe_config] double wide: 0
>[  142.544964] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  142.544974] [drm:intel_dump_pipe_config] planes on this crtc
>[  142.544989] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 enabled
>[  142.545002] [drm:intel_dump_pipe_config] 	FB:132, fb = 3840x2160 format = 0x34325258
>[  142.545017] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
>[  142.545033] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  142.545046] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 enabled
>[  142.545057] [drm:intel_dump_pipe_config] 	FB:133, fb = 64x64 format = 0x34325258
>[  142.545072] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (132, 132) 64x64
>[  142.545087] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  142.545102] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  142.545162] [drm:intel_power_well_enable] enabling dpio-common-d
>[  142.564019] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  142.573281] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  142.573315] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  142.573328] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  142.573343] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  142.573357] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  142.573371] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  142.573383] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  142.573398] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  142.573412] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  142.573426] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  142.573465] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  142.714415] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.714436] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.754144] [drm:drm_dp_dpcd_access] too many retries, giving up
>[  142.754346] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* failed to enable link training
>[  142.808401] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.808422] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.853600] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  142.853621] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.855465] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  142.899444] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  142.899465] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.943319] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  142.943341] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  142.987302] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  142.987324] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.031203] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  143.031224] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.033729] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  143.038403] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  143.038440] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  143.038454] [drm:intel_enable_pipe] enabling pipe C
>[  143.038494] [drm:intel_psr_enable] PSR not supported by this panel
>[  143.055623] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  143.055657] [drm:verify_crtc_state] [CRTC:36]
>[  143.066527] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  143.106480] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  143.122407] [drm:drm_mode_addfb2] [FB:134]
>[  143.140196] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  143.140213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  143.155302] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  143.188556] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  143.188569] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  143.205350] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  143.239321] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  143.255452] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  143.255479] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  143.255498] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  143.272176] [drm:intel_disable_pipe] disabling pipe C
>[  143.290531] [drm:intel_dp_link_down] 
>[  143.307943] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  143.318423] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  143.318435] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  143.322624] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  143.322637] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  143.322640] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  143.322644] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  143.322648] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  143.322652] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  143.322656] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  143.322661] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  143.322665] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  143.322668] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  143.322672] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  143.322679] [drm:intel_power_well_disable] disabling dpio-common-d
>[  143.330940] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  143.339089] [drm:verify_crtc_state] [CRTC:36]
>[  143.341544] [drm:drm_mode_addfb2] [FB:134]
>[  143.351004] [drm:drm_mode_addfb2] [FB:135]
>[  143.351438] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  143.351445] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  143.351468] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  143.351472] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  143.351477] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  143.351481] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  143.351483] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  143.351487] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  143.351492] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880272f02000 for pipe C
>[  143.351494] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  143.351496] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  143.351499] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  143.351502] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  143.351505] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  143.351507] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  143.351509] [drm:intel_dump_pipe_config] requested mode:
>[  143.351513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  143.351515] [drm:intel_dump_pipe_config] adjusted mode:
>[  143.351519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  143.351522] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  143.351525] [drm:intel_dump_pipe_config] port clock: 270000
>[  143.351527] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  143.351529] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  143.351532] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  143.351534] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  143.351536] [drm:intel_dump_pipe_config] ips: 0
>[  143.351538] [drm:intel_dump_pipe_config] double wide: 0
>[  143.351540] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  143.351542] [drm:intel_dump_pipe_config] planes on this crtc
>[  143.351546] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  143.351549] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  143.351552] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  143.351555] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  143.351559] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  143.351694] [drm:intel_power_well_enable] enabling dpio-common-d
>[  143.368531] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  143.377845] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  143.377878] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  143.377892] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  143.377906] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  143.377920] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  143.377934] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  143.377946] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  143.377961] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  143.377975] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  143.377989] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  143.378029] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  143.517477] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  143.517498] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.521297] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  143.563088] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  143.563110] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.606960] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  143.607062] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  143.609196] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  143.653217] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  143.653238] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.697681] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  143.697703] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.741862] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  143.741884] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.786288] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  143.786310] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  143.788549] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  143.793521] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  143.793558] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  143.793572] [drm:intel_enable_pipe] enabling pipe C
>[  143.793612] [drm:intel_psr_enable] PSR not supported by this panel
>[  143.811132] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  143.811166] [drm:verify_crtc_state] [CRTC:36]
>[  143.821958] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  143.827467] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  143.827503] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  143.860871] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  143.894877] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  143.910933] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  143.910955] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  143.910977] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  143.911101] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  143.911112] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  143.911128] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  143.911148] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff8802731fb000 for pipe C
>[  143.911159] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  143.911169] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  143.911183] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  143.911199] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  143.911213] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  143.911223] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  143.911232] [drm:intel_dump_pipe_config] requested mode:
>[  143.911252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  143.911262] [drm:intel_dump_pipe_config] adjusted mode:
>[  143.911280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  143.911297] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  143.911308] [drm:intel_dump_pipe_config] port clock: 270000
>[  143.911318] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  143.911330] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  143.911360] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  143.911407] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  143.911446] [drm:intel_dump_pipe_config] ips: 0
>[  143.911486] [drm:intel_dump_pipe_config] double wide: 0
>[  143.911530] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  143.911569] [drm:intel_dump_pipe_config] planes on this crtc
>[  143.911604] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 enabled
>[  143.911617] [drm:intel_dump_pipe_config] 	FB:134, fb = 1920x1080 format = 0x34325258
>[  143.911634] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
>[  143.911658] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  143.911671] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 enabled
>[  143.911683] [drm:intel_dump_pipe_config] 	FB:135, fb = 64x64 format = 0x34325258
>[  143.911698] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (132, 132) 64x64
>[  143.911713] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  143.911729] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  143.911795] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  143.928165] [drm:intel_disable_pipe] disabling pipe C
>[  143.944437] [drm:intel_dp_link_down] 
>[  143.965762] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  143.976640] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  143.976676] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  143.981419] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  143.981454] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  143.981467] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  143.981482] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  143.981496] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  143.981511] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  143.981523] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  143.981537] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  143.981551] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  143.981565] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  143.981587] [drm:intel_power_well_disable] disabling dpio-common-d
>[  143.990339] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  143.999639] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  143.999667] [drm:verify_crtc_state] [CRTC:36]
>[  143.999837] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  143.999853] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  143.999872] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  143.999888] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  143.999900] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  143.999914] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  143.999933] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff8802731fe000 for pipe C
>[  143.999944] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  143.999954] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  143.999968] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  143.999983] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  143.999997] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  144.000008] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  144.000017] [drm:intel_dump_pipe_config] requested mode:
>[  144.000037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  144.000046] [drm:intel_dump_pipe_config] adjusted mode:
>[  144.000064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  144.000081] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  144.000092] [drm:intel_dump_pipe_config] port clock: 270000
>[  144.000102] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  144.000114] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  144.000126] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  144.000137] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  144.000147] [drm:intel_dump_pipe_config] ips: 0
>[  144.000157] [drm:intel_dump_pipe_config] double wide: 0
>[  144.000170] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  144.000179] [drm:intel_dump_pipe_config] planes on this crtc
>[  144.000194] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 enabled
>[  144.000207] [drm:intel_dump_pipe_config] 	FB:134, fb = 1920x1080 format = 0x34325258
>[  144.000223] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
>[  144.000238] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  144.000251] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 enabled
>[  144.000262] [drm:intel_dump_pipe_config] 	FB:135, fb = 64x64 format = 0x34325258
>[  144.000277] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (132, 132) 64x64
>[  144.000292] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  144.000308] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  144.000366] [drm:intel_power_well_enable] enabling dpio-common-d
>[  144.018872] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  144.028281] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  144.028315] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  144.028328] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  144.028343] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  144.028358] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  144.028372] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  144.028384] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  144.028398] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  144.028412] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  144.028425] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  144.028465] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  144.169088] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  144.169109] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  144.172365] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  144.214298] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  144.214320] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  144.258049] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  144.258070] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  144.259987] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  144.304703] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  144.304724] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  144.348722] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  144.348744] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  144.392856] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  144.392877] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  144.437098] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  144.437120] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  144.439416] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  144.444494] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 256 / 511 / 511
>[  144.444531] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=136, cursor=63, sprite0=135, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  144.444545] [drm:intel_enable_pipe] enabling pipe C
>[  144.444585] [drm:intel_psr_enable] PSR not supported by this panel
>[  144.461628] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  144.461661] [drm:verify_crtc_state] [CRTC:36]
>[  144.472634] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  144.512565] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  144.528866] kms_plane: starting subtest plane-panning-top-left-pipe-C-plane-1
>[  144.529227] [drm:drm_mode_addfb2] [FB:136]
>[  144.580083] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  144.580095] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  144.595050] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  144.628292] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  144.628321] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  144.645292] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  144.695692] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  144.712331] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  144.712404] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  144.712452] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  144.728604] [drm:intel_disable_pipe] disabling pipe C
>[  144.745428] [drm:intel_dp_link_down] 
>[  144.765882] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  144.776637] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  144.776673] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  144.781511] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  144.781546] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  144.781560] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  144.781574] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  144.781589] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  144.781603] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  144.781618] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  144.781633] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  144.781647] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  144.781661] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  144.781674] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  144.781697] [drm:intel_power_well_disable] disabling dpio-common-d
>[  144.790375] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  144.799547] [drm:verify_crtc_state] [CRTC:36]
>[  144.823252] [drm:drm_mode_addfb2] [FB:136]
>[  144.862372] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  144.862384] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-3]
>[  144.862408] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  144.862411] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  144.862416] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  144.862420] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  144.862422] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  144.862427] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  144.862431] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880079a44000 for pipe C
>[  144.862433] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  144.862436] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  144.862439] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  144.862442] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  144.862444] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  144.862447] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  144.862448] [drm:intel_dump_pipe_config] requested mode:
>[  144.862453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  144.862455] [drm:intel_dump_pipe_config] adjusted mode:
>[  144.862458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  144.862462] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  144.862464] [drm:intel_dump_pipe_config] port clock: 270000
>[  144.862466] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  144.862468] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  144.862471] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  144.862473] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  144.862475] [drm:intel_dump_pipe_config] ips: 0
>[  144.862477] [drm:intel_dump_pipe_config] double wide: 0
>[  144.862480] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  144.862482] [drm:intel_dump_pipe_config] planes on this crtc
>[  144.862485] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  144.862488] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  144.862491] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  144.862494] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  144.862498] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  144.862899] [drm:intel_power_well_enable] enabling dpio-common-d
>[  144.881420] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x0d0007ff)
>[  144.890365] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  144.890381] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  144.890385] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  144.890391] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  144.890396] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  144.890401] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  144.890406] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  144.890412] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  144.890417] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  144.890422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  144.890440] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  145.031187] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  145.031209] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  145.034689] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  145.076647] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  145.076670] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  145.120790] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  145.120811] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  145.122871] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  145.167405] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  145.167426] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  145.210688] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  145.210709] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  145.255266] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  145.255287] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  145.298710] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  145.298732] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  145.301404] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  145.305791] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  145.305828] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  145.305842] [drm:intel_enable_pipe] enabling pipe C
>[  145.305882] [drm:intel_psr_enable] PSR not supported by this panel
>[  145.323092] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  145.323124] [drm:verify_crtc_state] [CRTC:36]
>[  145.339622] [drm:pipe_crc_set_source] collecting CRCs for pipe C, DP-D
>[  145.373632] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[  145.390305] [drm:drm_mode_setcrtc] [CRTC:36:crtc-2]
>[  145.390381] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  145.390429] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  145.406719] [drm:intel_disable_pipe] disabling pipe C
>[  145.422863] [drm:intel_dp_link_down] 
>[  145.441658] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  145.452752] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  145.452788] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  145.457497] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  145.457532] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  145.457545] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  145.457560] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  145.457574] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  145.457589] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  145.457604] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  145.457618] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  145.457632] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  145.457645] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  145.457658] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  145.457681] [drm:intel_power_well_disable] disabling dpio-common-d
>[  145.466067] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  145.475208] [drm:verify_crtc_state] [CRTC:36]
>[  145.499078] [drm:drm_mode_addfb2] [FB:136]
>[  145.573399] kms_plane: starting subtest plane-panning-bottom-right-pipe-C-plane-1
>[  145.575647] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-C-plane-1
>[  145.577682] kms_plane: starting subtest plane-position-covered-pipe-C-plane-2
>[  145.579802] kms_plane: starting subtest plane-position-hole-pipe-C-plane-2
>[  145.581819] kms_plane: starting subtest plane-position-hole-dpms-pipe-C-plane-2
>[  145.583902] kms_plane: starting subtest plane-panning-top-left-pipe-C-plane-2
>[  145.585906] kms_plane: starting subtest plane-panning-bottom-right-pipe-C-plane-2
>[  145.587934] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-C-plane-2
>[  145.589959] kms_plane: starting subtest plane-position-covered-pipe-C-plane-3
>[  145.592014] kms_plane: starting subtest plane-position-hole-pipe-C-plane-3
>[  145.593981] kms_plane: starting subtest plane-position-hole-dpms-pipe-C-plane-3
>[  145.596080] kms_plane: starting subtest plane-panning-top-left-pipe-C-plane-3
>[  145.598097] kms_plane: starting subtest plane-panning-bottom-right-pipe-C-plane-3
>[  145.600160] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-C-plane-3
>[  145.602193] kms_plane: exiting, ret=99
>[  145.602333] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  145.602335] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  145.602339] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  145.602347] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  145.602348] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  145.602351] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  145.602354] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880274f5b800 for pipe A
>[  145.602355] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  145.602356] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  145.602358] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  145.602360] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  145.602362] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  145.602363] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  145.602363] [drm:intel_dump_pipe_config] requested mode:
>[  145.602366] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  145.602367] [drm:intel_dump_pipe_config] adjusted mode:
>[  145.602370] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  145.602372] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  145.602373] [drm:intel_dump_pipe_config] port clock: 270000
>[  145.602374] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  145.602375] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  145.602376] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  145.602377] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  145.602378] [drm:intel_dump_pipe_config] ips: 0
>[  145.602379] [drm:intel_dump_pipe_config] double wide: 0
>[  145.602380] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  145.602381] [drm:intel_dump_pipe_config] planes on this crtc
>[  145.602385] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled
>[  145.602387] [drm:intel_dump_pipe_config] 	FB:111, fb = 3840x2160 format = 0x34325258
>[  145.602387] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
>[  145.602388] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  145.602391] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 enabled
>[  145.602393] [drm:intel_dump_pipe_config] 	FB:121, fb = 64x64 format = 0x34325258
>[  145.602394] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 4294967196x4294967196 dst (100, 100) 4294967196x4294967196
>[  145.602395] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0
>[  145.602397] [drm:connected_sink_compute_bpp] [CONNECTOR:53:DP-3] checking for sink bpp constrains
>[  145.602398] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 18
>[  145.602400] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  145.602402] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  145.602403] [drm:intel_dp_compute_config] DP link bw required 267300 available 432000
>[  145.602404] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  145.602406] [drm:intel_dump_pipe_config] [CRTC:36][modeset] config ffff880274f5e000 for pipe C
>[  145.602407] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  145.602408] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  145.602410] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  145.602411] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  145.602413] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  145.602414] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  145.602414] [drm:intel_dump_pipe_config] requested mode:
>[  145.602417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  145.602418] [drm:intel_dump_pipe_config] adjusted mode:
>[  145.602420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  145.602422] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  145.602423] [drm:intel_dump_pipe_config] port clock: 270000
>[  145.602424] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  145.602425] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  145.602426] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  145.602428] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  145.602428] [drm:intel_dump_pipe_config] ips: 0
>[  145.602429] [drm:intel_dump_pipe_config] double wide: 0
>[  145.602430] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  145.602431] [drm:intel_dump_pipe_config] planes on this crtc
>[  145.602433] [drm:intel_dump_pipe_config] STANDARD PLANE:34 plane: 2.0 idx: 8 disabled, scaler_id = 0
>[  145.602434] [drm:intel_dump_pipe_config] CURSOR PLANE:35 plane: 2.3 idx: 9 disabled, scaler_id = 0
>[  145.602436] [drm:intel_dump_pipe_config] STANDARD PLANE:37 plane: 2.1 idx: 10 disabled, scaler_id = 0
>[  145.602437] [drm:intel_dump_pipe_config] STANDARD PLANE:38 plane: 2.2 idx: 11 disabled, scaler_id = 0
>[  145.602440] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  145.602468] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  145.633150] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  145.633574] [drm:intel_disable_pipe] disabling pipe B
>[  145.668143] [drm:intel_dp_link_down] 
>[  145.699266] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x050007fd)
>[  145.710949] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  145.711053] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  145.711071] [drm:intel_power_well_enable] enabling dpio-common-d
>[  145.729317] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x050007ff)
>[  145.738652] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  145.738671] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  145.738676] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  145.738685] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  145.738693] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  145.738701] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  145.738708] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  145.738716] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  145.738724] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  145.738731] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  145.738765] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  145.960313] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  145.960319] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  145.961267] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  146.046682] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  146.046688] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.047939] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  146.048149] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  146.048161] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  146.048170] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  146.048408] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  146.048428] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  146.048433] [drm:intel_enable_pipe] enabling pipe A
>[  146.048463] [drm:intel_psr_enable] PSR not supported by this panel
>[  146.048972] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  146.187525] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  146.187531] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.232691] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  146.232692] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  146.232698] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.276489] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  146.276495] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  146.278333] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  146.321997] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  146.322003] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.366262] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  146.366268] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.410320] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  146.410327] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.455537] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  146.455543] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  146.457726] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  146.462637] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  146.462659] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  146.462665] [drm:intel_enable_pipe] enabling pipe C
>[  146.462699] [drm:intel_psr_enable] PSR not supported by this panel
>[  146.482171] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  146.482192] [drm:verify_crtc_state] [CRTC:26]
>[  146.494144] [drm:verify_crtc_state] [CRTC:31]
>[  146.494167] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  146.494177] [drm:verify_crtc_state] [CRTC:36]
>[  146.536376] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  146.536384] [drm:i915_pages_create_for_stolen] offset=0x9000, size=16384
>[  146.537293] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  146.537301] [drm:i915_pages_create_for_stolen] offset=0xd000, size=16384
>[  146.537831] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  146.537838] [drm:i915_pages_create_for_stolen] offset=0x11000, size=16384
>[  146.538150] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  146.538157] [drm:i915_pages_create_for_stolen] offset=0x15000, size=16384
>[  233.271881] kms_plane: executing
>[  233.272053] [drm:i915_gem_open] 
>[  233.272677] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  233.272686] [drm:i915_pages_create_for_stolen] offset=0x19000, size=16384
>[  233.273860] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  233.273869] [drm:i915_pages_create_for_stolen] offset=0x1d000, size=16384
>[  233.274463] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  233.274469] [drm:i915_pages_create_for_stolen] offset=0x21000, size=16384
>[  233.274715] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  233.274721] [drm:i915_pages_create_for_stolen] offset=0x25000, size=16384
>[  233.275787] [drm:i915_gem_open] 
>[  233.278098] kms_plane: starting subtest plane-position-covered-pipe-A-plane-1
>[  233.278218] [drm:drm_mode_addfb2] [FB:111]
>[  233.332723] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  233.332738] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  233.383540] [drm:pipe_crc_set_source] collecting CRCs for pipe A, DP-B
>[  233.451587] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  233.484441] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  233.484528] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  233.484591] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  233.516761] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  233.518178] [drm:intel_disable_pipe] disabling pipe A
>[  233.550126] [drm:intel_dp_link_down] 
>[  233.582080] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  233.593474] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  233.593510] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  233.598142] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  233.614618] [drm:intel_disable_pipe] disabling pipe C
>[  233.630885] [drm:intel_dp_link_down] 
>[  233.652716] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  233.676047] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz
>[  233.676078] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  233.676102] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  233.676117] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  233.676131] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  233.676145] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  233.676159] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  233.676171] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  233.676185] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  233.676199] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  233.676212] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  233.676225] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  233.676270] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x256007ff)
>[  233.815574] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  233.815594] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  233.817896] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  233.859809] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  233.859831] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  233.903568] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  233.903589] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  233.905951] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  233.949595] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  233.949616] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  233.993696] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  233.993717] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.038080] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  234.038102] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.081188] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.081209] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.083731] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  234.084072] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  234.084091] [drm:intel_enable_pipe] enabling pipe C
>[  234.084129] [drm:intel_psr_enable] PSR not supported by this panel
>[  234.101135] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  234.110568] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  234.119943] [drm:verify_crtc_state] [CRTC:26]
>[  234.119988] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  234.120007] [drm:verify_crtc_state] [CRTC:36]
>[  234.158101] [drm:drm_mode_addfb2] [FB:111]
>[  234.199141] [drm:drm_mode_addfb2] [FB:120]
>[  234.199809] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  234.199817] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  234.199840] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  234.199843] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  234.199848] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  234.199857] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  234.199859] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  234.199863] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  234.199868] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880274f5e000 for pipe A
>[  234.199870] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  234.199872] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  234.199875] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  234.199878] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  234.199881] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  234.199883] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  234.199885] [drm:intel_dump_pipe_config] requested mode:
>[  234.199889] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  234.199891] [drm:intel_dump_pipe_config] adjusted mode:
>[  234.199895] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  234.199898] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  234.199900] [drm:intel_dump_pipe_config] port clock: 270000
>[  234.199902] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  234.199905] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  234.199907] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  234.199909] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  234.199911] [drm:intel_dump_pipe_config] ips: 0
>[  234.199913] [drm:intel_dump_pipe_config] double wide: 0
>[  234.199916] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  234.199918] [drm:intel_dump_pipe_config] planes on this crtc
>[  234.199920] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0
>[  234.199924] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  234.199926] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0
>[  234.199929] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0
>[  234.199938] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  234.200742] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  234.218925] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  234.225947] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  234.234719] [drm:intel_disable_pipe] disabling pipe C
>[  234.251027] [drm:intel_dp_link_down] 
>[  234.272540] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  234.295870] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz
>[  234.295900] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  234.295924] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  234.295936] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  234.295950] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  234.295964] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  234.295978] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  234.295990] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  234.296005] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  234.296018] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  234.296032] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  234.296073] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  234.517320] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.517342] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.518422] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  234.603599] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.603621] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  234.689004] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.689025] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.690736] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  234.690955] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  234.690976] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  234.690991] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  234.691232] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  234.691261] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  234.691273] [drm:intel_enable_pipe] enabling pipe A
>[  234.691309] [drm:intel_psr_enable] PSR not supported by this panel
>[  234.691827] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  234.831925] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.831946] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.835301] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  234.877427] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.877449] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  234.921306] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  234.921328] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  234.923438] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  234.966747] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  234.966769] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  235.011309] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  235.011330] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  235.055699] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  235.055720] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  235.100275] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  235.100296] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  235.102894] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  235.108259] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  235.108296] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  235.108310] [drm:intel_enable_pipe] enabling pipe C
>[  235.108350] [drm:intel_psr_enable] PSR not supported by this panel
>[  235.125326] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  235.125360] [drm:verify_crtc_state] [CRTC:26]
>[  235.136687] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  235.136716] [drm:verify_crtc_state] [CRTC:36]
>[  235.148767] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  235.158534] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 256 / 511 / 511
>[  235.158570] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  235.225533] [drm:pipe_crc_set_source] collecting CRCs for pipe A, DP-B
>[  235.293058] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  235.325084] [drm:pipe_crc_set_source] collecting CRCs for pipe A, DP-B
>[  235.393058] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  235.425556] [drm:drm_mode_addfb2] [FB:121]
>[  235.445517] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0]
>[  235.445538] [drm:check_src_coords] Invalid source coordinates 3840.000000x2160.000000+0.000000+0.000000
>[  235.445733] kms_plane: starting subtest plane-position-hole-pipe-A-plane-1
>[  235.450418] kms_plane: starting subtest plane-position-hole-dpms-pipe-A-plane-1
>[  235.453374] kms_plane: starting subtest plane-panning-top-left-pipe-A-plane-1
>[  235.456331] kms_plane: starting subtest plane-panning-bottom-right-pipe-A-plane-1
>[  235.459319] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-A-plane-1
>[  235.462104] kms_plane: starting subtest plane-position-covered-pipe-A-plane-2
>[  235.464228] kms_plane: starting subtest plane-position-hole-pipe-A-plane-2
>[  235.466347] kms_plane: starting subtest plane-position-hole-dpms-pipe-A-plane-2
>[  235.468431] kms_plane: starting subtest plane-panning-top-left-pipe-A-plane-2
>[  235.470590] kms_plane: starting subtest plane-panning-bottom-right-pipe-A-plane-2
>[  235.472720] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-A-plane-2
>[  235.474671] kms_plane: starting subtest plane-position-covered-pipe-A-plane-3
>[  235.476506] kms_plane: starting subtest plane-position-hole-pipe-A-plane-3
>[  235.478360] kms_plane: starting subtest plane-position-hole-dpms-pipe-A-plane-3
>[  235.480186] kms_plane: starting subtest plane-panning-top-left-pipe-A-plane-3
>[  235.482051] kms_plane: starting subtest plane-panning-bottom-right-pipe-A-plane-3
>[  235.483881] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-A-plane-3
>[  235.485770] kms_plane: starting subtest plane-position-covered-pipe-B-plane-1
>[  235.485861] [drm:drm_mode_addfb2] [FB:123]
>[  235.523659] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  235.523670] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  235.523700] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  235.523703] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  235.523709] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  235.523719] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  235.523721] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  235.523725] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  235.523730] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880274f5e000 for pipe B
>[  235.523732] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  235.523734] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  235.523737] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  235.523740] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  235.523743] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  235.523745] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  235.523747] [drm:intel_dump_pipe_config] requested mode:
>[  235.523751] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  235.523753] [drm:intel_dump_pipe_config] adjusted mode:
>[  235.523757] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  235.523760] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  235.523762] [drm:intel_dump_pipe_config] port clock: 270000
>[  235.523764] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  235.523767] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  235.523769] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  235.523772] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  235.523773] [drm:intel_dump_pipe_config] ips: 0
>[  235.523775] [drm:intel_dump_pipe_config] double wide: 0
>[  235.523778] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  235.523780] [drm:intel_dump_pipe_config] planes on this crtc
>[  235.523783] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  235.523786] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  235.523789] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  235.523792] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  235.523796] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  235.524607] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  235.524697] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  235.525062] [drm:intel_disable_pipe] disabling pipe A
>[  235.558288] [drm:intel_dp_link_down] 
>[  235.589812] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  235.600866] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  235.600902] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  235.605663] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  235.605694] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  235.605707] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  235.605722] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  235.605736] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  235.605750] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  235.605762] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  235.605776] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  235.605791] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  235.605804] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  235.605844] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x356007ff)
>[  235.614459] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x3d6007ff)
>[  235.835945] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  235.835966] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  235.836877] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  235.922001] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  235.922022] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  236.007406] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  236.007427] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.008861] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  236.009081] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  236.009102] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  236.009116] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  236.009815] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x2d6007ff)
>[  236.023214] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  236.023252] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  236.023266] [drm:intel_enable_pipe] enabling pipe B
>[  236.023303] [drm:intel_psr_enable] PSR not supported by this panel
>[  236.057004] [drm:verify_crtc_state] [CRTC:26]
>[  236.057045] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  236.057065] [drm:verify_crtc_state] [CRTC:31]
>[  236.090540] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  236.158540] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  236.191107] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  236.191193] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  236.191255] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  236.223662] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  236.224459] [drm:intel_disable_pipe] disabling pipe B
>[  236.258587] [drm:intel_dp_link_down] 
>[  236.289844] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  236.300749] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  236.300785] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  236.305402] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  236.309083] [drm:intel_disable_pipe] disabling pipe C
>[  236.325348] [drm:intel_dp_link_down] 
>[  236.348366] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  236.371698] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz
>[  236.371728] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  236.371752] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  236.371767] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  236.371781] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  236.371795] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  236.371809] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  236.371821] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  236.371835] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  236.371848] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  236.371862] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  236.371875] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  236.371919] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x256007ff)
>[  236.511712] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  236.511733] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.513812] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  236.555760] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  236.555782] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.599848] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  236.599869] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  236.601770] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  236.645290] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  236.645311] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.689441] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  236.689462] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.733691] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  236.733712] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.777781] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  236.777801] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  236.780111] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  236.780456] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  236.780476] [drm:intel_enable_pipe] enabling pipe C
>[  236.780514] [drm:intel_psr_enable] PSR not supported by this panel
>[  236.797549] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  236.806601] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  236.816012] [drm:verify_crtc_state] [CRTC:31]
>[  236.816056] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  236.816076] [drm:verify_crtc_state] [CRTC:36]
>[  236.854169] [drm:drm_mode_addfb2] [FB:122]
>[  236.894919] [drm:drm_mode_addfb2] [FB:123]
>[  236.895464] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  236.895470] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  236.895492] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  236.895495] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  236.895501] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  236.895510] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  236.895513] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  236.895516] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  236.895521] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880274f5c800 for pipe B
>[  236.895523] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  236.895525] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  236.895528] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  236.895531] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  236.895534] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  236.895536] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  236.895538] [drm:intel_dump_pipe_config] requested mode:
>[  236.895542] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  236.895544] [drm:intel_dump_pipe_config] adjusted mode:
>[  236.895547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  236.895551] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  236.895553] [drm:intel_dump_pipe_config] port clock: 270000
>[  236.895555] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  236.895557] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  236.895560] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  236.895562] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  236.895564] [drm:intel_dump_pipe_config] ips: 0
>[  236.895566] [drm:intel_dump_pipe_config] double wide: 0
>[  236.895569] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  236.895571] [drm:intel_dump_pipe_config] planes on this crtc
>[  236.895574] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  236.895577] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  236.895580] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  236.895583] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  236.895594] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  236.896292] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  236.914634] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  236.923934] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  236.931121] [drm:intel_disable_pipe] disabling pipe C
>[  236.947591] [drm:intel_dp_link_down] 
>[  236.968185] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  236.990704] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz
>[  236.990734] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  236.990758] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  236.990769] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  236.990784] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  236.990798] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  236.990812] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  236.990824] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  236.990839] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  236.990852] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  236.990865] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  236.990909] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x150007ff)
>[  237.000320] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0007ff)
>[  237.221590] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.221611] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.222504] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  237.307188] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.307209] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  237.392577] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.392598] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.393787] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  237.394010] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  237.394030] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  237.394045] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  237.394317] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x0d0007ff)
>[  237.403922] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  237.403958] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  237.403971] [drm:intel_enable_pipe] enabling pipe B
>[  237.404008] [drm:intel_psr_enable] PSR not supported by this panel
>[  237.404098] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  237.543435] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.543456] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.546432] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  237.588323] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.588345] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.632403] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.632424] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  237.634367] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  237.678442] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  237.678463] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.722490] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.722512] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.765791] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  237.765813] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.809245] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  237.809266] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  237.811710] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  237.815916] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  237.815953] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  237.815967] [drm:intel_enable_pipe] enabling pipe C
>[  237.816008] [drm:intel_psr_enable] PSR not supported by this panel
>[  237.837722] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  237.837755] [drm:verify_crtc_state] [CRTC:31]
>[  237.848924] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  237.848952] [drm:verify_crtc_state] [CRTC:36]
>[  237.861150] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  237.871049] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 256 / 511 / 511
>[  237.871086] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  237.938016] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  238.005765] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  238.037788] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  238.105764] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  238.138056] kms_plane: starting subtest plane-position-hole-pipe-B-plane-1
>[  238.138384] [drm:drm_mode_addfb2] [FB:124]
>[  238.189782] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  238.189794] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  238.204569] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  238.271046] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  238.271075] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  238.304495] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  238.372611] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  238.405410] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  238.405501] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  238.405563] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  238.437952] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  238.438923] [drm:intel_disable_pipe] disabling pipe B
>[  238.472030] [drm:intel_dp_link_down] 
>[  238.501621] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  238.512668] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  238.512704] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  238.517432] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  238.533429] [drm:intel_disable_pipe] disabling pipe C
>[  238.551791] [drm:intel_dp_link_down] 
>[  238.572379] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  238.594949] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz
>[  238.594979] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  238.595002] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  238.595017] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  238.595032] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  238.595046] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  238.595060] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  238.595072] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  238.595086] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  238.595100] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  238.595113] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  238.595127] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  238.595171] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x256007ff)
>[  238.734623] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  238.734645] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  238.737928] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  238.778709] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  238.778730] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  238.822406] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  238.822427] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  238.824220] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  238.867980] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  238.868001] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  238.912237] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  238.912257] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  238.957221] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  238.957242] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.001202] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.001223] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.003661] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  239.004000] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  239.004019] [drm:intel_enable_pipe] enabling pipe C
>[  239.004057] [drm:intel_psr_enable] PSR not supported by this panel
>[  239.021314] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  239.030204] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  239.039201] [drm:verify_crtc_state] [CRTC:31]
>[  239.039245] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  239.039266] [drm:verify_crtc_state] [CRTC:36]
>[  239.077833] [drm:drm_mode_addfb2] [FB:124]
>[  239.118962] [drm:drm_mode_addfb2] [FB:125]
>[  239.119509] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  239.119517] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  239.119539] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  239.119542] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  239.119547] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  239.119557] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  239.119559] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  239.119563] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  239.119567] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880272f03000 for pipe B
>[  239.119570] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  239.119572] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  239.119575] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  239.119578] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  239.119581] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  239.119583] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  239.119584] [drm:intel_dump_pipe_config] requested mode:
>[  239.119589] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  239.119591] [drm:intel_dump_pipe_config] adjusted mode:
>[  239.119594] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  239.119598] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  239.119600] [drm:intel_dump_pipe_config] port clock: 270000
>[  239.119602] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  239.119604] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  239.119607] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  239.119609] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  239.119611] [drm:intel_dump_pipe_config] ips: 0
>[  239.119613] [drm:intel_dump_pipe_config] double wide: 0
>[  239.119616] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  239.119618] [drm:intel_dump_pipe_config] planes on this crtc
>[  239.119621] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  239.119624] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  239.119627] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  239.119630] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  239.119639] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  239.120333] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  239.138597] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  239.148009] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  239.154810] [drm:intel_disable_pipe] disabling pipe C
>[  239.171037] [drm:intel_dp_link_down] 
>[  239.192256] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  239.214438] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz
>[  239.214467] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  239.214490] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  239.214502] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  239.214516] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  239.214530] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  239.214545] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  239.214556] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  239.214571] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  239.214585] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  239.214598] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  239.214641] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x150007ff)
>[  239.223880] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0007ff)
>[  239.436745] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.436766] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.438183] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  239.523315] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.523336] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  239.608154] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.608174] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.609781] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  239.610008] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  239.610028] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  239.610043] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  239.610793] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x0d0007ff)
>[  239.620018] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  239.620055] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  239.620068] [drm:intel_enable_pipe] enabling pipe B
>[  239.620104] [drm:intel_psr_enable] PSR not supported by this panel
>[  239.620194] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  239.754047] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.754068] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.757508] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  239.799589] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.799611] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.843967] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.843988] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  239.846178] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  239.890651] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  239.890672] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.932930] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  239.932951] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.977185] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  239.977207] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  239.979724] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  239.983979] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  239.984015] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  239.984030] [drm:intel_enable_pipe] enabling pipe C
>[  239.984070] [drm:intel_psr_enable] PSR not supported by this panel
>[  240.001454] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  240.001489] [drm:verify_crtc_state] [CRTC:31]
>[  240.012576] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  240.012605] [drm:verify_crtc_state] [CRTC:36]
>[  240.025035] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  240.054233] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 256 / 511 / 511
>[  240.054270] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  240.120809] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  240.188723] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  240.220749] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  240.288687] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  240.320933] kms_plane: starting subtest plane-position-hole-dpms-pipe-B-plane-1
>[  240.321696] [drm:drm_mode_addfb2] [FB:126]
>[  240.373519] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  240.373531] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  240.387210] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  240.453820] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  240.453849] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  240.487316] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  240.555217] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  240.587851] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  240.587940] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  240.588003] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  240.620461] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  240.621409] [drm:intel_disable_pipe] disabling pipe B
>[  240.653739] [drm:intel_dp_link_down] 
>[  240.686061] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  240.695789] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  240.695825] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  240.700071] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  240.701926] [drm:intel_disable_pipe] disabling pipe C
>[  240.718023] [drm:intel_dp_link_down] 
>[  240.739759] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  240.753618] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz
>[  240.753648] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  240.753672] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  240.753688] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  240.753702] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  240.753716] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  240.753730] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  240.753742] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  240.753756] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  240.753770] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  240.753783] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  240.753797] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  240.753842] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x256007ff)
>[  240.892557] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  240.892578] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  240.896046] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  240.937969] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  240.937990] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  240.981200] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  240.981222] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  240.983532] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  241.027560] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  241.027582] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  241.071320] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  241.071341] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  241.115839] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  241.115861] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  241.160911] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  241.160932] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  241.163822] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  241.164160] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  241.164179] [drm:intel_enable_pipe] enabling pipe C
>[  241.164217] [drm:intel_psr_enable] PSR not supported by this panel
>[  241.181440] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  241.189453] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  241.197486] [drm:verify_crtc_state] [CRTC:31]
>[  241.197528] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  241.197548] [drm:verify_crtc_state] [CRTC:36]
>[  241.238897] [drm:drm_mode_addfb2] [FB:126]
>[  241.282071] [drm:drm_mode_addfb2] [FB:127]
>[  241.282642] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1]
>[  241.282649] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1]
>[  241.282673] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  241.282677] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  241.282682] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  241.282692] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  241.282694] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  241.282699] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  241.282703] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880079a46000 for pipe B
>[  241.282705] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  241.282707] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  241.282710] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  241.282713] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  241.282716] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  241.282718] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  241.282720] [drm:intel_dump_pipe_config] requested mode:
>[  241.282724] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  241.282726] [drm:intel_dump_pipe_config] adjusted mode:
>[  241.282730] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  241.282733] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  241.282735] [drm:intel_dump_pipe_config] port clock: 270000
>[  241.282737] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  241.282740] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  241.282742] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  241.282745] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  241.282746] [drm:intel_dump_pipe_config] ips: 0
>[  241.282748] [drm:intel_dump_pipe_config] double wide: 0
>[  241.282751] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  241.282753] [drm:intel_dump_pipe_config] planes on this crtc
>[  241.282756] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  241.282760] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  241.282762] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  241.282765] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  241.282775] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  241.283283] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  241.301643] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  241.310354] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  241.314808] [drm:intel_disable_pipe] disabling pipe C
>[  241.331210] [drm:intel_dp_link_down] 
>[  241.352457] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x050007ff)
>[  241.375486] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz
>[  241.375516] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  241.375540] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  241.375551] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  241.375566] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  241.375579] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  241.375593] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  241.375605] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  241.375619] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  241.375633] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  241.375647] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  241.375690] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x150007ff)
>[  241.385005] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0007ff)
>[  241.607672] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  241.607692] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  241.608493] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  241.693682] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  241.693703] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  241.776851] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  241.776872] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  241.863612] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  241.863633] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  241.864814] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  241.865027] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  241.865047] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  241.865061] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  241.867013] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x0d0007ff)
>[  241.877134] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  241.877171] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  241.877185] [drm:intel_enable_pipe] enabling pipe B
>[  241.877222] [drm:intel_psr_enable] PSR not supported by this panel
>[  241.877311] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0xc (PHY_CONTROL=0x2d6007ff)
>[  242.016991] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.017013] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.019461] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[  242.061581] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.061603] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.105632] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.105654] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 3
>[  242.107961] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  242.151663] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  242.151684] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.195421] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.195442] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.237214] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  242.237235] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.275947] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.275968] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.278645] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  242.283880] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  242.283916] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  242.283931] [drm:intel_enable_pipe] enabling pipe C
>[  242.283971] [drm:intel_psr_enable] PSR not supported by this panel
>[  242.311134] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  242.311169] [drm:verify_crtc_state] [CRTC:31]
>[  242.323323] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  242.323351] [drm:verify_crtc_state] [CRTC:36]
>[  242.335727] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  242.344256] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 256 / 511 / 511
>[  242.344292] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  242.411014] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  242.479040] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  242.511037] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  242.511059] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  242.511079] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  242.511116] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  242.511127] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  242.511143] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  242.511163] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880274f58800 for pipe B
>[  242.511173] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  242.511184] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  242.511198] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  242.511213] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  242.511227] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  242.511238] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  242.511247] [drm:intel_dump_pipe_config] requested mode:
>[  242.511266] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  242.511276] [drm:intel_dump_pipe_config] adjusted mode:
>[  242.511294] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  242.511311] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  242.511321] [drm:intel_dump_pipe_config] port clock: 270000
>[  242.511332] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  242.511343] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  242.511355] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  242.511367] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  242.511377] [drm:intel_dump_pipe_config] ips: 0
>[  242.511386] [drm:intel_dump_pipe_config] double wide: 0
>[  242.511399] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  242.511408] [drm:intel_dump_pipe_config] planes on this crtc
>[  242.511422] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 enabled
>[  242.511435] [drm:intel_dump_pipe_config] 	FB:126, fb = 3840x2160 format = 0x34325258
>[  242.511451] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 3840x2160 dst (0, 0) 3840x2160
>[  242.511466] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  242.511479] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 enabled
>[  242.511490] [drm:intel_dump_pipe_config] 	FB:127, fb = 64x64 format = 0x34325258
>[  242.511505] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (132, 132) 64x64
>[  242.511519] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  242.511536] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  242.511597] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  242.544249] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  242.545655] [drm:intel_disable_pipe] disabling pipe B
>[  242.579306] [drm:intel_dp_link_down] 
>[  242.609945] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  242.620857] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  242.620893] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  242.625539] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  242.625574] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  242.625587] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  242.625602] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  242.625616] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  242.625631] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  242.625642] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  242.625657] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  242.625670] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  242.625684] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  242.625708] [drm:intel_power_well_disable] disabling dpio-common-bc
>[  242.634967] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY0 (PHY_CONTROL=0x256007fe)
>[  242.644306] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  242.644335] [drm:verify_crtc_state] [CRTC:31]
>[  242.644491] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  242.644506] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  242.644525] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  242.644560] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  242.644571] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  242.644587] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  242.644606] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff8802731fe000 for pipe B
>[  242.644617] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  242.644627] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  242.644641] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  242.644656] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  242.644670] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  242.644681] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  242.644690] [drm:intel_dump_pipe_config] requested mode:
>[  242.644710] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  242.644719] [drm:intel_dump_pipe_config] adjusted mode:
>[  242.644738] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  242.644755] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  242.644765] [drm:intel_dump_pipe_config] port clock: 270000
>[  242.644776] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  242.644787] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  242.644799] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  242.644811] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  242.644821] [drm:intel_dump_pipe_config] ips: 0
>[  242.644830] [drm:intel_dump_pipe_config] double wide: 0
>[  242.644843] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  242.644852] [drm:intel_dump_pipe_config] planes on this crtc
>[  242.644867] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 enabled
>[  242.644880] [drm:intel_dump_pipe_config] 	FB:126, fb = 3840x2160 format = 0x34325258
>[  242.644896] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 3840x2160 dst (0, 0) 3840x2160
>[  242.644911] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  242.644923] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 enabled
>[  242.644935] [drm:intel_dump_pipe_config] 	FB:127, fb = 64x64 format = 0x34325258
>[  242.644950] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (132, 132) 64x64
>[  242.644964] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  242.644981] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  242.645039] [drm:intel_power_well_enable] enabling dpio-common-bc
>[  242.663279] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY0 (PHY_CONTROL=0x256007ff)
>[  242.672409] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  242.672444] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  242.672457] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  242.672471] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  242.672486] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  242.672500] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  242.672512] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  242.672527] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  242.672540] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  242.672554] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  242.672594] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x356007ff)
>[  242.681710] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x3d6007ff)
>[  242.896908] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.896929] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  242.897847] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  242.981033] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  242.981136] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  242.982375] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  242.982594] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  242.982616] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  242.982630] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  242.983393] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x2d6007ff)
>[  242.993527] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 256 / 511 / 511
>[  242.993562] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=16, cursor=63, sprite0=15, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  242.993577] [drm:intel_enable_pipe] enabling pipe B
>[  242.993614] [drm:intel_psr_enable] PSR not supported by this panel
>[  243.027413] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  243.027447] [drm:verify_crtc_state] [CRTC:31]
>[  243.039057] [drm:pipe_crc_set_source] collecting CRCs for pipe B, DP-B
>[  243.128702] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[  243.170930] kms_plane: starting subtest plane-panning-top-left-pipe-B-plane-1
>[  243.175689] kms_plane: starting subtest plane-panning-bottom-right-pipe-B-plane-1
>[  243.180500] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-plane-1
>[  243.183816] kms_plane: starting subtest plane-position-covered-pipe-B-plane-2
>[  243.186790] kms_plane: starting subtest plane-position-hole-pipe-B-plane-2
>[  243.189751] kms_plane: starting subtest plane-position-hole-dpms-pipe-B-plane-2
>[  243.192680] kms_plane: starting subtest plane-panning-top-left-pipe-B-plane-2
>[  243.195069] kms_plane: starting subtest plane-panning-bottom-right-pipe-B-plane-2
>[  243.197274] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-plane-2
>[  243.199441] kms_plane: starting subtest plane-position-covered-pipe-B-plane-3
>[  243.201634] kms_plane: starting subtest plane-position-hole-pipe-B-plane-3
>[  243.203802] kms_plane: starting subtest plane-position-hole-dpms-pipe-B-plane-3
>[  243.205911] kms_plane: starting subtest plane-panning-top-left-pipe-B-plane-3
>[  243.207810] kms_plane: starting subtest plane-panning-bottom-right-pipe-B-plane-3
>[  243.209727] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-plane-3
>[  243.211609] kms_plane: starting subtest plane-position-covered-pipe-C-plane-1
>[  243.211701] [drm:drm_mode_addfb2] [FB:128]
>[  243.249434] kms_plane: starting subtest plane-position-hole-pipe-C-plane-1
>[  243.249484] kms_plane: starting subtest plane-position-hole-dpms-pipe-C-plane-1
>[  243.249530] kms_plane: starting subtest plane-panning-top-left-pipe-C-plane-1
>[  243.249573] kms_plane: starting subtest plane-panning-bottom-right-pipe-C-plane-1
>[  243.249614] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-C-plane-1
>[  243.249657] kms_plane: starting subtest plane-position-covered-pipe-C-plane-2
>[  243.249697] kms_plane: starting subtest plane-position-hole-pipe-C-plane-2
>[  243.249738] kms_plane: starting subtest plane-position-hole-dpms-pipe-C-plane-2
>[  243.249778] kms_plane: starting subtest plane-panning-top-left-pipe-C-plane-2
>[  243.249817] kms_plane: starting subtest plane-panning-bottom-right-pipe-C-plane-2
>[  243.249857] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-C-plane-2
>[  243.249898] kms_plane: starting subtest plane-position-covered-pipe-C-plane-3
>[  243.249938] kms_plane: starting subtest plane-position-hole-pipe-C-plane-3
>[  243.249974] kms_plane: starting subtest plane-position-hole-dpms-pipe-C-plane-3
>[  243.250013] kms_plane: starting subtest plane-panning-top-left-pipe-C-plane-3
>[  243.250053] kms_plane: starting subtest plane-panning-bottom-right-pipe-C-plane-3
>[  243.250093] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-C-plane-3
>[  243.250135] kms_plane: exiting, ret=99
>[  243.250280] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains
>[  243.250282] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  243.250286] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz
>[  243.250295] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  243.250296] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000
>[  243.250299] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  243.250302] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880274f59000 for pipe A
>[  243.250304] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  243.250305] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  243.250306] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  243.250308] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[  243.250310] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  243.250311] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  243.250312] [drm:intel_dump_pipe_config] requested mode:
>[  243.250315] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  243.250316] [drm:intel_dump_pipe_config] adjusted mode:
>[  243.250318] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  243.250320] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x40 flags: 0x9
>[  243.250322] [drm:intel_dump_pipe_config] port clock: 270000
>[  243.250323] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[  243.250324] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  243.250325] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  243.250327] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  243.250327] [drm:intel_dump_pipe_config] ips: 0
>[  243.250328] [drm:intel_dump_pipe_config] double wide: 0
>[  243.250330] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  243.250331] [drm:intel_dump_pipe_config] planes on this crtc
>[  243.250335] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled
>[  243.250337] [drm:intel_dump_pipe_config] 	FB:111, fb = 3840x2160 format = 0x34325258
>[  243.250337] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
>[  243.250338] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  243.250341] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 enabled
>[  243.250343] [drm:intel_dump_pipe_config] 	FB:120, fb = 64x64 format = 0x34325258
>[  243.250344] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 4294967196x4294967196 dst (100, 100) 4294967196x4294967196
>[  243.250345] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0
>[  243.250349] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  243.250378] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  243.260622] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[  243.261143] [drm:intel_disable_pipe] disabling pipe B
>[  243.295438] [drm:intel_dp_link_down] 
>[  243.325425] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x256007ff)
>[  243.337156] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  243.337179] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  243.342014] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  243.342035] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  243.342040] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  243.342048] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  243.342057] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  243.342065] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  243.342072] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  243.342080] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  243.342089] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  243.342096] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  243.342130] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x2d6007ff)
>[  243.563051] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  243.563057] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  243.563874] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  243.647987] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  243.647993] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  243.733210] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  243.733216] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  243.818313] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  243.818319] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  243.819527] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  243.819739] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  243.819751] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44]
>[  243.819759] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  243.825468] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  243.825490] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  243.825497] [drm:intel_enable_pipe] enabling pipe A
>[  243.825531] [drm:intel_psr_enable] PSR not supported by this panel
>[  243.859209] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  243.859230] [drm:verify_crtc_state] [CRTC:26]
>[  243.870907] [drm:verify_crtc_state] [CRTC:31]
>[  243.899361] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  243.899369] [drm:i915_pages_create_for_stolen] offset=0x9000, size=16384
>[  243.900378] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  243.900384] [drm:i915_pages_create_for_stolen] offset=0xd000, size=16384
>[  243.900894] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  243.900900] [drm:i915_pages_create_for_stolen] offset=0x11000, size=16384
>[  243.901261] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  243.901268] [drm:i915_pages_create_for_stolen] offset=0x15000, size=16384
>[  265.609333] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00400000, dig 0x00400000, pins 0x00000080
>[  265.609359] [drm:intel_hpd_irq_handler] digital hpd port D - long
>[  265.609372] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 7 - cnt: 0
>[  265.609493] [drm:intel_dp_hpd_pulse] got hpd irq on port D - long
>[  265.609557] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[  265.609577] [drm:i915_hotplug_work_func] Connector HDMI-A-3 (pin 7) received hotplug event.
>[  265.609590] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-3]
>[  265.736971] [drm:intel_hdmi_detect] HDMI live status down
>[  265.737002] [drm:i915_hotplug_work_func] Connector DP-3 (pin 7) received hotplug event.
>[  265.737015] [drm:intel_dp_detect] [CONNECTOR:53:DP-3]
>[  265.737037] [drm:intel_hpd_irq_event] [CONNECTOR:53:DP-3] status updated from connected to disconnected
>[  265.737184] [drm:drm_fb_helper_hotplug_event] 
>[  265.737201] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1]
>[  265.737213] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
>[  265.739211] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  265.739228] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  265.739493] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  265.739515] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  265.739802] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  265.739820] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  265.740075] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  265.740101] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected
>[  265.740119] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[  265.740138] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[  265.740984] [drm:intel_dp_get_dpcd] DPCD: 11 0a c4 01 01 00 01 00 02 02 06 00 00 00 00
>[  265.741379] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[  265.741416] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[  265.741433] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[  265.741453] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[  265.742489] [drm:drm_edid_to_eld] ELD monitor ASUS PB287Q
>[  265.742513] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 600, latency present 0 0, video latency 0 0, audio latency 0 0
>[  265.742533] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  265.742831] [drm:drm_mode_debug_printmodeline] Modeline 117:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  265.742843] [drm:drm_mode_prune_invalid] Not using 3840x2160 mode: CLOCK_HIGH
>[  265.742879] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] probed modes :
>[  265.742898] [drm:drm_mode_debug_printmodeline] Modeline 59:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[  265.742918] [drm:drm_mode_debug_printmodeline] Modeline 61:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[  265.742937] [drm:drm_mode_debug_printmodeline] Modeline 60:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[  265.742956] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  265.742983] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  265.743002] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  265.743021] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  265.743040] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  265.743059] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  265.743078] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  265.743098] [drm:drm_mode_debug_printmodeline] Modeline 68:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  265.743117] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  265.743142] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  265.743161] [drm:drm_mode_debug_printmodeline] Modeline 67:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  265.743180] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  265.743199] [drm:drm_mode_debug_printmodeline] Modeline 69:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  265.743218] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  265.743237] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  265.743257] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  265.743284] [drm:drm_mode_debug_printmodeline] Modeline 98:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  265.743303] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  265.743322] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  265.743341] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  265.743360] [drm:drm_mode_debug_printmodeline] Modeline 108:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  265.743379] [drm:drm_mode_debug_printmodeline] Modeline 96:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  265.743398] [drm:drm_mode_debug_printmodeline] Modeline 82:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  265.743417] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  265.743443] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  265.743462] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  265.743481] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  265.743499] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  265.743518] [drm:drm_mode_debug_printmodeline] Modeline 103:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  265.743537] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  265.743556] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  265.743582] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  265.743601] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  265.743619] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  265.743638] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  265.743657] [drm:drm_mode_debug_printmodeline] Modeline 77:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  265.743670] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-2]
>[  265.743682] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[  265.869116] [drm:intel_hdmi_detect] HDMI live status down
>[  265.869147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-2] disconnected
>[  265.869165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:49:DP-2]
>[  265.869176] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[  265.869197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:49:DP-2] disconnected
>[  265.869209] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-3]
>[  265.869220] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-3]
>[  265.996976] [drm:intel_hdmi_detect] HDMI live status down
>[  265.997008] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-3] disconnected
>[  265.997025] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-3]
>[  265.997040] [drm:intel_dp_detect] [CONNECTOR:53:DP-3]
>[  265.997060] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-3] disconnected
>[  265.997099] [drm:drm_setup_crtcs] 
>[  265.997114] [drm:drm_enable_connectors] connector 40 enabled? no
>[  265.997124] [drm:drm_enable_connectors] connector 45 enabled? yes
>[  265.997135] [drm:drm_enable_connectors] connector 47 enabled? no
>[  265.997145] [drm:drm_enable_connectors] connector 49 enabled? no
>[  265.997156] [drm:drm_enable_connectors] connector 51 enabled? no
>[  265.997166] [drm:drm_enable_connectors] connector 53 enabled? no
>[  265.997179] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[  265.997194] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1
>[  265.997205] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0
>[  265.997223] [drm:intel_fb_initial_config] using first mode listed on connector DP-1
>[  265.997237] [drm:intel_fb_initial_config] connector DP-1 on pipe A [CRTC:26]: 3840x2160
>[  265.997248] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
>[  265.997258] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
>[  265.997268] [drm:intel_fb_initial_config] connector HDMI-A-3 not enabled, skipping
>[  265.997277] [drm:intel_fb_initial_config] connector DP-3 not enabled, skipping
>[  265.997291] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 26 (0,0)
>[  265.997427] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000
>[  265.997488] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  266.004197] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.006966] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.009622] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.012258] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.014840] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.017397] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.019939] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.022497] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.025040] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.027548] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.030069] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.032577] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.035098] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.037631] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.040120] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.042677] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.045187] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.047678] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.050177] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.052680] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.055165] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.057679] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.060164] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.062670] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.065176] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.067678] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.070171] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.072679] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.075167] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.077678] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.080162] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.082667] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x70150064
>[  266.082674] [drm:drm_dp_dpcd_access] too many retries, giving up
>[  266.082677] [drm:intel_dp_sink_dpms] failed to disable sink power state
>[  266.082687] [drm:intel_disable_pipe] disabling pipe C
>[  266.084763] [drm:intel_dp_link_down] 
>[  266.106293] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY1 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007ff)
>[  266.117272] [drm:vlv_pipe_set_fifo_size] Pipe C FIFO split 511 / 511 / 511
>[  266.117293] [drm:vlv_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0
>[  266.120742] [drm:verify_encoder_state] [ENCODER:39:TMDS-39]
>[  266.120760] [drm:verify_encoder_state] [ENCODER:44:TMDS-44]
>[  266.120767] [drm:verify_encoder_state] [ENCODER:46:TMDS-46]
>[  266.120788] [drm:verify_encoder_state] [ENCODER:48:TMDS-48]
>[  266.120796] [drm:verify_encoder_state] [ENCODER:50:TMDS-50]
>[  266.120807] [drm:verify_encoder_state] [ENCODER:52:TMDS-52]
>[  266.120822] [drm:intel_connector_verify_state] [CONNECTOR:40:HDMI-A-1]
>[  266.120830] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-2]
>[  266.120843] [drm:intel_connector_verify_state] [CONNECTOR:49:DP-2]
>[  266.121242] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-3]
>[  266.121253] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-3]
>[  266.121316] [drm:intel_power_well_disable] disabling dpio-common-d
>[  266.129242] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x0d0007fd)
>[  266.137786] [drm:verify_crtc_state] [CRTC:36]
>[  531.297056] [drm:i915_gem_open]

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Attachments on bug 86763: 110110 | 114187 | 121301 | 124242 | 124243

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