Attachment 124342 Details for Bug 96397 – regs dump (non-working)

regs dump (non-working)

regsdump (text/plain), 17.70 KB, created by Xavier Bachelot on 2016-06-05 22:37:38 UTC

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Creator: Xavier Bachelot

Created: 2016-06-05 22:37:38 UTC

Size: 17.70 KB

patch

obsolete

>via-chrome-tool (C) 2009 by VIA Technologies, Inc.
>This is FREE SOFTWARE with ABSOLUTELY NO WARRANTY
>
>Sequencer register dump:
>    0x00 = 0x00 (Reset)
>    0x01 = 0x01 (Clocking Mode)
>    0x02 = 0x0f (Map Mask)
>    0x03 = 0x00 (Character Map Select)
>    0x04 = 0x0e (Memory Mode)
>    0x10 = 0x01 (Extended Register Unlock)
>    0x11 = 0x78 (Configuration 0)
>    0x12 = 0x30 (Configuration 1)
>    0x13 = 0x08 (Configuration 2 (DVP1 strapping))
>    0x14 = 0x01 (Frame Buffer Size Control)
>    0x15 = 0xbe (Display Mode Control)
>    0x16 = 0x8f (Display FIFO Threshold Control)
>    0x17 = 0x1f (Display FIFO Control)
>    0x18 = 0x4f (Display Arbiter Control 0)
>    0x19 = 0x7f (Power Management)
>       0x01 CPU Interface Clock Control: 0x01
>       0x02 Display Interface Clock Control: 0x02
>       0x04 MC Interface Clock Control: 0x04
>       0x08 Typical Arbiter Interface Clock Control: 0x08
>       0x10 AGP Interface Clock Control: 0x10
>       0x20 P-Arbiter Interface Clock Control: 0x20
>       0x40 MIU/AGP Interface Clock Control: 0x40
>    0x1a = 0x1a (PCI Bus Control)
>    0x1b = 0xf0 (Power Management Control 0)
>       0x01 Primary Display's LUT Off: 0x00
>       0x18 Primary Display Engine VCK Gating: 0x10
>       0x60 Secondary Display Engine LCK Gating: 0x60
>    0x1c = 0xe0 (Horizontal Display Fetch Count Data)
>    0x1d = 0x01 (Horizontal Display Fetch Count Control)
>    0x1e = 0xf1 (Power Management Control)
>       0x01 ROC ECK: 0x01
>       0x02 Replace ECK by MCK: 0x00
>       0x08 Spread Spectrum: 0x00
>       0x30 DVP1 Power Control: 0x30
>       0xc0 VCP Power Control: 0xc0
>    0x20 = 0x00 (Typical Arbiter Control 0)
>    0x21 = 0x00 (Typical Arbiter Control 1)
>    0x22 = 0x1f (Display Arbiter Control 1)
>    0x26 = 0x3d (IIC Serial Port Control 0)
>    0x2a = 0x0f (Power Management Control 5)
>       0x03 LVDS Channel 1 Pad Control: 0x03
>       0x0c LVDS Channel 2 Pad Control: 0x0c
>       0x40 Sprad Spectrum Type FIFO: 0x00
>    0x2b = 0x00 (LVDS Interrupt Control)
>       0x01 MSI Pending IRQ Re-trigger: 0x00
>       0x02 CRT Hot Plug Detect Enable: 0x00
>       0x04 CRT Sense IRQ status: 0x00
>       0x08 CRT Sense IRQ enable: 0x00
>       0x10 LVDS Sense IRQ status: 0x00
>       0x20 LVDS Sense IRQ enable: 0x00
>    0x2c = 0x00 (General Purpose I/O Port)
>    0x2d = 0x3f (Power Management Control 1)
>       0x03 ECK Pll Power Control: 0x03
>       0x0c LCK PLL Power Control: 0x0c
>       0x30 VCK PLL Powre Control: 0x30
>       0xc0 E3_ECK_N Selection: 0x00
>    0x2e = 0xff (Power Management Control 2)
>       0x03 Video Playback Engine V3/V4 Gated Clock VCK: 0x03
>       0x0c PCI Master / DMA Gated Clock ECK/CPUCK: 0x0c
>       0x30 Video Processor Gated Clock ECK: 0x30
>       0xc0 Capturer Gated Clock ECK: 0xc0
>    0x31 = 0x3d (IIC Serial Port Control 1)
>    0x35 = 0x06 (Subsystem Vendor ID Low)
>    0x36 = 0x11 (Subsystem Vendor ID High)
>    0x37 = 0x22 (Subsystem ID Low)
>    0x38 = 0x31 (Subsystem ID High)
>    0x39 = 0x10 (BIOS Reserved Register 0)
>    0x3a = 0x0f (BIOS Reserved Register 1)
>    0x3b = 0x00 (PCI Revision ID Back Door)
>    0x3c = 0x00 (Miscellaneous)
>       0x01 AGP Bus Pack Door AGP3 Enable: 0x00
>       0x02 Switch 3 PLLs to Prime Output: 0x00
>       0x04 LCDCK PLL Locked Detect: 0x00
>       0x08 VCK PLL Locked Detect: 0x00
>       0x10 ECL PLL Locked Detect: 0x00
>       0x60 PLL Frequency Division Select for Testing: 0x00
>    0x3d = 0x00 (General Purpose I/O Port)
>    0x3e = 0x68 (Miscellaneous Register for AGP Mux)
>    0x3f = 0xff (Power Management Control 2)
>       0x03 Video Clock Control (Gated ECK): 0x03
>       0x0c 2D Clock Control (Gated ECK/CPUCK): 0x0c
>       0x30 3D Clock Control (Gated ECK): 0x30
>       0xc0 CR Clock Control (Gated ECK): 0xc0
>    0x40 = 0x00 (PLL Control)
>       0x01 Reset ECK PLL: 0x00
>       0x02 Reset VCK PLL: 0x00
>       0x04 Reset LCDCK PLL: 0x00
>       0x08 LVDS Interrupt Method: 0x00
>       0x30 Free Run ECK Frequency within Idle Mode: 0x00
>       0x80 CRT Sense Enable: 0x00
>    0x41 = 0xb0 (Typical Arbiter Control 1)
>    0x42 = 0x10 (Typical Arbiter Control 1)
>    0x43 = 0x00 (Graphics Bonding Option)
>       0x01 Notebook Used Flag: 0x00
>       0x04 Typical Channel 1 Arbiter Read Back Data Overwrite Flag: 0x00
>       0x08 Typical Channel 0 Arbiter Read Back Data Overwrite Flag: 0x00
>       0x10 IGA1 Display FIFO Underflow Flag: 0x00
>       0x20 IGA2 Dispaly FIFO Underflow Flag: 0x00
>       0x40 Windows Media Video Enable Flag: 0x00
>       0x80 Advance Video Enable Flag: 0x00
>    0x44 = 0xc3 (VCK Clock Synthesizer Vallue 0)
>    0x45 = 0x2a (VCK Clock Synthesizer Vallue 1)
>    0x46 = 0x03 (VCK Clock Synthesizer Vallue 2)
>    0x47 = 0x1d (ECK Clock Synthesizer Vallue 0)
>    0x48 = 0x07 (ECK Clock Synthesizer Vallue 1)
>    0x49 = 0x41 (ECK Clock Synthesizer Vallue 2)
>    0x4a = 0x46 (LDCK Clock Synthesizer Value 0)
>    0x4b = 0x48 (LDCK Clock Synthesizer Value 1)
>    0x4c = 0x00 (LDCK Clock Synthesizer Value 2)
>    0x4d = 0x00 (Preemptive Arbiter Control)
>    0x4e = 0x00 (Software Reset Control)
>    0x4f = 0x00 (CR Gating Clock Control)
>    0x50 = 0x00 (AGP Control)
>    0x51 = 0x00 (Display FIFO Control 1)
>    0x52 = 0x00 (Integrated TV Shadow Register Control)
>    0x53 = 0x00 (DAC Sense Control 1)
>    0x54 = 0x00 (DAC Sense Control 2)
>    0x55 = 0x00 (DAC Sense Control 3)
>    0x56 = 0x00 (DAC Sense Control 4)
>    0x57 = 0x00 (Display FIFO Control 2)
>    0x58 = 0x00 (GFX Power Control 1)
>    0x59 = 0x00 (GFX Power Control 2)
>       0x01 GFX-NM AGP Dynamic Clock Enable: 0x00
>       0x02 GFX-NM GMINT Channel 0 Dynamic Clock Enable: 0x00
>       0x04 GFX-NM GMINT Channel 1 Dynamic Clock Enable: 0x00
>       0x08 GFX-NM PCIC Dynamic Clock Enable: 0x00
>       0x10 GFX-NM IGA Dynamic Clock Enable: 0x00
>       0x20 IGA Low Thrshold Enable: 0x00
>       0x80 IGA1 Enable: 0x00
>    0x5a = 0x00 (PCI Bus Control 2)
>    0x5b = 0x00 (Device Used Status 0)
>       0x01 LVDS1 Used IGA2 Source: 0x00
>       0x02 LBDS1 Used IGA1 Source: 0x00
>       0x04 LVDS0 Used IGA2 Source: 0x00
>       0x08 LVDS1 Used IGA1 Source: 0x00
>       0x10 DAC0 Used IGA2 Source: 0x00
>       0x20 DAC0 Used IGA1 Source: 0x00
>       0x40 DAC0 User is TV: 0x00
>       0x80 DCVI Source Selection is TV: 0x00
>    0x5c = 0x00 (Device Used Status 1)
>       0x01 DVP1 Used IGA2 Source: 0x00
>       0x02 DVP1 Used IGA1 Source: 0x00
>       0x10 DAC1 Used IGA2 Source: 0x00
>       0x20 DAC1 Used IGA1 Source: 0x00
>       0x40 DAC1 User is TV: 0x00
>    0x5d = 0x00 (Timer Control)
>    0x5e = 0x00 (DAC Control 2)
>    0x60 = 0x00 (I2C Mode Control)
>    0x61 = 0x00 (I2C Host Address)
>    0x62 = 0x00 (I2C Host Data)
>    0x63 = 0x00 (I2C Host Control)
>    0x64 = 0x00 (I2C Status)
>    0x65 = 0x00 (Power Management Control 6)
>    0x66 = 0x00 (GTI Control 0)
>    0x67 = 0x00 (GTI Control 1)
>    0x68 = 0x00 (GTI Control 1)
>    0x69 = 0x00 (GTI Control 1)
>    0x6a = 0x00 (GTI Control 1)
>    0x6b = 0x00 (GTI Control 1)
>    0x6c = 0x00 (GTI Control 1)
>    0x6d = 0x00 (GTI Control 1)
>    0x6e = 0x00 (GTI Control 1)
>    0x6f = 0x00 (GTI Control 1)
>    0x70 = 0x00 (GARB Control 0)
>    0x71 = 0x00 (Typical Arbiter Control 2)
>    0x72 = 0x00 (Typical Arbiter Control 3)
>    0x73 = 0x00 (Typical Arbiter Control 4)
>    0x74 = 0x00 (Typical Arbiter Control 5)
>    0x75 = 0x00 (Typical Arbiter Control 6)
>    0x76 = 0x00 (Backlight Control 1)
>       0x01 Backlight Control Enable: 0x00
>    0x77 = 0x00 (Backlight Control 2)
>    0x78 = 0x00 (Backlight Control 3)
>
>Graphic Controller register dump:
>    0x00 = 0x00 (Set / Reset)
>    0x01 = 0x00 (Enable Set / Reset)
>    0x02 = 0x00 (Color Compare)
>    0x03 = 0x00 (Data Rotate)
>    0x04 = 0x00 (Read Map Select)
>    0x05 = 0x40 (Mode)
>    0x06 = 0x05 (Miscellaneous)
>    0x07 = 0x0f (Color Don't Care)
>    0x08 = 0xff (Bit Mask)
>    0x20 = 0x00 (Offset Register Control)
>    0x21 = 0x00 (Offset Register A)
>    0x22 = 0x00 (Offset Register B)
>
>CRT controller register dump:
>    0x00 = 0xff (Horizontal Total)
>    0x01 = 0xef (Horizontal Display End)
>    0x02 = 0xf0 (Start Horizontal Blank)
>    0x03 = 0x83 (End Horizontal Blank)
>    0x04 = 0xf6 (Start Horizontal Retrace)
>    0x05 = 0x19 (End Horizontal Retrace)
>    0x06 = 0x55 (Vertical Total)
>    0x07 = 0x10 (Overflow)
>    0x08 = 0x00 (Preset Row Scan)
>    0x09 = 0x40 (Max Scan Line)
>    0x0a = 0x1e (Cursor Start)
>    0x0b = 0x00 (Cursor End)
>    0x0c = 0x48 (Start Address High)
>    0x0d = 0x00 (Start Address Low)
>    0x0e = 0x00 (Cursor Location High)
>    0x0f = 0x00 (Cursor Location Low)
>    0x10 = 0x3b (Vertical Retrace Start)
>    0x11 = 0x0f (Vertical Retrace End)
>    0x12 = 0x37 (Vertical Display End)
>    0x13 = 0xc0 (Offset)
>    0x14 = 0x00 (Underline Location)
>    0x15 = 0x38 (Start Vertical Blank)
>    0x16 = 0x56 (End Vertical Blank)
>    0x17 = 0xe3 (CRTC Mode Control)
>    0x18 = 0xff (Line Compare)
>    0x30 = 0x00 (Display Fetch Blocking Control)
>    0x31 = 0x00 (Half Line Position)
>    0x32 = 0x00 (Mode Control)
>    0x33 = 0x06 (Hsync Adjuster)
>    0x34 = 0x3f (Starting Address Overflow)
>    0x35 = 0x7f (Extended Overflow)
>    0x36 = 0x01 (Power Management Control 3)
>    0x37 = 0x00 (DAC Control)
>    0x38 = 0x1f (Signature Data B0)
>    0x39 = 0x9f (Signature Data B1)
>    0x3a = 0x70 (Signature Data B2)
>    0x3b = 0x05 (Scratch Pad 2)
>    0x3c = 0x71 (Scratch Pad 3)
>    0x3d = 0x40 (Scratch Pad 4)
>    0x3e = 0x00 (Scratch Pad 5)
>    0x3f = 0x00 (Scratch Pad 6)
>    0x40 = 0x00 (Test Mode Control 0)
>    0x43 = 0x00 (IGA1 Display Control)
>    0x45 = 0x00 (Power Now Indicator Control 3)
>    0x46 = 0x00 (Test Mode Control 1)
>    0x47 = 0x00 (Test Mode Control 2)
>    0x48 = 0x00 (Starting Address Overflow)
>    0x50 = 0xff (Second CRTC Horizontal Total Period)
>    0x51 = 0xff (Second CRTC Horizontal Active Data Period)
>    0x52 = 0xff (Second CRTC Horizontal Blanking Start)
>    0x53 = 0xff (Second CRTC Horizontal Blanking End)
>    0x54 = 0xff (Second CRTC Horizontal Blanking Overflow)
>    0x55 = 0xff (Second CRTC Horizontal Period Overflow)
>    0x56 = 0xff (Second CRTC Horizontal Retrace Start)
>    0x57 = 0xff (Second CRTC Horizontal Retrace End)
>    0x58 = 0xff (Second CRTC Vertical Total Period)
>    0x59 = 0xff (Second CRTC Vertical Active Data Period)
>    0x5a = 0xff (Second CRTC Vertical Blanking Start)
>    0x5b = 0xff (Second CRTC Vertical Blanking End)
>    0x5c = 0xff (Second CRTC Vertical Blanking Overflow)
>    0x5d = 0xbf (Second CRTC Vertical Period Overflow)
>    0x5e = 0xff (Second CRTC Vertical Retrace Start)
>    0x5f = 0xff (Second CRTC Vertical Retrace End)
>    0x60 = 0x00 (Second CRTC Vertical Status 1)
>    0x61 = 0x20 (Second CRTC Vertical Status 2)
>    0x62 = 0xff (Second Display Starting Address Low)
>    0x63 = 0xff (Second Display Starting Address Middle)
>    0x64 = 0xff (Second Display Starting Address High)
>    0x65 = 0xff (Second Display Horizontal Quadword Count)
>    0x66 = 0xff (Second Display Horizontal Offset)
>    0x67 = 0xcf (Second Display Col Depth and Horiz Overfl)
>    0x68 = 0x67 (Second Display Queue Depth and Read Thresh)
>    0x69 = 0x00 (Second Display Interrupt Enable and Status)
>    0x6a = 0x80 (Second Display Channel and LCD Enable)
>    0x6b = 0x84 (Channel 1 and 2 Clock Mode Selection)
>    0x6c = 0x01 (TV Clock Control)
>    0x6d = 0xff (Horizontal Total Shadow)
>    0x6e = 0xff (End Horizontal Blanking Shadow)
>    0x6f = 0xff (Vertical Total Shadow)
>    0x70 = 0xff (Vertical Display Enable End Shadow)
>    0x71 = 0x7f (Vertical Display Overflow Shadow)
>    0x72 = 0xff (Start Vertical Blank Shadow)
>    0x73 = 0xff (End Vertical Blank Shadow)
>    0x74 = 0x77 (Vertical Blank Overflow Shadow)
>    0x75 = 0xff (Vertical Retrace Start Shadow)
>    0x76 = 0x7f (Vertical Retrace End Shadow)
>    0x77 = 0x00 (LCD Horizontal Scaling Factor)
>    0x78 = 0xff (LCD Vertical Scaling Facor)
>    0x79 = 0xf7 (LCD Scaling Control)
>    0x7a = 0x01 (LCD Scaling Parameter 1)
>    0x7b = 0x02 (LCD Scaling Parameter 2)
>    0x7c = 0x03 (LCD Scaling Parameter 3)
>    0x7d = 0x04 (LCD Scaling Parameter 4)
>    0x7e = 0x07 (LCD Scaling Parameter 5)
>    0x7f = 0x0a (LCD Scaling Parameter 6)
>    0x80 = 0x0d (LCD Scaling Parameter 7)
>    0x81 = 0x13 (LCD Scaling Parameter 8)
>    0x82 = 0x16 (LCD Scaling Parameter 9)
>    0x83 = 0x19 (LCD Scaling Parameter 10)
>    0x84 = 0x1c (LCD Scaling Parameter 11)
>    0x85 = 0x1d (LCD Scaling Parameter 12)
>    0x86 = 0x1e (LCD Scaling Parameter 13)
>    0x87 = 0x1f (LCD Scaling Parameter 14)
>    0x88 = 0x00 (LCD Panel Type)
>    0x8a = 0x88 (LCD Timing Control 1)
>    0x8b = 0x0d (LCD Power Sequence Control 0)
>    0x8c = 0x5d (LCD Power Sequence Control 1)
>    0x8d = 0x79 (LCD Power Sequence Control 2)
>    0x8e = 0xff (LCD Power Sequence Control 3)
>    0x8f = 0x10 (LCD Power Sequence Control 4)
>    0x90 = 0x0b (LCD Power Sequence Control 5)
>    0x91 = 0x01 (Software Cotnrol Power Sequence)
>    0x92 = 0x07 (Read Threshold 2)
>    0x94 = 0x00 (Expire Number and Display Queue Extend)
>    0x95 = 0x00 (Extend Threshold Bit)
>    0x97 = 0x00 (LVDS Channel 2 Function Select 0)
>    0x98 = 0x00 (LVDS Channel 2 Function Select 1)
>    0x99 = 0x00 (LVDS Channel 1 Function Select 0)
>    0x9a = 0x00 (LVDS Channel 1 Function Select 1)
>    0x9b = 0x00 (Digital Video Port 1 Function Select 0)
>    0x9c = 0x00 (Digital Video Port 1 Function Select 1)
>    0x9d = 0x00 (Power Now Control 2)
>    0x9e = 0x00 (Power Now Control 3)
>    0x9f = 0x00 (Power Now Control 4)
>    0xa0 = 0x00 (Horizontal Scaling Initial Value)
>    0xa1 = 0x00 (Vertical Scaling Initial Value)
>    0xa2 = 0x00 (Horizontal and Vertical Scaling Enable)
>    0xa3 = 0x00 (Second Display Starting Address Extended)
>    0xa5 = 0x00 (Second LCD Vertical Scaling Factor)
>    0xa6 = 0x00 (Second LCD Vertical Scaling Factor)
>    0xa7 = 0x00 (Expected IGA1 Vertical Display End)
>    0xa8 = 0x00 (Expected IGA1 Vertical Display End)
>    0xa9 = 0x00 (Hardware Gamma Control)
>    0xaa = 0x00 (FIFO Depth + Threshold Overflow)
>    0xab = 0x00 (IGA2 Inetrlace Half Line)
>    0xac = 0x00 (IGA2 Inetrlace Half Line)
>    0xaf = 0x00 (P-Arbiter Write Expired Number)
>    0xb0 = 0x00 (IGA2 Pack Circuit Request Threshold)
>    0xb1 = 0x00 (IGA2 Pack Circuit Request High Threshold)
>    0xb2 = 0x00 (IGA2 Pack Circuit Request Expire Threshold)
>    0xb3 = 0x00 (IGA2 Pack Circuit Control)
>    0xb4 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>    0xb5 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>    0xb6 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>    0xb7 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>    0xb8 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
>    0xb9 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
>    0xba = 0x00 (V Counter Set Pointer)
>    0xbb = 0x00 (V Counter Set Pointer)
>    0xbc = 0x00 (V Counter Reset Value)
>    0xbd = 0x00 (V Counter Reset Value)
>    0xbe = 0x00 (Frame Buffer Limit Value)
>    0xbf = 0x00 (Frame Buffer Limit Value)
>    0xc0 = 0x00 (Expected IGA1 Vertical Display End 1)
>    0xc1 = 0x00 (Expected IGA1 Vertical Display End 1)
>    0xc2 = 0x00 (Third LCD Vertical Scaling Factor)
>    0xc3 = 0x00 (Third LCD Vertical Scaling Factor)
>    0xc4 = 0x00 (Expected IGA1 Vertical Display End 2)
>    0xc5 = 0x00 (Expected IGA1 Vertical Display End 2)
>    0xc7 = 0x00 (Fourth LCD Vertical Scaling Factor)
>    0xc8 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>    0xc9 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>    0xca = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>    0xcb = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>    0xd0 = 0x00 (LVDS PLL1 Control)
>    0xd1 = 0x00 (LVDS PLL2 Control)
>    0xd2 = 0x00 (LVDS Control)
>    0xd3 = 0x00 (LVDS Second Power Sequence Control 0)
>    0xd4 = 0x00 (LVDS Second Power Sequence Control 1)
>    0xd5 = 0x00 (LVDS Texting Mode Control)
>    0xd6 = 0x00 (DCVI Control Register 0)
>    0xd7 = 0x00 (DCVI Control Register 1)
>    0xd9 = 0x00 (Scaling Down Source Data Offset Control)
>    0xda = 0x00 (Scaling Down Source Data Offset Control)
>    0xdb = 0x00 (Scaling Down Source Data Offset Control)
>    0xdc = 0x00 (Scaling Down Vertical Scale Control)
>    0xdd = 0x00 (Scaling Down Vertical Scale Control)
>    0xde = 0x00 (Scaling Down Vertical Scale Control)
>    0xdf = 0x00 (Scaling Down Vertical Scale Control)
>    0xe0 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>    0xe1 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>    0xe2 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>    0xe3 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>    0xe4 = 0x00 (Scaling Down SW Source FB Stride)
>    0xe5 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>    0xe6 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>    0xe7 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>    0xe8 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>    0xe9 = 0x00 (Scaling Down Destination FB Starting Addr 2)
>    0xea = 0x00 (Scaling Down Destination FB Starting Addr 2)
>    0xeb = 0x00 (Scaling Down Destination FB Starting Addr 2)
>    0xec = 0x00 (IGA1 Down Scaling Destination Control)
>    0xf0 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
>    0xf1 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
>    0xf2 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
>    0xf3 = 0x00 (Snapshot Mode Control)
>    0xf4 = 0x00 (Snapshot Mode Control)
>    0xf5 = 0x00 (Snapshot Mode Control)
>    0xf6 = 0x00 (Snapshot Mode Control)
>
>VCK PLL: dm=195, dtx=2, dr=5, dn=1 VCK Fvco=940215 kHz, Fout=94021 kHz
>ECK PLL: dm=29, dtx=3, dr=0, dn=32 ECK Fvco=13054 kHz, Fout=0 kHz
>LDCK PLL: dm=326, dtx=0, dr=1, dn=0 LDCK Fvco=2348152 kHz, Fout=1174076 kHz
>SL in System memory: 0x0, RTSF in SL: 0x0
>Primary Display:
>    H total=2080, active=1920, blank (1928-32), sync(1968-200)
>    V total=1111, active=1080, blank (1081-87), sync(1083-15)
>base_addr=0x003f4800, bpp=32
>
>Secondary Display:
>    H total=3840, active=1792, blank (1792-5888), sync(4095-511)
>    V total=1792, active=1792, blank (1792-1792), sync(2047-31)
>base_addr=0x03fffff8, bpp=32
>
>Panel Scaling enabled, mode Interpolation
>Scaling Factors: horizontal=3072, vertical=2046
>
>LVDS Seq Mode: LVDS1 + LVDS2
>LVDS CRT Mode: LVDS1 + LVDS2
>LVDS Channel 1 Format SPWG, Power Up
>LVDS Channel 2 Format SPWG, Power Up
>

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Attachments on bug 96397: 124341 | 124342 | 124343 | 124344 | 124345 | 124346 | 124393 | 124397 | 124430

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