Attachment 124375 Details for Bug 96296 – global_bandwidth_v16_local_offset asm dump

global_bandwidth_v16_local_offset asm dump

global_offset.asm (text/plain), 14.98 KB, created by Jan Vesely on 2016-06-06 17:59:35 UTC

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Creator: Jan Vesely

Created: 2016-06-06 17:59:35 UTC

Size: 14.98 KB

patch

obsolete

>	.section	.AMDGPU.csdata
>	;SQ_PGM_RESOURCES:STACK_SIZE = 0
>	.section	.AMDGPU.config
>	.long	166100
>	.long	62
>	.long	165900
>	.long	0
>	.long	166120
>	.long	0
>	.text
>	.globl	global_bandwidth_v16_global_offset
>	.p2align	8
>	.type	global_bandwidth_v16_global_offset,@function
>global_bandwidth_v16_global_offset:     ; @global_bandwidth_v16_global_offset
>.Lfunc_begin9:
>; BB#0:                                 ; %entry
>	.loc	5 4 27 discriminator 1  ; ./generic/lib/workitem/get_global_id.cl:4:27
>	ALU 20, @0x90, KC0[CB0:0-32], KC1[]
>	TEX 6 @16
>	ALU 31, @0xa5, KC0[CB0:0-32], KC1[]
>	TEX 10 @30
>	ALU 29, @0xc5, KC0[CB0:0-32], KC1[]
>	TEX 10 @52
>	ALU 17, @0xe3, KC0[CB0:0-32], KC1[]
>	TEX 14 @0x4a
>	ALU 14, @0xf5, KC0[], KC1[]
>	TEX 15 @0x68
>	ALU 0x6d, @0x104, KC0[], KC1[]
>	TEX 3 @0x88
>	ALU 0x72, @0x172, KC0[CB0:0-32], KC1[]
>	MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
>	CF_END
>	PAD
>	Fetch clause starting at 16:
>	VTX_READ_128 T6.XYZW, T10.X, 16
>	VTX_READ_128 T7.XYZW, T9.X, 16
>	VTX_READ_128 T1.XYZW, T8.X, 48
>	VTX_READ_128 T2.XYZW, T11.X, 48
>	VTX_READ_128 T3.XYZW, T0.X, 48
>	VTX_READ_128 T4.XYZW, T10.X, 48
>	VTX_READ_128 T5.XYZW, T9.X, 48
>	Fetch clause starting at 30:
>	VTX_READ_128 T18.XYZW, T17.X, 16
>	VTX_READ_128 T19.XYZW, T16.X, 48
>	VTX_READ_128 T20.XYZW, T15.X, 48
>	VTX_READ_128 T21.XYZW, T14.X, 16
>	VTX_READ_128 T22.XYZW, T8.X, 16
>	VTX_READ_128 T23.XYZW, T13.X, 48
>	VTX_READ_128 T24.XYZW, T12.X, 48
>	VTX_READ_128 T25.XYZW, T11.X, 16
>	VTX_READ_128 T26.XYZW, T0.X, 16
>	VTX_READ_128 T27.XYZW, T17.X, 48
>	VTX_READ_128 T28.XYZW, T14.X, 48
>	Fetch clause starting at 52:
>	VTX_READ_128 T30.XYZW, T26.X, 48
>	VTX_READ_128 T31.XYZW, T6.X, 48
>	VTX_READ_128 T32.XYZW, T15.X, 16
>	VTX_READ_128 T33.XYZW, T11.X, 0
>	VTX_READ_128 T34.XYZW, T0.X, 0
>	VTX_READ_128 T35.XYZW, T13.X, 16
>	VTX_READ_128 T36.XYZW, T7.X, 48
>	VTX_READ_128 T37.XYZW, T29.X, 48
>	VTX_READ_128 T38.XYZW, T12.X, 16
>	VTX_READ_128 T39.XYZW, T10.X, 0
>	VTX_READ_128 T40.XYZW, T9.X, 0
>	Fetch clause starting at 0x4a:
>	VTX_READ_128 T41.XYZW, T7.X, 32
>	VTX_READ_128 T42.XYZW, T18.X, 16
>	VTX_READ_128 T43.XYZW, T29.X, 32
>	VTX_READ_128 T44.XYZW, T16.X, 32
>	VTX_READ_128 T45.XYZW, T18.X, 0
>	VTX_READ_128 T11.XYZW, T11.X, 32
>	VTX_READ_128 T46.XYZW, T0.X, 32
>	VTX_READ_128 T47.XYZW, T17.X, 0
>	VTX_READ_128 T48.XYZW, T7.X, 16
>	VTX_READ_128 T49.XYZW, T29.X, 16
>	VTX_READ_128 T50.XYZW, T14.X, 0
>	VTX_READ_128 T10.XYZW, T10.X, 32
>	VTX_READ_128 T9.XYZW, T9.X, 32
>	VTX_READ_128 T51.XYZW, T8.X, 0
>	VTX_READ_128 T52.XYZW, T16.X, 16
>	Fetch clause starting at 0x68:
>	VTX_READ_128 T53.XYZW, T26.X, 0
>	VTX_READ_128 T54.XYZW, T6.X, 0
>	VTX_READ_128 T55.XYZW, T15.X, 32
>	VTX_READ_128 T56.XYZW, T13.X, 32
>	VTX_READ_128 T57.XYZW, T7.X, 0
>	VTX_READ_128 T29.XYZW, T29.X, 0
>	VTX_READ_128 T58.XYZW, T12.X, 32
>	VTX_READ_128 T17.XYZW, T17.X, 32
>	VTX_READ_128 T16.XYZW, T16.X, 0
>	VTX_READ_128 T15.XYZW, T15.X, 0
>	VTX_READ_128 T14.XYZW, T14.X, 32
>	VTX_READ_128 T59.XYZW, T8.X, 32
>	VTX_READ_128 T13.XYZW, T13.X, 0
>	VTX_READ_128 T60.XYZW, T26.X, 16
>	VTX_READ_128 T61.XYZW, T6.X, 16
>	VTX_READ_128 T12.XYZW, T12.X, 0
>	Fetch clause starting at 0x88:
>	VTX_READ_128 T7.XYZW, T18.X, 48
>	VTX_READ_128 T13.XYZW, T18.X, 32
>	VTX_READ_128 T15.XYZW, T26.X, 32
>	VTX_READ_128 T6.XYZW, T6.X, 32
>	ALU clause starting at 0x90:
>	  MULLO_INT * T0.Y, KC0[1].Z, T1.X,  
>	.loc	5 4 48 discriminator 4  ; ./generic/lib/workitem/get_global_id.cl:4:48
>	  ADD_INT * T0.W, T0.X, PS,  
>	  ADD_INT * T1.W, KC0[0].W, PV.W,  
>	  ADD_INT * T2.W, PV.W, KC0[0].W,  
>	  ADD_INT   T3.W, PV.W, KC0[0].W,  
>	  LSHL * T2.W, PV.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T0.X, KC0[2].Y, PS,  
>	  ADD_INT   T8.W, PV.W, KC0[0].W,  
>	  LSHL * T2.W, PV.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T11.X, KC0[2].Y, PS,  
>	  LSHL * T2.W, PV.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T8.X, KC0[2].Y, PV.W,  
>	  LSHL * T2.W, T0.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T9.X, KC0[2].Y, PV.W,  
>	  LSHL * T1.W, T1.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT * T10.X, KC0[2].Y, PV.W,  
>	ALU clause starting at 0xa5:
>	  ADD_INT * T8.W, T8.W, KC0[0].W,  
>	  ADD_INT * T9.W, PV.W, KC0[0].W,  
>	  ADD_INT * T10.W, PV.W, KC0[0].W,  
>	  ADD_INT   T11.W, PV.W, KC0[0].W,  
>	  LSHL * T10.W, PV.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T12.X, KC0[2].Y, PS,  
>	  LSHL * T10.W, PV.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T13.X, KC0[2].Y, PV.W,  
>	  ADD   T0.Z, T5.W, 0.0,  
>	  ADD_INT   T5.W, T11.W, KC0[0].W,  BS:VEC_120/SCL_212
>	  LSHL * T8.W, T8.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T14.X, KC0[2].Y, PS,  
>	  ADD_INT   T8.Z, PV.W, KC0[0].W,  
>	  ADD   T4.W, PV.Z, T4.W,  
>	  LSHL * T5.W, PV.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T15.X, KC0[2].Y, PS,  
>	  ADD   T3.W, PV.W, T3.W,  
>	  LSHL * T4.W, PV.Z, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T16.X, KC0[2].Y, PS,  
>	  ADD   T0.Z, PV.W, T2.W,  
>	  ADD_INT   T2.W, T8.Z, KC0[0].W,  
>	  LSHL * T3.W, T9.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T17.X, KC0[2].Y, PS,  
>	  ADD_INT   T8.Z, PV.W, KC0[0].W,  
>	  ADD   T1.W, PV.Z, T1.W,  
>	  ADD * T3.W, T7.Z, 0.0,  
>	ALU clause starting at 0xc5:
>	  ADD   T0.Z, T3.W, T6.Z,  
>	  ADD   T1.W, T1.W, T28.W,  BS:VEC_120/SCL_212
>	  ADD_INT * T3.W, T8.Z, KC0[0].W,  
>	  ADD_INT   T0.Y, PS, KC0[0].W,  
>	  ADD   T6.Z, PV.W, T27.W,  
>	  ADD   T1.W, PV.Z, T26.Z,  
>	  LSHL * T2.W, T2.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T29.X, KC0[2].Y, PS,  
>	  ADD   T8.Y, T7.X, 0.0,  
>	  ADD   T0.Z, PV.W, T25.Z,  
>	  ADD   T1.W, PV.Z, T24.W,  
>	  LSHL * T2.W, T8.Z, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T7.X, KC0[2].Y, PS,  
>	  ADD   T9.Y, PV.W, T23.W,  
>	  ADD   T0.Z, PV.Z, T22.Z,  
>	  ADD   T1.W, PV.Y, T6.X,  
>	  LSHL * T2.W, T3.W, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T6.X, KC0[2].Y, PS,  
>	  ADD   T8.Y, PV.W, T26.X,  
>	  ADD   T0.Z, PV.Z, T21.Z,  
>	  ADD   T1.W, PV.Y, T20.W,  
>	  LSHL * T2.W, T0.Y, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T26.X, KC0[2].Y, PS,  
>	  ADD   T6.Z, PV.W, T19.W,  
>	  ADD   T1.W, PV.Z, T18.Z,  
>	  ADD * T2.W, PV.Y, T25.X,  
>	ALU clause starting at 0xe3:
>	  ADD   T2.W, T2.W, T22.X,  
>	  ADD * T3.W, T40.Z, 0.0,  
>	  ADD_INT   T22.X, T0.Y, KC0[0].W,  
>	  ADD   T0.Y, PS, T39.Z,  
>	  ADD   T0.Z, PV.W, T21.X,  
>	  ADD   T1.W, T1.W, T38.Z,  BS:VEC_201
>	  ADD * T2.W, T6.Z, T37.W,  
>	  ADD   T21.X, PS, T36.W,  
>	  ADD   T8.Y, PV.W, T35.Z,  
>	  ADD   T0.Z, PV.Z, T18.X,  
>	  ADD   T1.W, PV.Y, T34.Z,  BS:VEC_021/SCL_122
>	  LSHL * T2.W, PV.X, literal.x,  
>	6(8.407791e-45), 0(0.000000e+00)
>	  ADD_INT   T18.X, KC0[2].Y, PS,  
>	  ADD   T0.Y, PV.W, T33.Z,  
>	  ADD   T0.Z, PV.Z, T38.X,  
>	  ADD   T1.W, PV.Y, T32.Z,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T31.W,  
>	ALU clause starting at 0xf5:
>	  ADD   T0.X, T2.W, T30.W,  
>	  ADD   T8.Y, T1.W, T52.Z,  BS:VEC_201
>	  ADD   T0.Z, T0.Z, T35.X,  BS:VEC_120/SCL_212
>	  ADD * T1.W, T0.Y, T51.Z,  BS:VEC_021/SCL_122
>	  ADD * T2.W, T9.W, 0.0,  
>	  ADD   T21.X, PV.W, T10.W,  
>	  ADD   T0.Y, T1.W, T50.Z,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, T0.Z, T32.X,  
>	  ADD   T1.W, T7.W, 0.0,  BS:VEC_201
>	  ADD * T2.W, T8.Y, T49.Z,  
>	  ADD   T22.X, PS, T48.Z,  
>	  ADD   T8.Y, PV.W, T6.W,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T52.X,  
>	  ADD   T1.W, PV.Y, T47.Z,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T46.W,  
>	ALU clause starting at 0x104:
>	  ADD   T7.X, T2.W, T11.W,  
>	  ADD   T0.Y, T1.W, T12.Z,  BS:VEC_201
>	  ADD * T0.Z, T0.Z, T49.X,  BS:VEC_120/SCL_212
>	  ADD   T1.W, T8.Y, T26.W,  
>	  ADD * T2.W, T22.X, T61.Z,  
>	  ADD   T8.X, PS, T60.Z,  
>	  ADD   T8.Y, PV.W, T25.W,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, T0.Z, T48.X,  
>	  ADD   T1.W, T0.Y, T13.Z,  BS:VEC_021/SCL_122
>	  ADD * T2.W, T7.X, T59.W,  
>	  ADD   T7.X, PS, T14.W,  
>	  ADD   T0.Y, T40.Y, 0.0,  
>	  ADD   T6.Z, T40.X, 0.0,  
>	  ADD   T1.W, PV.W, T15.Z,  
>	  ADD * T2.W, PV.Z, T61.X,  
>	  ADD   T21.X, PS, T60.X,  
>	  ADD   T40.Y, PV.W, T16.Z,  
>	  ADD   T0.Z, PV.Z, T39.X,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T39.Y,  
>	  ADD * T2.W, PV.X, T17.W,  
>	  ADD   T7.X, PS, T58.W,  
>	  ADD   T0.Y, T40.W, 0.0,  
>	  ADD   T6.Z, PV.W, T34.Y,  
>	  ADD   T1.W, PV.Z, T34.X,  
>	  ADD * T2.W, PV.Y, T29.Z,  
>	  ADD   T22.X, PS, T57.Z,  
>	  ADD   T34.Y, PV.W, T33.X,  
>	  ADD   T0.Z, PV.Z, T33.Y,  
>	  ADD   T1.W, PV.Y, T39.W,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T56.W,  
>	  ADD   T7.X, PS, T55.W,  
>	  ADD   T0.Y, PV.W, T34.W,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T51.Y,  
>	  ADD   T1.W, PV.Y, T51.X,  
>	  ADD * T2.W, PV.X, T54.Z,  
>	  ADD   T22.X, PS, T53.Z,  
>	  ADD   T33.Y, PV.W, T50.X,  
>	  ADD   T0.Z, PV.Z, T50.Y,  
>	  ADD   T1.W, PV.Y, T33.W,  
>	  ADD * T2.W, T5.Y, 0.0,  
>	  ADD   T25.X, T7.Y, 0.0,  
>	  ADD   T0.Y, PS, T4.Y,  
>	  ADD   T6.Z, PV.W, T51.W,  
>	  ADD   T1.W, PV.Z, T47.Y,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.Y, T47.X,  
>	  ADD   T12.X, PS, T12.X,  
>	  ADD   T4.Y, PV.W, T12.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T50.W,  
>	  ADD   T1.W, PV.Y, T3.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T6.Y,  
>	  ADD   T25.X, PS, T26.Y,  
>	  ADD   T0.Y, PV.W, T2.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T47.W,  
>	  ADD   T1.W, PV.Y, T13.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T13.X,  
>	  ADD   T12.X, PS, T15.X,  
>	  ADD   T2.Y, PV.W, T15.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T12.W,  
>	  ADD   T1.W, PV.Y, T1.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T25.Y,  
>	  ADD   T13.X, PS, T22.Y,  
>	  ADD   T0.Y, PV.W, T28.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T13.W,  
>	  ADD   T1.W, PV.Y, T16.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T16.X,  
>	  ADD   T12.X, PS, T29.X,  
>	  ADD   T1.Y, PV.W, T29.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T15.W,  
>	  ADD   T1.W, PV.Y, T27.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T21.Y,  
>	  ADD   T13.X, PS, T18.Y,  
>	  ADD   T0.Y, PV.W, T24.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T16.W,  
>	  ADD   T1.W, PV.Y, T57.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T57.X,  
>	  ADD   T12.X, PS, T54.X,  
>	  ADD   T1.Y, PV.W, T54.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T29.W,  
>	  ADD   T1.W, PV.Y, T23.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T38.Y,  
>	  ADD   T13.X, PS, T35.Y,  
>	  ADD   T0.Y, PV.W, T20.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T57.W,  
>	  ADD   T1.W, PV.Y, T53.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T53.X,  
>	  ADD   T12.X, PS, T45.X,  
>	  ADD   T1.Y, PV.W, T45.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T54.W,  
>	  ADD   T1.W, PV.Y, T19.Y,  BS:VEC_102/SCL_221
>	  ADD * T2.W, PV.X, T32.Y,  
>	  ADD   T13.X, PS, T52.Y,  
>	  ADD   T0.Y, PV.W, T37.Y,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Z, T53.W,  
>	  ADD   T1.W, PV.X, PV.Y,  
>	  ADD * T2.W, T22.X, T45.Z,  
>	  ADD   T12.X, PS, PV.W,  
>	  ADD   T1.Y, PV.Z, T45.W,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Y, T36.Y,  
>	  ADD   T1.W, PV.X, T49.Y,  BS:VEC_021/SCL_122
>	  ADD * T2.W, T7.X, T44.W,  
>	  ADD   T7.X, PS, T43.W,  
>	  ADD   T0.Y, PV.W, T48.Y,  
>	  ADD   T0.Z, PV.Z, T31.Y,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, PV.X,  
>	  ADD * T2.W, T21.X, T42.X,  
>	  ADD   T12.X, PS, PV.W,  
>	  ADD   T1.Y, PV.Z, T30.Y,  
>	  ADD   T0.Z, PV.Y, T61.Y,  BS:VEC_102/SCL_221
>	  ADD   T1.W, PV.X, T41.W,  BS:VEC_021/SCL_122
>	  ADD * T2.W, T8.Y, T22.W,  
>	ALU clause starting at 0x172:
>	  ADD   T8.Z, T2.W, T21.W,  
>	  ADD   T2.W, T9.Y, 0.0,  
>	  ADD * T3.W, T9.X, 0.0,  
>	  ADD   T9.X, T9.Z, 0.0,  
>	  ADD   T0.Y, PS, T10.X,  
>	  ADD   T9.Z, PV.W, T10.Y,  
>	  ADD   T2.W, PV.Z, T18.W,  BS:VEC_102/SCL_221
>	  ADD * T1.W, T1.W, T6.W,  
>	  ADD   T10.X, PS, T15.W,  
>	  ADD   T2.Y, PV.W, T38.W,  BS:VEC_021/SCL_122
>	  ADD   T8.Z, PV.Z, T46.Y,  
>	  ADD   T1.W, PV.Y, T46.X,  
>	  ADD * T2.W, PV.X, T10.Z,  
>	  ADD   T5.X, T5.X, 0.0,  
>	  ADD   T0.Y, PS, T46.Z,  
>	  ADD   T9.Z, PV.W, T11.X,  
>	  ADD   T1.W, PV.Z, T11.Y,  
>	  ADD * T2.W, PV.Y, T35.W,  
>	  ADD   T9.X, PS, T32.W,  
>	  ADD   T2.Y, PV.W, T59.Y,  
>	  ADD   T8.Z, PV.Z, T59.X,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T11.Z,  
>	  ADD * T2.W, PV.X, T4.X,  
>	  ADD   T4.X, T5.Z, 0.0,  
>	  ADD   T0.Y, PS, T3.X,  
>	  ADD   T5.Z, PV.W, T59.Z,  
>	  ADD   T1.W, PV.Z, T14.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.Y, T14.Y,  
>	  ADD   T3.X, PS, T17.Y,  
>	  ADD   T2.Y, PV.W, T17.X,  
>	  ADD   T5.Z, PV.Z, T14.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T2.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T4.Z,  
>	  ADD   T2.X, PS, T3.Z,  
>	  ADD   T0.Y, PV.W, T1.X,  
>	  ADD   T3.Z, PV.Z, T17.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T58.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T58.Y,  
>	  ADD   T1.X, PS, T56.Y,  
>	  ADD   T2.Y, PV.W, T56.X,  
>	  ADD   T3.Z, PV.Z, T58.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T28.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T2.Z,  
>	  ADD   T2.X, PS, T1.Z,  
>	  ADD   T0.Y, PV.W, T27.X,  
>	  ADD   T1.Z, PV.Z, T56.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T55.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T55.Y,  
>	  ADD   T1.X, PS, T44.Y,  
>	  ADD   T2.Y, PV.W, T44.X,  
>	  ADD   T1.Z, PV.Z, T55.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T24.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T28.Z,  
>	  ADD   T2.X, PS, T27.Z,  
>	  ADD   T0.Y, PV.W, T23.X,  
>	  ADD   T1.Z, PV.Z, T44.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T43.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T43.Y,  
>	  ADD   T1.X, PS, T41.Y,  
>	  ADD   T2.Y, PV.W, T41.X,  
>	  ADD   T1.Z, PV.Z, T43.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T20.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T24.Z,  
>	  ADD   T2.X, PS, T23.Z,  
>	  ADD   T0.Y, PV.W, T19.X,  
>	  ADD   T1.Z, PV.Z, T41.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T6.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T6.Y,  
>	  ADD   T1.X, PS, T15.Y,  
>	  ADD   T2.Y, PV.W, T15.X,  
>	  ADD   T1.Z, PV.Z, T6.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T37.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T20.Z,  
>	  ADD   T2.X, PS, T19.Z,  
>	  ADD   T0.Y, PV.W, T36.X,  
>	  ADD   T1.Z, PV.Z, T15.Z,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, T13.X,  BS:VEC_021/SCL_122
>	  ADD * T2.W, PV.X, T13.Y,  
>	  ADD   T1.X, PV.W, PS,  
>	  ADD   T2.Y, PV.Z, T13.Z,  
>	  ADD   T1.Z, PV.Y, T31.X,  
>	  ADD   T1.W, PV.X, T37.Z,  BS:VEC_021/SCL_122
>	  ADD * T2.W, T9.X, T52.W,  
>	  ADD   T2.X, PS, T49.W,  BS:VEC_021/SCL_122
>	  ADD   T0.Y, PV.W, T36.Z,  
>	  ADD   T1.Z, PV.Z, T30.X,  
>	  ADD   T1.W, PV.Y, PV.X,  
>	  ADD * T2.W, T10.X, T13.W,  
>	  ADD   T1.X, PS, PV.W,  
>	  ADD   T2.Y, PV.Z, T7.X,  
>	  ADD   T1.Z, PV.Y, T31.Z,  
>	  ADD   T1.W, PV.X, T48.W,  
>	  ADD * T2.W, T0.Z, T60.Y,  
>	  ADD   T2.X, PS, T42.Y,  BS:VEC_102/SCL_221
>	  ADD   T0.Y, PV.W, T61.W,  
>	  ADD   T0.Z, PV.Z, T30.Z,  
>	  ADD   T1.W, PV.Y, PV.X,  
>	  ADD * T2.W, T1.Y, T7.Y,  
>	  ADD   T1.X, PS, PV.W,  
>	  ADD   T1.Y, PV.Z, T7.Z,  BS:VEC_021/SCL_122
>	  ADD   T0.Z, PV.Y, T60.W,  
>	  ADD   T1.W, PV.X, T12.X,  
>	  ADD * T2.W, T8.X, T42.Z,  
>	  ADD   T0.Y, PS, PV.W,  
>	  ADD   T0.Z, PV.Z, T42.W,  BS:VEC_021/SCL_122
>	  ADD   T1.W, PV.Y, PV.X,  
>	  ADD * T2.W, T0.X, T7.W,  
>	  LSHL   T1.Z, T0.W, literal.x,  
>	  ADD   T0.W, PS, PV.W,  
>	  ADD * T1.W, PV.Z, PV.Y,  
>	2(2.802597e-45), 0(0.000000e+00)
>	  ADD   T0.X, PS, PV.W,  
>	  ADD_INT * T0.W, KC0[2].Z, PV.Z,  
>	  LSHR * T1.X, PV.W, literal.x,  
>	2(2.802597e-45), 0(0.000000e+00)
>.Lfunc_end9:
>	.size	global_bandwidth_v16_global_offset, .Lfunc_end9-global_bandwidth_v16_global_offset
>

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Attachments on bug 96296: 124221 | 124375 | 130914

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