Attachment 124397 Details for Bug 96397 – [PATCH] Initializing CR6A, CR6B, and CR6C when mode setting is done

[patch] [PATCH] Initializing CR6A, CR6B, and CR6C when mode setting is done

Proposed-0001-Initializing-CR6A-CR6B-and-CR6C-when-mode-setting-is.patch (text/plain), 5.89 KB, created by Kevin Brace on 2016-06-08 04:38:34 UTC

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Creator: Kevin Brace

Created: 2016-06-08 04:38:34 UTC

Size: 5.89 KB

patch

obsolete

>From f855107338d89e28dcaca8de328a63eb1d4cf076 Mon Sep 17 00:00:00 2001
>From: Kevin Brace <"Kevin's e-mail address">
>Date: Tue, 7 Jun 2016 21:19:52 -0700
>Subject: [PATCH] Initializing CR6A, CR6B, and CR6C when mode setting is done
>
>Not all the register fields of CR6A (3X5.6A), CR6B (3X5.6B), and
>CR6C (3X5.6C) were being initialized, and as a result, specifying
>the availability of TV out in the BIOS setup will lead to analog out
>(VGA) not working properly. This bug was observed with VIA Embedded
>EPIA-M mainboard (CLE266 chipset with VT1622 TV encoder).
>
>Signed-off-by: Xavier Bachelot <"Xavier's e-mail address">
>Signed-off-by: Kevin Brace <"Kevin's e-mail address">
>---
> src/via_display.c |   90 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 90 insertions(+)
>
>diff --git a/src/via_display.c b/src/via_display.c
>index 957d02f..7dd00d4 100644
>--- a/src/via_display.c
>+++ b/src/via_display.c
>@@ -311,6 +311,9 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
>     temp = hwp->readCrtc(hwp, 0x36);
>     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                         "CR36: 0x%02X\n", temp));
>+    temp = hwp->readCrtc(hwp, 0x6B);
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>+                        "CR6B: 0x%02X\n", temp));
> #endif
> 
>     /* Be careful with 3C5.15[5] - Wrap Around Disable.
>@@ -493,6 +496,11 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
>      *               1: Enable */
>     ViaCrtcMask(hwp, 0x36, 0x01, 0x01);
> 
>+    /* 3X5.6B[3] - Simultaneous Display Enable
>+     *             0: Disable
>+     *             1: Enable */
>+    ViaCrtcMask(hwp, 0x6B, 0x00, 0x08);
>+
>     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                         "Exiting viaIGAInitCommon.\n"));
> }
>@@ -524,6 +532,12 @@ viaIGA1Init(ScrnInfoPtr pScrn)
>     temp = hwp->readCrtc(hwp, 0x33);
>     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                         "CR33: 0x%02X\n", temp));
>+    temp = hwp->readCrtc(hwp, 0x6B);
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>+                        "CR6B: 0x%02X\n", temp));
>+    temp = hwp->readCrtc(hwp, 0x6C);
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>+                        "CR6C: 0x%02X\n", temp));
> #endif
> 
>     /* 3C5.1B[7:6] - Secondary Display Engine (Gated Clock <LCK>)
>@@ -611,6 +625,27 @@ viaIGA1Init(ScrnInfoPtr pScrn)
>      *               111: Shift to early time by 2 characters */
>     ViaCrtcMask(hwp, 0x33, 0x00, 0xCF);
> 
>+    /* TV out uses division by 2 mode.
>+     * Other devices like analog (VGA), DVI, flat panel, etc.,
>+     * use normal mode. */
>+    /* 3X5.6B[7:6] - First Display Channel Clock Mode Selection
>+     *               0x: Normal
>+     *               1x: Division by 2 */
>+    ViaCrtcMask(hwp, 0x6B, 0x00, 0xC0);
>+
>+    /* 3X5.6C[7:5] - VCK PLL Reference Clock Source Selection
>+     *               000: From XI pin
>+     *               001: From TVXI
>+     *               01x: From TVPLL
>+     *               100: Reserved
>+     *               101: DVP1TVCLKR
>+     *               110: CAP0 Clock
>+     *               111: CAP1 Clock
>+     * 3X5.6C[4]   - VCK Source Selection
>+     *               0: VCK PLL output clock
>+     *               1: VCK PLL reference clock */
>+    ViaCrtcMask(hwp, 0x6C, 0x00, 0xF0);
>+
>     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                         "Exiting viaIGA1Init.\n"));
> }
>@@ -1693,6 +1728,15 @@ viaIGA2Init(ScrnInfoPtr pScrn)
>     temp = hwp->readSeq(hwp, 0x2D);
>     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                         "SR2D: 0x%02X\n", temp));
>+    temp = hwp->readCrtc(hwp, 0x6A);
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>+                        "CR6A: 0x%02X\n", temp));
>+    temp = hwp->readCrtc(hwp, 0x6B);
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>+                        "CR6B: 0x%02X\n", temp));
>+    temp = hwp->readCrtc(hwp, 0x6C);
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>+                        "CR6C: 0x%02X\n", temp));
> #endif
> 
>     /* 3C5.1B[7:6] - Secondary Display Engine (Gated Clock <LCK>)
>@@ -1729,6 +1773,52 @@ viaIGA2Init(ScrnInfoPtr pScrn)
>      *               11: PLL on/off according to the PMS */
>     ViaSeqMask(hwp, 0x2D, 0x0C, 0x0C);
> 
>+    /* 3X5.6A[7] - Second Display Channel Enable
>+     *             0: Disable
>+     *             1: Enable
>+     * 3X5.6A[6] - Second Display Channel Reset
>+     *             0: Reset
>+     * 3X5.6A[5] - Second Display 8/6 Bits LUT
>+     *             0: 6-bit
>+     *             1: 8-bit
>+     * 3X5.6A[4] - Horizontal Count by 2
>+     *             0: Disable
>+     *             1: Enable
>+     * 3X5.6A[1] - LCD Gamma Enable
>+     *             0: Disable
>+     *             1: Enable
>+     * 3X5.6A[0] - LCD Pre-fetch Mode Enable
>+     *             0: Disable
>+     *             1: Enable */
>+    ViaCrtcMask(hwp, 0x6A, 0x80, 0xB3);
>+
>+    /* TV out uses division by 2 mode.
>+     * Other devices like analog (VGA), DVI, flat panel, etc.,
>+     * use normal mode. */
>+    /* 3X5.6B[5:4] - Second Display Channel Clock Mode Selection
>+     *               0x: Normal
>+     *               1x: Division by 2
>+     * 3X5.6B[2]   - IGA2 Screen Off
>+     *               0: Normal
>+     *               1: Screen off
>+     * 3X5.6B[1]   - IGA2 Screen Off Selection Method
>+     *               0: IGA2 Screen off
>+     *               1: IGA1 Screen off */
>+    ViaCrtcMask(hwp, 0x6B, 0x00, 0x36);
>+
>+    /* 3X5.6C[3:1] - LCDCK PLL Reference Clock Source Selection
>+     *               000: From XI pin
>+     *               001: From TVXI
>+     *               01x: From TVPLL
>+     *               100: Reserved
>+     *               101: DVP1TVCLKR
>+     *               110: CAP0 Clock
>+     *               111: CAP1 Clock
>+     * 3X5.6C[0]   - LCDCK Source Selection
>+     *               0: LCDCK PLL output clock
>+     *               1: LCDCK PLL reference clock */
>+    ViaCrtcMask(hwp, 0x6C, 0x00, 0x0F);
>+
>     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                         "Exiting viaIGA2Init.\n"));
> }
>-- 
>1.7.9.5
>

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Attachments on bug 96397: 124341 | 124342 | 124343 | 124344 | 124345 | 124346 | 124393 | 124397 | 124430

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