Attachment 124747 Details for Bug 86365 – dmesg_bxt

dmesg_bxt

dmesg (text/plain), 1008.01 KB, created by Humberto Israel Perez Rodriguez on 2016-06-28 00:10:06 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Humberto Israel Perez Rodriguez

Created: 2016-06-28 00:10:06 UTC

Size: 1008.01 KB

patch

obsolete

>[    0.000000] Linux version 4.7.0-rc4-nightly+ (jenkins@vanaheimr) (gcc version 4.8.4 (Ubuntu 4.8.4-2ubuntu1~14.04.3) ) #2 SMP Mon Jun 27 02:07:11 CEST 2016
>[    0.000000] Command line: vmlinuz root=/dev/sda2 initrd=initrd.img idle=halt log_buf_len=4M i915.enable_rc6=1 i915.preliminary_hw_support=1 drm.debug=0xe i915.enable_guc_submission=1 acpi=off
>[    0.000000] KERNEL supported cpus:
>[    0.000000]   Intel GenuineIntel
>[    0.000000]   AMD AuthenticAMD
>[    0.000000]   Centaur CentaurHauls
>[    0.000000] x86/fpu: xstate_offset[3]:  960, xstate_sizes[3]:   64
>[    0.000000] x86/fpu: xstate_offset[4]: 1024, xstate_sizes[4]:   64
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>[    0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 1088 bytes, using 'standard' format.
>[    0.000000] x86/fpu: Using 'eager' FPU context switches.
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000effffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000f000000-0x0000000012151fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000012152000-0x0000000077ff8fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000077ff9000-0x0000000079da8fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000079da9000-0x0000000079e08fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x0000000079e09000-0x0000000079e38fff] ACPI data
>[    0.000000] BIOS-e820: [mem 0x0000000079e39000-0x000000007ac2bfff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007ac2c000-0x000000007ac2cfff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000007ac2d000-0x000000007ac56fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007ac57000-0x000000007affffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000e3ffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000047fffffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] efi: EFI v2.50 by EDK II
>[    0.000000] efi:  ACPI=0x79e38000  ACPI 2.0=0x79e38014  ESRT=0x79d74000  SMBIOS=0x7815a000  SMBIOS 3.0=0x78158000  PROP=0x7a06c920 
>[    0.000000] efi: requested map not found.
>[    0.000000] esrt: ESRT header is not in the memory map.
>[    0.000000] SMBIOS 3.0.0 present.
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] e820: last_pfn = 0x480000 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: uncachable
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 0000000000 mask 7F80000000 write-back
>[    0.000000]   1 base 007C000000 mask 7FFC000000 uncachable
>[    0.000000]   2 base 007B000000 mask 7FFF000000 uncachable
>[    0.000000]   3 base 0100000000 mask 7F00000000 write-back
>[    0.000000]   4 base 0200000000 mask 7F00000000 write-back
>[    0.000000]   5 base 0300000000 mask 7F00000000 write-back
>[    0.000000]   6 base 0400000000 mask 7F80000000 write-back
>[    0.000000]   7 base 00FF800000 mask 70FF800000 write-combining
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- WT  
>[    0.000000] e820: last_pfn = 0x7b000 max_arch_pfn = 0x400000000
>[    0.000000] Scanning 1 areas for low memory corruption
>[    0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] BRK [0x02013000, 0x02013fff] PGTABLE
>[    0.000000] BRK [0x02014000, 0x02014fff] PGTABLE
>[    0.000000] BRK [0x02015000, 0x02015fff] PGTABLE
>[    0.000000] BRK [0x02016000, 0x02016fff] PGTABLE
>[    0.000000] BRK [0x02017000, 0x02017fff] PGTABLE
>[    0.000000] BRK [0x02018000, 0x02018fff] PGTABLE
>[    0.000000] log_buf_len: 4194304 bytes
>[    0.000000] early log buf free: 257444(98%)
>[    0.000000] RAMDISK: [mem 0x72da8000-0x74ba0fff]
>[    0.000000] No NUMA configuration found
>[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000047fffffff]
>[    0.000000] NODE_DATA(0) allocated [mem 0x47fbfa000-0x47fbfdfff]
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000047fffffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>[    0.000000]   node   0: [mem 0x0000000000059000-0x000000000009dfff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x000000000effffff]
>[    0.000000]   node   0: [mem 0x0000000012152000-0x0000000077ff8fff]
>[    0.000000]   node   0: [mem 0x0000000079e39000-0x000000007ac2bfff]
>[    0.000000]   node   0: [mem 0x000000007ac57000-0x000000007affffff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000047fffffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000047fffffff]
>[    0.000000] On node 0 totalpages: 4153311
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 21 pages reserved
>[    0.000000]   DMA zone: 3996 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 7490 pages used for memmap
>[    0.000000]   DMA32 zone: 479299 pages, LIFO batch:31
>[    0.000000]   Normal zone: 57344 pages used for memmap
>[    0.000000]   Normal zone: 3670016 pages, LIFO batch:31
>[    0.000000] Reserving Intel graphics memory at 0x000000007c000000-0x000000007fffffff
>[    0.000000] SFI: Simple Firmware Interface v0.81 http://simplefirmware.org
>[    0.000000] smpboot: Allowing 1 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0f000000-0x12151fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x77ff9000-0x79da8fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x79da9000-0x79e08fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x79e09000-0x79e38fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ac2c000-0x7ac2cfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ac2d000-0x7ac56fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x80000000-0xdfffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xe3ffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe4000000-0xfed00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xffffffff]
>[    0.000000] e820: [mem 0x80000000-0xdfffffff] available for PCI devices
>[    0.000000] Booting paravirtualized kernel on bare hardware
>[    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
>[    0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:1 nr_node_ids:1
>[    0.000000] percpu: Embedded 35 pages/cpu @ffff88047f800000 s102744 r8192 d32424 u2097152
>[    0.000000] pcpu-alloc: s102744 r8192 d32424 u2097152 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 
>[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 4088392
>[    0.000000] Policy zone: Normal
>[    0.000000] Kernel command line: vmlinuz root=/dev/sda2 initrd=initrd.img idle=halt log_buf_len=4M i915.enable_rc6=1 i915.preliminary_hw_support=1 drm.debug=0xe i915.enable_guc_submission=1 acpi=off
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
>[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
>[    0.000000] Memory: 16188436K/16613244K available (7829K kernel code, 1311K rwdata, 3620K rodata, 1508K init, 1308K bss, 424808K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] 	Build-time adjustment of leaf fanout to 64.
>[    0.000000] 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
>[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=1
>[    0.000000] NR_IRQS:16640 nr_irqs:32 16
>[    0.000000] 	Offload RCU callbacks from all CPUs
>[    0.000000] 	Offload RCU callbacks from CPUs: 0.
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] tsc: Fast TSC calibration using PIT
>[    0.000000] tsc: Detected 4411.738 MHz processor
>[    0.000025] Calibrating delay loop (skipped), value calculated using timer frequency.. 8823.47 BogoMIPS (lpj=17646952)
>[    0.000030] pid_max: default: 32768 minimum: 301
>[    0.000258] Security Framework initialized
>[    0.000261] Yama: becoming mindful.
>[    0.000267] AppArmor: AppArmor initialized
>[    0.000833] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
>[    0.003178] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.004230] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.004243] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.004420] CPU: Physical Processor ID: 0
>[    0.004424] CPU: Processor Core ID: 0
>[    0.004432] mce: CPU supports 7 MCE banks
>[    0.004443] CPU0: Thermal monitoring enabled (TM1)
>[    0.004466] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0
>[    0.004468] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
>[    0.010412] Freeing SMP alternatives memory: 32K (ffffffff81ec2000 - ffffffff81eca000)
>[    0.014627] ftrace: allocating 31359 entries in 123 pages
>[    0.033514] smpboot: Max logical packages: 1
>[    0.033520] smpboot: weird, boot CPU (#0) not listed by the BIOS
>[    0.033522] smpboot: SMP motherboard not detected
>[    0.033523] smpboot: SMP disabled
>[    0.033529] x2apic: IRQ remapping doesn't support X2APIC mode
>[    0.033550] TSC deadline timer enabled
>[    0.033552] Performance Events: PEBS fmt3+, 32-deep LBR, Goldmont events, full-width counters, Intel PMU driver.
>[    0.033564] ... version:                4
>[    0.033565] ... bit width:              48
>[    0.033567] ... generic registers:      4
>[    0.033569] ... value mask:             0000ffffffffffff
>[    0.033571] ... max period:             0000ffffffffffff
>[    0.033573] ... fixed-purpose events:   3
>[    0.033574] ... event mask:             000000070000000f
>[    0.033973] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
>[    0.033989] x86: Booted up 1 node, 1 CPUs
>[    0.033991] smpboot: Total of 1 processors activated (8823.47 BogoMIPS)
>[    0.034337] devtmpfs: initialized
>[    0.034378] x86/mm: Memory block size: 128MB
>[    0.038130] evm: security.selinux
>[    0.038133] evm: security.SMACK64
>[    0.038135] evm: security.ima
>[    0.038136] evm: security.capability
>[    0.038196] PM: Registering ACPI NVS region [mem 0x79da9000-0x79e08fff] (393216 bytes)
>[    0.038203] PM: Registering ACPI NVS region [mem 0x7ac2c000-0x7ac2cfff] (4096 bytes)
>[    0.038235] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
>[    0.038254] pinctrl core: initialized pinctrl subsystem
>[    0.038334] RTC time:  0:00:24, date: 06/28/16
>[    0.039028] NET: Registered protocol family 16
>[    0.039134] cpuidle: using governor ladder
>[    0.039136] cpuidle: using governor menu
>[    0.039233] PCI: Using configuration type 1 for base access
>[    0.040119] HugeTLB registered 1 GB page size, pre-allocated 0 pages
>[    0.040122] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[    0.040245] ACPI: Interpreter disabled.
>[    0.040291] vgaarb: loaded
>[    0.040380] SCSI subsystem initialized
>[    0.040399] libata version 3.00 loaded.
>[    0.040422] usbcore: registered new interface driver usbfs
>[    0.040429] usbcore: registered new interface driver hub
>[    0.040436] usbcore: registered new device driver usb
>[    0.040509] PCI: Probing PCI hardware
>[    0.040512] PCI: root bus 00: using default resources
>[    0.040513] PCI: Probing PCI hardware (bus 00)
>[    0.040531] PCI host bridge to bus 0000:00
>[    0.040535] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
>[    0.040537] pci_bus 0000:00: root bus resource [mem 0x00000000-0x7fffffffff]
>[    0.040540] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
>[    0.040548] pci 0000:00:00.0: [8086:5af0] type 00 class 0x060000
>[    0.040600] pci 0000:00:02.0: [8086:5a84] type 00 class 0x030000
>[    0.040606] pci 0000:00:02.0: reg 0x10: [mem 0x90000000-0x90ffffff 64bit]
>[    0.040610] pci 0000:00:02.0: reg 0x18: [mem 0x80000000-0x8fffffff 64bit pref]
>[    0.040613] pci 0000:00:02.0: reg 0x20: [io  0x2000-0x203f]
>[    0.040644] vgaarb: setting as boot device: PCI:0000:00:02.0
>[    0.040647] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
>[    0.040656] pci 0000:00:03.0: [8086:5a88] type 00 class 0x048000
>[    0.040661] pci 0000:00:03.0: reg 0x10: [mem 0x91000000-0x91ffffff 64bit]
>[    0.040710] pci 0000:00:0e.0: [8086:5a98] type 00 class 0x040300
>[    0.040718] pci 0000:00:0e.0: reg 0x10: [mem 0x92310000-0x92313fff 64bit]
>[    0.040732] pci 0000:00:0e.0: reg 0x20: [mem 0x92000000-0x920fffff 64bit]
>[    0.040753] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold
>[    0.040784] pci 0000:00:0f.0: [8086:5a9a] type 00 class 0x078000
>[    0.040797] pci 0000:00:0f.0: reg 0x10: [mem 0x92318000-0x92318fff 64bit]
>[    0.040834] pci 0000:00:0f.0: PME# supported from D3hot
>[    0.040869] pci 0000:00:11.0: [8086:5aa2] type 00 class 0x005007
>[    0.040879] pci 0000:00:11.0: reg 0x10: [mem 0x92314000-0x92315fff 64bit]
>[    0.040885] pci 0000:00:11.0: reg 0x18: [mem 0x9231b000-0x9231bfff 64bit]
>[    0.040933] pci 0000:00:12.0: [8086:5ae3] type 00 class 0x010601
>[    0.040939] pci 0000:00:12.0: reg 0x10: [mem 0x92316000-0x92317fff]
>[    0.040943] pci 0000:00:12.0: reg 0x14: [mem 0x92342000-0x923420ff]
>[    0.040946] pci 0000:00:12.0: reg 0x18: [io  0x2080-0x2087]
>[    0.040949] pci 0000:00:12.0: reg 0x1c: [io  0x2088-0x208b]
>[    0.040953] pci 0000:00:12.0: reg 0x20: [io  0x2060-0x207f]
>[    0.040956] pci 0000:00:12.0: reg 0x24: [mem 0x92340000-0x923407ff]
>[    0.040972] pci 0000:00:12.0: PME# supported from D3hot
>[    0.040999] pci 0000:00:13.0: [8086:5ada] type 01 class 0x060400
>[    0.041023] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold
>[    0.041061] pci 0000:00:14.0: [8086:5ad7] type 01 class 0x060400
>[    0.041091] pci 0000:00:14.0: PME# supported from D0 D3hot D3cold
>[    0.041133] pci 0000:00:15.0: [8086:5aa8] type 00 class 0x0c0330
>[    0.041141] pci 0000:00:15.0: reg 0x10: [mem 0x92300000-0x9230ffff 64bit]
>[    0.041166] pci 0000:00:15.0: PME# supported from D3hot D3cold
>[    0.041202] pci 0000:00:16.0: [8086:5aac] type 00 class 0x118000
>[    0.041211] pci 0000:00:16.0: reg 0x10: [mem 0x9231c000-0x9231cfff 64bit]
>[    0.041216] pci 0000:00:16.0: reg 0x18: [mem 0x9231d000-0x9231dfff 64bit]
>[    0.041260] pci 0000:00:16.1: [8086:5aae] type 00 class 0x118000
>[    0.041269] pci 0000:00:16.1: reg 0x10: [mem 0x9231e000-0x9231efff 64bit]
>[    0.041275] pci 0000:00:16.1: reg 0x18: [mem 0x9231f000-0x9231ffff 64bit]
>[    0.041319] pci 0000:00:16.2: [8086:5ab0] type 00 class 0x118000
>[    0.041328] pci 0000:00:16.2: reg 0x10: [mem 0x92320000-0x92320fff 64bit]
>[    0.041334] pci 0000:00:16.2: reg 0x18: [mem 0x92321000-0x92321fff 64bit]
>[    0.041380] pci 0000:00:16.3: [8086:5ab2] type 00 class 0x118000
>[    0.041389] pci 0000:00:16.3: reg 0x10: [mem 0x92322000-0x92322fff 64bit]
>[    0.041394] pci 0000:00:16.3: reg 0x18: [mem 0x92323000-0x92323fff 64bit]
>[    0.041444] pci 0000:00:17.0: [8086:5ab4] type 00 class 0x118000
>[    0.041454] pci 0000:00:17.0: reg 0x10: [mem 0x92324000-0x92324fff 64bit]
>[    0.041459] pci 0000:00:17.0: reg 0x18: [mem 0x92325000-0x92325fff 64bit]
>[    0.041504] pci 0000:00:17.1: [8086:5ab6] type 00 class 0x118000
>[    0.041513] pci 0000:00:17.1: reg 0x10: [mem 0x92326000-0x92326fff 64bit]
>[    0.041519] pci 0000:00:17.1: reg 0x18: [mem 0x92327000-0x92327fff 64bit]
>[    0.041578] pci 0000:00:17.2: [8086:5ab8] type 00 class 0x118000
>[    0.041589] pci 0000:00:17.2: reg 0x10: [mem 0x92328000-0x92328fff 64bit]
>[    0.041594] pci 0000:00:17.2: reg 0x18: [mem 0x92329000-0x92329fff 64bit]
>[    0.041641] pci 0000:00:17.3: [8086:5aba] type 00 class 0x118000
>[    0.041650] pci 0000:00:17.3: reg 0x10: [mem 0x9232a000-0x9232afff 64bit]
>[    0.041656] pci 0000:00:17.3: reg 0x18: [mem 0x9232b000-0x9232bfff 64bit]
>[    0.041706] pci 0000:00:18.0: [8086:5abc] type 00 class 0x118000
>[    0.041714] pci 0000:00:18.0: reg 0x10: [mem 0x9232c000-0x9232cfff 64bit]
>[    0.041721] pci 0000:00:18.0: reg 0x18: [mem 0x9232d000-0x9232dfff 64bit]
>[    0.041766] pci 0000:00:18.1: [8086:5abe] type 00 class 0x118000
>[    0.041775] pci 0000:00:18.1: reg 0x10: [mem 0x9232e000-0x9232efff 64bit]
>[    0.041781] pci 0000:00:18.1: reg 0x18: [mem 0x9232f000-0x9232ffff 64bit]
>[    0.041827] pci 0000:00:18.2: [8086:5ac0] type 00 class 0x118000
>[    0.041836] pci 0000:00:18.2: reg 0x10: [mem 0x92330000-0x92330fff 64bit]
>[    0.041841] pci 0000:00:18.2: reg 0x18: [mem 0x92331000-0x92331fff 64bit]
>[    0.041885] pci 0000:00:18.3: [8086:5aee] type 00 class 0x118000
>[    0.041894] pci 0000:00:18.3: reg 0x10: [mem 0x92332000-0x92332fff 64bit]
>[    0.041899] pci 0000:00:18.3: reg 0x18: [mem 0x92333000-0x92333fff 64bit]
>[    0.041949] pci 0000:00:19.0: [8086:5ac2] type 00 class 0x118000
>[    0.041958] pci 0000:00:19.0: reg 0x10: [mem 0x92334000-0x92334fff 64bit]
>[    0.041963] pci 0000:00:19.0: reg 0x18: [mem 0x92335000-0x92335fff 64bit]
>[    0.042007] pci 0000:00:19.1: [8086:5ac4] type 00 class 0x118000
>[    0.042016] pci 0000:00:19.1: reg 0x10: [mem 0x92336000-0x92336fff 64bit]
>[    0.042021] pci 0000:00:19.1: reg 0x18: [mem 0x92337000-0x92337fff 64bit]
>[    0.042066] pci 0000:00:19.2: [8086:5ac6] type 00 class 0x118000
>[    0.042076] pci 0000:00:19.2: reg 0x10: [mem 0x92338000-0x92338fff 64bit]
>[    0.042081] pci 0000:00:19.2: reg 0x18: [mem 0x92339000-0x92339fff 64bit]
>[    0.042134] pci 0000:00:1b.0: [8086:5aca] type 00 class 0x080501
>[    0.042142] pci 0000:00:1b.0: reg 0x10: [mem 0x9233a000-0x9233afff 64bit]
>[    0.042147] pci 0000:00:1b.0: reg 0x18: [mem 0x9233b000-0x9233bfff 64bit]
>[    0.042190] pci 0000:00:1c.0: [8086:5acc] type 00 class 0x080501
>[    0.042198] pci 0000:00:1c.0: reg 0x10: [mem 0x9233c000-0x9233cfff 64bit]
>[    0.042203] pci 0000:00:1c.0: reg 0x18: [mem 0x9233d000-0x9233dfff 64bit]
>[    0.042247] pci 0000:00:1e.0: [8086:5ad0] type 00 class 0x080501
>[    0.042255] pci 0000:00:1e.0: reg 0x10: [mem 0x9233e000-0x9233efff 64bit]
>[    0.042260] pci 0000:00:1e.0: reg 0x18: [mem 0x9233f000-0x9233ffff 64bit]
>[    0.042304] pci 0000:00:1f.0: [8086:5ae8] type 00 class 0x060100
>[    0.042378] pci 0000:00:1f.1: [8086:5ad4] type 00 class 0x0c0500
>[    0.042394] pci 0000:00:1f.1: reg 0x10: [mem 0x92341000-0x923410ff 64bit]
>[    0.042415] pci 0000:00:1f.1: reg 0x20: [io  0x2040-0x205f]
>[    0.042500] pci 0000:01:00.0: [8086:1539] type 00 class 0x020000
>[    0.042512] pci 0000:01:00.0: reg 0x10: [mem 0x92200000-0x9221ffff]
>[    0.042523] pci 0000:01:00.0: reg 0x18: [io  0x1000-0x101f]
>[    0.042531] pci 0000:01:00.0: reg 0x1c: [mem 0x92220000-0x92223fff]
>[    0.042576] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
>[    0.049591] pci 0000:00:13.0: PCI bridge to [bus 01]
>[    0.049595] pci 0000:00:13.0:   bridge window [io  0x1000-0x1fff]
>[    0.049596] pci 0000:00:13.0:   bridge window [mem 0x92200000-0x922fffff]
>[    0.049704] pci 0000:02:00.0: [8086:095a] type 00 class 0x028000
>[    0.049754] pci 0000:02:00.0: reg 0x10: [mem 0x92100000-0x92101fff 64bit]
>[    0.049917] pci 0000:02:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug
>[    0.050078] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
>[    0.057673] pci 0000:00:14.0: PCI bridge to [bus 02]
>[    0.057682] pci 0000:00:14.0:   bridge window [mem 0x92100000-0x921fffff]
>[    0.057698] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 02
>[    0.057792] PCI: pci_cache_line_size set to 64 bytes
>[    0.057927] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    0.057928] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>[    0.057929] e820: reserve RAM buffer [mem 0x0f000000-0x0fffffff]
>[    0.057929] e820: reserve RAM buffer [mem 0x77ff9000-0x77ffffff]
>[    0.057930] e820: reserve RAM buffer [mem 0x7ac2c000-0x7bffffff]
>[    0.057931] e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff]
>[    0.057990] NetLabel: Initializing
>[    0.057993] NetLabel:  domain hash size = 128
>[    0.057995] NetLabel:  protocols = UNLABELED CIPSOv4
>[    0.058003] NetLabel:  unlabeled traffic allowed by default
>[    0.058089] clocksource: Switched to clocksource refined-jiffies
>[    0.061788] VFS: Disk quotas dquot_6.6.0
>[    0.061799] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>[    0.061841] AppArmor: AppArmor Filesystem Enabled
>[    0.061868] pnp: PnP ACPI: disabled
>[    0.062986] pci 0000:00:13.0: PCI bridge to [bus 01]
>[    0.062991] pci 0000:00:13.0:   bridge window [io  0x1000-0x1fff]
>[    0.062995] pci 0000:00:13.0:   bridge window [mem 0x92200000-0x922fffff]
>[    0.062999] pci 0000:00:14.0: PCI bridge to [bus 02]
>[    0.063006] pci 0000:00:14.0:   bridge window [mem 0x92100000-0x921fffff]
>[    0.063015] pci_bus 0000:00: resource 4 [io  0x0000-0xffff]
>[    0.063016] pci_bus 0000:00: resource 5 [mem 0x00000000-0x7fffffffff]
>[    0.063017] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
>[    0.063019] pci_bus 0000:01: resource 1 [mem 0x92200000-0x922fffff]
>[    0.063020] pci_bus 0000:02: resource 1 [mem 0x92100000-0x921fffff]
>[    0.063034] NET: Registered protocol family 2
>[    0.063160] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
>[    0.063395] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>[    0.063572] TCP: Hash tables configured (established 131072 bind 65536)
>[    0.063599] UDP hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.063673] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.063762] NET: Registered protocol family 1
>[    0.063775] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>[    0.063794] pci 0000:00:15.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.063881] PCI: CLS 64 bytes, default 64
>[    0.063918] Trying to unpack rootfs image as initramfs...
>[    0.375738] Freeing initrd memory: 30692K (ffff880072da8000 - ffff880074ba1000)
>[    0.375744] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    0.375747] software IO TLB [mem 0x6eda8000-0x72da8000] (64MB) mapped at [ffff88006eda8000-ffff880072da7fff]
>[    0.375820] platform rtc_cmos: registered platform RTC device (no PNP device found)
>[    0.375838] Scanning for low memory corruption every 60 seconds
>[    0.375987] futex hash table entries: 256 (order: 2, 16384 bytes)
>[    0.375997] audit: initializing netlink subsys (disabled)
>[    0.376008] audit: type=2000 audit(1467072023.344:1): initialized
>[    0.376207] Initialise system trusted keyrings
>[    0.376252] workingset: timestamp_bits=38 max_order=22 bucket_order=0
>[    0.377641] fuse init (API version 7.24)
>[    0.377723] Key type big_key registered
>[    0.377904] Key type asymmetric registered
>[    0.377906] Asymmetric key parser 'x509' registered
>[    0.377930] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
>[    0.377949] io scheduler noop registered
>[    0.377951] io scheduler deadline registered (default)
>[    0.377973] io scheduler cfq registered
>[    0.378023] pcieport 0000:00:13.0: can't find IRQ for PCI INT C; please try using pci=biosirq
>[    0.378075] pcieport 0000:00:14.0: can't find IRQ for PCI INT B; please try using pci=biosirq
>[    0.378144] pcieport 0000:00:13.0: Signaling PME through PCIe PME interrupt
>[    0.378147] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
>[    0.378150] pcie_pme 0000:00:13.0:pcie001: service driver pcie_pme loaded
>[    0.378166] pcieport 0000:00:14.0: Signaling PME through PCIe PME interrupt
>[    0.378168] pci 0000:02:00.0: Signaling PME through PCIe PME interrupt
>[    0.378175] pcie_pme 0000:00:14.0:pcie001: service driver pcie_pme loaded
>[    0.378179] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[    0.378184] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
>[    0.378202] efifb: probing for efifb
>[    0.378212] efifb: framebuffer at 0x80000000, using 9000k, total 9000k
>[    0.378214] efifb: mode is 1920x1200x32, linelength=7680, pages=1
>[    0.378216] efifb: scrolling: redraw
>[    0.378218] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
>[    0.382763] Console: switching to colour frame buffer device 240x75
>[    0.387258] fb0: EFI VGA frame buffer device
>[    0.387279] ipmi message handler version 39.2
>[    0.387357] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
>[    0.407420] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[    0.408315] Linux agpgart interface v0.103
>[    0.409859] brd: module loaded
>[    0.410503] loop: module loaded
>[    0.410767] libphy: Fixed MDIO Bus: probed
>[    0.410839] tun: Universal TUN/TAP device driver, 1.6
>[    0.410855] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
>[    0.410897] PPP generic driver version 2.4.2
>[    0.410941] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    0.410964] ohci-pci: OHCI PCI platform driver
>[    0.410983] ohci-platform: OHCI generic platform driver
>[    0.411006] uhci_hcd: USB Universal Host Controller Interface driver
>[    0.411045] i8042: PNP: No PS/2 controller found. Probing ports directly.
>[    0.411367] i8042: Warning: Keylock active
>[    0.412548] serio: i8042 KBD port at 0x60,0x64 irq 1
>[    0.412567] serio: i8042 AUX port at 0x60,0x64 irq 12
>[    0.412655] mousedev: PS/2 mouse device common for all mice
>[    0.412811] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
>[    0.412849] rtc_cmos rtc_cmos: alarms up to one day, 114 bytes nvram
>[    0.412897] device-mapper: uevent: version 1.0.3
>[    0.412952] device-mapper: ioctl: 4.34.0-ioctl (2015-10-28) initialised: dm-devel@redhat.com
>[    0.412982] ledtrig-cpu: registered to indicate activity on CPUs
>[    0.413001] EFI Variables Facility v0.08 2004-May-17
>[    0.416270] NET: Registered protocol family 10
>[    0.416420] NET: Registered protocol family 17
>[    0.416449] Key type dns_resolver registered
>[    0.416569] microcode: CPU0 sig=0x506c9, pf=0x1, revision=0xe
>[    0.416606] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[    0.416706] registered taskstats version 1
>[    0.416723] Loading compiled-in X.509 certificates
>[    0.418486] Loaded X.509 cert 'Build time autogenerated kernel key: dd9ecf96289de4a65ccac44a28fae143855fb1de'
>[    0.420653] Key type trusted registered
>[    0.422766] Key type encrypted registered
>[    0.422785] AppArmor: AppArmor sha1 policy hashing enabled
>[    0.422802] ima: No TPM chip found, activating TPM-bypass!
>[    0.422832] evm: HMAC attrs: 0x1
>[    0.423061]   Magic number: 4:63:2
>[    0.423125] rtc_cmos rtc_cmos: setting system clock to 2016-06-28 00:00:25 UTC (1467072025)
>[    0.423170] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
>[    0.423191] EDD information not available.
>[    0.423241] PM: Hibernation image not present or could not be loaded.
>[    0.423878] Freeing unused kernel memory: 1508K (ffffffff81d49000 - ffffffff81ec2000)
>[    0.423904] Write protecting the kernel read-only data: 12288k
>[    0.424035] Freeing unused kernel memory: 348K (ffff8800017a9000 - ffff880001800000)
>[    0.424780] Freeing unused kernel memory: 476K (ffff880001b89000 - ffff880001c00000)
>[    0.432002] random: udevadm urandom read with 1 bits of entropy available
>[    0.466799] ahci 0000:00:12.0: version 3.0
>[    0.466806] ahci 0000:00:12.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.473573] pps_core: LinuxPPS API ver. 1 registered
>[    0.474682] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    0.482819] PTP clock support registered
>[    0.485922] sdhci: Secure Digital Host Controller Interface driver
>[    0.487043] sdhci: Copyright(c) Pierre Ossman
>[    0.490616] [drm] Initialized drm 1.1.0 20060810
>[    0.492379] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
>[    0.493519] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst 
>[    0.502862] dca service started, version 1.12.1
>[    0.504072] scsi host0: ahci
>[    0.508180] ata1: SATA max UDMA/133 abar m2048@0x92340000 port 0x92340100 irq 18
>[    0.515062] xhci_hcd 0000:00:15.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.516220] xhci_hcd 0000:00:15.0: xHCI Host Controller
>[    0.517382] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1
>[    0.519538] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810
>[    0.520680] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
>[    0.524522] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.3.0-k
>[    0.525676] igb: Copyright (c) 2007-2014 Intel Corporation.
>[    0.532174] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    0.533321] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    0.534466] usb usb1: Product: xHCI Host Controller
>[    0.535602] usb usb1: Manufacturer: Linux 4.7.0-rc4-nightly+ xhci-hcd
>[    0.536744] usb usb1: SerialNumber: 0000:00:15.0
>[    0.539471] igb 0000:01:00.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.554921] hub 1-0:1.0: USB hub found
>[    0.562354] hub 1-0:1.0: 8 ports detected
>[    0.563620] xhci_hcd 0000:00:15.0: xHCI Host Controller
>[    0.564766] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2
>[    0.565944] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    0.567094] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    0.568236] usb usb2: Product: xHCI Host Controller
>[    0.569383] usb usb2: Manufacturer: Linux 4.7.0-rc4-nightly+ xhci-hcd
>[    0.570537] usb usb2: SerialNumber: 0000:00:15.0
>[    0.576017] pps pps0: new PPS source ptp0
>[    0.577169] igb 0000:01:00.0: added PHC on eth0
>[    0.578315] igb 0000:01:00.0: Intel(R) Gigabit Ethernet Network Connection
>[    0.579463] igb 0000:01:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 90:49:fa:01:93:40
>[    0.580611] igb 0000:01:00.0: eth0: PBA No: FFFFFF-0FF
>[    0.581757] igb 0000:01:00.0: Using MSI-X interrupts. 1 rx queue(s), 1 tx queue(s)
>[    0.591736] Setting dangerous option enable_rc6 - tainting kernel
>[    0.593911] hub 2-0:1.0: USB hub found
>[    0.595066] Setting dangerous option preliminary_hw_support - tainting kernel
>[    0.596226] Setting dangerous option enable_guc_submission - tainting kernel
>[    0.598834] hub 2-0:1.0: 7 ports detected
>[    0.602565] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    0.603764] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    0.605959] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    0.607139] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.619813] i915 0000:00:02.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.621006] [drm:intel_detect_pch] No PCH found.
>[    0.621008] [drm:get_allowed_dc_mask] Allowed DC state mask 09
>[    0.621017] [drm:i915_dump_device_info] i915 device info: gen=9, pciid=0x5a84 rev=0x0a flags=need_gfx_hws,is_broxton,is_preliminary,has_fbc,has_hotplug,has_ddi,has_fpga_dbg,
>[    0.621096] [drm:intel_device_info_runtime_init] slice total: 1
>[    0.621096] [drm:intel_device_info_runtime_init] subslice total: 3
>[    0.621097] [drm:intel_device_info_runtime_init] subslice per slice: 3
>[    0.621098] [drm:intel_device_info_runtime_init] EU total: 18
>[    0.621099] [drm:intel_device_info_runtime_init] EU per subslice: 6
>[    0.621099] [drm:intel_device_info_runtime_init] has slice power gating: n
>[    0.621100] [drm:intel_device_info_runtime_init] has subslice power gating: y
>[    0.621101] [drm:intel_device_info_runtime_init] has EU power gating: y
>[    0.621102] [drm:intel_device_info_runtime_init] ppgtt mode: 3
>[    0.621114] [drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K
>[    0.621115] [drm] Memory usable by graphics device = 4096M
>[    0.622301] [drm:i915_ggtt_init_hw] GMADR size = 256M
>[    0.622301] [drm:i915_ggtt_init_hw] GTT stolen size = 64M
>[    0.622307] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[    0.623516] checking generic (80000000 8ca000) vs hw (80000000 10000000)
>[    0.623517] fb: switching to inteldrmfb from EFI VGA
>[    0.624722] Console: switching to colour dummy device 80x25
>[    0.627872] [drm] Replacing VGA console driver
>[    0.627965] [drm:intel_opregion_setup] graphic opregion physical addr: 0x79df2018
>[    0.627969] [drm:intel_opregion_setup] Public ACPI methods supported
>[    0.627970] [drm:intel_opregion_setup] ASLE supported
>[    0.627972] [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (RVDA)
>[    0.627993] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    0.627995] [drm] Driver supports precise vblank timestamp query.
>[    0.627998] [drm:init_vbt_defaults] Set default to SSC at 100000 kHz
>[    0.627999] [drm:intel_bios_init] VBT signature "$VBT BROXTON        ", BDB version 207
>[    0.628000] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[    0.628001] [drm:parse_general_definitions] crt_ddc_bus_pin: 2
>[    0.628002] [drm:intel_opregion_get_panel_type] Failed to get panel details from OpRegion (-19)
>[    0.628003] [drm:parse_lfp_panel_data] Panel type: 2 (VBT)
>[    0.628004] [drm:parse_lfp_panel_data] DRRS supported mode is seamless
>[    0.628005] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
>[    0.628007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    0.628008] [drm:parse_lfp_panel_data] VBT initial LVDS value 300
>[    0.628009] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180
>[    0.628010] [drm:parse_sdvo_device_mapping] Unsupported child device size for SDVO mapping.
>[    0.628011] [drm:parse_device_mapping] Expected child device config size for VBT version 207 not known; assuming 38
>[    0.628012] [drm:parse_driver_features] DRRS State Enabled:1
>[    0.628014] [drm:parse_ddi_port] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[    0.628015] [drm:parse_ddi_port] VBT HDMI level shift for port A: 0
>[    0.628016] [drm:parse_ddi_port] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    0.628016] [drm:parse_ddi_port] VBT HDMI level shift for port B: 8
>[    0.628017] [drm:parse_ddi_port] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    0.628018] [drm:parse_ddi_port] VBT HDMI level shift for port C: 8
>[    0.628024] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
>[    0.628026] [drm:intel_power_well_enable] enabling power well 1
>[    0.628029] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz
>[    0.628041] [drm:intel_power_well_enable] enabling always-on
>[    0.628042] [drm:intel_power_well_enable] enabling DC off
>[    0.628043] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
>[    0.628045] [drm:intel_power_well_enable] enabling power well 2
>[    0.628046] [drm:intel_power_well_enable] enabling dpio-common-a
>[    0.630129] igb 0000:01:00.0 enp1s0: renamed from eth0
>[    0.634249] [drm:intel_power_well_enable] enabling dpio-common-bc
>[    0.634259] [drm:bxt_ddi_phy_init] DDI PHY 0 already enabled, won't reprogram it
>[    0.634261] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
>[    0.634280] [drm:bxt_ddi_phy_init] DDI PHY 1 already enabled, won't reprogram it
>[    0.634289] [drm:bxt_ddi_phy_init] DDI PHY 0 already enabled, won't reprogram it
>[    0.634292] [drm:intel_csr_ucode_init] Loading i915/bxt_dmc_ver1.bin
>[    0.634390] [drm] Finished loading i915/bxt_dmc_ver1.bin (v1.7)
>[    0.634465] [drm:intel_fbc_init] Sanitized enable_fbc value: 0
>[    0.642156] [drm:intel_print_wm_latency] Gen9 Plane WM0 latency 9 (9.0 usec)
>[    0.642164] [drm:intel_print_wm_latency] Gen9 Plane WM1 latency 9 (9.0 usec)
>[    0.642165] [drm:intel_print_wm_latency] Gen9 Plane WM2 latency 10 (10.0 usec)
>[    0.642165] [drm:intel_print_wm_latency] Gen9 Plane WM3 latency 24 (24.0 usec)
>[    0.642166] [drm:intel_print_wm_latency] Gen9 Plane WM4 latency 24 (24.0 usec)
>[    0.642167] [drm:intel_print_wm_latency] Gen9 Plane WM5 latency 24 (24.0 usec)
>[    0.642168] [drm:intel_print_wm_latency] Gen9 Plane WM6 latency 24 (24.0 usec)
>[    0.642169] [drm:intel_print_wm_latency] Gen9 Plane WM7 latency 24 (24.0 usec)
>[    0.642170] [drm:intel_modeset_init] 3 display pipes available.
>[    0.642183] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz
>[    0.642184] [drm:intel_update_max_cdclk] Max CD clock rate: 624000 kHz
>[    0.642185] [drm:intel_update_max_cdclk] Max dotclock rate: 624000 kHz
>[    0.642187] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[    0.642493] [drm:intel_ddi_init] BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing
>[    0.642495] [drm:intel_dp_init_connector] Adding eDP connector on port A
>[    0.642503] [drm:intel_pps_dump_state] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 5000
>[    0.642505] [drm:intel_pps_dump_state] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[    0.642506] [drm:intel_dp_init_panel_power_sequencer] panel power up delay 200, power down delay 50, power cycle delay 500
>[    0.642507] [drm:intel_dp_init_panel_power_sequencer] backlight on delay 1, off delay 200
>[    0.642508] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[    0.642509] [drm:intel_edp_panel_vdd_sanitize] VDD left on by BIOS, adjusting state tracking
>[    0.642611] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[    0.642750] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[    0.642823] [drm:intel_dp_get_dpcd] EDP DPCD : 02 fb c7
>[    0.642824] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[    0.642826] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    0.642827] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[    0.642828] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[    0.643627] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.643628] [drm:intel_dp_drrs_init] Downclock mode is not found. DRRS not supported
>[    0.643630] [drm:get_backlight_max_vbt] VBT defined backlight frequency 200 Hz
>[    0.643631] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, disabled, brightness 0/96000
>[    0.643636] [drm:intel_dp_init_connector] Adding DP connector on port B
>[    0.643643] [drm:intel_hdmi_init_connector] Adding HDMI connector on port B
>[    0.643649] [drm:intel_dp_init_connector] Adding DP connector on port C
>[    0.643654] [drm:intel_hdmi_init_connector] Adding HDMI connector on port C
>[    0.643656] [drm:intel_dsi_init] 
>[    0.643667] [drm:intel_modeset_readout_hw_state] [CRTC:26:pipe A] hw state readout: enabled
>[    0.643669] [drm:intel_modeset_readout_hw_state] [CRTC:31:pipe B] hw state readout: disabled
>[    0.643671] [drm:intel_modeset_readout_hw_state] [CRTC:36:pipe C] hw state readout: disabled
>[    0.643672] [drm:intel_modeset_readout_hw_state] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[    0.643677] [drm:intel_modeset_readout_hw_state] PORT PLL B hw state readout: crtc_mask 0x00000001, on 1
>[    0.643678] [drm:intel_modeset_readout_hw_state] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[    0.643680] [drm:intel_modeset_readout_hw_state] [ENCODER:38:DDI A] hw state readout: disabled, pipe A
>[    0.643686] [drm:intel_modeset_readout_hw_state] [ENCODER:46:DDI B] hw state readout: enabled, pipe A
>[    0.643687] [drm:intel_modeset_readout_hw_state] [ENCODER:48:DP-MST A] hw state readout: disabled, pipe A
>[    0.643688] [drm:intel_modeset_readout_hw_state] [ENCODER:49:DP-MST B] hw state readout: disabled, pipe B
>[    0.643689] [drm:intel_modeset_readout_hw_state] [ENCODER:50:DP-MST C] hw state readout: disabled, pipe C
>[    0.643690] [drm:intel_modeset_readout_hw_state] [ENCODER:53:DDI C] hw state readout: disabled, pipe A
>[    0.643691] [drm:intel_modeset_readout_hw_state] [ENCODER:55:DP-MST A] hw state readout: disabled, pipe A
>[    0.643692] [drm:intel_modeset_readout_hw_state] [ENCODER:56:DP-MST B] hw state readout: disabled, pipe B
>[    0.643693] [drm:intel_modeset_readout_hw_state] [ENCODER:57:DP-MST C] hw state readout: disabled, pipe C
>[    0.643694] [drm:intel_modeset_readout_hw_state] [CONNECTOR:39:eDP-1] hw state readout: disabled
>[    0.643696] [drm:intel_modeset_readout_hw_state] [CONNECTOR:47:DP-1] hw state readout: enabled
>[    0.643697] [drm:intel_modeset_readout_hw_state] [CONNECTOR:51:HDMI-A-1] hw state readout: disabled
>[    0.643699] [drm:intel_modeset_readout_hw_state] [CONNECTOR:54:DP-2] hw state readout: disabled
>[    0.643700] [drm:intel_modeset_readout_hw_state] [CONNECTOR:58:HDMI-A-2] hw state readout: disabled
>[    0.643706] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][setup_hw_state] config ffff88046738d000 for pipe A
>[    0.643707] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    0.643707] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    0.643708] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.643710] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 1794230, gmch_n: 8388608, link_m: 149519, link_n: 524288, tu: 64
>[    0.643711] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.643711] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.643712] [drm:intel_dump_pipe_config] requested mode:
>[    0.643714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 153999 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[    0.643715] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.643716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 153999 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[    0.643717] [drm:intel_dump_crtc_timings] crtc timings: 153999 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x40 flags: 0x9
>[    0.643718] [drm:intel_dump_pipe_config] port clock: 540000
>[    0.643719] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[    0.643720] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>[    0.643721] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.643722] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x078004b0, enabled
>[    0.643722] [drm:intel_dump_pipe_config] ips: 0
>[    0.643723] [drm:intel_dump_pipe_config] double wide: 0
>[    0.643724] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[    0.643725] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.643726] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[    0.643727] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[    0.643728] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[    0.643729] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[    0.643730] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][setup_hw_state] config ffff880467860000 for pipe B
>[    0.643731] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    0.643731] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[    0.643732] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.643733] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.643735] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.643735] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.643736] [drm:intel_dump_pipe_config] requested mode:
>[    0.643737] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.643738] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.643739] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.643741] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    0.643741] [drm:intel_dump_pipe_config] port clock: 0
>[    0.643742] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[    0.643743] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[    0.643744] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.643745] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.643745] [drm:intel_dump_pipe_config] ips: 0
>[    0.643746] [drm:intel_dump_pipe_config] double wide: 0
>[    0.643747] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[    0.643748] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.643749] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1
>[    0.643750] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[    0.643751] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[    0.643751] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[    0.643753] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][setup_hw_state] config ffff880467190800 for pipe C
>[    0.643753] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    0.643754] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[    0.643755] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.643756] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.643757] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.643758] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.643759] [drm:intel_dump_pipe_config] requested mode:
>[    0.643760] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.643760] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.643762] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.643763] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    0.643764] [drm:intel_dump_pipe_config] port clock: 0
>[    0.643764] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[    0.643765] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[    0.643766] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.643767] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.643768] [drm:intel_dump_pipe_config] ips: 0
>[    0.643768] [drm:intel_dump_pipe_config] double wide: 0
>[    0.643770] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[    0.643770] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.643771] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[    0.643772] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[    0.643773] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[    0.643788] [drm:skylake_get_initial_plane_config] pipe A with fb: size=1920x1200@32, offset=0, pitch 7680, size 0x8ca000
>[    0.643789] [drm:i915_gem_object_create_stolen_for_preallocated] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=8ca000
>[    0.643792] [drm:i915_pages_create_for_stolen] offset=0x0, size=9216000
>[    0.643794] [drm:intel_alloc_initial_plane_obj] initial plane fb obj ffff88046718a000
>[    0.643795] [drm:intel_guc_init] GuC firmware pending, path i915/bxt_guc_ver8_7.bin
>[    0.643796] [drm:guc_fw_fetch] before requesting firmware: GuC fw fetch status PENDING
>[    0.643832] [drm:guc_fw_fetch] fetch GuC fw from i915/bxt_guc_ver8_7.bin succeeded, fw ffff880467a57d80
>[    0.643833] [drm:guc_fw_fetch] firmware version 8.7 OK (minimum 8.7)
>[    0.643868] [drm:guc_fw_fetch] GuC fw fetch status SUCCESS, obj ffff88046718a240
>[    0.643942] [drm:i915_gem_setup_global_gtt] reserving preallocated space: 0 + 8ca000
>[    0.643943] [drm:i915_gem_setup_global_gtt] clearing unused GTT space: [8ca000, fffff000]
>[    0.643958] [drm:i915_gem_context_init] LR context support initialized
>[    0.643966] [drm:intel_init_pipe_control] render ring pipe control offset: 0x008cb000
>[    0.643971] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.643973] [drm:i915_pages_create_for_stolen] offset=0x8ca000, size=16384
>[    0.643993] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.643995] [drm:i915_pages_create_for_stolen] offset=0x8ce000, size=16384
>[    0.644001] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.644002] [drm:i915_pages_create_for_stolen] offset=0x8d2000, size=16384
>[    0.644010] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.644011] [drm:i915_pages_create_for_stolen] offset=0x8d6000, size=16384
>[    0.644020] [drm:gen8_init_common_ring] Execlists enabled for render ring
>[    0.644042] [drm:gen8_init_common_ring] Execlists enabled for blitter ring
>[    0.644060] [drm:gen8_init_common_ring] Execlists enabled for bsd ring
>[    0.644080] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring
>[    0.644097] [drm:intel_guc_setup] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch SUCCESS, load NONE
>[    0.644099] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load PENDING
>[    0.646138] [drm:guc_ucode_xfer_dma] DMA status 0x10, GuC status 0x8002f0ec
>[    0.646139] [drm:guc_ucode_xfer_dma] returning 0
>[    0.646140] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load SUCCESS
>[    0.646149] [drm:select_doorbell_register] assigned normal priority doorbell id 0x0
>[    0.646150] [drm:select_doorbell_cacheline] selected doorbell cacheline 0x0, next 0x40, linesize 64
>[    0.646161] [drm:guc_client_alloc] new priority 2 client ffff88046cf8cf00: ctx_index 0
>[    0.646162] [drm:guc_client_alloc] doorbell id 0, cacheline offset 0x0
>[    0.649141] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz
>[    0.649147] [drm:intel_fbdev_init_bios] found possible fb from plane A
>[    0.649148] [drm:intel_fbdev_init_bios] pipe B not active or no fb, skipping
>[    0.649149] [drm:intel_fbdev_init_bios] pipe C not active or no fb, skipping
>[    0.649150] [drm:intel_fbdev_init_bios] checking plane A for BIOS fb
>[    0.649151] [drm:intel_fbdev_init_bios] pipe A area: 1920x1200, bpp: 32, size: 9216000
>[    0.649152] [drm:intel_fbdev_init_bios] fb big enough for plane A (9216000 >= 9216000)
>[    0.649153] [drm:intel_fbdev_init_bios] pipe B not active, skipping
>[    0.649154] [drm:intel_fbdev_init_bios] pipe C not active, skipping
>[    0.649155] [drm:intel_fbdev_init_bios] using BIOS fb for initial console
>[    0.649158] [drm:bxt_hpd_irq_setup] Invert bit setting: hp_ctl:18001819 hp_port:38
>[    0.649660] [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered
>[    0.649663] [drm:intel_dp_connector_register] registering DPDDC-A bus for card0-eDP-1
>[    0.649857] [drm:intel_dp_connector_register] registering DPDDC-B bus for card0-DP-1
>[    0.650192] [drm:intel_dp_connector_register] registering DPDDC-C bus for card0-DP-2
>[    0.650431] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1]
>[    0.650432] [drm:intel_dp_detect] [CONNECTOR:39:eDP-1]
>[    0.650479] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    0.650488] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.651501] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[    0.651579] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[    0.651690] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] status updated from unknown to connected
>[    0.651698] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.651700] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes :
>[    0.651701] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[    0.651703] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[    0.651703] [drm:intel_dp_detect] [CONNECTOR:47:DP-1]
>[    0.651808] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[    0.651884] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
>[    0.651886] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    0.651887] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[    0.651888] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[    0.651986] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    0.652008] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    0.653023] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    0.653030] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.654117] [drm:intel_dp_probe_mst] Sink is not MST capable
>[    0.654223] [drm:drm_dp_i2c_do_msg] native defer
>[    0.658201] [drm:drm_dp_i2c_do_msg] native defer
>[    0.662141] [drm:drm_dp_i2c_do_msg] native defer
>[    0.666106] [drm:drm_dp_i2c_do_msg] native defer
>[    0.670073] [drm:drm_dp_i2c_do_msg] native defer
>[    0.674035] [drm:drm_dp_i2c_do_msg] native defer
>[    0.678005] [drm:drm_dp_i2c_do_msg] native defer
>[    0.681969] [drm:drm_dp_i2c_do_msg] native defer
>[    0.685932] [drm:drm_dp_i2c_do_msg] native defer
>[    0.689929] [drm:drm_dp_i2c_do_msg] native defer
>[    0.693894] [drm:drm_dp_i2c_do_msg] native defer
>[    0.697858] [drm:drm_dp_i2c_do_msg] native defer
>[    0.701826] [drm:drm_dp_i2c_do_msg] native defer
>[    0.705786] [drm:drm_dp_i2c_do_msg] native defer
>[    0.709749] [drm:drm_dp_i2c_do_msg] native defer
>[    0.713712] [drm:drm_dp_i2c_do_msg] native defer
>[    0.717673] [drm:drm_dp_i2c_do_msg] native defer
>[    0.721607] [drm:drm_dp_i2c_do_msg] native defer
>[    0.725569] [drm:drm_dp_i2c_do_msg] native defer
>[    0.729533] [drm:drm_dp_i2c_do_msg] native defer
>[    0.733492] [drm:drm_dp_i2c_do_msg] native defer
>[    0.737488] [drm:drm_dp_i2c_do_msg] native defer
>[    0.741450] [drm:drm_dp_i2c_do_msg] native defer
>[    0.745412] [drm:drm_dp_i2c_do_msg] native defer
>[    0.749371] [drm:drm_dp_i2c_do_msg] native defer
>[    0.753333] [drm:drm_dp_i2c_do_msg] native defer
>[    0.757293] [drm:drm_dp_i2c_do_msg] native defer
>[    0.761258] [drm:drm_dp_i2c_do_msg] native defer
>[    0.765214] [drm:drm_dp_i2c_do_msg] native defer
>[    0.769040] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    0.769152] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] status updated from unknown to connected
>[    0.769177] [drm:drm_edid_to_eld] ELD monitor DELL 2408WFP
>[    0.769178] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[    0.769179] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    0.769187] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[    0.769188] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    0.769190] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[    0.769190] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[    0.769192] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[    0.769193] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    0.769195] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes :
>[    0.769196] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[    0.769198] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    0.769199] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    0.769201] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    0.769202] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    0.769204] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[    0.769205] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    0.769207] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    0.769208] [drm:drm_mode_debug_printmodeline] Modeline 69:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    0.769209] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    0.769211] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    0.769212] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    0.769214] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    0.769215] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    0.769217] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    0.769218] [drm:drm_mode_debug_printmodeline] Modeline 89:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    0.769220] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    0.769221] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    0.769222] [drm:drm_mode_debug_printmodeline] Modeline 90:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    0.769224] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    0.769225] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    0.769227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1]
>[    0.769228] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-1]
>[    0.769266] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.769267] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.769305] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.769306] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    0.769343] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.769344] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.769380] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.769381] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] status updated from unknown to disconnected
>[    0.769382] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected
>[    0.769383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2]
>[    0.769384] [drm:intel_dp_detect] [CONNECTOR:54:DP-2]
>[    0.769486] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[    0.769558] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[    0.769560] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    0.769561] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[    0.769562] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[    0.770912] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] status updated from unknown to connected
>[    0.770917] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.770919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes :
>[    0.770921] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    0.770923] [drm:drm_mode_debug_printmodeline] Modeline 84:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[    0.770924] [drm:drm_mode_debug_printmodeline] Modeline 85:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[    0.770925] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    0.770927] [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[    0.770928] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    0.770930] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    0.770931] [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    0.770933] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    0.770934] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    0.770935] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    0.770936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2]
>[    0.770937] [drm:intel_hdmi_detect] [CONNECTOR:58:HDMI-A-2]
>[    0.770975] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.770975] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.771012] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.771013] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    0.771051] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.771052] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.771088] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.771089] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] status updated from unknown to disconnected
>[    0.771090] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected
>[    0.771092] [drm:drm_setup_crtcs] 
>[    0.771093] [drm:drm_enable_connectors] connector 39 enabled? yes
>[    0.771094] [drm:drm_enable_connectors] connector 47 enabled? yes
>[    0.771094] [drm:drm_enable_connectors] connector 51 enabled? no
>[    0.771095] [drm:drm_enable_connectors] connector 54 enabled? yes
>[    0.771096] [drm:drm_enable_connectors] connector 58 enabled? no
>[    0.771097] [drm:intel_fb_initial_config] connector eDP-1 has no encoder or crtc, skipping
>[    0.771098] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1
>[    0.771099] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0
>[    0.771100] [drm:intel_fb_initial_config] connector DP-1 on [CRTC:26:pipe A]: 1920x1200
>[    0.771101] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[    0.771102] [drm:intel_fb_initial_config] connector DP-2 has no encoder or crtc, skipping
>[    0.771103] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
>[    0.771103] [drm:intel_fb_initial_config] fallback: Not all outputs enabled
>[    0.771104] [drm:intel_fb_initial_config] Enabled: 1, detected: 3
>[    0.771105] [drm:intel_fb_initial_config] Not using firmware configuration
>[    0.771106] [drm:drm_target_preferred] looking for cmdline mode on connector 39
>[    0.771107] [drm:drm_target_preferred] looking for preferred mode on connector 39 0
>[    0.771108] [drm:drm_target_preferred] found mode 1920x1080
>[    0.771108] [drm:drm_target_preferred] looking for cmdline mode on connector 47
>[    0.771109] [drm:drm_target_preferred] looking for preferred mode on connector 47 0
>[    0.771110] [drm:drm_target_preferred] found mode 1920x1200
>[    0.771111] [drm:drm_target_preferred] looking for cmdline mode on connector 54
>[    0.771111] [drm:drm_target_preferred] looking for preferred mode on connector 54 0
>[    0.771112] [drm:drm_target_preferred] found mode 1920x1080
>[    0.771113] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    0.771117] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 26 (0,0)
>[    0.771118] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[    0.771119] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0)
>[    0.771120] [drm:intelfb_create] re-using BIOS fb
>[    0.771124] [drm:intelfb_create] allocated 1920x1200 fb: 0x00000000, bo ffff88046718a000
>[    0.771147] [drm:drm_fb_helper_hotplug_event] 
>[    0.771148] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1]
>[    0.771149] [drm:intel_dp_detect] [CONNECTOR:39:eDP-1]
>[    0.771274] fbcon: inteldrmfb (fb0) is primary device
>[    0.771316] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[    0.771532] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[    0.771616] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.771617] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes :
>[    0.771618] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[    0.771619] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[    0.771620] [drm:intel_dp_detect] [CONNECTOR:47:DP-1]
>[    0.771721] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[    0.771793] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
>[    0.771794] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    0.771795] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[    0.771795] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[    0.771969] [drm:intel_dp_probe_mst] Sink is not MST capable
>[    0.772072] [drm:drm_edid_to_eld] ELD monitor DELL 2408WFP
>[    0.772073] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[    0.772073] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    0.772081] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[    0.772082] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    0.772083] [drm:drm_mode_debug_printmodeline] Modeline 120:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[    0.772083] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[    0.772084] [drm:drm_mode_debug_printmodeline] Modeline 132:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[    0.772085] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    0.772087] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes :
>[    0.772088] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[    0.772089] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    0.772090] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    0.772091] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    0.772092] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    0.772093] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[    0.772094] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    0.772095] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    0.772096] [drm:drm_mode_debug_printmodeline] Modeline 69:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    0.772097] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    0.772098] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    0.772099] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    0.772100] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    0.772101] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    0.772102] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    0.772103] [drm:drm_mode_debug_printmodeline] Modeline 89:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    0.772104] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    0.772105] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    0.772106] [drm:drm_mode_debug_printmodeline] Modeline 90:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    0.772107] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    0.772108] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    0.772109] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1]
>[    0.772110] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-1]
>[    0.772147] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.772148] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.772183] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.772184] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    0.772220] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.772220] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.772256] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.772257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected
>[    0.772257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2]
>[    0.772258] [drm:intel_dp_detect] [CONNECTOR:54:DP-2]
>[    0.772361] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[    0.772433] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[    0.772434] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    0.772434] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[    0.772435] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[    0.772520] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.772523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes :
>[    0.772524] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    0.772525] [drm:drm_mode_debug_printmodeline] Modeline 84:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[    0.772526] [drm:drm_mode_debug_printmodeline] Modeline 85:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[    0.772527] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    0.772528] [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[    0.772529] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    0.772530] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    0.772531] [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    0.772532] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    0.772533] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    0.772534] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    0.772535] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2]
>[    0.772535] [drm:intel_hdmi_detect] [CONNECTOR:58:HDMI-A-2]
>[    0.772572] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.772573] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.772608] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.772609] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    0.772645] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.772645] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.772681] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.772681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected
>[    0.772684] [drm:drm_setup_crtcs] 
>[    0.772685] [drm:drm_enable_connectors] connector 39 enabled? yes
>[    0.772685] [drm:drm_enable_connectors] connector 47 enabled? yes
>[    0.772685] [drm:drm_enable_connectors] connector 51 enabled? no
>[    0.772686] [drm:drm_enable_connectors] connector 54 enabled? yes
>[    0.772686] [drm:drm_enable_connectors] connector 58 enabled? no
>[    0.772687] [drm:intel_fb_initial_config] connector eDP-1 has no encoder or crtc, skipping
>[    0.772688] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1
>[    0.772688] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0
>[    0.772689] [drm:intel_fb_initial_config] connector DP-1 on [CRTC:26:pipe A]: 1920x1200
>[    0.772689] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[    0.772690] [drm:intel_fb_initial_config] connector DP-2 has no encoder or crtc, skipping
>[    0.772690] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
>[    0.772690] [drm:intel_fb_initial_config] fallback: Not all outputs enabled
>[    0.772691] [drm:intel_fb_initial_config] Enabled: 1, detected: 3
>[    0.772691] [drm:intel_fb_initial_config] Not using firmware configuration
>[    0.772692] [drm:drm_target_preferred] looking for cmdline mode on connector 39
>[    0.772692] [drm:drm_target_preferred] looking for preferred mode on connector 39 0
>[    0.772693] [drm:drm_target_preferred] found mode 1920x1080
>[    0.772693] [drm:drm_target_preferred] looking for cmdline mode on connector 47
>[    0.772693] [drm:drm_target_preferred] looking for preferred mode on connector 47 0
>[    0.772694] [drm:drm_target_preferred] found mode 1920x1200
>[    0.772694] [drm:drm_target_preferred] looking for cmdline mode on connector 54
>[    0.772694] [drm:drm_target_preferred] looking for preferred mode on connector 54 0
>[    0.772695] [drm:drm_target_preferred] found mode 1920x1080
>[    0.772695] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    0.772699] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 26 (0,0)
>[    0.772700] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[    0.772701] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0)
>[    0.772710] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[    0.772711] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[    0.772712] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[    0.772713] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[    0.772714] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[    0.772716] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[    0.772716] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[    0.772717] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    0.772718] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046717e000 for pipe A
>[    0.772719] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[    0.772719] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    0.772720] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.772720] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[    0.772721] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.772721] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.772722] [drm:intel_dump_pipe_config] requested mode:
>[    0.772723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[    0.772723] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.772724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[    0.772725] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[    0.772725] [drm:intel_dump_pipe_config] port clock: 270000
>[    0.772726] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    0.772726] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    0.772727] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.772727] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.772728] [drm:intel_dump_pipe_config] ips: 0
>[    0.772728] [drm:intel_dump_pipe_config] double wide: 0
>[    0.772729] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[    0.772730] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.772731] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[    0.772732] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[    0.772732] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[    0.772733] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[    0.772733] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[    0.772734] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[    0.772734] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[    0.772735] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[    0.772735] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[    0.772737] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[    0.772737] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[    0.772738] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    0.772739] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88046717e800 for pipe B
>[    0.772739] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    0.772739] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    0.772740] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.772741] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[    0.772741] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.772742] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    0.772742] [drm:intel_dump_pipe_config] requested mode:
>[    0.772743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[    0.772743] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.772744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[    0.772745] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[    0.772746] [drm:intel_dump_pipe_config] port clock: 162000
>[    0.772746] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[    0.772747] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[    0.772747] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.772748] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.772748] [drm:intel_dump_pipe_config] ips: 0
>[    0.772748] [drm:intel_dump_pipe_config] double wide: 0
>[    0.772749] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[    0.772749] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.772750] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1
>[    0.772750] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[    0.772751] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[    0.772751] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[    0.772752] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[    0.772752] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[    0.772753] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    0.772754] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[    0.772754] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    0.772755] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    0.772756] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046717f000 for pipe C
>[    0.772756] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    0.772756] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    0.772757] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.772758] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    0.772758] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.772759] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.772759] [drm:intel_dump_pipe_config] requested mode:
>[    0.772760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    0.772760] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.772761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    0.772762] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    0.772763] [drm:intel_dump_pipe_config] port clock: 162000
>[    0.772763] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    0.772764] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[    0.772764] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.772764] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.772765] [drm:intel_dump_pipe_config] ips: 0
>[    0.772765] [drm:intel_dump_pipe_config] double wide: 0
>[    0.772766] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[    0.772766] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.772767] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[    0.772767] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[    0.772768] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[    0.772769] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[    0.772771] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    0.772772] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[    0.772772] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[    0.772774] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[    0.772774] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[    0.772775] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[    0.772776] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[    0.772776] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[    0.772776] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[    0.772777] [drm:skl_update_scaler] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[    0.772778] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[    0.772778] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[    0.772779] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[    0.772779] [drm:skl_update_scaler] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>[    0.772794] [drm:intel_disable_pipe] disabling pipe A
>[    0.776976] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[    0.776982] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[    0.776985] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[    0.792761] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[    0.792761] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[    0.792762] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[    0.792762] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[    0.792763] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[    0.792764] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[    0.792764] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[    0.792771] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[    0.792771] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[    0.792771] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[    0.792772] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[    0.792773] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[    0.792774] [drm:verify_single_dpll_state] PORT PLL A
>[    0.792775] [drm:verify_single_dpll_state] PORT PLL B
>[    0.792775] [drm:verify_single_dpll_state] PORT PLL C
>[    0.792780] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[    0.792781] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[    0.792803] [drm:edp_panel_on] Turn eDP port A panel power on
>[    0.792803] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[    0.832323] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[    0.832362] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0
>[    0.832503] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    0.832508] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.834627] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    0.834643] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    0.835653] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    0.835657] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.875810] usb 1-2: new high-speed USB device number 2 using xhci_hcd
>[    0.986355] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[    0.989974] ata1.00: ATA-9: INTEL SSDSC2BW080A4, LAFi, max UDMA/133
>[    0.989975] ata1.00: 156301488 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[    0.996517] ata1.00: configured for UDMA/133
>[    0.996581] scsi 0:0:0:0: Direct-Access     ATA      INTEL SSDSC2BW08 LAFi PQ: 0 ANSI: 5
>[    0.996875] sd 0:0:0:0: Attached scsi generic sg0 type 0
>[    0.996917] sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB)
>[    0.996952] sd 0:0:0:0: [sda] Write Protect is off
>[    0.996953] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    0.997063] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    0.997336] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    0.997342] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    0.998400] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    0.998429] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    0.999446] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    0.999450] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.000521]  sda: sda1 sda2 sda3
>[    1.000986] sd 0:0:0:0: [sda] Attached SCSI disk
>[    1.002447] usb 1-2: New USB device found, idVendor=05e3, idProduct=0608
>[    1.002448] usb 1-2: New USB device strings: Mfr=0, Product=1, SerialNumber=0
>[    1.002449] usb 1-2: Product: USB2.0 Hub
>[    1.002803] hub 1-2:1.0: USB hub found
>[    1.002884] hub 1-2:1.0: 4 ports detected
>[    1.003612] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.003618] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.004639] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.004649] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    1.005655] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    1.005658] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.112460] usb 1-4: new high-speed USB device number 3 using xhci_hcd
>[    1.140012] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 0000006a
>[    1.140012] [drm:wait_panel_status] Wait complete
>[    1.140013] [drm:wait_panel_on] Wait for panel power on
>[    1.140015] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000006b
>[    1.199006] [drm:wait_panel_status] Wait complete
>[    1.199725] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[    1.199725] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[    1.199944] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[    1.200458] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[    1.200494] [drm:skylake_pfit_enable] for crtc_state = ffff88046717e000
>[    1.200539] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[    1.200542] [drm:intel_enable_pipe] enabling pipe A
>[    1.200549] [drm:intel_edp_backlight_on] 
>[    1.200550] [drm:intel_panel_enable_backlight] pipe A
>[    1.200551] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000
>[    1.206870] [drm:intel_psr_enable] PSR not supported on this platform
>[    1.206871] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[    1.206890] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[    1.206891] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[    1.207623] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[    1.207623] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[    1.211027] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[    1.218663] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[    1.218701] [drm:skylake_pfit_enable] for crtc_state = ffff88046717e800
>[    1.218748] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[    1.218750] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[    1.218751] [drm:intel_enable_pipe] enabling pipe B
>[    1.218759] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[    1.218760] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[    1.218769] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[    1.218769] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[    1.222649] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[    1.222649] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[    1.227095] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[    1.227095] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[    1.227423] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[    1.227949] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[    1.227949] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[    1.230457] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[    1.230495] [drm:skylake_pfit_enable] for crtc_state = ffff88046717f000
>[    1.230545] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[    1.230546] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[    1.230547] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[    1.230549] [drm:intel_enable_pipe] enabling pipe C
>[    1.234694] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[    1.234697] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[    1.234708] [drm:intel_ddi_get_config] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[    1.234712] [drm:verify_single_dpll_state] PORT PLL A
>[    1.234720] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[    1.234722] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[    1.234730] [drm:verify_single_dpll_state] PORT PLL B
>[    1.234737] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[    1.234738] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[    1.234747] [drm:verify_single_dpll_state] PORT PLL C
>[    1.234767] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    1.234768] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[    1.234769] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[    1.238830] Console: switching to colour frame buffer device 240x75
>[    1.238842] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    1.238843] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[    1.238843] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[    1.247785] [drm:drm_fb_helper_hotplug_event] 
>[    1.247785] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1]
>[    1.247786] [drm:intel_dp_detect] [CONNECTOR:39:eDP-1]
>[    1.247937] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[    1.248012] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[    1.248138] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    1.248139] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes :
>[    1.248141] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[    1.248141] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[    1.248142] [drm:intel_dp_detect] [CONNECTOR:47:DP-1]
>[    1.248256] usb 1-4: New USB device found, idVendor=0b95, idProduct=7720
>[    1.248258] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
>[    1.248258] usb 1-4: Product: AX88772 
>[    1.248259] usb 1-4: SerialNumber: 00D92D
>[    1.248288] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[    1.248591] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
>[    1.248592] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    1.248593] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[    1.248594] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[    1.248827] [drm:intel_dp_probe_mst] Sink is not MST capable
>[    1.248890] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.248897] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.249919] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.249928] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    1.251323] [drm:drm_edid_to_eld] ELD monitor DELL 2408WFP
>[    1.251324] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[    1.251324] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    1.251334] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[    1.251334] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    1.251335] [drm:drm_mode_debug_printmodeline] Modeline 122:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[    1.251336] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[    1.251337] [drm:drm_mode_debug_printmodeline] Modeline 134:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[    1.251337] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    1.251339] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes :
>[    1.251340] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[    1.251341] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    1.251342] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    1.251344] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    1.251345] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    1.251346] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[    1.251347] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    1.251348] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    1.251349] [drm:drm_mode_debug_printmodeline] Modeline 69:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    1.251350] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    1.251351] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    1.251352] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    1.251353] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    1.251354] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    1.251355] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    1.251356] [drm:drm_mode_debug_printmodeline] Modeline 89:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    1.251357] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    1.251358] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    1.251359] [drm:drm_mode_debug_printmodeline] Modeline 90:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    1.251360] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    1.251361] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    1.251362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1]
>[    1.251362] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-1]
>[    1.251403] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    1.251403] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    1.251407] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    1.251412] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.252419] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    1.252420] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    1.252459] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    1.252460] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    1.252519] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    1.252520] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected
>[    1.252521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2]
>[    1.252522] [drm:intel_dp_detect] [CONNECTOR:54:DP-2]
>[    1.252998] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[    1.253088] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[    1.253090] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[    1.253090] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[    1.253091] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[    1.253217] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    1.253220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes :
>[    1.253222] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    1.253223] [drm:drm_mode_debug_printmodeline] Modeline 84:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[    1.253224] [drm:drm_mode_debug_printmodeline] Modeline 85:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[    1.253225] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    1.253226] [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[    1.253227] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    1.253228] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    1.253229] [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    1.253230] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    1.253231] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    1.253232] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    1.253233] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2]
>[    1.253233] [drm:intel_hdmi_detect] [CONNECTOR:58:HDMI-A-2]
>[    1.253272] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    1.253273] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    1.253283] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    1.254641] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    1.254642] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    1.255687] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    1.255689] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    1.255730] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    1.255733] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected
>[    1.255736] [drm:drm_setup_crtcs] 
>[    1.255737] [drm:drm_enable_connectors] connector 39 enabled? yes
>[    1.255738] [drm:drm_enable_connectors] connector 47 enabled? yes
>[    1.255739] [drm:drm_enable_connectors] connector 51 enabled? no
>[    1.255740] [drm:drm_enable_connectors] connector 54 enabled? yes
>[    1.255741] [drm:drm_enable_connectors] connector 58 enabled? no
>[    1.255742] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1
>[    1.255743] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0
>[    1.255745] [drm:intel_fb_initial_config] connector eDP-1 on [CRTC:26:pipe A]: 1920x1080
>[    1.255746] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1
>[    1.255747] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0
>[    1.255748] [drm:intel_fb_initial_config] connector DP-1 on [CRTC:31:pipe B]: 1920x1200
>[    1.255749] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[    1.255750] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-2
>[    1.255755] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-2 0
>[    1.255756] [drm:intel_fb_initial_config] connector DP-2 on [CRTC:36:pipe C]: 1920x1080
>[    1.255757] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
>[    1.255758] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 26 (0,0)
>[    1.255760] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[    1.255761] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0)
>[    1.255774] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    1.255775] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[    1.255776] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[    1.309619] usb 1-2.1: new low-speed USB device number 4 using xhci_hcd
>[    1.388048] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x3f97b6076f1, max_idle_ns: 440795317110 ns
>[    1.389430] clocksource: Switched to clocksource tsc
>[    1.398159] usb 1-2.1: New USB device found, idVendor=04b3, idProduct=310c
>[    1.399536] usb 1-2.1: New USB device strings: Mfr=0, Product=2, SerialNumber=0
>[    1.400904] usb 1-2.1: Product: USB Optical Mouse
>[    1.406380] hidraw: raw HID events driver (C) Jiri Kosina
>[    1.409051] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.410438] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.412845] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.414251] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    1.416627] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    1.417981] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.422766] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.424121] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.425792] usbcore: registered new interface driver usbhid
>[    1.427139] usbhid: USB HID core driver
>[    1.429692] input: USB Optical Mouse as /devices/pci0000:00/0000:00:15.0/usb1/1-2/1-2.1/1-2.1:1.0/0003:04B3:310C.0001/input/input3
>[    1.431293] hid-generic 0003:04B3:310C.0001: input,hidraw0: USB HID v1.11 Mouse [USB Optical Mouse] on usb-0000:00:15.0-2.1/input0
>[    1.433715] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.435113] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    1.438436] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    1.439825] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.442222] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.443591] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.509353] usb 1-7: new full-speed USB device number 5 using xhci_hcd
>[    1.637664] usb 1-7: New USB device found, idVendor=8087, idProduct=0a2a
>[    1.639036] usb 1-7: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    1.643168] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.644568] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    1.646984] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    1.648343] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.650739] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.652104] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.709352] usb 1-2.4: new low-speed USB device number 6 using xhci_hcd
>[    1.801048] usb 1-2.4: New USB device found, idVendor=03f0, idProduct=0024
>[    1.802411] usb 1-2.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    1.803774] usb 1-2.4: Product: HP Basic USB Keyboard
>[    1.805128] usb 1-2.4: Manufacturer: CHICONY
>[    1.811116] input: CHICONY HP Basic USB Keyboard as /devices/pci0000:00/0000:00:15.0/usb1/1-2/1-2.4/1-2.4:1.0/0003:03F0:0024.0002/input/input4
>[    1.867971] hid-generic 0003:03F0:0024.0002: input,hidraw1: USB HID v1.11 Keyboard [CHICONY HP Basic USB Keyboard] on usb-0000:00:15.0-2.4/input0
>[    1.870286] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.871705] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    1.874229] [drm] RC6 on
>[    1.875651] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    1.877066] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.879508] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    1.880919] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    1.883358] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    1.884782] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    3.749351] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[    3.749354] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[    6.345498] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
>[    6.414375] systemd[1]: systemd 229 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN)
>[    6.415963] systemd[1]: Detected architecture x86-64.
>[    6.423879] systemd[1]: Set hostname to <gfx-072>.
>[    6.461889] systemd[1]: Listening on udev Kernel Socket.
>[    6.465591] systemd[1]: Created slice User and Session Slice.
>[    6.469156] systemd[1]: Reached target Remote File Systems (Pre).
>[    6.472725] systemd[1]: Reached target Remote File Systems.
>[    6.476301] systemd[1]: Listening on fsck to fsckd communication Socket.
>[    6.479885] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>[    6.483434] systemd[1]: Listening on Syslog Socket.
>[    6.487076] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
>[    6.490713] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
>[    6.494354] systemd[1]: Listening on Journal Socket.
>[    6.497963] systemd[1]: Listening on Journal Socket (/dev/log).
>[    6.501600] systemd[1]: Listening on udev Control Socket.
>[    6.505218] systemd[1]: Listening on Journal Audit Socket.
>[    6.508816] systemd[1]: Reached target Encrypted Volumes.
>[    6.512390] systemd[1]: Created slice System Slice.
>[    6.516134] systemd[1]: Started Braille Device Support.
>[    6.522299] systemd[1]: Created slice system-getty.slice.
>[    6.526951] systemd[1]: Starting Journal Service...
>[    6.539043] systemd[1]: Starting Create list of required static device nodes for the current kernel...
>[    6.544326] systemd[1]: Starting Uncomplicated firewall...
>[    6.553279] systemd[1]: Reached target Slices.
>[    6.562502] systemd[1]: Started Read required files in advance.
>[    6.567406] systemd[1]: Mounting Huge Pages File System...
>[    6.579331] systemd[1]: Mounting POSIX Message Queue File System...
>[    6.589304] systemd[1]: Starting Load Kernel Modules...
>[    6.601220] systemd[1]: Mounting Debug File System...
>[    6.603157] lp: driver loaded but no devices found
>[    6.608119] ppdev: user-space parallel port driver
>[    6.609450] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    6.609455] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.610475] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    6.610479] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.611491] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    6.611500] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    6.613420] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    6.613427] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.614452] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    6.614459] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.615472] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    6.615481] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    6.637193] systemd[1]: Created slice system-systemd\x2dfsck.slice.
>[    6.642139] systemd[1]: Mounted Huge Pages File System.
>[    6.645327] systemd[1]: Mounted Debug File System.
>[    6.648502] systemd[1]: Mounted POSIX Message Queue File System.
>[    6.651740] systemd[1]: Started Journal Service.
>[    6.721554] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
>[    6.769859] systemd-journald[219]: Received request to flush runtime journal from PID 1
>[    6.899142] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
>[    6.906407] mei_me 0000:00:0f.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.922231] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    6.922238] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.923270] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    6.923274] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.924299] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    6.924308] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    6.931075] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=92160/96000
>[    6.931076] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[    6.981162] Bluetooth: Core ver 2.21
>[    6.981173] NET: Registered protocol family 31
>[    6.981173] Bluetooth: HCI device and connection manager initialized
>[    6.981176] Bluetooth: HCI socket layer initialized
>[    6.981177] Bluetooth: L2CAP socket layer initialized
>[    6.981180] Bluetooth: SCO socket layer initialized
>[    6.992948] Intel(R) Wireless WiFi driver for Linux
>[    6.992950] Copyright(c) 2003- 2015 Intel Corporation
>[    6.993056] iwlwifi 0000:02:00.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.997169] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    6.997176] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.998203] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    6.998207] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    6.999222] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    6.999232] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.000781] iwlwifi 0000:02:00.0: Direct firmware load for iwlwifi-7265D-21.ucode failed with error -2
>[    7.000783] iwlwifi 0000:02:00.0: Falling back to user helper
>[    7.021289] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    7.021296] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.022323] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    7.022327] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.023341] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    7.023351] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.038540] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    7.038548] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.039577] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    7.039581] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.040594] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    7.040604] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.042174] usbcore: registered new interface driver btusb
>[    7.048620] Bluetooth: hci0: read Intel version: 370810011003110e00
>[    7.048988] Bluetooth: hci0: Intel Bluetooth firmware file: intel/ibt-hw-37.8.10-fw-1.10.3.11.e.bseq
>[    7.069478] Adding 3994620k swap on /dev/sda3.  Priority:-1 extents:1 across:3994620k SSFS
>[    7.106790] random: nonblocking pool is initialized
>[    7.128009] Bluetooth: hci0: Intel Bluetooth firmware patch completed and activated
>[    7.188441] SSE version of gcm_enc/dec engaged.
>[    7.315707] audit: type=1400 audit(1467072032.392:2): apparmor="STATUS" operation="profile_load" name="/usr/lib/lightdm/lightdm-guest-session" pid=420 comm="apparmor_parser"
>[    7.315712] audit: type=1400 audit(1467072032.392:3): apparmor="STATUS" operation="profile_load" name="chromium" pid=420 comm="apparmor_parser"
>[    7.330418] audit: type=1400 audit(1467072032.408:4): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=425 comm="apparmor_parser"
>[    7.330423] audit: type=1400 audit(1467072032.408:5): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=425 comm="apparmor_parser"
>[    7.330426] audit: type=1400 audit(1467072032.408:6): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-helper" pid=425 comm="apparmor_parser"
>[    7.330429] audit: type=1400 audit(1467072032.408:7): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=425 comm="apparmor_parser"
>[    7.355671] snd_hda_intel 0000:00:0e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.355700] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[    7.357667] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    7.357676] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.358705] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    7.358709] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.359723] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    7.359735] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.363795] audit: type=1400 audit(1467072032.440:8): apparmor="STATUS" operation="profile_load" name="/usr/bin/evince" pid=436 comm="apparmor_parser"
>[    7.363798] audit: type=1400 audit(1467072032.440:9): apparmor="STATUS" operation="profile_load" name="sanitized_helper" pid=436 comm="apparmor_parser"
>[    7.363800] audit: type=1400 audit(1467072032.440:10): apparmor="STATUS" operation="profile_load" name="/usr/bin/evince-previewer" pid=436 comm="apparmor_parser"
>[    7.363802] audit: type=1400 audit(1467072032.440:11): apparmor="STATUS" operation="profile_load" name="sanitized_helper" pid=436 comm="apparmor_parser"
>[    7.406175] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[    7.406177] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[    7.406179] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[    7.406180] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[    7.406181] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[    7.406182] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[    7.409361] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    7.409368] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.410393] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    7.410397] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.411412] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    7.411422] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.431773] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    7.431780] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.432804] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    7.432809] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.434215] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    7.434229] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.440611] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input5
>[    7.440651] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input6
>[    7.440688] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input7
>[    7.440723] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input8
>[    7.440758] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input9
>[    7.452692] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    7.452693] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[    7.452694] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[    7.516405] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    7.516406] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[    7.516407] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[    7.550324] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    7.550331] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.551355] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    7.551360] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    7.552373] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    7.552382] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    7.617533] iwlwifi 0000:02:00.0: Direct firmware load for iwlwifi-7265D-20.ucode failed with error -2
>[    7.617535] iwlwifi 0000:02:00.0: Falling back to user helper
>[    7.714810] iwlwifi 0000:02:00.0: Direct firmware load for iwlwifi-7265D-19.ucode failed with error -2
>[    7.714811] iwlwifi 0000:02:00.0: Falling back to user helper
>[    7.719529] iwlwifi 0000:02:00.0: Direct firmware load for iwlwifi-7265D-18.ucode failed with error -2
>[    7.719529] iwlwifi 0000:02:00.0: Falling back to user helper
>[    7.730148] iwlwifi 0000:02:00.0: Direct firmware load for iwlwifi-7265D-17.ucode failed with error -2
>[    7.730149] iwlwifi 0000:02:00.0: Falling back to user helper
>[    7.759411] iwlwifi 0000:02:00.0: loaded firmware version 16.242414.0 op_mode iwlmvm
>[    7.846281] iwlwifi 0000:02:00.0: Detected Intel(R) Dual Band Wireless AC 7265, REV=0x210
>[    7.849626] iwlwifi 0000:02:00.0: L1 Enabled - LTR Enabled
>[    7.849830] iwlwifi 0000:02:00.0: L1 Enabled - LTR Enabled
>[    7.900991] ieee80211 phy0: Selected rate control algorithm 'iwl-mvm-rs'
>[    7.913754] iwlwifi 0000:02:00.0 wlp2s0: renamed from wlan0
>[    8.074772] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
>[    8.074774] Bluetooth: BNEP filters: protocol multicast
>[    8.074777] Bluetooth: BNEP socket layer initialized
>[    8.147031] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>[    8.163500] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>[    8.192144] IPv6: ADDRCONF(NETDEV_UP): wlp2s0: link is not ready
>[    8.193481] iwlwifi 0000:02:00.0: L1 Enabled - LTR Enabled
>[    8.193659] iwlwifi 0000:02:00.0: L1 Enabled - LTR Enabled
>[    8.221450] iwlwifi 0000:02:00.0: L1 Enabled - LTR Enabled
>[    8.221613] iwlwifi 0000:02:00.0: L1 Enabled - LTR Enabled
>[    8.227357] IPv6: ADDRCONF(NETDEV_UP): wlp2s0: link is not ready
>[    8.286080] IPv6: ADDRCONF(NETDEV_UP): wlp2s0: link is not ready
>[    8.977915] asix 1-4:1.0 eth0: register 'asix' at usb-0000:00:15.0-4, ASIX AX88772 USB 2.0 Ethernet, 00:10:60:31:c2:b6
>[    8.978205] usbcore: registered new interface driver asix
>[    8.978768] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a)
>[    8.978775] sdhci-pci 0000:00:1c.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    8.979802] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a)
>[    8.979806] sdhci-pci 0000:00:1e.0: can't find IRQ for PCI INT A; please try using pci=biosirq
>[    8.980819] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a)
>[    8.980829] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio
>[    9.021053] asix 1-4:1.0 enx00106031c2b6: renamed from eth0
>[    9.027136] IPv6: ADDRCONF(NETDEV_UP): enx00106031c2b6: link is not ready
>[    9.028199] asix 1-4:1.0 enx00106031c2b6: link down
>[    9.028778] IPv6: ADDRCONF(NETDEV_UP): enx00106031c2b6: link is not ready
>[    9.424931] IPv6: ADDRCONF(NETDEV_CHANGE): enx00106031c2b6: link becomes ready
>[    9.425096] asix 1-4:1.0 enx00106031c2b6: link up, 100Mbps, full-duplex, lpa 0xC5E1
>[   17.281225] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   17.281227] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   17.281227] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   29.346387] kms_pipe_crc_basic: executing
>[   29.346588] [drm:i915_gem_open] 
>[   29.346721] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   29.346724] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   29.346785] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   29.346787] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   29.346800] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   29.346802] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   29.346812] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   29.346813] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   29.347146] [drm:i915_gem_open] 
>[   29.347302] [drm:i915_gem_open] 
>[   29.348429] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   29.349298] [drm:drm_mode_addfb2] [FB:96]
>[   29.353725] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   29.353729] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   29.353737] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   29.360341] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   29.380943] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   29.385147] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   29.385150] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   29.385152] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   29.385180] [drm:intel_edp_backlight_off] 
>[   29.585350] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   29.585362] [drm:intel_disable_pipe] disabling pipe A
>[   29.589420] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   29.589423] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   29.589463] [drm:edp_panel_off] Turn eDP port A panel power off
>[   29.589464] [drm:wait_panel_off] Wait for panel power off time
>[   29.589466] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   29.602605] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   29.602607] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   29.602608] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   29.602618] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   29.613348] [drm:wait_panel_status] Wait complete
>[   29.613351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   29.613364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   29.613369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   29.613373] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   29.613376] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   29.613377] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   29.613378] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   29.613379] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   29.613380] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   29.613380] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   29.613381] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   29.613382] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   29.613383] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   29.613384] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   29.613385] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   29.613387] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   29.613389] [drm:verify_single_dpll_state] PORT PLL A
>[   29.613390] [drm:verify_single_dpll_state] PORT PLL B
>[   29.613394] [drm:verify_single_dpll_state] PORT PLL C
>[   29.613402] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   29.613403] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   29.613415] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   29.613416] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   29.613421] [drm:intel_power_well_disable] disabling dpio-common-a
>[   29.613423] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   29.613645] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   29.613669] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   29.618796] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   29.622001] [drm:drm_mode_addfb2] [FB:96]
>[   29.625695] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   29.625699] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   29.625706] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   29.625707] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   29.625709] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   29.625719] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   29.625721] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   29.625722] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   29.625724] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   29.625725] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e8800 for pipe A
>[   29.625726] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   29.625727] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   29.625728] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   29.625729] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   29.625730] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   29.625731] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   29.625732] [drm:intel_dump_pipe_config] requested mode:
>[   29.625733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   29.625734] [drm:intel_dump_pipe_config] adjusted mode:
>[   29.625736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   29.625743] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   29.625744] [drm:intel_dump_pipe_config] port clock: 270000
>[   29.625745] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   29.625746] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   29.625747] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   29.625748] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   29.625749] [drm:intel_dump_pipe_config] ips: 0
>[   29.625749] [drm:intel_dump_pipe_config] double wide: 0
>[   29.625751] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   29.625752] [drm:intel_dump_pipe_config] planes on this crtc
>[   29.625752] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   29.625753] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   29.625754] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   29.625755] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   29.625757] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   29.625759] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   29.625761] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   29.625762] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   29.625763] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   29.625854] [drm:intel_power_well_enable] enabling dpio-common-a
>[   29.633361] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   29.633362] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   29.633363] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   29.633364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   29.633365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   29.633366] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   29.633367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   29.633367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   29.633368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   29.633369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   29.633372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   29.633374] [drm:verify_single_dpll_state] PORT PLL A
>[   29.633375] [drm:verify_single_dpll_state] PORT PLL B
>[   29.633379] [drm:verify_single_dpll_state] PORT PLL C
>[   29.633387] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   29.633388] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   29.633415] [drm:edp_panel_on] Turn eDP port A panel power on
>[   29.633416] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   30.097368] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   30.097369] [drm:wait_panel_status] Wait complete
>[   30.097371] [drm:wait_panel_on] Wait for panel power on
>[   30.097372] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[   30.124018] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   30.124020] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   30.124022] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   30.124032] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   30.157347] [drm:wait_panel_status] Wait complete
>[   30.157351] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   30.157354] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   30.158071] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.158072] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.158291] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.158809] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.158848] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   30.158899] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   30.159210] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   30.163185] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.163188] [drm:intel_enable_pipe] enabling pipe A
>[   30.163191] [drm:intel_edp_backlight_on] 
>[   30.163192] [drm:intel_panel_enable_backlight] pipe A
>[   30.163194] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   30.165434] [drm:intel_psr_enable] PSR not supported on this platform
>[   30.165435] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   30.165449] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.165452] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.165453] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.165462] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.165467] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.165468] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.167341] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.167344] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.167359] [drm:verify_single_dpll_state] PORT PLL A
>[   30.171576] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   30.192170] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   30.196372] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.196375] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.196390] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.196401] [drm:intel_edp_backlight_off] 
>[   30.397350] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   30.397362] [drm:intel_disable_pipe] disabling pipe A
>[   30.401448] [drm:edp_panel_off] Turn eDP port A panel power off
>[   30.401449] [drm:wait_panel_off] Wait for panel power off time
>[   30.401451] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060
>[   30.414573] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   30.414575] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   30.414577] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   30.414587] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   30.425348] [drm:wait_panel_status] Wait complete
>[   30.425352] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   30.425366] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   30.425371] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.425373] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.425375] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.425377] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.425378] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.425379] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.425380] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.425380] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.425381] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.425382] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.425383] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.425384] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.425385] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.425387] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.425389] [drm:verify_single_dpll_state] PORT PLL A
>[   30.425390] [drm:verify_single_dpll_state] PORT PLL B
>[   30.425395] [drm:verify_single_dpll_state] PORT PLL C
>[   30.425403] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.425405] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.425416] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.425417] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.425422] [drm:intel_power_well_disable] disabling dpio-common-a
>[   30.425424] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.429900] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.432374] [drm:drm_mode_addfb2] [FB:96]
>[   30.436401] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.436405] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   30.436420] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   30.436421] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.436423] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   30.436426] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   30.436434] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   30.436435] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.436437] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   30.436438] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   30.436438] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.436440] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.436441] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   30.436442] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.436443] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   30.436443] [drm:intel_dump_pipe_config] requested mode:
>[   30.436445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   30.436446] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.436447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   30.436449] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   30.436449] [drm:intel_dump_pipe_config] port clock: 162000
>[   30.436450] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   30.436451] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   30.436452] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.436453] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.436454] [drm:intel_dump_pipe_config] ips: 0
>[   30.436454] [drm:intel_dump_pipe_config] double wide: 0
>[   30.436456] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.436457] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.436458] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   30.436459] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   30.436460] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   30.436461] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   30.436462] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.436465] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.436466] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   30.436468] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   30.436469] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   30.436470] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.436471] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   30.436575] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   30.436634] [drm:intel_disable_pipe] disabling pipe B
>[   30.441400] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   30.441406] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   30.441409] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.441413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.441415] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.441416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.441416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.441417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.441418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.441419] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.441420] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.441420] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.441421] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.441422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.441424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.441425] [drm:verify_single_dpll_state] PORT PLL A
>[   30.441427] [drm:verify_single_dpll_state] PORT PLL B
>[   30.441427] [drm:verify_single_dpll_state] PORT PLL C
>[   30.441434] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   30.441435] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   30.442166] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.442167] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.445859] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.453349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.453390] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   30.453439] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.453442] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.453443] [drm:intel_enable_pipe] enabling pipe A
>[   30.453447] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   30.453449] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   30.453505] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.453507] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.457600] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.457603] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.457614] [drm:verify_single_dpll_state] PORT PLL B
>[   30.457620] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   30.461846] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   30.482443] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   30.486651] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.486654] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.486655] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.486682] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   30.486690] [drm:intel_disable_pipe] disabling pipe A
>[   30.493424] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   30.493429] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   30.493433] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.493435] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.493437] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.493438] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.493439] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.493439] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.493440] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.493441] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.493442] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.493442] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.493443] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.493444] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.493446] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.493447] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.493449] [drm:verify_single_dpll_state] PORT PLL A
>[   30.493450] [drm:verify_single_dpll_state] PORT PLL B
>[   30.493451] [drm:verify_single_dpll_state] PORT PLL C
>[   30.493457] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.493460] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.493467] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.495628] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.498521] [drm:drm_mode_addfb2] [FB:96]
>[   30.502487] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.502491] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   30.502506] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   30.502507] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.502509] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   30.502512] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   30.502513] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   30.502514] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.502522] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e8800 for pipe A
>[   30.502523] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   30.502524] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.502525] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.502526] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   30.502527] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.502528] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   30.502529] [drm:intel_dump_pipe_config] requested mode:
>[   30.502530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   30.502531] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.502533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   30.502534] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   30.502535] [drm:intel_dump_pipe_config] port clock: 162000
>[   30.502536] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   30.502537] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   30.502538] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.502538] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.502539] [drm:intel_dump_pipe_config] ips: 0
>[   30.502540] [drm:intel_dump_pipe_config] double wide: 0
>[   30.502541] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.502542] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.502543] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   30.502544] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   30.502545] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   30.502546] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   30.502548] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.502550] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.502552] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   30.502553] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   30.502554] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.502652] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.502654] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.502654] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.502655] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.502656] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.502657] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.502658] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.502658] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.502659] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.502660] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.502661] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.502663] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.502664] [drm:verify_single_dpll_state] PORT PLL A
>[   30.502665] [drm:verify_single_dpll_state] PORT PLL B
>[   30.502666] [drm:verify_single_dpll_state] PORT PLL C
>[   30.502673] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   30.502674] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   30.503409] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.503410] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.506297] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.513351] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.513398] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   30.513450] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   30.514773] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.514782] [drm:intel_enable_pipe] enabling pipe A
>[   30.514786] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   30.514787] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   30.514846] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.514848] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.514853] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.514855] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.518934] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.518938] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.518949] [drm:verify_single_dpll_state] PORT PLL B
>[   30.523172] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   30.543780] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   30.547986] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.547989] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.547991] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.548017] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   30.548025] [drm:intel_disable_pipe] disabling pipe A
>[   30.553401] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   30.553407] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   30.553410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.553412] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.553413] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.553415] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.553416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.553416] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.553417] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.553418] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.553419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.553419] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.553420] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.553421] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.553423] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.553424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.553426] [drm:verify_single_dpll_state] PORT PLL A
>[   30.553427] [drm:verify_single_dpll_state] PORT PLL B
>[   30.553428] [drm:verify_single_dpll_state] PORT PLL C
>[   30.553434] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.553436] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.553444] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.558063] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.560507] [drm:drm_mode_addfb2] [FB:96]
>[   30.564187] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.564190] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   30.564206] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   30.564207] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.564209] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   30.564217] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   30.564218] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   30.564219] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.564221] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   30.564222] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   30.564223] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.564224] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.564225] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   30.564226] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.564227] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   30.564228] [drm:intel_dump_pipe_config] requested mode:
>[   30.564229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   30.564230] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.564232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   30.564233] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   30.564234] [drm:intel_dump_pipe_config] port clock: 162000
>[   30.564234] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   30.564235] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   30.564236] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.564237] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.564238] [drm:intel_dump_pipe_config] ips: 0
>[   30.564239] [drm:intel_dump_pipe_config] double wide: 0
>[   30.564240] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.564241] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.564242] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   30.564243] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   30.564244] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   30.564245] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   30.564246] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.564249] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.564250] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   30.564252] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   30.564253] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   30.564254] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.564255] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   30.564345] [drm:intel_disable_pipe] disabling pipe C
>[   30.569401] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   30.569406] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   30.569409] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.569410] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.569412] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.569412] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.569413] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.569414] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.569415] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.569416] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.569416] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.569417] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.569418] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.569419] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.569421] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.569422] [drm:verify_single_dpll_state] PORT PLL A
>[   30.569423] [drm:verify_single_dpll_state] PORT PLL B
>[   30.569424] [drm:verify_single_dpll_state] PORT PLL C
>[   30.569427] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   30.569428] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   30.570158] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.570160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.574069] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   30.574071] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.574295] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.574822] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   30.574823] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   30.577437] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.577477] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   30.577523] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.577526] [drm:intel_enable_pipe] enabling pipe A
>[   30.577538] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.581675] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   30.581677] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.581689] [drm:verify_single_dpll_state] PORT PLL C
>[   30.581694] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   30.585900] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   30.606498] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   30.610701] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   30.610703] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.610716] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.610733] [drm:intel_disable_pipe] disabling pipe A
>[   30.617400] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   30.617405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   30.617408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   30.625351] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   30.625353] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.625361] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.625362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.625363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.625364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.625365] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.625366] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.625367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.625368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.625369] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.625370] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.625371] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.625372] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   30.625373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.625374] [drm:verify_single_dpll_state] PORT PLL A
>[   30.625375] [drm:verify_single_dpll_state] PORT PLL B
>[   30.625376] [drm:verify_single_dpll_state] PORT PLL C
>[   30.625380] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   30.625381] [drm:intel_power_well_disable] disabling power well 2
>[   30.625384] [drm:skl_set_power_well] Disabling power well 2
>[   30.625386] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.625389] [drm:intel_power_well_disable] disabling DC off
>[   30.625390] [drm:gen9_enable_dc5] Enabling DC5
>[   30.625391] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   30.625393] [drm:intel_power_well_disable] disabling always-on
>[   30.626943] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.627264] [drm:drm_mode_addfb2] [FB:96]
>[   30.631202] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   30.631206] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   30.631213] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   30.631214] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.631216] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   30.631218] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   30.631219] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   30.631220] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.631221] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e8800 for pipe A
>[   30.631222] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   30.631223] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.631224] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.631225] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   30.631227] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.631227] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   30.631228] [drm:intel_dump_pipe_config] requested mode:
>[   30.631230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   30.631239] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.631240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   30.631248] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   30.631248] [drm:intel_dump_pipe_config] port clock: 162000
>[   30.631249] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   30.631250] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   30.631251] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.631252] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.631253] [drm:intel_dump_pipe_config] ips: 0
>[   30.631253] [drm:intel_dump_pipe_config] double wide: 0
>[   30.631255] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.631256] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.631257] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   30.631258] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   30.631259] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   30.631260] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   30.631262] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.631264] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.631266] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   30.631267] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   30.631269] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.631352] [drm:intel_power_well_enable] enabling always-on
>[   30.631353] [drm:intel_power_well_enable] enabling DC off
>[   30.631416] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   30.631419] [drm:intel_power_well_enable] enabling power well 2
>[   30.631420] [drm:skl_set_power_well] Enabling power well 2
>[   30.631423] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   30.631424] [drm:intel_power_well_enable] enabling dpio-common-a
>[   30.641353] [drm:intel_power_well_disable] disabling dpio-common-a
>[   30.641364] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   30.649351] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   30.649353] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.649361] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.649362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.649363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.649364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.649364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.649365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.649366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.649367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.649368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.649369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.649370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.649371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.649373] [drm:verify_single_dpll_state] PORT PLL A
>[   30.649374] [drm:verify_single_dpll_state] PORT PLL B
>[   30.649375] [drm:verify_single_dpll_state] PORT PLL C
>[   30.649380] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   30.649381] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   30.650118] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.650119] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.654050] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   30.654051] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.654276] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.654803] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   30.654804] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   30.657446] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.657487] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   30.657533] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.657535] [drm:intel_enable_pipe] enabling pipe A
>[   30.657557] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.657561] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.661694] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   30.661696] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.661709] [drm:verify_single_dpll_state] PORT PLL C
>[   30.665920] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   30.686518] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   30.690742] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   30.690745] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.690747] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.690756] [drm:intel_disable_pipe] disabling pipe A
>[   30.697400] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   30.697406] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   30.697408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   30.705351] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   30.705353] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.705361] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.705362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.705363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.705364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.705364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.705366] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.705366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.705367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.705368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   30.705369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   30.705370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.705372] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   30.705373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.705374] [drm:verify_single_dpll_state] PORT PLL A
>[   30.705375] [drm:verify_single_dpll_state] PORT PLL B
>[   30.705376] [drm:verify_single_dpll_state] PORT PLL C
>[   30.705379] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   30.705380] [drm:intel_power_well_disable] disabling power well 2
>[   30.705383] [drm:skl_set_power_well] Disabling power well 2
>[   30.705385] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   30.705387] [drm:intel_power_well_disable] disabling DC off
>[   30.705389] [drm:gen9_enable_dc5] Enabling DC5
>[   30.705390] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   30.705392] [drm:intel_power_well_disable] disabling always-on
>[   30.706636] kms_pipe_crc_basic: exiting, ret=0
>[   30.706744] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   30.706745] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.706747] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.706747] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   30.706750] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   30.706750] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   30.706751] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.706752] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e8800 for pipe A
>[   30.706752] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   30.706753] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.706754] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.706754] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   30.706755] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.706755] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   30.706756] [drm:intel_dump_pipe_config] requested mode:
>[   30.706757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   30.706757] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.706758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   30.706759] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   30.706760] [drm:intel_dump_pipe_config] port clock: 270000
>[   30.706760] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   30.706761] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   30.706761] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.706762] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.706762] [drm:intel_dump_pipe_config] ips: 0
>[   30.706762] [drm:intel_dump_pipe_config] double wide: 0
>[   30.706764] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.706764] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.706764] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   30.706765] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   30.706765] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   30.706766] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   30.706767] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   30.706767] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.706768] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   30.706769] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   30.706770] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   30.706770] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.706771] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8804694eb800 for pipe B
>[   30.706771] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   30.706772] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.706772] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.706773] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   30.706774] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.706774] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   30.706775] [drm:intel_dump_pipe_config] requested mode:
>[   30.706776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   30.706776] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.706777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   30.706778] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   30.706778] [drm:intel_dump_pipe_config] port clock: 162000
>[   30.706779] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   30.706779] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   30.706780] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.706780] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.706780] [drm:intel_dump_pipe_config] ips: 0
>[   30.706781] [drm:intel_dump_pipe_config] double wide: 0
>[   30.706782] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.706782] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.706784] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   30.706785] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   30.706785] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   30.706785] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   30.706786] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   30.706786] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   30.706787] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   30.706787] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   30.706788] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   30.706789] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   30.706789] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   30.706790] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   30.706790] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e9000 for pipe C
>[   30.706791] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   30.706791] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   30.706792] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   30.706793] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   30.706793] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   30.706794] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   30.706794] [drm:intel_dump_pipe_config] requested mode:
>[   30.706795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   30.706795] [drm:intel_dump_pipe_config] adjusted mode:
>[   30.706796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   30.706797] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   30.706798] [drm:intel_dump_pipe_config] port clock: 162000
>[   30.706798] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   30.706798] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   30.706799] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   30.706799] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   30.706800] [drm:intel_dump_pipe_config] ips: 0
>[   30.706800] [drm:intel_dump_pipe_config] double wide: 0
>[   30.706801] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   30.706801] [drm:intel_dump_pipe_config] planes on this crtc
>[   30.706803] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   30.706803] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   30.706804] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   30.706804] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   30.706804] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   30.706806] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   30.706807] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   30.706808] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   30.706809] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   30.706810] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   30.706811] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   30.706812] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   30.706812] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   30.706813] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   30.706813] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   30.706814] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   30.706814] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   30.706815] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   30.706825] [drm:intel_power_well_enable] enabling always-on
>[   30.706825] [drm:intel_power_well_enable] enabling DC off
>[   30.706888] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   30.706891] [drm:intel_power_well_enable] enabling dpio-common-a
>[   30.713367] [drm:intel_power_well_enable] enabling power well 2
>[   30.713368] [drm:skl_set_power_well] Enabling power well 2
>[   30.717351] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   30.721361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   30.729350] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   30.729350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   30.729351] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   30.729352] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   30.729353] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   30.729353] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   30.729360] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   30.729360] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   30.729360] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   30.729361] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   30.729361] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   30.729363] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   30.729364] [drm:verify_single_dpll_state] PORT PLL A
>[   30.729365] [drm:verify_single_dpll_state] PORT PLL B
>[   30.729365] [drm:verify_single_dpll_state] PORT PLL C
>[   30.729370] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   30.729371] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   30.729393] [drm:edp_panel_on] Turn eDP port A panel power on
>[   30.729394] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   30.909350] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   30.909351] [drm:wait_panel_status] Wait complete
>[   30.909351] [drm:wait_panel_on] Wait for panel power on
>[   30.909353] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   30.936010] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   30.936011] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   30.936012] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   30.936015] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   30.969348] [drm:wait_panel_status] Wait complete
>[   30.969350] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   30.969352] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   30.970067] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.970068] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.970286] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.970800] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.970836] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   30.970882] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.970884] [drm:intel_enable_pipe] enabling pipe A
>[   30.970892] [drm:intel_edp_backlight_on] 
>[   30.970893] [drm:intel_panel_enable_backlight] pipe A
>[   30.970894] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   30.977348] [drm:intel_psr_enable] PSR not supported on this platform
>[   30.977349] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   30.977366] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   30.977367] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   30.978099] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.978100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.981574] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.989348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.989386] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   30.989434] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.989435] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.989437] [drm:intel_enable_pipe] enabling pipe B
>[   30.989449] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   30.989450] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   30.989503] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   30.989504] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   30.990236] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   30.990237] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.993789] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   30.993789] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   30.994013] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   30.994539] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   30.994539] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   30.997348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   30.997386] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9000
>[   30.997437] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   30.997438] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   30.997439] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   30.997441] [drm:intel_enable_pipe] enabling pipe C
>[   31.001588] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   31.001590] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   31.001603] [drm:verify_single_dpll_state] PORT PLL A
>[   31.001611] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   31.001612] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   31.001622] [drm:verify_single_dpll_state] PORT PLL B
>[   31.001628] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   31.001629] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   31.001637] [drm:verify_single_dpll_state] PORT PLL C
>[   31.006635] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.006637] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   31.006699] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.006702] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   31.006715] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.006717] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   31.006727] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.006728] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   31.048426] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   31.048429] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   31.048430] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   31.619799] kms_pipe_crc_basic: executing
>[   31.619992] [drm:i915_gem_open] 
>[   31.620120] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.620122] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   31.620184] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.620185] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   31.620197] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.620199] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   31.620211] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   31.620212] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   31.620552] [drm:i915_gem_open] 
>[   31.620706] [drm:i915_gem_open] 
>[   31.622138] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   31.623000] [drm:drm_mode_addfb2] [FB:96]
>[   31.626839] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   31.626843] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   31.626860] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   31.632598] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   31.653201] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   31.657412] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   31.657415] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   31.657416] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   31.657444] [drm:intel_edp_backlight_off] 
>[   31.861349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   31.861360] [drm:intel_disable_pipe] disabling pipe A
>[   31.865446] [drm:edp_panel_off] Turn eDP port A panel power off
>[   31.865447] [drm:wait_panel_off] Wait for panel power off time
>[   31.865449] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   31.878582] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   31.878584] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   31.878585] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   31.878595] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   31.889349] [drm:wait_panel_status] Wait complete
>[   31.889352] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   31.889364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   31.889369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   31.889371] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   31.889374] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   31.889375] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   31.889376] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   31.889377] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   31.889378] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   31.889378] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   31.889379] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   31.889380] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   31.889381] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   31.889382] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   31.889383] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   31.889385] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   31.889387] [drm:verify_single_dpll_state] PORT PLL A
>[   31.889388] [drm:verify_single_dpll_state] PORT PLL B
>[   31.889392] [drm:verify_single_dpll_state] PORT PLL C
>[   31.889401] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   31.889402] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   31.889411] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   31.889413] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   31.889419] [drm:intel_power_well_disable] disabling dpio-common-a
>[   31.889421] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   31.890685] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   31.890726] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   31.892972] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   31.895916] [drm:drm_mode_addfb2] [FB:96]
>[   31.899586] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   31.899589] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   31.899596] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   31.899597] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   31.899600] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   31.899601] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   31.899604] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   31.899604] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   31.899606] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   31.899607] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467143800 for pipe A
>[   31.899617] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   31.899624] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   31.899625] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   31.899626] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   31.899627] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   31.899628] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   31.899629] [drm:intel_dump_pipe_config] requested mode:
>[   31.899630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   31.899631] [drm:intel_dump_pipe_config] adjusted mode:
>[   31.899632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   31.899634] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   31.899635] [drm:intel_dump_pipe_config] port clock: 270000
>[   31.899635] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   31.899636] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   31.899637] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   31.899638] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   31.899639] [drm:intel_dump_pipe_config] ips: 0
>[   31.899640] [drm:intel_dump_pipe_config] double wide: 0
>[   31.899641] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   31.899642] [drm:intel_dump_pipe_config] planes on this crtc
>[   31.899643] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   31.899644] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   31.899645] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   31.899645] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   31.899647] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   31.899649] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   31.899651] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   31.899652] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   31.899654] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   31.899743] [drm:intel_power_well_enable] enabling dpio-common-a
>[   31.905362] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   31.905363] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   31.905364] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   31.905365] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   31.905366] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   31.905367] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   31.905368] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   31.905368] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   31.905369] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   31.905370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   31.905373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   31.905375] [drm:verify_single_dpll_state] PORT PLL A
>[   31.905376] [drm:verify_single_dpll_state] PORT PLL B
>[   31.905380] [drm:verify_single_dpll_state] PORT PLL C
>[   31.905388] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   31.905389] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   31.905414] [drm:edp_panel_on] Turn eDP port A panel power on
>[   31.905415] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   32.373350] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   32.373352] [drm:wait_panel_status] Wait complete
>[   32.373353] [drm:wait_panel_on] Wait for panel power on
>[   32.373361] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   32.400017] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   32.400019] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   32.400020] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   32.400032] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   32.425347] [drm:wait_panel_status] Wait complete
>[   32.425352] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   32.425360] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   32.426072] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   32.426073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.426291] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   32.426807] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   32.426844] [drm:skylake_pfit_enable] for crtc_state = ffff880467143800
>[   32.426898] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   32.427968] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   32.429503] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.429506] [drm:intel_enable_pipe] enabling pipe A
>[   32.429510] [drm:intel_edp_backlight_on] 
>[   32.429511] [drm:intel_panel_enable_backlight] pipe A
>[   32.429512] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   32.433434] [drm:intel_psr_enable] PSR not supported on this platform
>[   32.433435] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   32.433453] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.433455] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   32.433456] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.433466] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.433468] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   32.433469] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.433653] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.433656] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.433669] [drm:verify_single_dpll_state] PORT PLL A
>[   32.437899] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   32.458482] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   32.462686] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.462688] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.462690] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.462714] [drm:intel_edp_backlight_off] 
>[   32.665349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   32.665360] [drm:intel_disable_pipe] disabling pipe A
>[   32.669423] [drm:edp_panel_off] Turn eDP port A panel power off
>[   32.669424] [drm:wait_panel_off] Wait for panel power off time
>[   32.669426] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   32.682561] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   32.682563] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   32.682565] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   32.682575] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   32.701362] [drm:wait_panel_status] Wait complete
>[   32.701365] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   32.701371] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   32.701376] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   32.701378] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.701380] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.701382] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.701382] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.701383] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.701384] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.701385] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.701386] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.701386] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.701387] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.701388] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.701389] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.701391] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.701394] [drm:verify_single_dpll_state] PORT PLL A
>[   32.701395] [drm:verify_single_dpll_state] PORT PLL B
>[   32.701399] [drm:verify_single_dpll_state] PORT PLL C
>[   32.701407] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   32.701409] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.701418] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   32.701419] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.701425] [drm:intel_power_well_disable] disabling dpio-common-a
>[   32.701428] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.706823] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.711076] [drm:drm_mode_addfb2] [FB:96]
>[   32.715119] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.715123] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   32.715139] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   32.715141] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.715143] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   32.715145] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   32.715146] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   32.715147] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.715149] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9800 for pipe A
>[   32.715150] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   32.715151] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.715152] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.715153] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   32.715161] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.715162] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   32.715163] [drm:intel_dump_pipe_config] requested mode:
>[   32.715164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   32.715165] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.715166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   32.715168] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   32.715169] [drm:intel_dump_pipe_config] port clock: 162000
>[   32.715169] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   32.715170] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   32.715171] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.715172] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.715173] [drm:intel_dump_pipe_config] ips: 0
>[   32.715174] [drm:intel_dump_pipe_config] double wide: 0
>[   32.715175] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.715176] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.715177] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   32.715178] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   32.715179] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   32.715180] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   32.715181] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.715184] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.715185] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   32.715187] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   32.715188] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   32.715189] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.715190] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   32.715292] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   32.715342] [drm:intel_disable_pipe] disabling pipe B
>[   32.721399] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   32.721405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   32.721408] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.721411] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.721413] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.721414] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.721415] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.721415] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.721416] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.721417] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.721418] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.721418] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.721419] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.721420] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.721422] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.721423] [drm:verify_single_dpll_state] PORT PLL A
>[   32.721425] [drm:verify_single_dpll_state] PORT PLL B
>[   32.721425] [drm:verify_single_dpll_state] PORT PLL C
>[   32.721432] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   32.721433] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   32.722167] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   32.722168] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.725862] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   32.733349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   32.733390] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   32.733439] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.733442] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.733443] [drm:intel_enable_pipe] enabling pipe A
>[   32.733453] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   32.733454] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   32.733510] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.733513] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.737600] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.737603] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.737616] [drm:verify_single_dpll_state] PORT PLL B
>[   32.737622] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   32.741831] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   32.762446] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   32.766652] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.766655] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.766656] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.766682] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   32.766691] [drm:intel_disable_pipe] disabling pipe A
>[   32.773400] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   32.773406] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   32.773409] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.773412] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.773413] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.773414] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.773415] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.773416] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.773417] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.773417] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.773418] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.773419] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.773420] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.773421] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.773422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.773423] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.773425] [drm:verify_single_dpll_state] PORT PLL A
>[   32.773426] [drm:verify_single_dpll_state] PORT PLL B
>[   32.773427] [drm:verify_single_dpll_state] PORT PLL C
>[   32.773433] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.773436] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.773443] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.776795] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.779673] [drm:drm_mode_addfb2] [FB:96]
>[   32.783654] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.783657] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   32.783664] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   32.783665] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.783667] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   32.783670] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   32.783671] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   32.783681] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.783689] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467143800 for pipe A
>[   32.783690] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   32.783691] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.783692] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.783693] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   32.783694] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.783695] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   32.783696] [drm:intel_dump_pipe_config] requested mode:
>[   32.783698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   32.783698] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.783700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   32.783701] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   32.783702] [drm:intel_dump_pipe_config] port clock: 162000
>[   32.783703] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   32.783704] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   32.783705] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.783705] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.783706] [drm:intel_dump_pipe_config] ips: 0
>[   32.783707] [drm:intel_dump_pipe_config] double wide: 0
>[   32.783708] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.783709] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.783710] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   32.783711] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   32.783712] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   32.783713] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   32.783714] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.783717] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.783719] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   32.783720] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   32.783721] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.783819] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.783821] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.783822] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.783823] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.783823] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.783824] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.783825] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.783826] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.783826] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.783827] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.783828] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.783830] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.783832] [drm:verify_single_dpll_state] PORT PLL A
>[   32.783833] [drm:verify_single_dpll_state] PORT PLL B
>[   32.783834] [drm:verify_single_dpll_state] PORT PLL C
>[   32.783840] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   32.783841] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   32.784576] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   32.784577] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.786303] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   32.793349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   32.793390] [drm:skylake_pfit_enable] for crtc_state = ffff880467143800
>[   32.793437] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   32.795933] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.795943] [drm:intel_enable_pipe] enabling pipe A
>[   32.795946] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   32.795948] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   32.796007] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.796010] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.796015] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.796017] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.800105] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.800109] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.800120] [drm:verify_single_dpll_state] PORT PLL B
>[   32.804342] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   32.824950] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   32.829157] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.829159] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.829172] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.829188] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   32.829197] [drm:intel_disable_pipe] disabling pipe A
>[   32.833393] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   32.833398] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   32.833402] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.833404] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.833405] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.833407] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.833407] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.833408] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.833409] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.833410] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.833411] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.833411] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.833412] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.833413] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.833415] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.833416] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.833418] [drm:verify_single_dpll_state] PORT PLL A
>[   32.833421] [drm:verify_single_dpll_state] PORT PLL B
>[   32.833422] [drm:verify_single_dpll_state] PORT PLL C
>[   32.833428] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.833430] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   32.833438] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.839182] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.841705] [drm:drm_mode_addfb2] [FB:96]
>[   32.845289] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.845293] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   32.845308] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   32.845309] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.845311] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   32.845313] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   32.845320] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   32.845322] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.845323] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880077863800 for pipe A
>[   32.845324] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   32.845325] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.845326] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.845327] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   32.845328] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.845329] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   32.845330] [drm:intel_dump_pipe_config] requested mode:
>[   32.845331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   32.845332] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.845334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   32.845335] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   32.845336] [drm:intel_dump_pipe_config] port clock: 162000
>[   32.845337] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   32.845337] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   32.845338] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.845339] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.845340] [drm:intel_dump_pipe_config] ips: 0
>[   32.845341] [drm:intel_dump_pipe_config] double wide: 0
>[   32.845342] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.845343] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.845352] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   32.845353] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   32.845354] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   32.845355] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   32.845357] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.845359] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.845360] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   32.845362] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   32.845363] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   32.845364] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.845365] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   32.846000] [drm:intel_disable_pipe] disabling pipe C
>[   32.853397] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   32.853402] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   32.853405] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.853406] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.853408] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.853409] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.853409] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.853410] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.853411] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.853412] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.853413] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.853414] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.853414] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.853416] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.853417] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.853418] [drm:verify_single_dpll_state] PORT PLL A
>[   32.853419] [drm:verify_single_dpll_state] PORT PLL B
>[   32.853420] [drm:verify_single_dpll_state] PORT PLL C
>[   32.853423] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   32.853424] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   32.854155] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   32.854156] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.858067] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   32.858068] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.858293] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   32.858819] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   32.858820] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   32.861442] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   32.861482] [drm:skylake_pfit_enable] for crtc_state = ffff880077863800
>[   32.861528] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.861530] [drm:intel_enable_pipe] enabling pipe A
>[   32.861542] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.865685] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   32.865688] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.865699] [drm:verify_single_dpll_state] PORT PLL C
>[   32.865704] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   32.869909] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   32.890508] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   32.894752] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   32.894755] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.894757] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.894767] [drm:intel_disable_pipe] disabling pipe A
>[   32.901400] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   32.901405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   32.901408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   32.909368] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   32.909370] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.909371] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.909372] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.909373] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.909374] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.909375] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.909376] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.909377] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.909377] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.909378] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.909379] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.909381] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.909382] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   32.909383] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.909384] [drm:verify_single_dpll_state] PORT PLL A
>[   32.909385] [drm:verify_single_dpll_state] PORT PLL B
>[   32.909386] [drm:verify_single_dpll_state] PORT PLL C
>[   32.909389] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   32.909390] [drm:intel_power_well_disable] disabling power well 2
>[   32.909393] [drm:skl_set_power_well] Disabling power well 2
>[   32.909396] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.909398] [drm:intel_power_well_disable] disabling DC off
>[   32.909399] [drm:gen9_enable_dc5] Enabling DC5
>[   32.909400] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   32.909402] [drm:intel_power_well_disable] disabling always-on
>[   32.910963] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.911286] [drm:drm_mode_addfb2] [FB:96]
>[   32.915202] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   32.915206] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   32.915212] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   32.915221] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.915223] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   32.915225] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   32.915234] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   32.915235] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.915237] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467355800 for pipe A
>[   32.915238] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   32.915239] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.915240] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.915241] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   32.915242] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.915243] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   32.915243] [drm:intel_dump_pipe_config] requested mode:
>[   32.915245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   32.915246] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.915247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   32.915249] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   32.915249] [drm:intel_dump_pipe_config] port clock: 162000
>[   32.915250] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   32.915251] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   32.915252] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.915253] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.915254] [drm:intel_dump_pipe_config] ips: 0
>[   32.915254] [drm:intel_dump_pipe_config] double wide: 0
>[   32.915256] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.915257] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.915258] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   32.915259] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   32.915260] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   32.915260] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   32.915263] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.915265] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.915267] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   32.915268] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   32.915270] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.915353] [drm:intel_power_well_enable] enabling always-on
>[   32.915354] [drm:intel_power_well_enable] enabling DC off
>[   32.915417] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   32.915420] [drm:intel_power_well_enable] enabling power well 2
>[   32.915422] [drm:skl_set_power_well] Enabling power well 2
>[   32.915425] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   32.915426] [drm:intel_power_well_enable] enabling dpio-common-a
>[   32.925353] [drm:intel_power_well_disable] disabling dpio-common-a
>[   32.925364] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   32.933351] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   32.933353] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.933360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.933362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.933363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.933364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.933364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.933365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.933366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.933367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.933368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.933369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.933370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.933371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.933373] [drm:verify_single_dpll_state] PORT PLL A
>[   32.933374] [drm:verify_single_dpll_state] PORT PLL B
>[   32.933375] [drm:verify_single_dpll_state] PORT PLL C
>[   32.933380] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   32.933381] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   32.934116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   32.934118] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.938060] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   32.938062] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   32.938286] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   32.938813] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   32.938814] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   32.941433] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   32.941473] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   32.941519] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.941522] [drm:intel_enable_pipe] enabling pipe A
>[   32.941542] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.941546] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   32.945679] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   32.945681] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.945694] [drm:verify_single_dpll_state] PORT PLL C
>[   32.949908] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   32.970502] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   32.974707] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   32.974710] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.974722] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.974738] [drm:intel_disable_pipe] disabling pipe A
>[   32.981399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   32.981405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   32.981408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   32.989351] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   32.989353] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   32.989360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   32.989362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   32.989363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   32.989363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   32.989364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   32.989365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   32.989366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   32.989367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   32.989368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   32.989369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   32.989370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   32.989371] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   32.989372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   32.989374] [drm:verify_single_dpll_state] PORT PLL A
>[   32.989375] [drm:verify_single_dpll_state] PORT PLL B
>[   32.989375] [drm:verify_single_dpll_state] PORT PLL C
>[   32.989378] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   32.989379] [drm:intel_power_well_disable] disabling power well 2
>[   32.989382] [drm:skl_set_power_well] Disabling power well 2
>[   32.989385] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   32.989387] [drm:intel_power_well_disable] disabling DC off
>[   32.989388] [drm:gen9_enable_dc5] Enabling DC5
>[   32.989389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   32.989391] [drm:intel_power_well_disable] disabling always-on
>[   32.990629] kms_pipe_crc_basic: exiting, ret=0
>[   32.990743] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   32.990743] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.990745] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.990746] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   32.990748] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   32.990749] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   32.990750] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.990751] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467355800 for pipe A
>[   32.990751] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   32.990752] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.990752] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.990753] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   32.990754] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.990754] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   32.990754] [drm:intel_dump_pipe_config] requested mode:
>[   32.990756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   32.990756] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.990757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   32.990758] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   32.990759] [drm:intel_dump_pipe_config] port clock: 270000
>[   32.990759] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   32.990759] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   32.990760] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.990761] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.990761] [drm:intel_dump_pipe_config] ips: 0
>[   32.990761] [drm:intel_dump_pipe_config] double wide: 0
>[   32.990762] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.990763] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.990763] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   32.990764] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   32.990764] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   32.990765] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   32.990765] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   32.990766] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.990767] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   32.990768] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   32.990769] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   32.990769] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.990770] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff880467143800 for pipe B
>[   32.990770] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   32.990771] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.990771] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.990772] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   32.990773] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.990773] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   32.990773] [drm:intel_dump_pipe_config] requested mode:
>[   32.990774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   32.990775] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.990776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   32.990777] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   32.990777] [drm:intel_dump_pipe_config] port clock: 162000
>[   32.990777] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   32.990778] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   32.990778] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.990779] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.990779] [drm:intel_dump_pipe_config] ips: 0
>[   32.990780] [drm:intel_dump_pipe_config] double wide: 0
>[   32.990781] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.990781] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.990783] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   32.990784] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   32.990784] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   32.990784] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   32.990785] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   32.990785] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   32.990786] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   32.990786] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   32.990787] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   32.990788] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   32.990788] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   32.990789] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   32.990789] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467357800 for pipe C
>[   32.990790] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   32.990790] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   32.990791] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   32.990791] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   32.990792] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   32.990793] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   32.990793] [drm:intel_dump_pipe_config] requested mode:
>[   32.990794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   32.990794] [drm:intel_dump_pipe_config] adjusted mode:
>[   32.990795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   32.990796] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   32.990796] [drm:intel_dump_pipe_config] port clock: 162000
>[   32.990797] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   32.990797] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   32.990798] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   32.990798] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   32.990799] [drm:intel_dump_pipe_config] ips: 0
>[   32.990799] [drm:intel_dump_pipe_config] double wide: 0
>[   32.990800] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   32.990800] [drm:intel_dump_pipe_config] planes on this crtc
>[   32.990802] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   32.990802] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   32.990802] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   32.990803] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   32.990803] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   32.990805] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   32.990806] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   32.990807] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   32.990808] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   32.990809] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   32.990810] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   32.990810] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   32.990811] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   32.990812] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   32.990812] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   32.990813] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   32.990813] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   32.990814] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   32.990824] [drm:intel_power_well_enable] enabling always-on
>[   32.990825] [drm:intel_power_well_enable] enabling DC off
>[   32.990888] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   32.990890] [drm:intel_power_well_enable] enabling dpio-common-a
>[   32.997366] [drm:intel_power_well_enable] enabling power well 2
>[   32.997367] [drm:skl_set_power_well] Enabling power well 2
>[   33.001351] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   33.005361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   33.013367] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   33.013367] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   33.013368] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   33.013368] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   33.013369] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   33.013369] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   33.013370] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   33.013370] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   33.013370] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   33.013371] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   33.013371] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   33.013373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   33.013374] [drm:verify_single_dpll_state] PORT PLL A
>[   33.013375] [drm:verify_single_dpll_state] PORT PLL B
>[   33.013375] [drm:verify_single_dpll_state] PORT PLL C
>[   33.013380] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   33.013381] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   33.013403] [drm:edp_panel_on] Turn eDP port A panel power on
>[   33.013404] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   33.177350] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   33.177350] [drm:wait_panel_status] Wait complete
>[   33.177351] [drm:wait_panel_on] Wait for panel power on
>[   33.177352] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   33.203999] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   33.204000] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   33.204001] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   33.204004] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   33.233347] [drm:wait_panel_status] Wait complete
>[   33.233350] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   33.233351] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   33.234062] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   33.234063] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   33.234281] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   33.234796] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   33.234832] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   33.234877] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   33.234880] [drm:intel_enable_pipe] enabling pipe A
>[   33.234888] [drm:intel_edp_backlight_on] 
>[   33.234888] [drm:intel_panel_enable_backlight] pipe A
>[   33.234889] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   33.241349] [drm:intel_psr_enable] PSR not supported on this platform
>[   33.241350] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   33.241367] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   33.241367] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   33.242100] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   33.242100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   33.245574] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   33.253348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   33.253386] [drm:skylake_pfit_enable] for crtc_state = ffff880467143800
>[   33.253434] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   33.253435] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   33.253437] [drm:intel_enable_pipe] enabling pipe B
>[   33.253448] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   33.253449] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   33.253506] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   33.253506] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   33.254237] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   33.254237] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   33.257789] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   33.257789] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   33.258013] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   33.258539] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   33.258539] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   33.261348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   33.261386] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   33.261437] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   33.261438] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   33.261440] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   33.261442] [drm:intel_enable_pipe] enabling pipe C
>[   33.265589] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   33.265591] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   33.265605] [drm:verify_single_dpll_state] PORT PLL A
>[   33.265612] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   33.265615] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   33.265624] [drm:verify_single_dpll_state] PORT PLL B
>[   33.265629] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   33.265631] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   33.265640] [drm:verify_single_dpll_state] PORT PLL C
>[   33.270641] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.270644] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   33.270703] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.270705] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   33.270717] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.270718] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   33.270728] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.270729] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   33.271247] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   33.271250] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   33.271251] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   33.564547] kms_pipe_crc_basic: executing
>[   33.564734] [drm:i915_gem_open] 
>[   33.564855] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.564857] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   33.564921] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.564922] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   33.564934] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.564936] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   33.564946] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   33.564947] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   33.565276] [drm:i915_gem_open] 
>[   33.565663] [drm:i915_gem_open] 
>[   33.566793] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   33.567658] [drm:drm_mode_addfb2] [FB:96]
>[   33.571503] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   33.571507] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   33.571515] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   33.578197] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   33.598798] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   33.603005] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   33.603008] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   33.603010] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   33.603033] [drm:intel_edp_backlight_off] 
>[   33.805349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   33.805360] [drm:intel_disable_pipe] disabling pipe A
>[   33.809455] [drm:edp_panel_off] Turn eDP port A panel power off
>[   33.809457] [drm:wait_panel_off] Wait for panel power off time
>[   33.809459] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   33.822597] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   33.822599] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   33.822600] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   33.822611] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   33.833348] [drm:wait_panel_status] Wait complete
>[   33.833351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   33.833364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   33.833369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   33.833370] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   33.833373] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   33.833375] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   33.833375] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   33.833376] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   33.833377] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   33.833378] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   33.833379] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   33.833379] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   33.833380] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   33.833381] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   33.833383] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   33.833384] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   33.833386] [drm:verify_single_dpll_state] PORT PLL A
>[   33.833387] [drm:verify_single_dpll_state] PORT PLL B
>[   33.833394] [drm:verify_single_dpll_state] PORT PLL C
>[   33.833402] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   33.833403] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   33.833412] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   33.833413] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   33.833418] [drm:intel_power_well_disable] disabling dpio-common-a
>[   33.833421] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   33.836176] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   33.836315] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   33.838738] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   33.841292] [drm:drm_mode_addfb2] [FB:96]
>[   33.844996] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   33.845000] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   33.845007] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   33.845008] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   33.845010] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   33.845011] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   33.845021] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   33.845022] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   33.845024] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   33.845031] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e8800 for pipe A
>[   33.845032] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   33.845033] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   33.845034] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   33.845035] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   33.845036] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   33.845037] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   33.845038] [drm:intel_dump_pipe_config] requested mode:
>[   33.845040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   33.845040] [drm:intel_dump_pipe_config] adjusted mode:
>[   33.845042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   33.845043] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   33.845044] [drm:intel_dump_pipe_config] port clock: 270000
>[   33.845045] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   33.845046] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   33.845047] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   33.845047] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   33.845048] [drm:intel_dump_pipe_config] ips: 0
>[   33.845049] [drm:intel_dump_pipe_config] double wide: 0
>[   33.845050] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   33.845051] [drm:intel_dump_pipe_config] planes on this crtc
>[   33.845052] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   33.845053] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   33.845054] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   33.845055] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   33.845057] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   33.845059] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   33.845061] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   33.845062] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   33.845063] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   33.845153] [drm:intel_power_well_enable] enabling dpio-common-a
>[   33.849361] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   33.849363] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   33.849364] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   33.849365] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   33.849366] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   33.849367] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   33.849367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   33.849368] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   33.849369] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   33.849370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   33.849373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   33.849374] [drm:verify_single_dpll_state] PORT PLL A
>[   33.849376] [drm:verify_single_dpll_state] PORT PLL B
>[   33.849380] [drm:verify_single_dpll_state] PORT PLL C
>[   33.849388] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   33.849389] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   33.849412] [drm:edp_panel_on] Turn eDP port A panel power on
>[   33.849413] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   34.317352] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   34.317360] [drm:wait_panel_status] Wait complete
>[   34.317361] [drm:wait_panel_on] Wait for panel power on
>[   34.317363] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   34.344009] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   34.344011] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   34.344013] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   34.344023] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   34.377347] [drm:wait_panel_status] Wait complete
>[   34.377353] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   34.377361] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   34.378072] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   34.378073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.378291] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   34.378808] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   34.378847] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   34.378900] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   34.381885] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   34.383092] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.383101] [drm:intel_enable_pipe] enabling pipe A
>[   34.383104] [drm:intel_edp_backlight_on] 
>[   34.383105] [drm:intel_panel_enable_backlight] pipe A
>[   34.383106] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   34.385456] [drm:intel_psr_enable] PSR not supported on this platform
>[   34.385458] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   34.385474] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.385476] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   34.385478] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.385489] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.385491] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   34.385492] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.387250] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.387254] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.387267] [drm:verify_single_dpll_state] PORT PLL A
>[   34.391497] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   34.412078] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   34.416284] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.416287] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.416289] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.416311] [drm:intel_edp_backlight_off] 
>[   34.617349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   34.617361] [drm:intel_disable_pipe] disabling pipe A
>[   34.621435] [drm:edp_panel_off] Turn eDP port A panel power off
>[   34.621436] [drm:wait_panel_off] Wait for panel power off time
>[   34.621438] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   34.634565] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   34.634567] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   34.634569] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   34.634579] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   34.645348] [drm:wait_panel_status] Wait complete
>[   34.645351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   34.645364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   34.645371] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   34.645372] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.645375] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.645376] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.645377] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.645378] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.645379] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.645380] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.645381] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.645381] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.645382] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.645383] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.645384] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.645386] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.645388] [drm:verify_single_dpll_state] PORT PLL A
>[   34.645389] [drm:verify_single_dpll_state] PORT PLL B
>[   34.645393] [drm:verify_single_dpll_state] PORT PLL C
>[   34.645404] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   34.645405] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.645414] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   34.645416] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.645421] [drm:intel_power_well_disable] disabling dpio-common-a
>[   34.645423] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.649819] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.652305] [drm:drm_mode_addfb2] [FB:96]
>[   34.656354] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.656358] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   34.656373] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   34.656374] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.656376] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   34.656385] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   34.656386] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   34.656388] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.656389] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   34.656390] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   34.656391] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.656392] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.656393] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   34.656394] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.656395] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   34.656396] [drm:intel_dump_pipe_config] requested mode:
>[   34.656397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.656398] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.656400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.656401] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   34.656402] [drm:intel_dump_pipe_config] port clock: 162000
>[   34.656403] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   34.656403] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   34.656404] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.656405] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.656406] [drm:intel_dump_pipe_config] ips: 0
>[   34.656407] [drm:intel_dump_pipe_config] double wide: 0
>[   34.656408] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.656409] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.656410] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   34.656411] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   34.656412] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   34.656413] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   34.656414] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.656417] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.656418] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   34.656420] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   34.656421] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   34.656422] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.656423] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   34.656521] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   34.656572] [drm:intel_disable_pipe] disabling pipe B
>[   34.661399] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   34.661405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   34.661408] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.661411] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.661412] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.661413] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.661414] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.661415] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.661416] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.661416] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.661417] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.661418] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.661419] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.661420] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.661421] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.661423] [drm:verify_single_dpll_state] PORT PLL A
>[   34.661424] [drm:verify_single_dpll_state] PORT PLL B
>[   34.661425] [drm:verify_single_dpll_state] PORT PLL C
>[   34.661431] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   34.661432] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   34.662165] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   34.662166] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.665862] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   34.673349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   34.673389] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   34.673438] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.673441] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.673442] [drm:intel_enable_pipe] enabling pipe A
>[   34.673456] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   34.673457] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   34.673512] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.673514] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.677602] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.677605] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.677617] [drm:verify_single_dpll_state] PORT PLL B
>[   34.677622] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   34.681832] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   34.702455] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   34.706672] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.706675] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.706677] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.706699] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   34.706708] [drm:intel_disable_pipe] disabling pipe A
>[   34.713403] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   34.713408] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   34.713411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.713414] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.713415] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.713416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.713417] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.713418] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.713419] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.713420] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.713420] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.713421] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.713422] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.713423] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.713424] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.713426] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.713427] [drm:verify_single_dpll_state] PORT PLL A
>[   34.713428] [drm:verify_single_dpll_state] PORT PLL B
>[   34.713429] [drm:verify_single_dpll_state] PORT PLL C
>[   34.713436] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.713438] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.713446] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.718619] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.721159] [drm:drm_mode_addfb2] [FB:96]
>[   34.725165] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.725169] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   34.725175] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   34.725176] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.725178] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   34.725181] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   34.725182] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   34.725183] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.725185] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   34.725186] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   34.725186] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.725187] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.725189] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   34.725190] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.725191] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   34.725199] [drm:intel_dump_pipe_config] requested mode:
>[   34.725201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.725201] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.725203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.725204] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   34.725205] [drm:intel_dump_pipe_config] port clock: 162000
>[   34.725206] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   34.725207] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   34.725208] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.725208] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.725209] [drm:intel_dump_pipe_config] ips: 0
>[   34.725210] [drm:intel_dump_pipe_config] double wide: 0
>[   34.725212] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.725213] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.725214] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   34.725214] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   34.725215] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   34.725216] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   34.725218] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.725220] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.725222] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   34.725223] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   34.725225] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.725318] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.725319] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.725320] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.725321] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.725322] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.725323] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.725323] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.725324] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.725325] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.725326] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.725327] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.725328] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.725330] [drm:verify_single_dpll_state] PORT PLL A
>[   34.725331] [drm:verify_single_dpll_state] PORT PLL B
>[   34.725332] [drm:verify_single_dpll_state] PORT PLL C
>[   34.725339] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   34.725340] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   34.727429] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   34.727431] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.729644] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   34.737349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   34.737391] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   34.737438] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   34.741581] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.741584] [drm:intel_enable_pipe] enabling pipe A
>[   34.741588] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   34.741590] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   34.741649] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.741652] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.741657] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.741659] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.745739] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.745742] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.745753] [drm:verify_single_dpll_state] PORT PLL B
>[   34.749975] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   34.770583] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   34.774788] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.774791] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.774792] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.774802] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   34.774821] [drm:intel_disable_pipe] disabling pipe A
>[   34.781414] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   34.781419] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   34.781423] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.781425] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.781427] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.781428] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.781429] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.781429] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.781430] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.781431] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.781432] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.781432] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.781433] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.781434] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.781436] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.781437] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.781439] [drm:verify_single_dpll_state] PORT PLL A
>[   34.781440] [drm:verify_single_dpll_state] PORT PLL B
>[   34.781441] [drm:verify_single_dpll_state] PORT PLL C
>[   34.781447] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.781450] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   34.781457] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.784520] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.787333] [drm:drm_mode_addfb2] [FB:96]
>[   34.790983] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.790986] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   34.790993] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   34.790995] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.790997] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   34.790998] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   34.790999] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   34.791001] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.791002] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9800 for pipe A
>[   34.791003] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   34.791004] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.791005] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.791006] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   34.791007] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.791008] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   34.791009] [drm:intel_dump_pipe_config] requested mode:
>[   34.791010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   34.791019] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.791021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   34.791022] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   34.791023] [drm:intel_dump_pipe_config] port clock: 162000
>[   34.791023] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   34.791024] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   34.791025] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.791026] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.791027] [drm:intel_dump_pipe_config] ips: 0
>[   34.791028] [drm:intel_dump_pipe_config] double wide: 0
>[   34.791029] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.791031] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.791031] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   34.791032] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   34.791033] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   34.791034] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   34.791036] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.791038] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.791039] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   34.791041] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   34.791042] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   34.791043] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.791045] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   34.791135] [drm:intel_disable_pipe] disabling pipe C
>[   34.794176] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   34.794181] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   34.794184] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.794185] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.794186] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.794187] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.794188] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.794189] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.794190] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.794190] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.794191] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.794192] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.794193] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.794194] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.794196] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.794197] [drm:verify_single_dpll_state] PORT PLL A
>[   34.794198] [drm:verify_single_dpll_state] PORT PLL B
>[   34.794199] [drm:verify_single_dpll_state] PORT PLL C
>[   34.794202] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   34.794203] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   34.794933] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   34.794934] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.798078] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   34.798079] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.798303] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   34.798830] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   34.798831] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   34.801440] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   34.801480] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   34.801526] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.801529] [drm:intel_enable_pipe] enabling pipe A
>[   34.801541] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.805683] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   34.805685] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.805696] [drm:verify_single_dpll_state] PORT PLL C
>[   34.805702] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   34.809907] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   34.830506] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   34.834708] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   34.834711] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.834713] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.834722] [drm:intel_disable_pipe] disabling pipe A
>[   34.841399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   34.841404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   34.841407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   34.849351] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   34.849352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.849354] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.849362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.849363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.849363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.849364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.849365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.849366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.849367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.849368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.849369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.849370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.849371] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   34.849372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.849373] [drm:verify_single_dpll_state] PORT PLL A
>[   34.849375] [drm:verify_single_dpll_state] PORT PLL B
>[   34.849375] [drm:verify_single_dpll_state] PORT PLL C
>[   34.849378] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   34.849380] [drm:intel_power_well_disable] disabling power well 2
>[   34.849383] [drm:skl_set_power_well] Disabling power well 2
>[   34.849385] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.849387] [drm:intel_power_well_disable] disabling DC off
>[   34.849389] [drm:gen9_enable_dc5] Enabling DC5
>[   34.849390] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   34.849391] [drm:intel_power_well_disable] disabling always-on
>[   34.850947] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.851258] [drm:drm_mode_addfb2] [FB:96]
>[   34.855234] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   34.855238] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   34.855244] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   34.855245] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.855247] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   34.855249] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   34.855250] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   34.855251] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.855253] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   34.855254] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   34.855255] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.855256] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.855257] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   34.855258] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.855267] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   34.855267] [drm:intel_dump_pipe_config] requested mode:
>[   34.855269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   34.855270] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.855271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   34.855273] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   34.855273] [drm:intel_dump_pipe_config] port clock: 162000
>[   34.855274] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   34.855275] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   34.855276] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.855277] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.855278] [drm:intel_dump_pipe_config] ips: 0
>[   34.855278] [drm:intel_dump_pipe_config] double wide: 0
>[   34.855280] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.855281] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.855282] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   34.855283] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   34.855284] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   34.855285] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   34.855287] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.855289] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.855291] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   34.855292] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   34.855294] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.855377] [drm:intel_power_well_enable] enabling always-on
>[   34.855378] [drm:intel_power_well_enable] enabling DC off
>[   34.855441] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   34.855444] [drm:intel_power_well_enable] enabling power well 2
>[   34.855445] [drm:skl_set_power_well] Enabling power well 2
>[   34.855449] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   34.855449] [drm:intel_power_well_enable] enabling dpio-common-a
>[   34.865565] [drm:intel_power_well_disable] disabling dpio-common-a
>[   34.865570] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   34.873351] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   34.873353] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.873360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.873362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.873363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.873363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.873364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.873365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.873366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.873367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.873368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.873369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.873370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.873371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.873372] [drm:verify_single_dpll_state] PORT PLL A
>[   34.873374] [drm:verify_single_dpll_state] PORT PLL B
>[   34.873375] [drm:verify_single_dpll_state] PORT PLL C
>[   34.873380] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   34.873381] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   34.874116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   34.874117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.878075] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   34.878077] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   34.878301] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   34.878828] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   34.878829] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   34.881439] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   34.881480] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   34.881526] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.881528] [drm:intel_enable_pipe] enabling pipe A
>[   34.881546] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.881550] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   34.885682] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   34.885684] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.885697] [drm:verify_single_dpll_state] PORT PLL C
>[   34.889907] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   34.910504] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   34.914710] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   34.914713] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.914725] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.914742] [drm:intel_disable_pipe] disabling pipe A
>[   34.921399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   34.921405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   34.921408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   34.929350] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   34.929352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.929360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.929361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.929362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.929363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.929364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.929365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.929366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.929366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.929367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   34.929368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   34.929369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.929371] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   34.929372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.929373] [drm:verify_single_dpll_state] PORT PLL A
>[   34.929374] [drm:verify_single_dpll_state] PORT PLL B
>[   34.929375] [drm:verify_single_dpll_state] PORT PLL C
>[   34.929378] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   34.929379] [drm:intel_power_well_disable] disabling power well 2
>[   34.929382] [drm:skl_set_power_well] Disabling power well 2
>[   34.929384] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   34.929386] [drm:intel_power_well_disable] disabling DC off
>[   34.929388] [drm:gen9_enable_dc5] Enabling DC5
>[   34.929389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   34.929391] [drm:intel_power_well_disable] disabling always-on
>[   34.930631] kms_pipe_crc_basic: exiting, ret=0
>[   34.930738] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   34.930739] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.930741] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.930742] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   34.930744] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   34.930744] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   34.930745] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.930746] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   34.930747] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   34.930747] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.930748] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.930749] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   34.930749] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.930750] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   34.930750] [drm:intel_dump_pipe_config] requested mode:
>[   34.930751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   34.930752] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.930753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   34.930754] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   34.930754] [drm:intel_dump_pipe_config] port clock: 270000
>[   34.930755] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   34.930755] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   34.930756] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.930756] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.930756] [drm:intel_dump_pipe_config] ips: 0
>[   34.930757] [drm:intel_dump_pipe_config] double wide: 0
>[   34.930758] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.930758] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.930759] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   34.930759] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   34.930760] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   34.930760] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   34.930761] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   34.930762] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.930762] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   34.930764] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   34.930764] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   34.930765] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.930766] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8804694e9800 for pipe B
>[   34.930766] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   34.930766] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.930767] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.930768] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   34.930768] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.930769] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   34.930769] [drm:intel_dump_pipe_config] requested mode:
>[   34.930770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.930770] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.930771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.930772] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   34.930773] [drm:intel_dump_pipe_config] port clock: 162000
>[   34.930773] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   34.930774] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   34.930774] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.930775] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.930775] [drm:intel_dump_pipe_config] ips: 0
>[   34.930775] [drm:intel_dump_pipe_config] double wide: 0
>[   34.930776] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.930777] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.930778] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   34.930779] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   34.930779] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   34.930780] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   34.930780] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   34.930781] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   34.930781] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   34.930782] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   34.930782] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   34.930783] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   34.930784] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   34.930784] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   34.930785] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e8800 for pipe C
>[   34.930785] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   34.930786] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   34.930786] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   34.930787] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   34.930788] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   34.930788] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   34.930788] [drm:intel_dump_pipe_config] requested mode:
>[   34.930789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   34.930790] [drm:intel_dump_pipe_config] adjusted mode:
>[   34.930791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   34.930792] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   34.930792] [drm:intel_dump_pipe_config] port clock: 162000
>[   34.930792] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   34.930793] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   34.930793] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   34.930794] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   34.930794] [drm:intel_dump_pipe_config] ips: 0
>[   34.930794] [drm:intel_dump_pipe_config] double wide: 0
>[   34.930796] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   34.930796] [drm:intel_dump_pipe_config] planes on this crtc
>[   34.930797] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   34.930798] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   34.930798] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   34.930798] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   34.930799] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   34.930800] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   34.930802] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   34.930802] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   34.930803] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   34.930804] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   34.930805] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   34.930806] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   34.930806] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   34.930807] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   34.930807] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   34.930808] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   34.930808] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   34.930809] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   34.930819] [drm:intel_power_well_enable] enabling always-on
>[   34.930820] [drm:intel_power_well_enable] enabling DC off
>[   34.930883] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   34.930885] [drm:intel_power_well_enable] enabling dpio-common-a
>[   34.937366] [drm:intel_power_well_enable] enabling power well 2
>[   34.937367] [drm:skl_set_power_well] Enabling power well 2
>[   34.941351] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   34.945361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   34.953348] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   34.953349] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   34.953350] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   34.953351] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   34.953351] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   34.953352] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   34.953352] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   34.953353] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   34.953359] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   34.953360] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   34.953360] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   34.953362] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   34.953363] [drm:verify_single_dpll_state] PORT PLL A
>[   34.953364] [drm:verify_single_dpll_state] PORT PLL B
>[   34.953364] [drm:verify_single_dpll_state] PORT PLL C
>[   34.953369] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   34.953370] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   34.953392] [drm:edp_panel_on] Turn eDP port A panel power on
>[   34.953393] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   35.129349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   35.129350] [drm:wait_panel_status] Wait complete
>[   35.129350] [drm:wait_panel_on] Wait for panel power on
>[   35.129352] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   35.155998] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   35.155999] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   35.156000] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   35.156003] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   35.197360] [drm:wait_panel_status] Wait complete
>[   35.197362] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   35.197363] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   35.198073] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   35.198074] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   35.198292] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   35.198806] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   35.198843] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   35.198888] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   35.198890] [drm:intel_enable_pipe] enabling pipe A
>[   35.198898] [drm:intel_edp_backlight_on] 
>[   35.198899] [drm:intel_panel_enable_backlight] pipe A
>[   35.198900] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   35.205348] [drm:intel_psr_enable] PSR not supported on this platform
>[   35.205349] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   35.205368] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   35.205368] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   35.206100] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   35.206101] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   35.209575] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   35.217348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   35.217386] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   35.217433] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   35.217434] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   35.217436] [drm:intel_enable_pipe] enabling pipe B
>[   35.217448] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   35.217448] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   35.217505] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   35.217505] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   35.218236] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   35.218236] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   35.221792] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   35.221793] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   35.222018] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   35.222543] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   35.222544] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   35.225348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   35.225386] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   35.225437] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   35.225438] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   35.225439] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   35.225440] [drm:intel_enable_pipe] enabling pipe C
>[   35.229594] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   35.229595] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   35.229609] [drm:verify_single_dpll_state] PORT PLL A
>[   35.229616] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   35.229618] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   35.229628] [drm:verify_single_dpll_state] PORT PLL B
>[   35.229633] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   35.229635] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   35.229644] [drm:verify_single_dpll_state] PORT PLL C
>[   35.234642] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.234644] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   35.234705] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.234706] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   35.234719] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.234720] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   35.234730] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.234732] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   35.235242] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   35.235244] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   35.235245] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   35.489754] kms_pipe_crc_basic: executing
>[   35.489947] [drm:i915_gem_open] 
>[   35.490078] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.490080] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   35.490141] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.490142] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   35.490154] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.490156] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   35.490168] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   35.490169] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   35.490489] [drm:i915_gem_open] 
>[   35.490645] [drm:i915_gem_open] 
>[   35.491788] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   35.492653] [drm:drm_mode_addfb2] [FB:96]
>[   35.496794] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   35.496797] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   35.496805] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   35.504992] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   35.525586] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   35.529800] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   35.529803] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   35.529804] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   35.529815] [drm:intel_edp_backlight_off] 
>[   35.733349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   35.733354] [drm:intel_disable_pipe] disabling pipe A
>[   35.737437] [drm:edp_panel_off] Turn eDP port A panel power off
>[   35.737438] [drm:wait_panel_off] Wait for panel power off time
>[   35.737440] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060
>[   35.750562] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   35.750564] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   35.750565] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   35.750576] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   35.761348] [drm:wait_panel_status] Wait complete
>[   35.761351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   35.761364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   35.761369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   35.761371] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   35.761374] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   35.761375] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   35.761376] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   35.761377] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   35.761378] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   35.761379] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   35.761379] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   35.761380] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   35.761381] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   35.761382] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   35.761383] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   35.761385] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   35.761387] [drm:verify_single_dpll_state] PORT PLL A
>[   35.761388] [drm:verify_single_dpll_state] PORT PLL B
>[   35.761392] [drm:verify_single_dpll_state] PORT PLL C
>[   35.761400] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   35.761401] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   35.761410] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   35.761412] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   35.761419] [drm:intel_power_well_disable] disabling dpio-common-a
>[   35.761422] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   35.763115] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   35.763132] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   35.765111] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   35.768067] [drm:drm_mode_addfb2] [FB:96]
>[   35.771749] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   35.771752] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   35.771759] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   35.771760] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   35.771762] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   35.771764] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   35.771766] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   35.771767] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   35.771768] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   35.771770] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9000 for pipe A
>[   35.771771] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   35.771771] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   35.771773] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   35.771774] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   35.771775] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   35.771776] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   35.771776] [drm:intel_dump_pipe_config] requested mode:
>[   35.771778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   35.771779] [drm:intel_dump_pipe_config] adjusted mode:
>[   35.771788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   35.771789] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   35.771790] [drm:intel_dump_pipe_config] port clock: 270000
>[   35.771791] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   35.771792] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   35.771793] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   35.771794] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   35.771794] [drm:intel_dump_pipe_config] ips: 0
>[   35.771795] [drm:intel_dump_pipe_config] double wide: 0
>[   35.771797] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   35.771797] [drm:intel_dump_pipe_config] planes on this crtc
>[   35.771798] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   35.771799] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   35.771800] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   35.771801] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   35.771803] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   35.771805] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   35.771807] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   35.771808] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   35.771809] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   35.771902] [drm:intel_power_well_enable] enabling dpio-common-a
>[   35.777361] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   35.777363] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   35.777364] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   35.777364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   35.777365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   35.777366] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   35.777367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   35.777368] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   35.777368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   35.777369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   35.777372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   35.777374] [drm:verify_single_dpll_state] PORT PLL A
>[   35.777375] [drm:verify_single_dpll_state] PORT PLL B
>[   35.777379] [drm:verify_single_dpll_state] PORT PLL C
>[   35.777389] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   35.777390] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   35.777412] [drm:edp_panel_on] Turn eDP port A panel power on
>[   35.777413] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   36.245352] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   36.245360] [drm:wait_panel_status] Wait complete
>[   36.245361] [drm:wait_panel_on] Wait for panel power on
>[   36.245362] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   36.272021] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   36.272023] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   36.272024] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   36.272034] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   36.309362] [drm:wait_panel_status] Wait complete
>[   36.309365] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   36.309367] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   36.310080] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   36.310081] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.310299] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   36.310816] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   36.310853] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9000
>[   36.310907] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   36.312813] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   36.313988] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.313991] [drm:intel_enable_pipe] enabling pipe A
>[   36.313994] [drm:intel_edp_backlight_on] 
>[   36.313995] [drm:intel_panel_enable_backlight] pipe A
>[   36.313996] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   36.317463] [drm:intel_psr_enable] PSR not supported on this platform
>[   36.317464] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   36.317480] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.317482] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   36.317484] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.317495] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.317497] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   36.317498] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.318147] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.318150] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.318163] [drm:verify_single_dpll_state] PORT PLL A
>[   36.322381] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   36.342977] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   36.347200] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.347203] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.347205] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.347216] [drm:intel_edp_backlight_off] 
>[   36.549361] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   36.549366] [drm:intel_disable_pipe] disabling pipe A
>[   36.553429] [drm:edp_panel_off] Turn eDP port A panel power off
>[   36.553430] [drm:wait_panel_off] Wait for panel power off time
>[   36.553432] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   36.566573] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   36.566576] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   36.566577] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   36.566588] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   36.577348] [drm:wait_panel_status] Wait complete
>[   36.577351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   36.577366] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   36.577372] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   36.577373] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.577376] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.577377] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.577378] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.577379] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.577380] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.577381] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.577381] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.577382] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.577383] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.577384] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.577385] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.577387] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.577390] [drm:verify_single_dpll_state] PORT PLL A
>[   36.577391] [drm:verify_single_dpll_state] PORT PLL B
>[   36.577395] [drm:verify_single_dpll_state] PORT PLL C
>[   36.577403] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   36.577405] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.577418] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   36.577419] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.577425] [drm:intel_power_well_disable] disabling dpio-common-a
>[   36.577428] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.583238] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.587355] [drm:drm_mode_addfb2] [FB:96]
>[   36.591384] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.591388] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   36.591395] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   36.591396] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.591398] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   36.591401] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   36.591402] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   36.591403] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.591405] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   36.591406] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   36.591406] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.591407] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.591409] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   36.591410] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.591411] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   36.591411] [drm:intel_dump_pipe_config] requested mode:
>[   36.591413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   36.591423] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.591425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   36.591426] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   36.591427] [drm:intel_dump_pipe_config] port clock: 162000
>[   36.591428] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   36.591429] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   36.591430] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.591431] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.591431] [drm:intel_dump_pipe_config] ips: 0
>[   36.591432] [drm:intel_dump_pipe_config] double wide: 0
>[   36.591434] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.591434] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.591435] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   36.591436] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   36.591437] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   36.591438] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   36.591440] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.591442] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.591443] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   36.591445] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   36.591446] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   36.591447] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.591448] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   36.591550] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   36.591601] [drm:intel_disable_pipe] disabling pipe B
>[   36.597401] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   36.597407] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   36.597410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.597413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.597414] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.597415] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.597416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.597417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.597418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.597418] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.597419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.597420] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.597421] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.597422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.597423] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.597425] [drm:verify_single_dpll_state] PORT PLL A
>[   36.597426] [drm:verify_single_dpll_state] PORT PLL B
>[   36.597427] [drm:verify_single_dpll_state] PORT PLL C
>[   36.597433] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   36.597434] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   36.598167] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   36.598168] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.601866] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   36.609349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   36.609389] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   36.609438] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.609440] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.609442] [drm:intel_enable_pipe] enabling pipe A
>[   36.609457] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   36.609458] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   36.609514] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.609518] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.613604] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.613607] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.613618] [drm:verify_single_dpll_state] PORT PLL B
>[   36.613624] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   36.617834] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   36.638447] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   36.642657] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.642660] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.642662] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.642683] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   36.642692] [drm:intel_disable_pipe] disabling pipe A
>[   36.649402] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   36.649408] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   36.649411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.649413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.649415] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.649416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.649417] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.649417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.649418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.649419] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.649420] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.649421] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.649422] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.649422] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.649424] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.649425] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.649427] [drm:verify_single_dpll_state] PORT PLL A
>[   36.649428] [drm:verify_single_dpll_state] PORT PLL B
>[   36.649429] [drm:verify_single_dpll_state] PORT PLL C
>[   36.649435] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.649438] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.649445] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.653734] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.656225] [drm:drm_mode_addfb2] [FB:96]
>[   36.660242] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.660246] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   36.660253] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   36.660254] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.660256] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   36.660258] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   36.660259] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   36.660260] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.660262] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880077863800 for pipe A
>[   36.660263] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   36.660264] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.660265] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.660266] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   36.660267] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.660268] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   36.660269] [drm:intel_dump_pipe_config] requested mode:
>[   36.660270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   36.660279] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.660281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   36.660282] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   36.660283] [drm:intel_dump_pipe_config] port clock: 162000
>[   36.660283] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   36.660284] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   36.660285] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.660286] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.660287] [drm:intel_dump_pipe_config] ips: 0
>[   36.660288] [drm:intel_dump_pipe_config] double wide: 0
>[   36.660289] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.660290] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.660291] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   36.660292] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   36.660293] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   36.660294] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   36.660296] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.660298] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.660300] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   36.660301] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   36.660302] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.660400] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.660402] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.660402] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.660403] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.660404] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.660405] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.660406] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.660406] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.660407] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.660408] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.660409] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.660411] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.660412] [drm:verify_single_dpll_state] PORT PLL A
>[   36.660414] [drm:verify_single_dpll_state] PORT PLL B
>[   36.660414] [drm:verify_single_dpll_state] PORT PLL C
>[   36.660421] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   36.660422] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   36.661157] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   36.661158] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.665581] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   36.673349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   36.673389] [drm:skylake_pfit_enable] for crtc_state = ffff880077863800
>[   36.673437] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   36.676644] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.676653] [drm:intel_enable_pipe] enabling pipe A
>[   36.676657] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   36.676658] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   36.676718] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.676720] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.676725] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.676727] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.680806] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.680809] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.680821] [drm:verify_single_dpll_state] PORT PLL B
>[   36.685044] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   36.705643] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   36.709861] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.709864] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.709866] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.709884] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   36.709893] [drm:intel_disable_pipe] disabling pipe A
>[   36.717401] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   36.717406] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   36.717410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.717412] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.717413] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.717415] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.717415] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.717416] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.717417] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.717418] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.717419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.717419] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.717420] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.717421] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.717422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.717424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.717426] [drm:verify_single_dpll_state] PORT PLL A
>[   36.717427] [drm:verify_single_dpll_state] PORT PLL B
>[   36.717427] [drm:verify_single_dpll_state] PORT PLL C
>[   36.717435] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.717438] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   36.717446] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.719586] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.722398] [drm:drm_mode_addfb2] [FB:96]
>[   36.726050] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.726054] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   36.726061] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   36.726062] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.726064] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   36.726066] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   36.726067] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   36.726069] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.726070] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467356000 for pipe A
>[   36.726071] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   36.726072] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.726073] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.726074] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   36.726075] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.726076] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   36.726077] [drm:intel_dump_pipe_config] requested mode:
>[   36.726078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   36.726079] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.726081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   36.726090] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   36.726091] [drm:intel_dump_pipe_config] port clock: 162000
>[   36.726091] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   36.726092] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   36.726093] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.726094] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.726095] [drm:intel_dump_pipe_config] ips: 0
>[   36.726096] [drm:intel_dump_pipe_config] double wide: 0
>[   36.726097] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.726098] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.726099] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   36.726100] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   36.726101] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   36.726102] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   36.726103] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.726106] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.726107] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   36.726109] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   36.726110] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   36.726111] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.726112] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   36.726203] [drm:intel_disable_pipe] disabling pipe C
>[   36.729945] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   36.729950] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   36.729953] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.729955] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.729956] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.729957] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.729957] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.729958] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.729959] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.729960] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.729961] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.729962] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.729963] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.729964] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.729965] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.729966] [drm:verify_single_dpll_state] PORT PLL A
>[   36.729967] [drm:verify_single_dpll_state] PORT PLL B
>[   36.729968] [drm:verify_single_dpll_state] PORT PLL C
>[   36.729972] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   36.729972] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   36.730703] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   36.730704] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.734078] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   36.734079] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.734303] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   36.734830] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   36.734831] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   36.737435] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   36.737475] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   36.737521] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.737524] [drm:intel_enable_pipe] enabling pipe A
>[   36.737536] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.741683] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   36.741685] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.741696] [drm:verify_single_dpll_state] PORT PLL C
>[   36.741702] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   36.745907] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   36.766506] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   36.770712] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   36.770715] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.770717] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.770727] [drm:intel_disable_pipe] disabling pipe A
>[   36.777399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   36.777404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   36.777407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   36.785350] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   36.785352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.785360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.785361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.785362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.785363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.785363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.785365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.785365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.785366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.785367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.785368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.785369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.785370] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   36.785372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.785373] [drm:verify_single_dpll_state] PORT PLL A
>[   36.785374] [drm:verify_single_dpll_state] PORT PLL B
>[   36.785375] [drm:verify_single_dpll_state] PORT PLL C
>[   36.785378] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   36.785379] [drm:intel_power_well_disable] disabling power well 2
>[   36.785382] [drm:skl_set_power_well] Disabling power well 2
>[   36.785384] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.785386] [drm:intel_power_well_disable] disabling DC off
>[   36.785388] [drm:gen9_enable_dc5] Enabling DC5
>[   36.785389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   36.785391] [drm:intel_power_well_disable] disabling always-on
>[   36.786945] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.787268] [drm:drm_mode_addfb2] [FB:96]
>[   36.791535] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   36.791538] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   36.791545] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   36.791546] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.791548] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   36.791550] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   36.791551] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   36.791552] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.791554] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467355800 for pipe A
>[   36.791555] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   36.791555] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.791556] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.791558] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   36.791559] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.791559] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   36.791560] [drm:intel_dump_pipe_config] requested mode:
>[   36.791562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   36.791563] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.791564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   36.791573] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   36.791574] [drm:intel_dump_pipe_config] port clock: 162000
>[   36.791575] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   36.791576] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   36.791577] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.791578] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.791578] [drm:intel_dump_pipe_config] ips: 0
>[   36.791579] [drm:intel_dump_pipe_config] double wide: 0
>[   36.791581] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.791581] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.791582] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   36.791583] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   36.791584] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   36.791585] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   36.791587] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.791590] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.791592] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   36.791593] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   36.791594] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.791677] [drm:intel_power_well_enable] enabling always-on
>[   36.791678] [drm:intel_power_well_enable] enabling DC off
>[   36.791741] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   36.791744] [drm:intel_power_well_enable] enabling power well 2
>[   36.791746] [drm:skl_set_power_well] Enabling power well 2
>[   36.791749] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   36.791750] [drm:intel_power_well_enable] enabling dpio-common-a
>[   36.801352] [drm:intel_power_well_disable] disabling dpio-common-a
>[   36.801363] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   36.809350] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   36.809352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.809360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.809362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.809363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.809363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.809364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.809365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.809366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.809366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.809367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.809368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.809370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.809371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.809372] [drm:verify_single_dpll_state] PORT PLL A
>[   36.809373] [drm:verify_single_dpll_state] PORT PLL B
>[   36.809374] [drm:verify_single_dpll_state] PORT PLL C
>[   36.809380] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   36.809380] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   36.810116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   36.810117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.814069] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   36.814070] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   36.814294] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   36.814821] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   36.814822] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   36.817440] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   36.817481] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   36.817527] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.817529] [drm:intel_enable_pipe] enabling pipe A
>[   36.817550] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.817554] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   36.821687] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   36.821689] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.821702] [drm:verify_single_dpll_state] PORT PLL C
>[   36.825916] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   36.846509] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   36.850719] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   36.850722] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.850723] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.850733] [drm:intel_disable_pipe] disabling pipe A
>[   36.857399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   36.857405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   36.857408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   36.865431] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   36.865432] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.865434] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.865435] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.865436] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.865437] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.865438] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.865439] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.865439] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.865440] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.865441] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   36.865442] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   36.865443] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.865445] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   36.865446] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.865447] [drm:verify_single_dpll_state] PORT PLL A
>[   36.865448] [drm:verify_single_dpll_state] PORT PLL B
>[   36.865449] [drm:verify_single_dpll_state] PORT PLL C
>[   36.865452] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   36.865454] [drm:intel_power_well_disable] disabling power well 2
>[   36.865457] [drm:skl_set_power_well] Disabling power well 2
>[   36.865459] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   36.865461] [drm:intel_power_well_disable] disabling DC off
>[   36.865463] [drm:gen9_enable_dc5] Enabling DC5
>[   36.865464] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   36.865465] [drm:intel_power_well_disable] disabling always-on
>[   36.866847] kms_pipe_crc_basic: exiting, ret=0
>[   36.866955] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   36.866956] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.866958] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.866959] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   36.866961] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   36.866961] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   36.866962] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.866963] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467355800 for pipe A
>[   36.866964] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   36.866964] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.866965] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.866966] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   36.866966] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.866967] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   36.866967] [drm:intel_dump_pipe_config] requested mode:
>[   36.866968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   36.866969] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.866970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   36.866971] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   36.866971] [drm:intel_dump_pipe_config] port clock: 270000
>[   36.866972] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   36.866972] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   36.866973] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.866973] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.866973] [drm:intel_dump_pipe_config] ips: 0
>[   36.866974] [drm:intel_dump_pipe_config] double wide: 0
>[   36.866975] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.866975] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.866976] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   36.866976] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   36.866977] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   36.866977] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   36.866978] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   36.866979] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.866979] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   36.866981] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   36.866981] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   36.866982] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.866983] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff880467356000 for pipe B
>[   36.866983] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   36.866983] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.866984] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.866985] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   36.866985] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.866986] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   36.866986] [drm:intel_dump_pipe_config] requested mode:
>[   36.866987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   36.866987] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.866988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   36.866989] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   36.866990] [drm:intel_dump_pipe_config] port clock: 162000
>[   36.866990] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   36.866991] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   36.866991] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.866992] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.866992] [drm:intel_dump_pipe_config] ips: 0
>[   36.866992] [drm:intel_dump_pipe_config] double wide: 0
>[   36.866993] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.866994] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.866995] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   36.866996] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   36.866996] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   36.866997] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   36.866997] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   36.866998] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   36.866998] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   36.866999] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   36.866999] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   36.867000] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   36.867001] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   36.867001] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   36.867002] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467357800 for pipe C
>[   36.867002] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   36.867003] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   36.867003] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   36.867004] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   36.867005] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   36.867005] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   36.867005] [drm:intel_dump_pipe_config] requested mode:
>[   36.867006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   36.867007] [drm:intel_dump_pipe_config] adjusted mode:
>[   36.867008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   36.867009] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   36.867009] [drm:intel_dump_pipe_config] port clock: 162000
>[   36.867009] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   36.867010] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   36.867010] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   36.867011] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   36.867011] [drm:intel_dump_pipe_config] ips: 0
>[   36.867012] [drm:intel_dump_pipe_config] double wide: 0
>[   36.867013] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   36.867013] [drm:intel_dump_pipe_config] planes on this crtc
>[   36.867014] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   36.867015] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   36.867015] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   36.867015] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   36.867016] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   36.867017] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   36.867019] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   36.867020] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   36.867020] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   36.867022] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   36.867022] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   36.867023] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   36.867024] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   36.867024] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   36.867025] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   36.867025] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   36.867026] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   36.867026] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   36.867037] [drm:intel_power_well_enable] enabling always-on
>[   36.867037] [drm:intel_power_well_enable] enabling DC off
>[   36.867100] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   36.867103] [drm:intel_power_well_enable] enabling dpio-common-a
>[   36.873366] [drm:intel_power_well_enable] enabling power well 2
>[   36.873367] [drm:skl_set_power_well] Enabling power well 2
>[   36.877351] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   36.881360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   36.889349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   36.889350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   36.889351] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   36.889351] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   36.889352] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   36.889352] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   36.889353] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   36.889353] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   36.889360] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   36.889360] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   36.889361] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   36.889362] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   36.889363] [drm:verify_single_dpll_state] PORT PLL A
>[   36.889364] [drm:verify_single_dpll_state] PORT PLL B
>[   36.889365] [drm:verify_single_dpll_state] PORT PLL C
>[   36.889370] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   36.889370] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   36.889393] [drm:edp_panel_on] Turn eDP port A panel power on
>[   36.889393] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   37.061359] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   37.061360] [drm:wait_panel_status] Wait complete
>[   37.061361] [drm:wait_panel_on] Wait for panel power on
>[   37.061362] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   37.088007] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   37.088008] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   37.088008] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   37.088012] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   37.121347] [drm:wait_panel_status] Wait complete
>[   37.121349] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   37.121351] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   37.122061] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   37.122061] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   37.122279] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   37.122793] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   37.122829] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   37.122874] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   37.122877] [drm:intel_enable_pipe] enabling pipe A
>[   37.122885] [drm:intel_edp_backlight_on] 
>[   37.122886] [drm:intel_panel_enable_backlight] pipe A
>[   37.122887] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   37.129349] [drm:intel_psr_enable] PSR not supported on this platform
>[   37.129350] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   37.129367] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   37.129368] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   37.130100] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   37.130100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   37.133573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   37.141347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   37.141386] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   37.141433] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   37.141434] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   37.141436] [drm:intel_enable_pipe] enabling pipe B
>[   37.141449] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   37.141450] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   37.141503] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   37.141503] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   37.142234] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   37.142234] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   37.145789] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   37.145789] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   37.146013] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   37.146539] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   37.146539] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   37.149348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   37.149386] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   37.149436] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   37.149439] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   37.149440] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   37.149442] [drm:intel_enable_pipe] enabling pipe C
>[   37.153588] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   37.153590] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   37.153603] [drm:verify_single_dpll_state] PORT PLL A
>[   37.153612] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   37.153613] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   37.153622] [drm:verify_single_dpll_state] PORT PLL B
>[   37.153628] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   37.153629] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   37.153637] [drm:verify_single_dpll_state] PORT PLL C
>[   37.159425] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.159429] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   37.159489] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.159491] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   37.159504] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.159505] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   37.159516] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.159517] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   37.160019] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   37.160022] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   37.160023] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   37.356721] kms_pipe_crc_basic: executing
>[   37.356909] [drm:i915_gem_open] 
>[   37.357026] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.357028] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   37.357070] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.357071] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   37.357084] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.357085] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   37.357100] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   37.357101] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   37.357618] [drm:i915_gem_open] 
>[   37.357777] [drm:i915_gem_open] 
>[   37.358934] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   37.359788] [drm:drm_mode_addfb2] [FB:96]
>[   37.363661] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   37.363664] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   37.363672] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   37.371084] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   37.391689] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   37.395902] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   37.395905] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   37.395906] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   37.395929] [drm:intel_edp_backlight_off] 
>[   37.597350] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   37.597362] [drm:intel_disable_pipe] disabling pipe A
>[   37.601417] [drm:edp_panel_off] Turn eDP port A panel power off
>[   37.601419] [drm:wait_panel_off] Wait for panel power off time
>[   37.601421] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   37.614553] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   37.614556] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   37.614557] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   37.614561] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   37.625354] [drm:wait_panel_status] Wait complete
>[   37.625360] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   37.625366] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   37.625371] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   37.625373] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   37.625377] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   37.625379] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   37.625380] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   37.625381] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   37.625381] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   37.625382] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   37.625383] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   37.625384] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   37.625384] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   37.625385] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   37.625387] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   37.625389] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   37.625392] [drm:verify_single_dpll_state] PORT PLL A
>[   37.625393] [drm:verify_single_dpll_state] PORT PLL B
>[   37.625397] [drm:verify_single_dpll_state] PORT PLL C
>[   37.625405] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   37.625407] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   37.625419] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   37.625420] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   37.625425] [drm:intel_power_well_disable] disabling dpio-common-a
>[   37.625428] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   37.631195] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   37.634111] [drm:drm_mode_addfb2] [FB:96]
>[   37.637785] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   37.637789] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   37.637796] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   37.637797] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   37.637799] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   37.637800] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   37.637803] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   37.637804] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   37.637805] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   37.637807] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   37.637808] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   37.637808] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   37.637809] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   37.637811] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   37.637812] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   37.637812] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   37.637813] [drm:intel_dump_pipe_config] requested mode:
>[   37.637815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   37.637816] [drm:intel_dump_pipe_config] adjusted mode:
>[   37.637817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   37.637827] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   37.637828] [drm:intel_dump_pipe_config] port clock: 270000
>[   37.637829] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   37.637830] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   37.637831] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   37.637832] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   37.637832] [drm:intel_dump_pipe_config] ips: 0
>[   37.637833] [drm:intel_dump_pipe_config] double wide: 0
>[   37.637835] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   37.637836] [drm:intel_dump_pipe_config] planes on this crtc
>[   37.637836] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   37.637837] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   37.637838] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   37.637839] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   37.637841] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   37.637843] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   37.637845] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   37.637846] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   37.637847] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   37.637937] [drm:intel_power_well_enable] enabling dpio-common-a
>[   37.645360] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   37.645362] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   37.645363] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   37.645364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   37.645365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   37.645366] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   37.645366] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   37.645367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   37.645368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   37.645369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   37.645372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   37.645373] [drm:verify_single_dpll_state] PORT PLL A
>[   37.645374] [drm:verify_single_dpll_state] PORT PLL B
>[   37.645379] [drm:verify_single_dpll_state] PORT PLL C
>[   37.645387] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   37.645388] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   37.645413] [drm:edp_panel_on] Turn eDP port A panel power on
>[   37.645414] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   38.109372] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   38.109373] [drm:wait_panel_status] Wait complete
>[   38.109377] [drm:wait_panel_on] Wait for panel power on
>[   38.109378] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   38.136035] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   38.136038] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   38.136039] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   38.136049] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   38.161385] [drm:wait_panel_status] Wait complete
>[   38.161390] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   38.161392] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   38.162105] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.162106] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.162326] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.162841] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.162879] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   38.162932] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   38.166530] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   38.167648] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.167657] [drm:intel_enable_pipe] enabling pipe A
>[   38.167660] [drm:intel_edp_backlight_on] 
>[   38.167661] [drm:intel_panel_enable_backlight] pipe A
>[   38.167663] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   38.169497] [drm:intel_psr_enable] PSR not supported on this platform
>[   38.169498] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   38.169515] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.169517] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.169518] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.169529] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.169531] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.169533] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.171810] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.171815] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.171828] [drm:verify_single_dpll_state] PORT PLL A
>[   38.176047] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   38.196639] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   38.200848] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.200850] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.200852] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.200875] [drm:intel_edp_backlight_off] 
>[   38.401350] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   38.401362] [drm:intel_disable_pipe] disabling pipe A
>[   38.405406] [drm:edp_panel_off] Turn eDP port A panel power off
>[   38.405408] [drm:wait_panel_off] Wait for panel power off time
>[   38.405410] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060
>[   38.418532] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   38.418534] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   38.418535] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   38.418546] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   38.421363] [drm:wait_panel_status] Wait complete
>[   38.421366] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   38.421371] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   38.421377] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.421378] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.421381] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.421383] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.421384] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.421385] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.421385] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.421386] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.421387] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.421388] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.421389] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.421390] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.421391] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.421393] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.421394] [drm:verify_single_dpll_state] PORT PLL A
>[   38.421395] [drm:verify_single_dpll_state] PORT PLL B
>[   38.421401] [drm:verify_single_dpll_state] PORT PLL C
>[   38.421409] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.421410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.421421] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.421422] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.421427] [drm:intel_power_well_disable] disabling dpio-common-a
>[   38.421430] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.423046] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   38.423093] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   38.425800] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.428565] [drm:drm_mode_addfb2] [FB:96]
>[   38.432582] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.432586] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   38.432593] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   38.432594] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.432596] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   38.432599] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   38.432600] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   38.432601] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.432603] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9800 for pipe A
>[   38.432604] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   38.432605] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.432606] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.432607] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   38.432608] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.432609] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   38.432609] [drm:intel_dump_pipe_config] requested mode:
>[   38.432611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   38.432620] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.432622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   38.432623] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   38.432624] [drm:intel_dump_pipe_config] port clock: 162000
>[   38.432625] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   38.432626] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   38.432627] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.432627] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.432628] [drm:intel_dump_pipe_config] ips: 0
>[   38.432629] [drm:intel_dump_pipe_config] double wide: 0
>[   38.432630] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.432631] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.432632] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   38.432633] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   38.432634] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   38.432635] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   38.432636] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.432639] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.432640] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   38.432642] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   38.432643] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   38.432644] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.432645] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   38.432746] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   38.432796] [drm:intel_disable_pipe] disabling pipe B
>[   38.437399] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   38.437407] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   38.437410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.437413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.437414] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.437415] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.437416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.437417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.437418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.437418] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.437419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.437420] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.437421] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.437422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.437423] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.437425] [drm:verify_single_dpll_state] PORT PLL A
>[   38.437426] [drm:verify_single_dpll_state] PORT PLL B
>[   38.437427] [drm:verify_single_dpll_state] PORT PLL C
>[   38.437433] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   38.437434] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   38.438167] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.438168] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.442114] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.449349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.449390] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   38.449437] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.449439] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.449440] [drm:intel_enable_pipe] enabling pipe A
>[   38.449455] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   38.449456] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   38.449514] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.449516] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.453602] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.453605] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.453616] [drm:verify_single_dpll_state] PORT PLL B
>[   38.453621] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   38.457830] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   38.478439] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   38.482653] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.482656] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.482658] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.482668] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   38.482687] [drm:intel_disable_pipe] disabling pipe A
>[   38.489401] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   38.489408] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   38.489412] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.489414] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.489416] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.489417] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.489418] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.489419] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.489419] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.489420] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.489421] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.489422] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.489423] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.489424] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.489425] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.489426] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.489428] [drm:verify_single_dpll_state] PORT PLL A
>[   38.489429] [drm:verify_single_dpll_state] PORT PLL B
>[   38.489430] [drm:verify_single_dpll_state] PORT PLL C
>[   38.489436] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.489439] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.489446] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.495197] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.497599] [drm:drm_mode_addfb2] [FB:96]
>[   38.501573] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.501577] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   38.501583] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   38.501584] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.501586] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   38.501589] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   38.501590] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   38.501591] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.501593] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9800 for pipe A
>[   38.501594] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   38.501595] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.501596] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.501597] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   38.501598] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.501599] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   38.501599] [drm:intel_dump_pipe_config] requested mode:
>[   38.501601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   38.501602] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.501603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   38.501605] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   38.501606] [drm:intel_dump_pipe_config] port clock: 162000
>[   38.501606] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   38.501607] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   38.501608] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.501609] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.501617] [drm:intel_dump_pipe_config] ips: 0
>[   38.501618] [drm:intel_dump_pipe_config] double wide: 0
>[   38.501620] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.501621] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.501621] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   38.501623] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   38.501624] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   38.501624] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   38.501626] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.501628] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.501630] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   38.501631] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   38.501633] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.501731] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.501733] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.501733] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.501734] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.501735] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.501736] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.501737] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.501737] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.501738] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.501739] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.501740] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.501742] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.501743] [drm:verify_single_dpll_state] PORT PLL A
>[   38.501745] [drm:verify_single_dpll_state] PORT PLL B
>[   38.501745] [drm:verify_single_dpll_state] PORT PLL C
>[   38.501752] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   38.501753] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   38.502489] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.502490] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.506616] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.513349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.513390] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   38.513442] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   38.513816] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.513818] [drm:intel_enable_pipe] enabling pipe A
>[   38.513822] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   38.513823] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   38.513882] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.513884] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.513889] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.513891] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.517980] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.517983] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.517994] [drm:verify_single_dpll_state] PORT PLL B
>[   38.522215] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   38.542824] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   38.547031] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.547034] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.547035] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.547057] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   38.547066] [drm:intel_disable_pipe] disabling pipe A
>[   38.553402] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   38.553408] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   38.553412] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.553414] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.553415] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.553416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.553417] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.553418] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.553419] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.553420] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.553420] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.553421] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.553422] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.553423] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.553424] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.553426] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.553427] [drm:verify_single_dpll_state] PORT PLL A
>[   38.553428] [drm:verify_single_dpll_state] PORT PLL B
>[   38.553429] [drm:verify_single_dpll_state] PORT PLL C
>[   38.553435] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.553438] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.553445] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.556745] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.559558] [drm:drm_mode_addfb2] [FB:96]
>[   38.563181] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.563184] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   38.563192] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   38.563193] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.563195] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   38.563197] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   38.563198] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   38.563199] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.563201] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   38.563201] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   38.563202] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.563203] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.563205] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   38.563206] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.563206] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   38.563207] [drm:intel_dump_pipe_config] requested mode:
>[   38.563209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   38.563210] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.563211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   38.563212] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   38.563213] [drm:intel_dump_pipe_config] port clock: 162000
>[   38.563222] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   38.563223] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   38.563224] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.563225] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.563225] [drm:intel_dump_pipe_config] ips: 0
>[   38.563226] [drm:intel_dump_pipe_config] double wide: 0
>[   38.563228] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.563228] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.563229] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   38.563230] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   38.563231] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   38.563232] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   38.563234] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.563236] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.563238] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   38.563239] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   38.563240] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   38.563241] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.563243] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   38.563330] [drm:intel_disable_pipe] disabling pipe C
>[   38.566283] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   38.566289] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   38.566292] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.566293] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.566294] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.566295] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.566296] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.566297] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.566298] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.566298] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.566299] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.566300] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.566301] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.566302] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.566304] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.566305] [drm:verify_single_dpll_state] PORT PLL A
>[   38.566306] [drm:verify_single_dpll_state] PORT PLL B
>[   38.566307] [drm:verify_single_dpll_state] PORT PLL C
>[   38.566310] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   38.566311] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   38.567041] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.567043] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.570089] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   38.570090] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.570314] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.570841] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   38.570842] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   38.573438] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.573478] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   38.573531] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.573533] [drm:intel_enable_pipe] enabling pipe A
>[   38.573546] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.577693] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   38.577696] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.577707] [drm:verify_single_dpll_state] PORT PLL C
>[   38.577713] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   38.581917] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   38.602516] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   38.606720] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   38.606723] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.606725] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.606744] [drm:intel_disable_pipe] disabling pipe A
>[   38.613399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   38.613404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   38.613407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   38.621350] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   38.621352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.621359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.621361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.621362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.621362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.621363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.621364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.621365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.621366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.621367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.621368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.621369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.621370] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   38.621371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.621373] [drm:verify_single_dpll_state] PORT PLL A
>[   38.621374] [drm:verify_single_dpll_state] PORT PLL B
>[   38.621375] [drm:verify_single_dpll_state] PORT PLL C
>[   38.621377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   38.621379] [drm:intel_power_well_disable] disabling power well 2
>[   38.621382] [drm:skl_set_power_well] Disabling power well 2
>[   38.621384] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.621386] [drm:intel_power_well_disable] disabling DC off
>[   38.621387] [drm:gen9_enable_dc5] Enabling DC5
>[   38.621389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   38.621390] [drm:intel_power_well_disable] disabling always-on
>[   38.622922] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.623221] [drm:drm_mode_addfb2] [FB:96]
>[   38.627458] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   38.627462] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   38.627469] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   38.627470] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.627472] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   38.627473] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   38.627474] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   38.627476] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.627477] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9800 for pipe A
>[   38.627478] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   38.627479] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.627480] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.627481] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   38.627482] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.627483] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   38.627484] [drm:intel_dump_pipe_config] requested mode:
>[   38.627485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   38.627486] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.627488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   38.627496] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   38.627497] [drm:intel_dump_pipe_config] port clock: 162000
>[   38.627498] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   38.627499] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   38.627500] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.627501] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.627502] [drm:intel_dump_pipe_config] ips: 0
>[   38.627502] [drm:intel_dump_pipe_config] double wide: 0
>[   38.627504] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.627505] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.627506] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   38.627507] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   38.627508] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   38.627509] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   38.627511] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.627513] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.627515] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   38.627516] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   38.627517] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.627601] [drm:intel_power_well_enable] enabling always-on
>[   38.627602] [drm:intel_power_well_enable] enabling DC off
>[   38.627665] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   38.627668] [drm:intel_power_well_enable] enabling power well 2
>[   38.627670] [drm:skl_set_power_well] Enabling power well 2
>[   38.627673] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   38.627674] [drm:intel_power_well_enable] enabling dpio-common-a
>[   38.637351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   38.637356] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   38.645350] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   38.645352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.645360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.645362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.645363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.645363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.645364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.645365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.645366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.645366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.645368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.645369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.645370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.645371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.645372] [drm:verify_single_dpll_state] PORT PLL A
>[   38.645373] [drm:verify_single_dpll_state] PORT PLL B
>[   38.645374] [drm:verify_single_dpll_state] PORT PLL C
>[   38.645379] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   38.645380] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   38.646115] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.646116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.650060] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   38.650061] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.650285] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.650813] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   38.650814] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   38.653435] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.653475] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   38.653521] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.653524] [drm:intel_enable_pipe] enabling pipe A
>[   38.653542] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.653546] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.657678] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   38.657681] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.657693] [drm:verify_single_dpll_state] PORT PLL C
>[   38.661903] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   38.682501] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   38.686706] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   38.686708] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.686710] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.686730] [drm:intel_disable_pipe] disabling pipe A
>[   38.693399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   38.693405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   38.693408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   38.701350] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   38.701352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.701359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.701361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.701362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.701362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.701363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.701364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.701365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.701366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.701367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.701368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.701369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.701370] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   38.701371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.701373] [drm:verify_single_dpll_state] PORT PLL A
>[   38.701374] [drm:verify_single_dpll_state] PORT PLL B
>[   38.701375] [drm:verify_single_dpll_state] PORT PLL C
>[   38.701377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   38.701379] [drm:intel_power_well_disable] disabling power well 2
>[   38.701382] [drm:skl_set_power_well] Disabling power well 2
>[   38.701384] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.701386] [drm:intel_power_well_disable] disabling DC off
>[   38.701388] [drm:gen9_enable_dc5] Enabling DC5
>[   38.701389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   38.701390] [drm:intel_power_well_disable] disabling always-on
>[   38.702625] kms_pipe_crc_basic: exiting, ret=0
>[   38.702734] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   38.702735] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.702736] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.702737] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   38.702739] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   38.702740] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   38.702741] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.702742] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694e9800 for pipe A
>[   38.702742] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   38.702743] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.702744] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.702744] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   38.702745] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.702745] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   38.702746] [drm:intel_dump_pipe_config] requested mode:
>[   38.702747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   38.702747] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.702748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   38.702749] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   38.702750] [drm:intel_dump_pipe_config] port clock: 270000
>[   38.702750] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   38.702751] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   38.702751] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.702752] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.702752] [drm:intel_dump_pipe_config] ips: 0
>[   38.702752] [drm:intel_dump_pipe_config] double wide: 0
>[   38.702754] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.702754] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.702754] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   38.702755] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   38.702755] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   38.702756] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   38.702757] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   38.702757] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.702758] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   38.702759] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   38.702760] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   38.702760] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.702761] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8804694eb800 for pipe B
>[   38.702761] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   38.702762] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.702762] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.702763] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   38.702764] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.702764] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   38.702764] [drm:intel_dump_pipe_config] requested mode:
>[   38.702766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   38.702766] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.702767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   38.702768] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   38.702768] [drm:intel_dump_pipe_config] port clock: 162000
>[   38.702769] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   38.702769] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   38.702770] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.702770] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.702770] [drm:intel_dump_pipe_config] ips: 0
>[   38.702771] [drm:intel_dump_pipe_config] double wide: 0
>[   38.702772] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.702772] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.702774] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   38.702775] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   38.702775] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   38.702775] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   38.702776] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   38.702776] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   38.702777] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   38.702777] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   38.702778] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   38.702779] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   38.702779] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   38.702780] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   38.702780] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e8800 for pipe C
>[   38.702781] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   38.702781] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   38.702782] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   38.702782] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   38.702783] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   38.702784] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   38.702784] [drm:intel_dump_pipe_config] requested mode:
>[   38.702785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   38.702785] [drm:intel_dump_pipe_config] adjusted mode:
>[   38.702786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   38.702787] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   38.702787] [drm:intel_dump_pipe_config] port clock: 162000
>[   38.702788] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   38.702788] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   38.702789] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   38.702789] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   38.702790] [drm:intel_dump_pipe_config] ips: 0
>[   38.702790] [drm:intel_dump_pipe_config] double wide: 0
>[   38.702791] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   38.702791] [drm:intel_dump_pipe_config] planes on this crtc
>[   38.702793] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   38.702793] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   38.702793] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   38.702794] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   38.702794] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   38.702796] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   38.702797] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   38.702798] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   38.702799] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   38.702800] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   38.702801] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   38.702801] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   38.702802] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   38.702803] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   38.702803] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   38.702804] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   38.702804] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   38.702805] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   38.702815] [drm:intel_power_well_enable] enabling always-on
>[   38.702816] [drm:intel_power_well_enable] enabling DC off
>[   38.702879] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   38.702881] [drm:intel_power_well_enable] enabling dpio-common-a
>[   38.709366] [drm:intel_power_well_enable] enabling power well 2
>[   38.709367] [drm:skl_set_power_well] Enabling power well 2
>[   38.713351] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   38.717361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   38.725348] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   38.725349] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   38.725350] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   38.725350] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   38.725351] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   38.725352] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   38.725352] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   38.725353] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   38.725353] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   38.725354] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   38.725360] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   38.725362] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   38.725363] [drm:verify_single_dpll_state] PORT PLL A
>[   38.725364] [drm:verify_single_dpll_state] PORT PLL B
>[   38.725364] [drm:verify_single_dpll_state] PORT PLL C
>[   38.725369] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   38.725370] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   38.725392] [drm:edp_panel_on] Turn eDP port A panel power on
>[   38.725393] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   38.913349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   38.913349] [drm:wait_panel_status] Wait complete
>[   38.913350] [drm:wait_panel_on] Wait for panel power on
>[   38.913352] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   38.940013] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   38.940014] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   38.940014] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   38.940017] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   38.965349] [drm:wait_panel_status] Wait complete
>[   38.965351] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   38.965353] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   38.966069] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.966069] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.966287] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.966802] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.966838] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   38.966883] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.966885] [drm:intel_enable_pipe] enabling pipe A
>[   38.966893] [drm:intel_edp_backlight_on] 
>[   38.966894] [drm:intel_panel_enable_backlight] pipe A
>[   38.966895] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   38.973348] [drm:intel_psr_enable] PSR not supported on this platform
>[   38.973348] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   38.973365] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   38.973366] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   38.974098] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.974099] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.977573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.985347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.985386] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   38.985433] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.985434] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.985436] [drm:intel_enable_pipe] enabling pipe B
>[   38.985449] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   38.985450] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   38.985508] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   38.985509] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   38.986240] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   38.986240] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.989790] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   38.989790] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   38.990015] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   38.990541] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   38.990541] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   38.993348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   38.993386] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   38.993436] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   38.993437] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   38.993438] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   38.993440] [drm:intel_enable_pipe] enabling pipe C
>[   38.997591] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   38.997593] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   38.997607] [drm:verify_single_dpll_state] PORT PLL A
>[   38.997614] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   38.997615] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   38.997625] [drm:verify_single_dpll_state] PORT PLL B
>[   38.997631] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   38.997632] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   38.997642] [drm:verify_single_dpll_state] PORT PLL C
>[   39.002623] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.002625] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   39.002698] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.002699] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   39.002713] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.002714] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   39.002725] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.002726] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   39.003240] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   39.003242] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   39.003243] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   39.205189] kms_pipe_crc_basic: executing
>[   39.205448] [drm:i915_gem_open] 
>[   39.205570] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.205572] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   39.205632] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.205634] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   39.205646] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.205647] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   39.205658] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   39.205659] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   39.206014] [drm:i915_gem_open] 
>[   39.206162] [drm:i915_gem_open] 
>[   39.207339] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   39.208209] [drm:drm_mode_addfb2] [FB:96]
>[   39.212176] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   39.212180] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   39.212187] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   39.219231] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   39.239835] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   39.244041] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   39.244043] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   39.244045] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   39.244055] [drm:intel_edp_backlight_off] 
>[   39.445348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   39.445361] [drm:intel_disable_pipe] disabling pipe A
>[   39.449433] [drm:edp_panel_off] Turn eDP port A panel power off
>[   39.449435] [drm:wait_panel_off] Wait for panel power off time
>[   39.449438] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   39.462565] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   39.462567] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   39.462569] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   39.462579] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   39.473347] [drm:wait_panel_status] Wait complete
>[   39.473351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   39.473367] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   39.473372] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   39.473373] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   39.473376] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   39.473378] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   39.473378] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   39.473379] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   39.473380] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   39.473381] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   39.473382] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   39.473382] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   39.473383] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   39.473384] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   39.473386] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   39.473387] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   39.473389] [drm:verify_single_dpll_state] PORT PLL A
>[   39.473391] [drm:verify_single_dpll_state] PORT PLL B
>[   39.473395] [drm:verify_single_dpll_state] PORT PLL C
>[   39.473404] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   39.473406] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   39.473415] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   39.473417] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   39.473422] [drm:intel_power_well_disable] disabling dpio-common-a
>[   39.473424] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   39.479287] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   39.482266] [drm:drm_mode_addfb2] [FB:96]
>[   39.485946] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   39.485950] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   39.485957] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   39.485958] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   39.485960] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   39.485961] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   39.485964] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   39.485965] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   39.485966] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   39.485967] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467355800 for pipe A
>[   39.485968] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   39.485969] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   39.485970] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   39.485971] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   39.485972] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   39.485973] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   39.485974] [drm:intel_dump_pipe_config] requested mode:
>[   39.485975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   39.485976] [drm:intel_dump_pipe_config] adjusted mode:
>[   39.485978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   39.485987] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   39.485988] [drm:intel_dump_pipe_config] port clock: 270000
>[   39.485988] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   39.485989] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   39.485990] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   39.485991] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   39.485992] [drm:intel_dump_pipe_config] ips: 0
>[   39.485993] [drm:intel_dump_pipe_config] double wide: 0
>[   39.485994] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   39.485995] [drm:intel_dump_pipe_config] planes on this crtc
>[   39.485996] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   39.485997] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   39.485998] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   39.485999] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   39.486000] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   39.486002] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   39.486004] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   39.486005] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   39.486006] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   39.486098] [drm:intel_power_well_enable] enabling dpio-common-a
>[   39.493361] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   39.493362] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   39.493364] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   39.493364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   39.493365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   39.493366] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   39.493367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   39.493367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   39.493368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   39.493369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   39.493372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   39.493374] [drm:verify_single_dpll_state] PORT PLL A
>[   39.493375] [drm:verify_single_dpll_state] PORT PLL B
>[   39.493379] [drm:verify_single_dpll_state] PORT PLL C
>[   39.493388] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   39.493388] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   39.493414] [drm:edp_panel_on] Turn eDP port A panel power on
>[   39.493415] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   39.957370] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   39.957371] [drm:wait_panel_status] Wait complete
>[   39.957372] [drm:wait_panel_on] Wait for panel power on
>[   39.957374] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   39.984021] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   39.984023] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   39.984025] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   39.984037] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   40.017346] [drm:wait_panel_status] Wait complete
>[   40.017351] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   40.017353] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   40.018069] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.018070] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.018288] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.018806] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.018843] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   40.018894] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   40.022932] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   40.024059] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.024067] [drm:intel_enable_pipe] enabling pipe A
>[   40.024072] [drm:intel_edp_backlight_on] 
>[   40.024073] [drm:intel_panel_enable_backlight] pipe A
>[   40.024074] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   40.025467] [drm:intel_psr_enable] PSR not supported on this platform
>[   40.025469] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   40.025484] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.025487] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.025488] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.025497] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.025500] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.025501] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.028219] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.028222] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.028235] [drm:verify_single_dpll_state] PORT PLL A
>[   40.032474] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   40.053047] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   40.057251] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.057254] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.057271] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.057282] [drm:intel_edp_backlight_off] 
>[   40.257348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   40.257359] [drm:intel_disable_pipe] disabling pipe A
>[   40.261422] [drm:edp_panel_off] Turn eDP port A panel power off
>[   40.261423] [drm:wait_panel_off] Wait for panel power off time
>[   40.261425] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   40.274558] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   40.274560] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   40.274561] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   40.274572] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   40.293411] [drm:wait_panel_status] Wait complete
>[   40.293414] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   40.293420] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   40.293425] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.293427] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.293429] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.293431] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.293432] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.293433] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.293433] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.293434] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.293435] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.293436] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.293436] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.293437] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.293439] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.293441] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.293443] [drm:verify_single_dpll_state] PORT PLL A
>[   40.293444] [drm:verify_single_dpll_state] PORT PLL B
>[   40.293449] [drm:verify_single_dpll_state] PORT PLL C
>[   40.293457] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.293459] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.293468] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.293470] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.293474] [drm:intel_power_well_disable] disabling dpio-common-a
>[   40.293477] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.295980] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   40.296008] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   40.299391] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.301644] [drm:drm_mode_addfb2] [FB:96]
>[   40.305656] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.305660] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   40.305668] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   40.305669] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.305671] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   40.305673] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   40.305674] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   40.305676] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.305677] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880077863800 for pipe A
>[   40.305678] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   40.305679] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.305680] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.305681] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   40.305682] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.305683] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   40.305684] [drm:intel_dump_pipe_config] requested mode:
>[   40.305685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   40.305686] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.305696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   40.305697] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   40.305698] [drm:intel_dump_pipe_config] port clock: 162000
>[   40.305699] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   40.305700] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   40.305701] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.305701] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.305702] [drm:intel_dump_pipe_config] ips: 0
>[   40.305703] [drm:intel_dump_pipe_config] double wide: 0
>[   40.305704] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.305705] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.305706] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   40.305707] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   40.305708] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   40.305709] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   40.305711] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.305713] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.305714] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   40.305716] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   40.305717] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   40.305718] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.305719] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   40.305820] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   40.305870] [drm:intel_disable_pipe] disabling pipe B
>[   40.310142] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   40.310147] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   40.310151] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.310154] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.310155] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.310156] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.310157] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.310158] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.310158] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.310159] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.310160] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.310161] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.310162] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.310163] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.310164] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.310166] [drm:verify_single_dpll_state] PORT PLL A
>[   40.310167] [drm:verify_single_dpll_state] PORT PLL B
>[   40.310168] [drm:verify_single_dpll_state] PORT PLL C
>[   40.310174] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   40.310175] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   40.310906] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.310907] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.313885] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.321349] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.321389] [drm:skylake_pfit_enable] for crtc_state = ffff880077863800
>[   40.321439] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.321441] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.321443] [drm:intel_enable_pipe] enabling pipe A
>[   40.321455] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   40.321456] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   40.321514] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.321517] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.325601] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.325605] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.325616] [drm:verify_single_dpll_state] PORT PLL B
>[   40.325624] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   40.329831] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   40.350446] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   40.354654] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.354657] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.354659] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.354669] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   40.354689] [drm:intel_disable_pipe] disabling pipe A
>[   40.361402] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   40.361407] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   40.361411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.361413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.361414] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.361416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.361416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.361417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.361418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.361419] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.361419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.361420] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.361421] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.361422] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.361423] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.361425] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.361426] [drm:verify_single_dpll_state] PORT PLL A
>[   40.361427] [drm:verify_single_dpll_state] PORT PLL B
>[   40.361428] [drm:verify_single_dpll_state] PORT PLL C
>[   40.361435] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.361437] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.361445] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.363485] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.366359] [drm:drm_mode_addfb2] [FB:96]
>[   40.370344] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.370348] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   40.370355] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   40.370356] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.370358] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   40.370360] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   40.370361] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   40.370362] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.370364] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467357800 for pipe A
>[   40.370373] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   40.370373] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.370374] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.370376] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   40.370377] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.370378] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   40.370378] [drm:intel_dump_pipe_config] requested mode:
>[   40.370380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   40.370381] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.370382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   40.370383] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   40.370390] [drm:intel_dump_pipe_config] port clock: 162000
>[   40.370391] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   40.370392] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   40.370393] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.370394] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.370394] [drm:intel_dump_pipe_config] ips: 0
>[   40.370395] [drm:intel_dump_pipe_config] double wide: 0
>[   40.370397] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.370397] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.370398] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   40.370399] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   40.370400] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   40.370401] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   40.370402] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.370405] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.370407] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   40.370408] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   40.370409] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.370507] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.370508] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.370509] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.370510] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.370511] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.370511] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.370512] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.370513] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.370514] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.370515] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.370516] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.370517] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.370519] [drm:verify_single_dpll_state] PORT PLL A
>[   40.370520] [drm:verify_single_dpll_state] PORT PLL B
>[   40.370521] [drm:verify_single_dpll_state] PORT PLL C
>[   40.370528] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   40.370528] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   40.371263] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.371264] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.374333] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.381348] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.381389] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   40.381436] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   40.382626] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.382635] [drm:intel_enable_pipe] enabling pipe A
>[   40.382639] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   40.382640] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   40.382699] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.382702] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.382707] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.382710] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.386786] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.386789] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.386800] [drm:verify_single_dpll_state] PORT PLL B
>[   40.391020] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   40.411630] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   40.415842] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.415845] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.415847] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.415857] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   40.415878] [drm:intel_disable_pipe] disabling pipe A
>[   40.421400] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   40.421405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   40.421409] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.421411] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.421412] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.421414] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.421414] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.421415] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.421416] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.421417] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.421418] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.421418] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.421419] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.421420] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.421422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.421423] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.421425] [drm:verify_single_dpll_state] PORT PLL A
>[   40.421426] [drm:verify_single_dpll_state] PORT PLL B
>[   40.421427] [drm:verify_single_dpll_state] PORT PLL C
>[   40.421435] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.421438] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.421445] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.425919] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.428354] [drm:drm_mode_addfb2] [FB:96]
>[   40.432034] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.432038] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   40.432045] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   40.432046] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.432048] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   40.432050] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   40.432051] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   40.432052] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.432054] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467357800 for pipe A
>[   40.432055] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   40.432055] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.432057] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.432058] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   40.432059] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.432060] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   40.432060] [drm:intel_dump_pipe_config] requested mode:
>[   40.432062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   40.432063] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.432064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   40.432066] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   40.432066] [drm:intel_dump_pipe_config] port clock: 162000
>[   40.432067] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   40.432068] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   40.432077] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.432078] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.432078] [drm:intel_dump_pipe_config] ips: 0
>[   40.432079] [drm:intel_dump_pipe_config] double wide: 0
>[   40.432081] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.432081] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.432082] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   40.432083] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   40.432084] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   40.432085] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   40.432087] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.432089] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.432090] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   40.432092] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   40.432093] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   40.432094] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.432096] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   40.432186] [drm:intel_disable_pipe] disabling pipe C
>[   40.434168] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   40.434173] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   40.434176] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.434178] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.434179] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.434180] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.434181] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.434181] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.434182] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.434183] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.434184] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.434185] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.434186] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.434187] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.434188] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.434189] [drm:verify_single_dpll_state] PORT PLL A
>[   40.434190] [drm:verify_single_dpll_state] PORT PLL B
>[   40.434191] [drm:verify_single_dpll_state] PORT PLL C
>[   40.434195] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   40.434195] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   40.434926] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.434927] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.438075] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   40.438076] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.438300] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.438827] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   40.438828] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   40.441439] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.441479] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   40.441525] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.441527] [drm:intel_enable_pipe] enabling pipe A
>[   40.441540] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.445680] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   40.445682] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.445693] [drm:verify_single_dpll_state] PORT PLL C
>[   40.445699] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   40.449902] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   40.470504] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   40.474707] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   40.474710] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.474711] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.474721] [drm:intel_disable_pipe] disabling pipe A
>[   40.481399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   40.481404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   40.481407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   40.489350] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   40.489352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.489360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.489361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.489362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.489363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.489363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.489365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.489365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.489366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.489367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.489368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.489369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.489371] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   40.489372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.489373] [drm:verify_single_dpll_state] PORT PLL A
>[   40.489374] [drm:verify_single_dpll_state] PORT PLL B
>[   40.489375] [drm:verify_single_dpll_state] PORT PLL C
>[   40.489378] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   40.489379] [drm:intel_power_well_disable] disabling power well 2
>[   40.489382] [drm:skl_set_power_well] Disabling power well 2
>[   40.489384] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.489386] [drm:intel_power_well_disable] disabling DC off
>[   40.489388] [drm:gen9_enable_dc5] Enabling DC5
>[   40.489389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   40.489391] [drm:intel_power_well_disable] disabling always-on
>[   40.491022] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.491353] [drm:drm_mode_addfb2] [FB:96]
>[   40.495517] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   40.495521] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   40.495527] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   40.495529] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.495531] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   40.495533] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   40.495533] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   40.495535] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.495536] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a388800 for pipe A
>[   40.495537] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   40.495538] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.495539] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.495540] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   40.495541] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.495542] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   40.495543] [drm:intel_dump_pipe_config] requested mode:
>[   40.495544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   40.495545] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.495547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   40.495548] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   40.495549] [drm:intel_dump_pipe_config] port clock: 162000
>[   40.495550] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   40.495550] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   40.495551] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.495552] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.495553] [drm:intel_dump_pipe_config] ips: 0
>[   40.495554] [drm:intel_dump_pipe_config] double wide: 0
>[   40.495555] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.495564] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.495565] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   40.495566] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   40.495567] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   40.495567] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   40.495570] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.495572] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.495574] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   40.495575] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   40.495577] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.495659] [drm:intel_power_well_enable] enabling always-on
>[   40.495661] [drm:intel_power_well_enable] enabling DC off
>[   40.495724] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   40.495726] [drm:intel_power_well_enable] enabling power well 2
>[   40.495728] [drm:skl_set_power_well] Enabling power well 2
>[   40.495731] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   40.495732] [drm:intel_power_well_enable] enabling dpio-common-a
>[   40.505353] [drm:intel_power_well_disable] disabling dpio-common-a
>[   40.505363] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   40.513350] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   40.513352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.513360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.513361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.513362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.513363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.513364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.513364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.513365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.513366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.513367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.513368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.513369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.513370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.513372] [drm:verify_single_dpll_state] PORT PLL A
>[   40.513373] [drm:verify_single_dpll_state] PORT PLL B
>[   40.513374] [drm:verify_single_dpll_state] PORT PLL C
>[   40.513379] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   40.513380] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   40.514116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.514117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.518070] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   40.518072] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.518296] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.518823] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   40.518824] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   40.521437] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.521477] [drm:skylake_pfit_enable] for crtc_state = ffff88046a388800
>[   40.521523] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.521526] [drm:intel_enable_pipe] enabling pipe A
>[   40.521540] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.521544] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.525676] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   40.525679] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.525691] [drm:verify_single_dpll_state] PORT PLL C
>[   40.529905] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   40.550499] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   40.554708] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   40.554711] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.554713] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.554723] [drm:intel_disable_pipe] disabling pipe A
>[   40.561398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   40.561404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   40.561407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   40.569350] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   40.569352] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.569359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.569361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.569361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.569362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.569363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.569364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.569365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.569366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.569367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.569368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.569369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.569370] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   40.569371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.569373] [drm:verify_single_dpll_state] PORT PLL A
>[   40.569374] [drm:verify_single_dpll_state] PORT PLL B
>[   40.569375] [drm:verify_single_dpll_state] PORT PLL C
>[   40.569377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   40.569379] [drm:intel_power_well_disable] disabling power well 2
>[   40.569382] [drm:skl_set_power_well] Disabling power well 2
>[   40.569384] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.569386] [drm:intel_power_well_disable] disabling DC off
>[   40.569387] [drm:gen9_enable_dc5] Enabling DC5
>[   40.569389] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   40.569390] [drm:intel_power_well_disable] disabling always-on
>[   40.570634] kms_pipe_crc_basic: exiting, ret=0
>[   40.570742] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   40.570742] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.570744] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.570745] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   40.570747] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   40.570748] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   40.570749] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.570750] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a388800 for pipe A
>[   40.570750] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   40.570751] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.570751] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.570752] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   40.570753] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.570753] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   40.570754] [drm:intel_dump_pipe_config] requested mode:
>[   40.570755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   40.570755] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.570756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   40.570757] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   40.570758] [drm:intel_dump_pipe_config] port clock: 270000
>[   40.570758] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   40.570758] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   40.570759] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.570760] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.570760] [drm:intel_dump_pipe_config] ips: 0
>[   40.570760] [drm:intel_dump_pipe_config] double wide: 0
>[   40.570761] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.570762] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.570762] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   40.570763] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   40.570763] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   40.570764] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   40.570765] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   40.570765] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.570766] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   40.570767] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   40.570768] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   40.570768] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.570769] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff880467357800 for pipe B
>[   40.570769] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   40.570770] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.570770] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.570771] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   40.570772] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.570772] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   40.570773] [drm:intel_dump_pipe_config] requested mode:
>[   40.570774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   40.570774] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.570775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   40.570776] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   40.570776] [drm:intel_dump_pipe_config] port clock: 162000
>[   40.570777] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   40.570777] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   40.570778] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.570778] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.570778] [drm:intel_dump_pipe_config] ips: 0
>[   40.570779] [drm:intel_dump_pipe_config] double wide: 0
>[   40.570780] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.570780] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.570782] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   40.570783] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   40.570783] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   40.570783] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   40.570784] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   40.570784] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   40.570785] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   40.570785] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   40.570786] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   40.570787] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   40.570787] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   40.570788] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   40.570789] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467356000 for pipe C
>[   40.570789] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   40.570789] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   40.570790] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   40.570791] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   40.570791] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   40.570792] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   40.570792] [drm:intel_dump_pipe_config] requested mode:
>[   40.570793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   40.570793] [drm:intel_dump_pipe_config] adjusted mode:
>[   40.570794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   40.570795] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   40.570796] [drm:intel_dump_pipe_config] port clock: 162000
>[   40.570796] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   40.570796] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   40.570797] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   40.570797] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   40.570798] [drm:intel_dump_pipe_config] ips: 0
>[   40.570798] [drm:intel_dump_pipe_config] double wide: 0
>[   40.570799] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   40.570799] [drm:intel_dump_pipe_config] planes on this crtc
>[   40.570801] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   40.570802] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   40.570802] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   40.570802] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   40.570803] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   40.570804] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   40.570805] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.570806] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   40.570807] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   40.570808] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   40.570809] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   40.570810] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   40.570810] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   40.570811] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   40.570811] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   40.570812] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   40.570812] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   40.570813] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   40.570823] [drm:intel_power_well_enable] enabling always-on
>[   40.570824] [drm:intel_power_well_enable] enabling DC off
>[   40.570887] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   40.570889] [drm:intel_power_well_enable] enabling dpio-common-a
>[   40.577366] [drm:intel_power_well_enable] enabling power well 2
>[   40.577367] [drm:skl_set_power_well] Enabling power well 2
>[   40.581351] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   40.585360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   40.593374] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   40.593375] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   40.593376] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   40.593376] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   40.593377] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   40.593377] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   40.593378] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   40.593378] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   40.593378] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   40.593379] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   40.593379] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   40.593381] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   40.593382] [drm:verify_single_dpll_state] PORT PLL A
>[   40.593383] [drm:verify_single_dpll_state] PORT PLL B
>[   40.593383] [drm:verify_single_dpll_state] PORT PLL C
>[   40.593389] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   40.593389] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   40.593411] [drm:edp_panel_on] Turn eDP port A panel power on
>[   40.593412] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   40.769349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   40.769349] [drm:wait_panel_status] Wait complete
>[   40.769350] [drm:wait_panel_on] Wait for panel power on
>[   40.769352] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   40.796013] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   40.796014] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   40.796015] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   40.796019] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   40.825347] [drm:wait_panel_status] Wait complete
>[   40.825349] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   40.825351] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   40.826062] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.826062] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.826280] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.826794] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.826830] [drm:skylake_pfit_enable] for crtc_state = ffff88046a388800
>[   40.826876] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.826878] [drm:intel_enable_pipe] enabling pipe A
>[   40.826886] [drm:intel_edp_backlight_on] 
>[   40.826887] [drm:intel_panel_enable_backlight] pipe A
>[   40.826888] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   40.833348] [drm:intel_psr_enable] PSR not supported on this platform
>[   40.833349] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   40.833366] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   40.833367] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   40.834099] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.834100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.837573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.845347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.845385] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   40.845433] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.845434] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.845436] [drm:intel_enable_pipe] enabling pipe B
>[   40.845447] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   40.845448] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   40.845502] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   40.845503] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   40.846235] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   40.846235] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.849787] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   40.849788] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   40.850011] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   40.850538] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   40.850538] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   40.853347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   40.853385] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   40.853436] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   40.853438] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   40.853439] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   40.853441] [drm:intel_enable_pipe] enabling pipe C
>[   40.857587] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   40.857590] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   40.857603] [drm:verify_single_dpll_state] PORT PLL A
>[   40.857610] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   40.857612] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   40.857621] [drm:verify_single_dpll_state] PORT PLL B
>[   40.857627] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   40.857628] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   40.857638] [drm:verify_single_dpll_state] PORT PLL C
>[   40.862653] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   40.862655] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   40.862714] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   40.862716] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   40.862728] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   40.862729] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   40.862738] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   40.862740] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   40.863256] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   40.863259] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   40.863260] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   41.009246] kms_pipe_crc_basic: executing
>[   41.009508] [drm:i915_gem_open] 
>[   41.009628] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   41.009630] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   41.009693] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   41.009694] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   41.009706] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   41.009707] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   41.009719] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   41.009720] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   41.010039] [drm:i915_gem_open] 
>[   41.010215] [drm:i915_gem_open] 
>[   41.011347] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   41.012202] [drm:drm_mode_addfb2] [FB:96]
>[   41.016171] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   41.016175] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   41.016182] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   41.021329] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   41.041933] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   41.046142] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   41.046145] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   41.046147] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   41.046167] [drm:intel_edp_backlight_off] 
>[   41.249356] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   41.249362] [drm:intel_disable_pipe] disabling pipe A
>[   41.253484] [drm:edp_panel_off] Turn eDP port A panel power off
>[   41.253485] [drm:wait_panel_off] Wait for panel power off time
>[   41.253487] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   41.266624] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   41.266626] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   41.266632] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   41.266636] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   41.277349] [drm:wait_panel_status] Wait complete
>[   41.277358] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   41.277364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   41.277370] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   41.277371] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   41.277374] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   41.277376] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   41.277377] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   41.277378] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   41.277378] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   41.277379] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   41.277380] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   41.277381] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   41.277381] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   41.277382] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   41.277384] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   41.277386] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   41.277387] [drm:verify_single_dpll_state] PORT PLL A
>[   41.277388] [drm:verify_single_dpll_state] PORT PLL B
>[   41.277392] [drm:verify_single_dpll_state] PORT PLL C
>[   41.277402] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   41.277403] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   41.277414] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   41.277416] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   41.277421] [drm:intel_power_well_disable] disabling dpio-common-a
>[   41.277423] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   41.279488] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   41.279505] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   41.280895] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   41.284346] [drm:drm_mode_addfb2] [FB:96]
>[   41.288045] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   41.288048] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   41.288055] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   41.288056] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   41.288058] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   41.288060] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   41.288062] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   41.288063] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   41.288073] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   41.288075] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a836000 for pipe A
>[   41.288075] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   41.288082] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   41.288083] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   41.288084] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   41.288085] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   41.288086] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   41.288087] [drm:intel_dump_pipe_config] requested mode:
>[   41.288089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   41.288089] [drm:intel_dump_pipe_config] adjusted mode:
>[   41.288091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   41.288092] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   41.288093] [drm:intel_dump_pipe_config] port clock: 270000
>[   41.288094] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   41.288095] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   41.288096] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   41.288097] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   41.288097] [drm:intel_dump_pipe_config] ips: 0
>[   41.288098] [drm:intel_dump_pipe_config] double wide: 0
>[   41.288100] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   41.288100] [drm:intel_dump_pipe_config] planes on this crtc
>[   41.288101] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   41.288102] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   41.288103] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   41.288104] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   41.288106] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   41.288108] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   41.288110] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   41.288111] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   41.288112] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   41.288200] [drm:intel_power_well_enable] enabling dpio-common-a
>[   41.293360] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   41.293362] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   41.293363] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   41.293364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   41.293365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   41.293365] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   41.293366] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   41.293367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   41.293368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   41.293369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   41.293371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   41.293373] [drm:verify_single_dpll_state] PORT PLL A
>[   41.293374] [drm:verify_single_dpll_state] PORT PLL B
>[   41.293378] [drm:verify_single_dpll_state] PORT PLL C
>[   41.293390] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   41.293391] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   41.293412] [drm:edp_panel_on] Turn eDP port A panel power on
>[   41.293414] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   41.761370] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   41.761371] [drm:wait_panel_status] Wait complete
>[   41.761373] [drm:wait_panel_on] Wait for panel power on
>[   41.761374] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   41.788027] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   41.788035] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   41.788036] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   41.788040] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   41.821346] [drm:wait_panel_status] Wait complete
>[   41.821356] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   41.821358] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   41.822068] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   41.822069] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   41.822290] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   41.822807] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   41.822849] [drm:skylake_pfit_enable] for crtc_state = ffff88046a836000
>[   41.822903] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   41.825050] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   41.826136] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   41.826139] [drm:intel_enable_pipe] enabling pipe A
>[   41.826142] [drm:intel_edp_backlight_on] 
>[   41.826143] [drm:intel_panel_enable_backlight] pipe A
>[   41.826144] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   41.829441] [drm:intel_psr_enable] PSR not supported on this platform
>[   41.829443] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   41.829458] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   41.829460] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   41.829462] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   41.829471] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   41.829474] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   41.829475] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   41.830286] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   41.830289] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   41.830303] [drm:verify_single_dpll_state] PORT PLL A
>[   41.834521] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   41.855114] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   41.859319] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   41.859337] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   41.859339] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   41.859350] [drm:intel_edp_backlight_off] 
>[   42.061360] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   42.061364] [drm:intel_disable_pipe] disabling pipe A
>[   42.065433] [drm:edp_panel_off] Turn eDP port A panel power off
>[   42.065435] [drm:wait_panel_off] Wait for panel power off time
>[   42.065437] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   42.078565] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   42.078567] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   42.078574] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   42.078578] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   42.089347] [drm:wait_panel_status] Wait complete
>[   42.089356] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   42.089364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   42.089369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   42.089371] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.089373] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.089375] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.089376] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.089377] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.089378] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.089378] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.089379] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.089380] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.089381] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.089382] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.089383] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.089385] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.089388] [drm:verify_single_dpll_state] PORT PLL A
>[   42.089389] [drm:verify_single_dpll_state] PORT PLL B
>[   42.089393] [drm:verify_single_dpll_state] PORT PLL C
>[   42.089402] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   42.089404] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.089413] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   42.089414] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.089419] [drm:intel_power_well_disable] disabling dpio-common-a
>[   42.089422] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.092453] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.095375] [drm:drm_mode_addfb2] [FB:96]
>[   42.099422] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.099425] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   42.099433] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   42.099434] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.099436] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   42.099438] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   42.099439] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   42.099441] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.099442] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a835800 for pipe A
>[   42.099443] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   42.099444] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.099445] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.099446] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   42.099447] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.099448] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   42.099449] [drm:intel_dump_pipe_config] requested mode:
>[   42.099450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   42.099451] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.099453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   42.099454] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   42.099462] [drm:intel_dump_pipe_config] port clock: 162000
>[   42.099463] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   42.099464] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   42.099465] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.099466] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.099467] [drm:intel_dump_pipe_config] ips: 0
>[   42.099468] [drm:intel_dump_pipe_config] double wide: 0
>[   42.099469] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.099470] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.099471] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   42.099472] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   42.099473] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   42.099474] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   42.099475] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.099478] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.099479] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   42.099481] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   42.099482] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   42.099483] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.099484] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   42.099588] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   42.099637] [drm:intel_disable_pipe] disabling pipe B
>[   42.105400] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   42.105405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   42.105409] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.105412] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.105413] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.105414] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.105415] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.105416] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.105417] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.105417] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.105418] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.105419] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.105420] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.105421] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.105422] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.105424] [drm:verify_single_dpll_state] PORT PLL A
>[   42.105425] [drm:verify_single_dpll_state] PORT PLL B
>[   42.105426] [drm:verify_single_dpll_state] PORT PLL C
>[   42.105432] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   42.105433] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   42.106166] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.106167] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.109866] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.117354] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.117393] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835800
>[   42.117442] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.117444] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.117446] [drm:intel_enable_pipe] enabling pipe A
>[   42.117452] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   42.117453] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   42.117509] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.117511] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.121598] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.121600] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.121611] [drm:verify_single_dpll_state] PORT PLL B
>[   42.121617] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   42.125827] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   42.146440] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   42.150646] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.150649] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.150651] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.150671] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   42.150679] [drm:intel_disable_pipe] disabling pipe A
>[   42.157401] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   42.157407] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   42.157410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.157413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.157414] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.157415] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.157416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.157417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.157418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.157419] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.157419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.157420] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.157421] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.157422] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.157423] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.157424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.157426] [drm:verify_single_dpll_state] PORT PLL A
>[   42.157427] [drm:verify_single_dpll_state] PORT PLL B
>[   42.157428] [drm:verify_single_dpll_state] PORT PLL C
>[   42.157434] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.157437] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.157445] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.161828] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.164317] [drm:drm_mode_addfb2] [FB:96]
>[   42.168332] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.168336] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   42.168342] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   42.168343] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.168345] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   42.168348] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   42.168349] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   42.168350] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.168352] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a836000 for pipe A
>[   42.168352] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   42.168353] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.168354] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.168356] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   42.168364] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.168365] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   42.168366] [drm:intel_dump_pipe_config] requested mode:
>[   42.168367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   42.168368] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.168370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   42.168371] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   42.168372] [drm:intel_dump_pipe_config] port clock: 162000
>[   42.168373] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   42.168373] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   42.168374] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.168375] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.168376] [drm:intel_dump_pipe_config] ips: 0
>[   42.168377] [drm:intel_dump_pipe_config] double wide: 0
>[   42.168378] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.168379] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.168380] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   42.168381] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   42.168382] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   42.168383] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   42.168385] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.168387] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.168389] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   42.168390] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   42.168391] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.168489] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.168490] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.168491] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.168492] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.168493] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.168493] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.168494] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.168495] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.168496] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.168497] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.168498] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.168499] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.168501] [drm:verify_single_dpll_state] PORT PLL A
>[   42.168502] [drm:verify_single_dpll_state] PORT PLL B
>[   42.168503] [drm:verify_single_dpll_state] PORT PLL C
>[   42.168509] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   42.168510] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   42.169247] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.169248] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.173584] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.181359] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.181398] [drm:skylake_pfit_enable] for crtc_state = ffff88046a836000
>[   42.181446] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   42.184747] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.184750] [drm:intel_enable_pipe] enabling pipe A
>[   42.184754] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   42.184755] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   42.184814] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.184816] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.184821] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.184823] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.188901] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.188904] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.188915] [drm:verify_single_dpll_state] PORT PLL B
>[   42.193137] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   42.213737] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   42.217950] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.217953] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.217955] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.217965] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   42.217983] [drm:intel_disable_pipe] disabling pipe A
>[   42.225393] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   42.225399] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   42.225402] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.225405] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.225406] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.225407] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.225408] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.225409] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.225409] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.225410] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.225411] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.225412] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.225413] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.225414] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.225415] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.225416] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.225418] [drm:verify_single_dpll_state] PORT PLL A
>[   42.225419] [drm:verify_single_dpll_state] PORT PLL B
>[   42.225420] [drm:verify_single_dpll_state] PORT PLL C
>[   42.225426] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.225429] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.225436] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.227700] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.230497] [drm:drm_mode_addfb2] [FB:96]
>[   42.234175] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.234179] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   42.234186] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   42.234187] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.234189] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   42.234190] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   42.234191] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   42.234200] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.234202] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834000 for pipe A
>[   42.234203] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   42.234204] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.234210] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.234212] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   42.234213] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.234213] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   42.234214] [drm:intel_dump_pipe_config] requested mode:
>[   42.234216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   42.234217] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.234218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   42.234219] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   42.234220] [drm:intel_dump_pipe_config] port clock: 162000
>[   42.234221] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   42.234222] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   42.234223] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.234224] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.234224] [drm:intel_dump_pipe_config] ips: 0
>[   42.234225] [drm:intel_dump_pipe_config] double wide: 0
>[   42.234227] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.234228] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.234228] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   42.234229] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   42.234230] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   42.234231] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   42.234233] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.234235] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.234237] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   42.234239] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   42.234239] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   42.234241] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.234242] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   42.234332] [drm:intel_disable_pipe] disabling pipe C
>[   42.237949] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   42.237954] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   42.237957] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.237959] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.237960] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.237961] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.237961] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.237962] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.237963] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.237964] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.237965] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.237966] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.237967] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.237968] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.237969] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.237970] [drm:verify_single_dpll_state] PORT PLL A
>[   42.237971] [drm:verify_single_dpll_state] PORT PLL B
>[   42.237972] [drm:verify_single_dpll_state] PORT PLL C
>[   42.237975] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   42.237976] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   42.238707] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.238708] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.242075] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   42.242077] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.242301] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.242827] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   42.242828] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   42.245434] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.245475] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834000
>[   42.245521] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.245524] [drm:intel_enable_pipe] enabling pipe A
>[   42.245536] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.249680] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   42.249683] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.249693] [drm:verify_single_dpll_state] PORT PLL C
>[   42.249699] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   42.253906] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   42.274504] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   42.278715] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   42.278718] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.278720] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.278742] [drm:intel_disable_pipe] disabling pipe A
>[   42.285398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   42.285403] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   42.285406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   42.293355] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   42.293357] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.293358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.293359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.293360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.293361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.293362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.293363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.293364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.293364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.293365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.293366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.293368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.293369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   42.293370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.293371] [drm:verify_single_dpll_state] PORT PLL A
>[   42.293372] [drm:verify_single_dpll_state] PORT PLL B
>[   42.293373] [drm:verify_single_dpll_state] PORT PLL C
>[   42.293376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   42.293377] [drm:intel_power_well_disable] disabling power well 2
>[   42.293380] [drm:skl_set_power_well] Disabling power well 2
>[   42.293383] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.293385] [drm:intel_power_well_disable] disabling DC off
>[   42.293386] [drm:gen9_enable_dc5] Enabling DC5
>[   42.293387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   42.293389] [drm:intel_power_well_disable] disabling always-on
>[   42.294956] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.295274] [drm:drm_mode_addfb2] [FB:96]
>[   42.299493] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.299497] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   42.299503] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   42.299504] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.299506] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   42.299508] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   42.299509] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   42.299511] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.299520] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a836000 for pipe A
>[   42.299521] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   42.299522] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.299523] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.299524] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   42.299530] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.299531] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   42.299532] [drm:intel_dump_pipe_config] requested mode:
>[   42.299534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   42.299534] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.299536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   42.299537] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   42.299538] [drm:intel_dump_pipe_config] port clock: 162000
>[   42.299539] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   42.299540] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   42.299541] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.299542] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.299542] [drm:intel_dump_pipe_config] ips: 0
>[   42.299543] [drm:intel_dump_pipe_config] double wide: 0
>[   42.299545] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.299545] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.299546] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   42.299547] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   42.299548] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   42.299549] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   42.299552] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.299554] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.299556] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   42.299557] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   42.299558] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.299641] [drm:intel_power_well_enable] enabling always-on
>[   42.299642] [drm:intel_power_well_enable] enabling DC off
>[   42.299706] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   42.299708] [drm:intel_power_well_enable] enabling power well 2
>[   42.299710] [drm:skl_set_power_well] Enabling power well 2
>[   42.299713] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   42.299714] [drm:intel_power_well_enable] enabling dpio-common-a
>[   42.309357] [drm:intel_power_well_disable] disabling dpio-common-a
>[   42.309362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   42.317356] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   42.317357] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.317359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.317360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.317361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.317362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.317363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.317364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.317364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.317365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.317366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.317367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.317369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.317370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.317371] [drm:verify_single_dpll_state] PORT PLL A
>[   42.317372] [drm:verify_single_dpll_state] PORT PLL B
>[   42.317373] [drm:verify_single_dpll_state] PORT PLL C
>[   42.317378] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   42.317379] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   42.318115] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.318116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.322074] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   42.322075] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.322300] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.322827] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   42.322828] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   42.325440] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.325480] [drm:skylake_pfit_enable] for crtc_state = ffff88046a836000
>[   42.325526] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.325529] [drm:intel_enable_pipe] enabling pipe A
>[   42.325543] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.325548] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.329680] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   42.329682] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.329695] [drm:verify_single_dpll_state] PORT PLL C
>[   42.333905] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   42.354503] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   42.358706] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   42.358709] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.358710] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.358720] [drm:intel_disable_pipe] disabling pipe A
>[   42.365399] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   42.365405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   42.365408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   42.373366] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   42.373367] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.373369] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.373370] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.373371] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.373372] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.373373] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.373374] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.373375] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.373376] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.373377] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.373377] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.373379] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.373380] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   42.373381] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.373382] [drm:verify_single_dpll_state] PORT PLL A
>[   42.373383] [drm:verify_single_dpll_state] PORT PLL B
>[   42.373384] [drm:verify_single_dpll_state] PORT PLL C
>[   42.373387] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   42.373389] [drm:intel_power_well_disable] disabling power well 2
>[   42.373392] [drm:skl_set_power_well] Disabling power well 2
>[   42.373394] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.373396] [drm:intel_power_well_disable] disabling DC off
>[   42.373398] [drm:gen9_enable_dc5] Enabling DC5
>[   42.373399] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   42.373401] [drm:intel_power_well_disable] disabling always-on
>[   42.374640] kms_pipe_crc_basic: exiting, ret=0
>[   42.374754] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   42.374754] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.374756] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.374757] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   42.374759] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   42.374760] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   42.374761] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.374762] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880077863800 for pipe A
>[   42.374762] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   42.374763] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.374763] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.374764] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   42.374765] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.374765] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   42.374765] [drm:intel_dump_pipe_config] requested mode:
>[   42.374767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   42.374767] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.374768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   42.374769] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   42.374769] [drm:intel_dump_pipe_config] port clock: 270000
>[   42.374770] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   42.374770] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   42.374771] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.374771] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.374772] [drm:intel_dump_pipe_config] ips: 0
>[   42.374772] [drm:intel_dump_pipe_config] double wide: 0
>[   42.374773] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.374774] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.374774] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   42.374775] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   42.374775] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   42.374776] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   42.374776] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   42.374777] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.374777] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   42.374779] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   42.374779] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   42.374780] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.374781] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88046a834000 for pipe B
>[   42.374781] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   42.374781] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.374782] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.374783] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   42.374784] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.374784] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   42.374784] [drm:intel_dump_pipe_config] requested mode:
>[   42.374785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   42.374786] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.374787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   42.374787] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   42.374788] [drm:intel_dump_pipe_config] port clock: 162000
>[   42.374788] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   42.374789] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   42.374789] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.374790] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.374790] [drm:intel_dump_pipe_config] ips: 0
>[   42.374790] [drm:intel_dump_pipe_config] double wide: 0
>[   42.374791] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.374792] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.374794] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   42.374794] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   42.374794] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   42.374795] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   42.374795] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   42.374796] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   42.374796] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   42.374797] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   42.374798] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   42.374799] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   42.374799] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   42.374799] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   42.374800] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a836000 for pipe C
>[   42.374801] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   42.374801] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   42.374802] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.374802] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   42.374803] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.374803] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   42.374804] [drm:intel_dump_pipe_config] requested mode:
>[   42.374805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   42.374805] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.374806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   42.374807] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   42.374807] [drm:intel_dump_pipe_config] port clock: 162000
>[   42.374808] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   42.374808] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   42.374809] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.374809] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.374809] [drm:intel_dump_pipe_config] ips: 0
>[   42.374810] [drm:intel_dump_pipe_config] double wide: 0
>[   42.374811] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   42.374811] [drm:intel_dump_pipe_config] planes on this crtc
>[   42.374812] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   42.374813] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   42.374813] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   42.374814] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   42.374814] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   42.374815] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.374817] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.374818] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   42.374819] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   42.374820] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   42.374821] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   42.374821] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.374822] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   42.374822] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   42.374823] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   42.374824] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   42.374824] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   42.374824] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   42.374835] [drm:intel_power_well_enable] enabling always-on
>[   42.374835] [drm:intel_power_well_enable] enabling DC off
>[   42.374898] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   42.374901] [drm:intel_power_well_enable] enabling dpio-common-a
>[   42.381364] [drm:intel_power_well_enable] enabling power well 2
>[   42.381365] [drm:skl_set_power_well] Enabling power well 2
>[   42.385356] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   42.389360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   42.397348] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   42.397354] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   42.397355] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   42.397355] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   42.397356] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   42.397356] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   42.397357] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   42.397357] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   42.397357] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   42.397358] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   42.397359] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   42.397360] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   42.397361] [drm:verify_single_dpll_state] PORT PLL A
>[   42.397362] [drm:verify_single_dpll_state] PORT PLL B
>[   42.397363] [drm:verify_single_dpll_state] PORT PLL C
>[   42.397368] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   42.397368] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   42.397390] [drm:edp_panel_on] Turn eDP port A panel power on
>[   42.397391] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   42.573355] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   42.573355] [drm:wait_panel_status] Wait complete
>[   42.573356] [drm:wait_panel_on] Wait for panel power on
>[   42.573357] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   42.600021] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   42.600021] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   42.600026] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   42.600031] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   42.633346] [drm:wait_panel_status] Wait complete
>[   42.633354] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   42.633355] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   42.634065] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.634065] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.634283] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.634797] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.634833] [drm:skylake_pfit_enable] for crtc_state = ffff880077863800
>[   42.634878] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.634881] [drm:intel_enable_pipe] enabling pipe A
>[   42.634889] [drm:intel_edp_backlight_on] 
>[   42.634890] [drm:intel_panel_enable_backlight] pipe A
>[   42.634890] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   42.641348] [drm:intel_psr_enable] PSR not supported on this platform
>[   42.641354] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   42.641365] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   42.641365] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   42.642098] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.642098] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.645573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.653347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.653386] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834000
>[   42.653434] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.653435] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   42.653437] [drm:intel_enable_pipe] enabling pipe B
>[   42.653447] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   42.653448] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   42.653504] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   42.653504] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   42.654236] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   42.654236] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.657792] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   42.657793] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   42.658016] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   42.658543] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   42.658543] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   42.661347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   42.661391] [drm:skylake_pfit_enable] for crtc_state = ffff88046a836000
>[   42.661443] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   42.661444] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   42.661445] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   42.661447] [drm:intel_enable_pipe] enabling pipe C
>[   42.665593] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   42.665594] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   42.665608] [drm:verify_single_dpll_state] PORT PLL A
>[   42.665616] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   42.665618] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   42.665626] [drm:verify_single_dpll_state] PORT PLL B
>[   42.665632] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   42.665633] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   42.665643] [drm:verify_single_dpll_state] PORT PLL C
>[   42.670624] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.670640] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   42.670681] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.670682] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   42.670695] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.670696] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   42.670706] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.670707] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   42.671243] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.671245] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   42.671246] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   42.765210] kms_pipe_crc_basic: executing
>[   42.765466] [drm:i915_gem_open] 
>[   42.765577] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.765579] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   42.765687] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.765688] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   42.765700] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.765702] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   42.765712] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   42.765713] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   42.765954] [drm:i915_gem_open] 
>[   42.766111] [drm:i915_gem_open] 
>[   42.767258] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   42.768128] [drm:drm_mode_addfb2] [FB:96]
>[   42.772235] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   42.772239] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   42.772246] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.779712] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   42.800316] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   42.804523] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   42.804526] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   42.804528] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   42.804539] [drm:intel_edp_backlight_off] 
>[   43.005348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   43.005361] [drm:intel_disable_pipe] disabling pipe A
>[   43.009439] [drm:edp_panel_off] Turn eDP port A panel power off
>[   43.009440] [drm:wait_panel_off] Wait for panel power off time
>[   43.009442] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   43.022578] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   43.022580] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   43.022587] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   43.022590] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   43.033348] [drm:wait_panel_status] Wait complete
>[   43.033356] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   43.033362] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   43.033367] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.033369] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.033371] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.033373] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.033374] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.033375] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.033376] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.033376] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.033377] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.033378] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.033379] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.033380] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.033381] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.033383] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.033386] [drm:verify_single_dpll_state] PORT PLL A
>[   43.033387] [drm:verify_single_dpll_state] PORT PLL B
>[   43.033391] [drm:verify_single_dpll_state] PORT PLL C
>[   43.033399] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.033400] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.033409] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.033411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.033417] [drm:intel_power_well_disable] disabling dpio-common-a
>[   43.033419] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.033743] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   43.033760] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   43.035576] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.038546] [drm:drm_mode_addfb2] [FB:96]
>[   43.042239] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.042242] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   43.042249] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   43.042250] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   43.042252] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.042253] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   43.042256] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   43.042257] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   43.042258] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   43.042267] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467357800 for pipe A
>[   43.042268] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   43.042269] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   43.042270] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   43.042271] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   43.042272] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   43.042273] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   43.042274] [drm:intel_dump_pipe_config] requested mode:
>[   43.042275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   43.042276] [drm:intel_dump_pipe_config] adjusted mode:
>[   43.042278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   43.042287] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   43.042288] [drm:intel_dump_pipe_config] port clock: 270000
>[   43.042289] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   43.042290] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   43.042291] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   43.042292] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   43.042292] [drm:intel_dump_pipe_config] ips: 0
>[   43.042293] [drm:intel_dump_pipe_config] double wide: 0
>[   43.042295] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   43.042296] [drm:intel_dump_pipe_config] planes on this crtc
>[   43.042296] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   43.042297] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   43.042298] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   43.042299] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   43.042301] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.042303] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.042305] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   43.042306] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   43.042307] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.042398] [drm:intel_power_well_enable] enabling dpio-common-a
>[   43.049360] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.049361] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.049362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.049363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.049364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.049365] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.049365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.049366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.049367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.049368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.049371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.049372] [drm:verify_single_dpll_state] PORT PLL A
>[   43.049373] [drm:verify_single_dpll_state] PORT PLL B
>[   43.049378] [drm:verify_single_dpll_state] PORT PLL C
>[   43.049386] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   43.049387] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   43.049409] [drm:edp_panel_on] Turn eDP port A panel power on
>[   43.049410] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   43.517369] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   43.517371] [drm:wait_panel_status] Wait complete
>[   43.517372] [drm:wait_panel_on] Wait for panel power on
>[   43.517374] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   43.544034] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   43.544042] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   43.544043] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   43.544047] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   43.577347] [drm:wait_panel_status] Wait complete
>[   43.577358] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   43.577360] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   43.578075] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   43.578076] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   43.578295] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   43.578811] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   43.578848] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   43.578902] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   43.579302] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   43.580341] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.580344] [drm:intel_enable_pipe] enabling pipe A
>[   43.580348] [drm:intel_edp_backlight_on] 
>[   43.580349] [drm:intel_panel_enable_backlight] pipe A
>[   43.580350] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   43.585356] [drm:intel_psr_enable] PSR not supported on this platform
>[   43.585357] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   43.585373] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.585375] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.585376] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.585386] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.585388] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.585390] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.588625] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.588628] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.588641] [drm:verify_single_dpll_state] PORT PLL A
>[   43.592874] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   43.613446] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   43.617650] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.617653] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.617655] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.617677] [drm:intel_edp_backlight_off] 
>[   43.821348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   43.821359] [drm:intel_disable_pipe] disabling pipe A
>[   43.825422] [drm:edp_panel_off] Turn eDP port A panel power off
>[   43.825424] [drm:wait_panel_off] Wait for panel power off time
>[   43.825426] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   43.838566] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   43.838574] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   43.838574] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   43.838579] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   43.849347] [drm:wait_panel_status] Wait complete
>[   43.849357] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   43.849363] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   43.849368] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.849370] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.849372] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.849374] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.849375] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.849376] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.849377] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.849377] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.849378] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.849379] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.849380] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.849381] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.849382] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.849384] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.849385] [drm:verify_single_dpll_state] PORT PLL A
>[   43.849387] [drm:verify_single_dpll_state] PORT PLL B
>[   43.849392] [drm:verify_single_dpll_state] PORT PLL C
>[   43.849400] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.849401] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.849410] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   43.849412] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.849416] [drm:intel_power_well_disable] disabling dpio-common-a
>[   43.849419] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.855203] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.857827] [drm:drm_mode_addfb2] [FB:96]
>[   43.861826] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.861829] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   43.861837] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   43.861838] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   43.861840] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   43.861842] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   43.861843] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   43.861845] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   43.861846] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467357800 for pipe A
>[   43.861847] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   43.861848] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   43.861849] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   43.861850] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   43.861851] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   43.861852] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   43.861853] [drm:intel_dump_pipe_config] requested mode:
>[   43.861854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   43.861865] [drm:intel_dump_pipe_config] adjusted mode:
>[   43.861866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   43.861868] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   43.861869] [drm:intel_dump_pipe_config] port clock: 162000
>[   43.861869] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   43.861870] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   43.861871] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   43.861872] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   43.861873] [drm:intel_dump_pipe_config] ips: 0
>[   43.861874] [drm:intel_dump_pipe_config] double wide: 0
>[   43.861875] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   43.861876] [drm:intel_dump_pipe_config] planes on this crtc
>[   43.861877] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   43.861878] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   43.861879] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   43.861880] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   43.861881] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.861884] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.861885] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   43.861887] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   43.861888] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   43.861889] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.861890] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   43.861994] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   43.862043] [drm:intel_disable_pipe] disabling pipe B
>[   43.865971] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   43.865976] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   43.865980] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.865983] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.865984] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.865985] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.865986] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.865987] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.865987] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.865988] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.865989] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.865990] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.865991] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.865991] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.865993] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.865996] [drm:verify_single_dpll_state] PORT PLL A
>[   43.865997] [drm:verify_single_dpll_state] PORT PLL B
>[   43.865998] [drm:verify_single_dpll_state] PORT PLL C
>[   43.866004] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   43.866005] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   43.866736] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   43.866737] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   43.869870] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   43.877354] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   43.877394] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   43.877443] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.877445] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.877447] [drm:intel_enable_pipe] enabling pipe A
>[   43.877455] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   43.877456] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   43.877512] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.877515] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.881601] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   43.881604] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.881615] [drm:verify_single_dpll_state] PORT PLL B
>[   43.881621] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   43.885830] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   43.906445] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   43.910654] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.910657] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.910659] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.910668] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   43.910688] [drm:intel_disable_pipe] disabling pipe A
>[   43.917401] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   43.917406] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   43.917409] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.917412] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.917413] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.917414] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.917415] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.917416] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.917417] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.917418] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.917418] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.917419] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.917420] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.917421] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   43.917422] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.917423] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.917425] [drm:verify_single_dpll_state] PORT PLL A
>[   43.917426] [drm:verify_single_dpll_state] PORT PLL B
>[   43.917427] [drm:verify_single_dpll_state] PORT PLL C
>[   43.917433] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.917436] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.917444] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.919887] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.922740] [drm:drm_mode_addfb2] [FB:96]
>[   43.926745] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.926749] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   43.926755] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   43.926757] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   43.926758] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   43.926761] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   43.926762] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   43.926763] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   43.926765] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   43.926766] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   43.926767] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   43.926768] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   43.926769] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   43.926770] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   43.926771] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   43.926771] [drm:intel_dump_pipe_config] requested mode:
>[   43.926773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   43.926782] [drm:intel_dump_pipe_config] adjusted mode:
>[   43.926783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   43.926785] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   43.926786] [drm:intel_dump_pipe_config] port clock: 162000
>[   43.926786] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   43.926787] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   43.926788] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   43.926789] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   43.926790] [drm:intel_dump_pipe_config] ips: 0
>[   43.926791] [drm:intel_dump_pipe_config] double wide: 0
>[   43.926792] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   43.926793] [drm:intel_dump_pipe_config] planes on this crtc
>[   43.926794] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   43.926795] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   43.926796] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   43.926797] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   43.926798] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.926800] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.926802] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   43.926803] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   43.926805] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.926902] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.926904] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.926905] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.926905] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.926906] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.926907] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.926908] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.926909] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.926909] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.926910] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.926911] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.926913] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.926915] [drm:verify_single_dpll_state] PORT PLL A
>[   43.926916] [drm:verify_single_dpll_state] PORT PLL B
>[   43.926917] [drm:verify_single_dpll_state] PORT PLL C
>[   43.926923] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   43.926924] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   43.927662] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   43.927663] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   43.930319] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   43.937354] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   43.937394] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   43.937444] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   43.939004] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.939007] [drm:intel_enable_pipe] enabling pipe A
>[   43.939011] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   43.939012] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   43.939071] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.939074] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.939078] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   43.939080] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.943159] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   43.943162] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.943173] [drm:verify_single_dpll_state] PORT PLL B
>[   43.947394] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   43.968003] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   43.972209] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.972212] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.972214] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.972224] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   43.972243] [drm:intel_disable_pipe] disabling pipe A
>[   43.977398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   43.977404] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   43.977407] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.977410] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.977411] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.977412] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.977413] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.977414] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.977415] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.977415] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.977416] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.977417] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.977418] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.977419] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   43.977420] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.977421] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.977423] [drm:verify_single_dpll_state] PORT PLL A
>[   43.977424] [drm:verify_single_dpll_state] PORT PLL B
>[   43.977425] [drm:verify_single_dpll_state] PORT PLL C
>[   43.977431] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.977434] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   43.977442] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   43.982306] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.984729] [drm:drm_mode_addfb2] [FB:96]
>[   43.988383] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   43.988387] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   43.988394] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   43.988395] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   43.988397] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   43.988399] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   43.988400] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   43.988401] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   43.988403] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   43.988404] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   43.988405] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   43.988406] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   43.988407] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   43.988408] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   43.988409] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   43.988409] [drm:intel_dump_pipe_config] requested mode:
>[   43.988411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   43.988412] [drm:intel_dump_pipe_config] adjusted mode:
>[   43.988413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   43.988415] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   43.988424] [drm:intel_dump_pipe_config] port clock: 162000
>[   43.988425] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   43.988426] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   43.988427] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   43.988427] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   43.988428] [drm:intel_dump_pipe_config] ips: 0
>[   43.988429] [drm:intel_dump_pipe_config] double wide: 0
>[   43.988430] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   43.988431] [drm:intel_dump_pipe_config] planes on this crtc
>[   43.988432] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   43.988433] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   43.988434] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   43.988435] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   43.988437] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   43.988439] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   43.988440] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   43.988442] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   43.988443] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   43.988444] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   43.988445] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   43.988533] [drm:intel_disable_pipe] disabling pipe C
>[   43.993402] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   43.993408] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   43.993411] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   43.993412] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   43.993414] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   43.993414] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   43.993415] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   43.993416] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   43.993417] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   43.993417] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   43.993418] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   43.993419] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   43.993420] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   43.993421] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   43.993423] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   43.993424] [drm:verify_single_dpll_state] PORT PLL A
>[   43.993425] [drm:verify_single_dpll_state] PORT PLL B
>[   43.993426] [drm:verify_single_dpll_state] PORT PLL C
>[   43.993429] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   43.993430] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   43.994161] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   43.994162] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   43.998326] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   43.998327] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   43.998551] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   43.999078] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   43.999079] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   44.001483] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   44.001523] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   44.001569] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.001571] [drm:intel_enable_pipe] enabling pipe A
>[   44.001584] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.005730] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   44.005732] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   44.005743] [drm:verify_single_dpll_state] PORT PLL C
>[   44.005749] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   44.009954] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   44.030548] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   44.034760] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   44.034763] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.034765] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.034775] [drm:intel_disable_pipe] disabling pipe A
>[   44.041398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   44.041403] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   44.041406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   44.049358] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   44.049359] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   44.049360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   44.049362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   44.049363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   44.049363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   44.049364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   44.049365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   44.049366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   44.049367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   44.049368] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   44.049369] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   44.049370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   44.049371] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   44.049372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   44.049374] [drm:verify_single_dpll_state] PORT PLL A
>[   44.049375] [drm:verify_single_dpll_state] PORT PLL B
>[   44.049376] [drm:verify_single_dpll_state] PORT PLL C
>[   44.049378] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   44.049380] [drm:intel_power_well_disable] disabling power well 2
>[   44.049383] [drm:skl_set_power_well] Disabling power well 2
>[   44.049385] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   44.049387] [drm:intel_power_well_disable] disabling DC off
>[   44.049389] [drm:gen9_enable_dc5] Enabling DC5
>[   44.049390] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   44.049392] [drm:intel_power_well_disable] disabling always-on
>[   44.050953] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   44.051266] [drm:drm_mode_addfb2] [FB:96]
>[   44.055516] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   44.055520] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   44.055526] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   44.055528] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   44.055529] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   44.055531] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   44.055532] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   44.055534] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   44.055535] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467357800 for pipe A
>[   44.055536] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   44.055537] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   44.055538] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   44.055539] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   44.055540] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   44.055541] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   44.055542] [drm:intel_dump_pipe_config] requested mode:
>[   44.055543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   44.055544] [drm:intel_dump_pipe_config] adjusted mode:
>[   44.055545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   44.055547] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   44.055548] [drm:intel_dump_pipe_config] port clock: 162000
>[   44.055556] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   44.055557] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   44.055558] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   44.055559] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   44.055560] [drm:intel_dump_pipe_config] ips: 0
>[   44.055560] [drm:intel_dump_pipe_config] double wide: 0
>[   44.055562] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   44.055563] [drm:intel_dump_pipe_config] planes on this crtc
>[   44.055564] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   44.055565] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   44.055566] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   44.055567] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   44.055569] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   44.055571] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.055573] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   44.055574] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   44.055575] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.055659] [drm:intel_power_well_enable] enabling always-on
>[   44.055660] [drm:intel_power_well_enable] enabling DC off
>[   44.055723] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   44.055726] [drm:intel_power_well_enable] enabling power well 2
>[   44.055727] [drm:skl_set_power_well] Enabling power well 2
>[   44.055731] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   44.055731] [drm:intel_power_well_enable] enabling dpio-common-a
>[   44.065357] [drm:intel_power_well_disable] disabling dpio-common-a
>[   44.065362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   44.073355] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   44.073357] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   44.073359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   44.073360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   44.073361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   44.073362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   44.073362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   44.073363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   44.073364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   44.073365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   44.073366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   44.073367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   44.073368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   44.073369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   44.073371] [drm:verify_single_dpll_state] PORT PLL A
>[   44.073372] [drm:verify_single_dpll_state] PORT PLL B
>[   44.073373] [drm:verify_single_dpll_state] PORT PLL C
>[   44.073378] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   44.073379] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   44.074114] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   44.074116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   44.078061] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   44.078063] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   44.078287] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   44.078814] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   44.078815] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   44.081441] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   44.081481] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   44.081527] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.081530] [drm:intel_enable_pipe] enabling pipe A
>[   44.081543] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.081547] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.085680] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   44.085682] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   44.085695] [drm:verify_single_dpll_state] PORT PLL C
>[   44.089907] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   44.110502] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   44.114705] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   44.114708] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.114710] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.114730] [drm:intel_disable_pipe] disabling pipe A
>[   44.121398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   44.121404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   44.121407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   44.129355] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   44.129357] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   44.129358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   44.129359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   44.129360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   44.129361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   44.129362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   44.129363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   44.129364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   44.129364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   44.129365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   44.129366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   44.129367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   44.129369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   44.129370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   44.129371] [drm:verify_single_dpll_state] PORT PLL A
>[   44.129372] [drm:verify_single_dpll_state] PORT PLL B
>[   44.129373] [drm:verify_single_dpll_state] PORT PLL C
>[   44.129376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   44.129377] [drm:intel_power_well_disable] disabling power well 2
>[   44.129380] [drm:skl_set_power_well] Disabling power well 2
>[   44.129382] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   44.129384] [drm:intel_power_well_disable] disabling DC off
>[   44.129386] [drm:gen9_enable_dc5] Enabling DC5
>[   44.129387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   44.129389] [drm:intel_power_well_disable] disabling always-on
>[   44.130654] kms_pipe_crc_basic: exiting, ret=0
>[   44.130762] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   44.130762] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   44.130764] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.130765] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   44.130767] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   44.130768] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   44.130769] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   44.130770] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   44.130770] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   44.130771] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   44.130771] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   44.130772] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   44.130773] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   44.130773] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   44.130773] [drm:intel_dump_pipe_config] requested mode:
>[   44.130775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   44.130775] [drm:intel_dump_pipe_config] adjusted mode:
>[   44.130776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   44.130777] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   44.130777] [drm:intel_dump_pipe_config] port clock: 270000
>[   44.130778] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   44.130778] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   44.130779] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   44.130780] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   44.130780] [drm:intel_dump_pipe_config] ips: 0
>[   44.130780] [drm:intel_dump_pipe_config] double wide: 0
>[   44.130781] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   44.130782] [drm:intel_dump_pipe_config] planes on this crtc
>[   44.130782] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   44.130783] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   44.130783] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   44.130784] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   44.130784] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   44.130785] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   44.130786] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   44.130787] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   44.130788] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   44.130788] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   44.130789] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88046a835000 for pipe B
>[   44.130789] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   44.130790] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   44.130790] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   44.130791] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   44.130792] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   44.130792] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   44.130792] [drm:intel_dump_pipe_config] requested mode:
>[   44.130793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   44.130794] [drm:intel_dump_pipe_config] adjusted mode:
>[   44.130795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   44.130796] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   44.130796] [drm:intel_dump_pipe_config] port clock: 162000
>[   44.130796] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   44.130797] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   44.130797] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   44.130798] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   44.130798] [drm:intel_dump_pipe_config] ips: 0
>[   44.130799] [drm:intel_dump_pipe_config] double wide: 0
>[   44.130800] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   44.130800] [drm:intel_dump_pipe_config] planes on this crtc
>[   44.130802] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   44.130802] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   44.130802] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   44.130803] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   44.130803] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   44.130804] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   44.130805] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   44.130805] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   44.130806] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   44.130807] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   44.130807] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   44.130808] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   44.130808] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835800 for pipe C
>[   44.130809] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   44.130809] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   44.130810] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   44.130810] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   44.130811] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   44.130811] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   44.130812] [drm:intel_dump_pipe_config] requested mode:
>[   44.130813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   44.130813] [drm:intel_dump_pipe_config] adjusted mode:
>[   44.130814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   44.130815] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   44.130815] [drm:intel_dump_pipe_config] port clock: 162000
>[   44.130816] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   44.130816] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   44.130817] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   44.130817] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   44.130817] [drm:intel_dump_pipe_config] ips: 0
>[   44.130818] [drm:intel_dump_pipe_config] double wide: 0
>[   44.130819] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   44.130819] [drm:intel_dump_pipe_config] planes on this crtc
>[   44.130820] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   44.130821] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   44.130821] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   44.130822] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   44.130822] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   44.130823] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   44.130825] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.130826] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   44.130827] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   44.130828] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   44.130828] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   44.130829] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.130830] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   44.130830] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   44.130831] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   44.130831] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   44.130832] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   44.130832] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   44.130843] [drm:intel_power_well_enable] enabling always-on
>[   44.130844] [drm:intel_power_well_enable] enabling DC off
>[   44.130907] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   44.130909] [drm:intel_power_well_enable] enabling dpio-common-a
>[   44.137365] [drm:intel_power_well_enable] enabling power well 2
>[   44.137366] [drm:skl_set_power_well] Enabling power well 2
>[   44.141367] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   44.145360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   44.153352] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   44.153354] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   44.153355] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   44.153355] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   44.153356] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   44.153356] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   44.153357] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   44.153357] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   44.153357] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   44.153358] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   44.153359] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   44.153360] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   44.153361] [drm:verify_single_dpll_state] PORT PLL A
>[   44.153362] [drm:verify_single_dpll_state] PORT PLL B
>[   44.153362] [drm:verify_single_dpll_state] PORT PLL C
>[   44.153368] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   44.153368] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   44.153390] [drm:edp_panel_on] Turn eDP port A panel power on
>[   44.153391] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   44.333357] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   44.333358] [drm:wait_panel_status] Wait complete
>[   44.333359] [drm:wait_panel_on] Wait for panel power on
>[   44.333360] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   44.360020] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   44.360021] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   44.360021] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   44.360031] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   44.385346] [drm:wait_panel_status] Wait complete
>[   44.385356] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   44.385357] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   44.386067] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   44.386068] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   44.386286] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   44.386800] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   44.386837] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   44.386882] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.386884] [drm:intel_enable_pipe] enabling pipe A
>[   44.386892] [drm:intel_edp_backlight_on] 
>[   44.386893] [drm:intel_panel_enable_backlight] pipe A
>[   44.386894] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   44.393347] [drm:intel_psr_enable] PSR not supported on this platform
>[   44.393354] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   44.393367] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   44.393367] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   44.394100] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   44.394100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   44.397573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   44.405347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   44.405391] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   44.405438] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.405439] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   44.405441] [drm:intel_enable_pipe] enabling pipe B
>[   44.405454] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   44.405455] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   44.405512] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   44.405513] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   44.406244] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   44.406244] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   44.409793] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   44.409793] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   44.410017] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   44.410542] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   44.410543] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   44.413347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   44.413391] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835800
>[   44.413441] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   44.413443] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   44.413444] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   44.413447] [drm:intel_enable_pipe] enabling pipe C
>[   44.417594] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   44.417596] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   44.417610] [drm:verify_single_dpll_state] PORT PLL A
>[   44.417619] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   44.417620] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   44.417629] [drm:verify_single_dpll_state] PORT PLL B
>[   44.417634] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   44.417636] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   44.417645] [drm:verify_single_dpll_state] PORT PLL C
>[   44.422648] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.422651] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   44.422691] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.422693] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   44.422706] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.422707] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   44.422718] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.422719] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   44.423240] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.423242] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   44.423243] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   44.588944] kms_pipe_crc_basic: executing
>[   44.589139] [drm:i915_gem_open] 
>[   44.589267] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.589269] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   44.589309] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.589311] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   44.589323] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.589324] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   44.589334] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   44.589335] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   44.589850] [drm:i915_gem_open] 
>[   44.590011] [drm:i915_gem_open] 
>[   44.591133] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[   44.592009] [drm:drm_mode_addfb2] [FB:96]
>[   44.595898] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   44.595901] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   44.595916] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.602023] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   44.622614] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   44.626818] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   44.626821] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.626823] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.626833] [drm:intel_edp_backlight_off] 
>[   44.829354] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   44.829360] [drm:intel_disable_pipe] disabling pipe A
>[   44.837396] [drm:edp_panel_off] Turn eDP port A panel power off
>[   44.837398] [drm:wait_panel_off] Wait for panel power off time
>[   44.837400] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060
>[   44.850524] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   44.850526] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   44.850533] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   44.850536] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   44.869363] [drm:wait_panel_status] Wait complete
>[   44.869366] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   44.869372] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   44.869377] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   44.869378] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   44.869381] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   44.869382] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   44.869383] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   44.869384] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   44.869385] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   44.869386] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   44.869386] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   44.869387] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   44.869388] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   44.869389] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   44.869390] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   44.869392] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   44.869394] [drm:verify_single_dpll_state] PORT PLL A
>[   44.869396] [drm:verify_single_dpll_state] PORT PLL B
>[   44.869401] [drm:verify_single_dpll_state] PORT PLL C
>[   44.869409] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   44.869411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   44.869420] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   44.869421] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   44.869426] [drm:intel_power_well_disable] disabling dpio-common-a
>[   44.869429] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   44.872566] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   44.872583] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[   44.875187] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   44.877518] [drm:drm_mode_addfb2] [FB:96]
>[   44.881130] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   44.881134] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   44.881140] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   44.881142] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   44.881144] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.881145] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   44.881148] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   44.881148] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   44.881158] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   44.881159] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467357800 for pipe A
>[   44.881160] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   44.881161] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   44.881162] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   44.881163] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   44.881164] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   44.881165] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   44.881166] [drm:intel_dump_pipe_config] requested mode:
>[   44.881167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   44.881174] [drm:intel_dump_pipe_config] adjusted mode:
>[   44.881175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   44.881177] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   44.881178] [drm:intel_dump_pipe_config] port clock: 270000
>[   44.881178] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   44.881179] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   44.881180] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   44.881181] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   44.881182] [drm:intel_dump_pipe_config] ips: 0
>[   44.881183] [drm:intel_dump_pipe_config] double wide: 0
>[   44.881184] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   44.881185] [drm:intel_dump_pipe_config] planes on this crtc
>[   44.881186] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   44.881187] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   44.881188] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   44.881189] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   44.881190] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   44.881193] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   44.881195] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   44.881196] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   44.881197] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   44.881289] [drm:intel_power_well_enable] enabling dpio-common-a
>[   44.885359] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   44.885361] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   44.885362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   44.885363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   44.885364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   44.885364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   44.885365] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   44.885366] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   44.885367] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   44.885368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   44.885370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   44.885372] [drm:verify_single_dpll_state] PORT PLL A
>[   44.885373] [drm:verify_single_dpll_state] PORT PLL B
>[   44.885377] [drm:verify_single_dpll_state] PORT PLL C
>[   44.885388] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   44.885389] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   44.885410] [drm:edp_panel_on] Turn eDP port A panel power on
>[   44.885411] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   45.341357] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   45.341359] [drm:wait_panel_status] Wait complete
>[   45.341360] [drm:wait_panel_on] Wait for panel power on
>[   45.341362] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   45.368010] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   45.368017] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   45.368018] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   45.368024] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   45.401347] [drm:wait_panel_status] Wait complete
>[   45.401360] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   45.401361] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   45.402076] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   45.402077] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.402296] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   45.402813] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   45.402850] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   45.402902] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   45.405721] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[   45.406829] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.406832] [drm:intel_enable_pipe] enabling pipe A
>[   45.406835] [drm:intel_edp_backlight_on] 
>[   45.406836] [drm:intel_panel_enable_backlight] pipe A
>[   45.406837] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   45.409449] [drm:intel_psr_enable] PSR not supported on this platform
>[   45.409450] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   45.409467] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.409470] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   45.409471] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.409480] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.409483] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   45.409484] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.410984] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.410987] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.411000] [drm:verify_single_dpll_state] PORT PLL A
>[   45.415220] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   45.435812] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   45.440038] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.440041] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.440043] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.440053] [drm:intel_edp_backlight_off] 
>[   45.641348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   45.641359] [drm:intel_disable_pipe] disabling pipe A
>[   45.645426] [drm:edp_panel_off] Turn eDP port A panel power off
>[   45.645428] [drm:wait_panel_off] Wait for panel power off time
>[   45.645431] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   45.658572] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   45.658574] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   45.658583] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   45.658586] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   45.669347] [drm:wait_panel_status] Wait complete
>[   45.669357] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   45.669363] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   45.669368] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   45.669370] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.669372] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.669374] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.669375] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.669375] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.669376] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.669377] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.669378] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.669379] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.669379] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.669380] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.669382] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.669383] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.669385] [drm:verify_single_dpll_state] PORT PLL A
>[   45.669386] [drm:verify_single_dpll_state] PORT PLL B
>[   45.669391] [drm:verify_single_dpll_state] PORT PLL C
>[   45.669399] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   45.669400] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.669409] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   45.669411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.669417] [drm:intel_power_well_disable] disabling dpio-common-a
>[   45.669419] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.673186] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.676060] [drm:drm_mode_addfb2] [FB:96]
>[   45.680080] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.680083] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   45.680091] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   45.680092] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.680094] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   45.680097] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   45.680098] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   45.680099] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.680101] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   45.680101] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   45.680102] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.680103] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.680105] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   45.680106] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.680106] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   45.680107] [drm:intel_dump_pipe_config] requested mode:
>[   45.680109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   45.680110] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.680111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   45.680112] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   45.680113] [drm:intel_dump_pipe_config] port clock: 162000
>[   45.680122] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   45.680123] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   45.680124] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.680125] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.680125] [drm:intel_dump_pipe_config] ips: 0
>[   45.680126] [drm:intel_dump_pipe_config] double wide: 0
>[   45.680128] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.680128] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.680129] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   45.680130] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   45.680131] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   45.680132] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   45.680134] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.680136] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.680138] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   45.680139] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   45.680140] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   45.680141] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.680143] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   45.680241] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   45.680292] [drm:intel_disable_pipe] disabling pipe B
>[   45.685400] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   45.685405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   45.685411] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.685414] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.685415] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.685416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.685417] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.685418] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.685418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.685419] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.685420] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.685421] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.685422] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.685423] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.685424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.685426] [drm:verify_single_dpll_state] PORT PLL A
>[   45.685427] [drm:verify_single_dpll_state] PORT PLL B
>[   45.685428] [drm:verify_single_dpll_state] PORT PLL C
>[   45.685434] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   45.685435] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   45.686167] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   45.686168] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.690114] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   45.697353] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   45.697395] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   45.697442] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.697444] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.697446] [drm:intel_enable_pipe] enabling pipe A
>[   45.697459] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   45.697460] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   45.697517] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.697519] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.701611] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.701614] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.701626] [drm:verify_single_dpll_state] PORT PLL B
>[   45.701631] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   45.705834] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   45.726449] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   45.730654] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.730657] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.730659] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.730684] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   45.730692] [drm:intel_disable_pipe] disabling pipe A
>[   45.737402] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   45.737407] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   45.737410] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.737413] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.737414] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.737415] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.737416] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.737417] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.737418] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.737419] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.737419] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.737420] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.737421] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.737422] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.737423] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.737424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.737426] [drm:verify_single_dpll_state] PORT PLL A
>[   45.737427] [drm:verify_single_dpll_state] PORT PLL B
>[   45.737428] [drm:verify_single_dpll_state] PORT PLL C
>[   45.737434] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.737437] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.737444] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.742561] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.745006] [drm:drm_mode_addfb2] [FB:96]
>[   45.749013] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.749016] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   45.749023] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   45.749024] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.749026] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   45.749028] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   45.749029] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   45.749031] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.749032] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   45.749033] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   45.749034] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.749035] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.749036] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   45.749037] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.749038] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   45.749039] [drm:intel_dump_pipe_config] requested mode:
>[   45.749040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   45.749041] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.749043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   45.749052] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   45.749053] [drm:intel_dump_pipe_config] port clock: 162000
>[   45.749054] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   45.749055] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   45.749055] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.749056] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.749057] [drm:intel_dump_pipe_config] ips: 0
>[   45.749058] [drm:intel_dump_pipe_config] double wide: 0
>[   45.749059] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.749060] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.749061] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   45.749062] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   45.749063] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   45.749064] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   45.749066] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.749068] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.749070] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B
>[   45.749071] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A
>[   45.749072] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.749170] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.749171] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.749172] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.749173] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.749174] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.749174] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.749175] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.749176] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.749177] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.749178] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.749179] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.749180] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.749182] [drm:verify_single_dpll_state] PORT PLL A
>[   45.749183] [drm:verify_single_dpll_state] PORT PLL B
>[   45.749184] [drm:verify_single_dpll_state] PORT PLL C
>[   45.749190] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26
>[   45.749191] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   45.751283] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   45.751285] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.753643] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   45.761354] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   45.761393] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   45.761440] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[   45.765443] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.765447] [drm:intel_enable_pipe] enabling pipe A
>[   45.765451] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   45.765452] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   45.765510] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.765513] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.765517] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.765519] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.769601] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.769604] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.769616] [drm:verify_single_dpll_state] PORT PLL B
>[   45.773828] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   45.794444] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   45.798650] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.798653] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.798654] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.798675] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A
>[   45.798684] [drm:intel_disable_pipe] disabling pipe A
>[   45.805410] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26
>[   45.805416] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   45.805419] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.805422] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.805423] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.805424] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.805425] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.805426] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.805426] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.805427] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.805428] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.805429] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.805430] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.805431] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.805432] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.805433] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.805435] [drm:verify_single_dpll_state] PORT PLL A
>[   45.805436] [drm:verify_single_dpll_state] PORT PLL B
>[   45.805437] [drm:verify_single_dpll_state] PORT PLL C
>[   45.805443] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.805446] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   45.805453] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.808341] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.811157] [drm:drm_mode_addfb2] [FB:96]
>[   45.814795] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.814798] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   45.814806] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   45.814807] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.814809] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   45.814811] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   45.814811] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   45.814813] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.814814] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   45.814815] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   45.814816] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.814817] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.814818] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   45.814819] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.814820] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   45.814821] [drm:intel_dump_pipe_config] requested mode:
>[   45.814823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   45.814823] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.814825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   45.814826] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   45.814827] [drm:intel_dump_pipe_config] port clock: 162000
>[   45.814828] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   45.814838] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   45.814839] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.814840] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.814841] [drm:intel_dump_pipe_config] ips: 0
>[   45.814841] [drm:intel_dump_pipe_config] double wide: 0
>[   45.814843] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.814844] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.814845] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   45.814846] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   45.814847] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   45.814848] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   45.814849] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.814852] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.814853] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   45.814855] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   45.814856] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   45.814857] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.814858] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   45.814946] [drm:intel_disable_pipe] disabling pipe C
>[   45.818423] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   45.818428] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   45.818432] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.818433] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.818434] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.818435] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.818436] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.818437] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.818437] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.818438] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.818439] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.818440] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.818441] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.818442] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.818443] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.818445] [drm:verify_single_dpll_state] PORT PLL A
>[   45.818446] [drm:verify_single_dpll_state] PORT PLL B
>[   45.818447] [drm:verify_single_dpll_state] PORT PLL C
>[   45.818450] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   45.818451] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   45.819181] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   45.819182] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.822324] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   45.822325] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.822549] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   45.823076] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   45.823077] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   45.825484] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   45.825524] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   45.825570] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.825573] [drm:intel_enable_pipe] enabling pipe A
>[   45.825585] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.829728] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   45.829730] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.829741] [drm:verify_single_dpll_state] PORT PLL C
>[   45.829747] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   45.833954] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   45.854551] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   45.858753] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   45.858755] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.858757] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.858766] [drm:intel_disable_pipe] disabling pipe A
>[   45.865400] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   45.865405] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   45.865408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   45.873355] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   45.873357] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.873358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.873359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.873360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.873361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.873362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.873363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.873364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.873364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.873365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.873366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.873367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.873369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   45.873370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.873371] [drm:verify_single_dpll_state] PORT PLL A
>[   45.873372] [drm:verify_single_dpll_state] PORT PLL B
>[   45.873373] [drm:verify_single_dpll_state] PORT PLL C
>[   45.873376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   45.873377] [drm:intel_power_well_disable] disabling power well 2
>[   45.873380] [drm:skl_set_power_well] Disabling power well 2
>[   45.873382] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.873385] [drm:intel_power_well_disable] disabling DC off
>[   45.873386] [drm:gen9_enable_dc5] Enabling DC5
>[   45.873387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   45.873389] [drm:intel_power_well_disable] disabling always-on
>[   45.874915] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.875216] [drm:drm_mode_addfb2] [FB:96]
>[   45.879462] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   45.879465] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   45.879472] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   45.879473] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.879475] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   45.879477] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   45.879478] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   45.879479] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.879480] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a835000 for pipe A
>[   45.879481] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   45.879482] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.879483] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.879484] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   45.879485] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.879486] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   45.879487] [drm:intel_dump_pipe_config] requested mode:
>[   45.879489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   45.879489] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.879491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   45.879492] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   45.879493] [drm:intel_dump_pipe_config] port clock: 162000
>[   45.879494] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   45.879495] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   45.879496] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.879504] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.879505] [drm:intel_dump_pipe_config] ips: 0
>[   45.879506] [drm:intel_dump_pipe_config] double wide: 0
>[   45.879507] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.879508] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.879509] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   45.879510] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   45.879511] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   45.879512] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   45.879514] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.879517] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.879519] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C
>[   45.879520] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A
>[   45.879521] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.879604] [drm:intel_power_well_enable] enabling always-on
>[   45.879605] [drm:intel_power_well_enable] enabling DC off
>[   45.879668] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   45.879671] [drm:intel_power_well_enable] enabling power well 2
>[   45.879672] [drm:skl_set_power_well] Enabling power well 2
>[   45.879676] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   45.879677] [drm:intel_power_well_enable] enabling dpio-common-a
>[   45.889358] [drm:intel_power_well_disable] disabling dpio-common-a
>[   45.889362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   45.897355] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   45.897356] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.897358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.897360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.897360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.897361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.897362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.897363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.897364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.897364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.897365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.897366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.897368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.897369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.897370] [drm:verify_single_dpll_state] PORT PLL A
>[   45.897371] [drm:verify_single_dpll_state] PORT PLL B
>[   45.897372] [drm:verify_single_dpll_state] PORT PLL C
>[   45.897377] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26
>[   45.897378] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   45.898114] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   45.898115] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.902306] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   45.902307] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   45.902531] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   45.903059] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   45.903060] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   45.909365] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   45.909406] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   45.909452] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.909454] [drm:intel_enable_pipe] enabling pipe A
>[   45.909476] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.909480] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   45.913612] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   45.913615] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.913628] [drm:verify_single_dpll_state] PORT PLL C
>[   45.917836] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   45.938435] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   45.942641] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   45.942644] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.942645] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.942666] [drm:intel_disable_pipe] disabling pipe A
>[   45.949398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26
>[   45.949404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   45.949406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   45.957355] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   45.957356] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.957357] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.957359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.957360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.957360] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.957361] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.957362] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.957363] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.957364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.957365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   45.957366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   45.957367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.957368] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   45.957369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.957370] [drm:verify_single_dpll_state] PORT PLL A
>[   45.957371] [drm:verify_single_dpll_state] PORT PLL B
>[   45.957372] [drm:verify_single_dpll_state] PORT PLL C
>[   45.957375] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   45.957376] [drm:intel_power_well_disable] disabling power well 2
>[   45.957379] [drm:skl_set_power_well] Disabling power well 2
>[   45.957382] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   45.957384] [drm:intel_power_well_disable] disabling DC off
>[   45.957385] [drm:gen9_enable_dc5] Enabling DC5
>[   45.957386] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   45.957388] [drm:intel_power_well_disable] disabling always-on
>[   45.958625] kms_pipe_crc_basic: exiting, ret=0
>[   45.958734] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   45.958735] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.958737] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.958738] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   45.958740] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   45.958740] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   45.958741] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.958742] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880467355800 for pipe A
>[   45.958743] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   45.958743] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.958744] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.958745] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   45.958745] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.958746] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   45.958746] [drm:intel_dump_pipe_config] requested mode:
>[   45.958747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   45.958748] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.958749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   45.958750] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   45.958750] [drm:intel_dump_pipe_config] port clock: 270000
>[   45.958751] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   45.958751] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   45.958752] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.958752] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.958752] [drm:intel_dump_pipe_config] ips: 0
>[   45.958753] [drm:intel_dump_pipe_config] double wide: 0
>[   45.958754] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.958754] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.958755] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[   45.958755] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   45.958756] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   45.958756] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   45.958757] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   45.958757] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.958758] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   45.958760] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   45.958760] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   45.958761] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.958762] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88046a835000 for pipe B
>[   45.958762] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   45.958762] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.958763] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.958764] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   45.958764] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.958765] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   45.958765] [drm:intel_dump_pipe_config] requested mode:
>[   45.958766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   45.958766] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.958767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   45.958768] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   45.958769] [drm:intel_dump_pipe_config] port clock: 162000
>[   45.958769] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   45.958770] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   45.958770] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.958771] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.958771] [drm:intel_dump_pipe_config] ips: 0
>[   45.958771] [drm:intel_dump_pipe_config] double wide: 0
>[   45.958772] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.958773] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.958774] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   45.958775] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   45.958775] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   45.958776] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   45.958776] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   45.958777] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   45.958777] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   45.958778] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   45.958778] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   45.958779] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   45.958780] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   45.958780] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   45.958781] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467356000 for pipe C
>[   45.958781] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   45.958782] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   45.958782] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   45.958783] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   45.958784] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   45.958784] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   45.958784] [drm:intel_dump_pipe_config] requested mode:
>[   45.958785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   45.958786] [drm:intel_dump_pipe_config] adjusted mode:
>[   45.958787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   45.958788] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   45.958788] [drm:intel_dump_pipe_config] port clock: 162000
>[   45.958788] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   45.958789] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   45.958789] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   45.958790] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   45.958790] [drm:intel_dump_pipe_config] ips: 0
>[   45.958791] [drm:intel_dump_pipe_config] double wide: 0
>[   45.958792] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   45.958792] [drm:intel_dump_pipe_config] planes on this crtc
>[   45.958793] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   45.958794] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   45.958794] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   45.958794] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   45.958795] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   45.958796] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   45.958798] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   45.958799] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   45.958799] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   45.958801] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   45.958801] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   45.958802] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   45.958803] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   45.958803] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   45.958804] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   45.958804] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   45.958805] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   45.958805] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   45.958815] [drm:intel_power_well_enable] enabling always-on
>[   45.958816] [drm:intel_power_well_enable] enabling DC off
>[   45.958879] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   45.958882] [drm:intel_power_well_enable] enabling dpio-common-a
>[   45.965367] [drm:intel_power_well_enable] enabling power well 2
>[   45.965368] [drm:skl_set_power_well] Enabling power well 2
>[   45.969355] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   45.973360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   45.981352] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   45.981354] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   45.981355] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   45.981355] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   45.981356] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   45.981356] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   45.981356] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   45.981357] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   45.981357] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   45.981358] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   45.981358] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   45.981360] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   45.981361] [drm:verify_single_dpll_state] PORT PLL A
>[   45.981362] [drm:verify_single_dpll_state] PORT PLL B
>[   45.981362] [drm:verify_single_dpll_state] PORT PLL C
>[   45.981367] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   45.981368] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   45.981390] [drm:edp_panel_on] Turn eDP port A panel power on
>[   45.981391] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   46.153354] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   46.153354] [drm:wait_panel_status] Wait complete
>[   46.153355] [drm:wait_panel_on] Wait for panel power on
>[   46.153356] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   46.180001] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   46.180002] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   46.180003] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   46.180011] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   46.221357] [drm:wait_panel_status] Wait complete
>[   46.221359] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   46.221360] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   46.222071] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   46.222071] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   46.222289] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   46.222804] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   46.222840] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   46.222885] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.222887] [drm:intel_enable_pipe] enabling pipe A
>[   46.222896] [drm:intel_edp_backlight_on] 
>[   46.222896] [drm:intel_panel_enable_backlight] pipe A
>[   46.222897] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   46.229354] [drm:intel_psr_enable] PSR not supported on this platform
>[   46.229354] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   46.229365] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   46.229365] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   46.230097] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   46.230098] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   46.233578] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   46.241347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   46.241391] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   46.241438] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.241439] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   46.241441] [drm:intel_enable_pipe] enabling pipe B
>[   46.241449] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   46.241450] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   46.241508] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   46.241508] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   46.242240] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   46.242241] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   46.245794] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   46.245794] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   46.246018] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   46.246545] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   46.246545] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   46.249347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   46.249391] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   46.249441] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.249443] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   46.249444] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   46.249445] [drm:intel_enable_pipe] enabling pipe C
>[   46.253594] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   46.253596] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   46.253610] [drm:verify_single_dpll_state] PORT PLL A
>[   46.253617] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   46.253618] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   46.253628] [drm:verify_single_dpll_state] PORT PLL B
>[   46.253633] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   46.253635] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   46.253644] [drm:verify_single_dpll_state] PORT PLL C
>[   46.258626] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   46.258628] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   46.258682] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   46.258683] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   46.258696] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   46.258697] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   46.258711] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   46.258712] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   46.259235] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   46.259238] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   46.259239] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   47.332664] kms_pipe_crc_basic: executing
>[   47.332862] [drm:i915_gem_open] 
>[   47.332989] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   47.332991] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   47.333031] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   47.333033] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   47.333045] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   47.333046] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   47.333056] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   47.333057] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   47.333619] [drm:i915_gem_open] 
>[   47.333780] [drm:i915_gem_open] 
>[   47.334931] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[   47.335777] [drm:drm_mode_addfb2] [FB:96]
>[   47.339650] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   47.339654] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   47.339669] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   47.339671] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   47.339679] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   47.339681] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   47.339683] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   47.339684] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   47.339685] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   47.339687] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a837000 for pipe C
>[   47.339688] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   47.339689] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   47.339690] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   47.339691] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   47.339692] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   47.339693] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   47.339694] [drm:intel_dump_pipe_config] requested mode:
>[   47.339695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   47.339696] [drm:intel_dump_pipe_config] adjusted mode:
>[   47.339697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   47.339699] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   47.339700] [drm:intel_dump_pipe_config] port clock: 270000
>[   47.339700] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   47.339701] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   47.339702] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   47.339703] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   47.339704] [drm:intel_dump_pipe_config] ips: 0
>[   47.339705] [drm:intel_dump_pipe_config] double wide: 0
>[   47.339706] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   47.339707] [drm:intel_dump_pipe_config] planes on this crtc
>[   47.339708] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   47.339710] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   47.339711] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[   47.339712] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   47.339713] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   47.339714] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   47.339717] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   47.339718] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   47.339719] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   47.339721] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   47.339722] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   47.339723] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   47.339820] [drm:intel_edp_backlight_off] 
>[   47.541348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   47.541359] [drm:intel_disable_pipe] disabling pipe A
>[   47.545455] [drm:edp_panel_off] Turn eDP port A panel power off
>[   47.545456] [drm:wait_panel_off] Wait for panel power off time
>[   47.545458] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   47.558605] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   47.558607] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   47.558608] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   47.558618] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   47.573361] [drm:wait_panel_status] Wait complete
>[   47.573364] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   47.573370] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   47.573377] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   47.573379] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   47.573384] [drm:intel_disable_pipe] disabling pipe C
>[   47.577499] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   47.577503] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   47.577506] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   47.577507] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   47.577508] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   47.577509] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   47.577510] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   47.577510] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   47.577512] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   47.577512] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   47.577513] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   47.577514] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   47.577516] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   47.577517] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   47.577518] [drm:verify_single_dpll_state] PORT PLL A
>[   47.577519] [drm:verify_single_dpll_state] PORT PLL B
>[   47.577523] [drm:verify_single_dpll_state] PORT PLL C
>[   47.577527] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   47.577539] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   47.577540] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   47.577562] [drm:edp_panel_on] Turn eDP port A panel power on
>[   47.577563] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   48.049360] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   48.049362] [drm:wait_panel_status] Wait complete
>[   48.049364] [drm:wait_panel_on] Wait for panel power on
>[   48.049365] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   48.076019] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   48.076021] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   48.076022] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   48.076032] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   48.105346] [drm:wait_panel_status] Wait complete
>[   48.105351] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   48.105359] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   48.106071] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   48.106072] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   48.106292] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   48.106808] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   48.106845] [drm:skylake_pfit_enable] for crtc_state = ffff88046a837000
>[   48.106894] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   48.106895] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   48.106898] [drm:intel_enable_pipe] enabling pipe C
>[   48.106901] [drm:intel_edp_backlight_on] 
>[   48.106902] [drm:intel_panel_enable_backlight] pipe C
>[   48.106905] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   48.113350] [drm:intel_psr_enable] PSR not supported on this platform
>[   48.113352] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   48.115194] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   48.115199] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   48.115201] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   48.115214] [drm:verify_single_dpll_state] PORT PLL A
>[   48.119425] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   48.140013] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   48.144221] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   48.144223] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   48.144225] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   48.144249] [drm:intel_edp_backlight_off] 
>[   48.345347] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   48.345352] [drm:intel_disable_pipe] disabling pipe C
>[   48.349418] [drm:edp_panel_off] Turn eDP port A panel power off
>[   48.349419] [drm:wait_panel_off] Wait for panel power off time
>[   48.349421] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   48.362561] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   48.362563] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   48.362565] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   48.362578] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   48.373346] [drm:wait_panel_status] Wait complete
>[   48.373350] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   48.373362] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   48.373366] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   48.373369] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   48.373371] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   48.373372] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   48.373373] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   48.373373] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   48.373374] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   48.373375] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   48.373376] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   48.373377] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   48.373378] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   48.373379] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   48.373381] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   48.373382] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   48.373383] [drm:verify_single_dpll_state] PORT PLL A
>[   48.373384] [drm:verify_single_dpll_state] PORT PLL B
>[   48.373388] [drm:verify_single_dpll_state] PORT PLL C
>[   48.373394] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   48.373397] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   48.373405] [drm:intel_power_well_disable] disabling dpio-common-a
>[   48.373408] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   48.378406] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   48.380987] [drm:drm_mode_addfb2] [FB:96]
>[   48.384676] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   48.384680] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   48.384686] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   48.384687] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   48.384690] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   48.384691] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   48.384694] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   48.384702] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   48.384703] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   48.384710] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835000 for pipe C
>[   48.384712] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   48.384712] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   48.384713] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   48.384715] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   48.384716] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   48.384716] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   48.384717] [drm:intel_dump_pipe_config] requested mode:
>[   48.384719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   48.384720] [drm:intel_dump_pipe_config] adjusted mode:
>[   48.384721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   48.384722] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   48.384723] [drm:intel_dump_pipe_config] port clock: 270000
>[   48.384724] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   48.384725] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   48.384726] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   48.384727] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   48.384728] [drm:intel_dump_pipe_config] ips: 0
>[   48.384728] [drm:intel_dump_pipe_config] double wide: 0
>[   48.384730] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   48.384731] [drm:intel_dump_pipe_config] planes on this crtc
>[   48.384732] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   48.384732] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   48.384733] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   48.384735] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   48.384737] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   48.384739] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   48.384740] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   48.384741] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   48.384825] [drm:intel_power_well_enable] enabling dpio-common-a
>[   48.389360] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   48.389362] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   48.389363] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   48.389364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   48.389365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   48.389366] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   48.389367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   48.389368] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   48.389369] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   48.389370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   48.389372] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   48.389373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   48.389374] [drm:verify_single_dpll_state] PORT PLL A
>[   48.389376] [drm:verify_single_dpll_state] PORT PLL B
>[   48.389380] [drm:verify_single_dpll_state] PORT PLL C
>[   48.389383] [drm:skl_wm_flush_pipe] flush pipe B (pass 1)
>[   48.393158] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   48.393168] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   48.393169] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   48.393191] [drm:edp_panel_on] Turn eDP port A panel power on
>[   48.393192] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   48.853348] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   48.853350] [drm:wait_panel_status] Wait complete
>[   48.853352] [drm:wait_panel_on] Wait for panel power on
>[   48.853359] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[   48.879995] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   48.879997] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   48.879999] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   48.880008] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   48.913346] [drm:wait_panel_status] Wait complete
>[   48.913350] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   48.913359] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   48.914072] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   48.914073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   48.914292] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   48.914807] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   48.914844] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   48.914893] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   48.914895] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   48.914897] [drm:intel_enable_pipe] enabling pipe C
>[   48.914900] [drm:intel_edp_backlight_on] 
>[   48.914902] [drm:intel_panel_enable_backlight] pipe C
>[   48.914904] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   48.921350] [drm:intel_psr_enable] PSR not supported on this platform
>[   48.921352] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   48.923193] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   48.923196] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   48.923210] [drm:verify_single_dpll_state] PORT PLL A
>[   48.927421] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   48.948012] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   48.952218] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   48.952221] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   48.952223] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   48.952250] [drm:intel_edp_backlight_off] 
>[   49.153348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   49.153359] [drm:intel_disable_pipe] disabling pipe C
>[   49.157403] [drm:edp_panel_off] Turn eDP port A panel power off
>[   49.157404] [drm:wait_panel_off] Wait for panel power off time
>[   49.157406] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   49.170535] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   49.170538] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   49.170539] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   49.170549] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   49.181347] [drm:wait_panel_status] Wait complete
>[   49.181350] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   49.181363] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   49.181367] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   49.181370] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.181371] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.181372] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.181373] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.181374] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.181375] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.181376] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.181377] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.181378] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.181378] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.181380] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.181381] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.181383] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.181384] [drm:verify_single_dpll_state] PORT PLL A
>[   49.181385] [drm:verify_single_dpll_state] PORT PLL B
>[   49.181389] [drm:verify_single_dpll_state] PORT PLL C
>[   49.181392] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   49.181395] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   49.181403] [drm:intel_power_well_disable] disabling dpio-common-a
>[   49.181406] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.185006] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.187902] [drm:drm_mode_addfb2] [FB:96]
>[   49.191882] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.191886] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   49.191893] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   49.191894] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.191896] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   49.191899] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   49.191900] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   49.191901] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.191903] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a837000 for pipe C
>[   49.191903] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   49.191904] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.191905] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.191907] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   49.191908] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.191916] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   49.191917] [drm:intel_dump_pipe_config] requested mode:
>[   49.191919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   49.191919] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.191921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   49.191922] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   49.191923] [drm:intel_dump_pipe_config] port clock: 162000
>[   49.191924] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   49.191925] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   49.191926] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.191927] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.191927] [drm:intel_dump_pipe_config] ips: 0
>[   49.191928] [drm:intel_dump_pipe_config] double wide: 0
>[   49.191930] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.191930] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.191931] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   49.191932] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   49.191933] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   49.191935] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   49.191937] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   49.191938] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.191940] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   49.191942] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   49.191943] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   49.191944] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.192041] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   49.192092] [drm:intel_disable_pipe] disabling pipe B
>[   49.197398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   49.197403] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   49.197408] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.197409] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.197410] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.197411] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.197411] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.197412] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.197413] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.197414] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.197415] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.197416] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.197417] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.197418] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.197419] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.197420] [drm:verify_single_dpll_state] PORT PLL A
>[   49.197422] [drm:verify_single_dpll_state] PORT PLL B
>[   49.197422] [drm:verify_single_dpll_state] PORT PLL C
>[   49.197426] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   49.197427] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   49.198159] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.198160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.202118] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.209347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.209388] [drm:skylake_pfit_enable] for crtc_state = ffff88046a837000
>[   49.209432] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   49.209435] [drm:intel_enable_pipe] enabling pipe C
>[   49.209438] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   49.209440] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   49.213592] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   49.213597] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.213599] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.213610] [drm:verify_single_dpll_state] PORT PLL B
>[   49.217818] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   49.238435] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   49.242635] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   49.242638] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.242640] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.242648] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   49.242668] [drm:intel_disable_pipe] disabling pipe C
>[   49.249399] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   49.249404] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   49.249407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   49.257349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.257351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.257359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.257360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.257361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.257362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.257362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.257363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.257364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.257365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.257366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.257367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.257368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.257369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.257371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.257372] [drm:verify_single_dpll_state] PORT PLL A
>[   49.257373] [drm:verify_single_dpll_state] PORT PLL B
>[   49.257374] [drm:verify_single_dpll_state] PORT PLL C
>[   49.257377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   49.257378] [drm:intel_power_well_disable] disabling power well 2
>[   49.257381] [drm:skl_set_power_well] Disabling power well 2
>[   49.257384] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.257385] [drm:intel_power_well_disable] disabling DC off
>[   49.257386] [drm:gen9_enable_dc5] Enabling DC5
>[   49.257388] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   49.257389] [drm:intel_power_well_disable] disabling always-on
>[   49.259034] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.259349] [drm:drm_mode_addfb2] [FB:96]
>[   49.263879] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.263882] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   49.263889] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   49.263890] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.263892] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   49.263895] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   49.263895] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   49.263897] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.263898] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835000 for pipe C
>[   49.263899] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   49.263900] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.263901] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.263902] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   49.263903] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.263904] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   49.263905] [drm:intel_dump_pipe_config] requested mode:
>[   49.263906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   49.263907] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.263909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   49.263910] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   49.263919] [drm:intel_dump_pipe_config] port clock: 162000
>[   49.263919] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   49.263920] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   49.263921] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.263922] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.263923] [drm:intel_dump_pipe_config] ips: 0
>[   49.263924] [drm:intel_dump_pipe_config] double wide: 0
>[   49.263925] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.263926] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.263927] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   49.263928] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   49.263929] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   49.263931] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   49.263933] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.263936] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   49.263937] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   49.263938] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.264029] [drm:intel_power_well_enable] enabling always-on
>[   49.264030] [drm:intel_power_well_enable] enabling DC off
>[   49.264093] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   49.264096] [drm:intel_power_well_enable] enabling power well 2
>[   49.264097] [drm:skl_set_power_well] Enabling power well 2
>[   49.264101] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   49.264102] [drm:intel_power_well_enable] enabling dpio-common-a
>[   49.273351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   49.273362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   49.281349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.281351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.281359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.281360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.281361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.281362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.281363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.281364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.281365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.281365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.281366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.281367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.281369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.281370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.281371] [drm:verify_single_dpll_state] PORT PLL A
>[   49.281372] [drm:verify_single_dpll_state] PORT PLL B
>[   49.281373] [drm:verify_single_dpll_state] PORT PLL C
>[   49.281379] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   49.281380] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   49.282117] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.282118] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.285854] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.293347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.293387] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   49.293432] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   49.293435] [drm:intel_enable_pipe] enabling pipe C
>[   49.293439] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   49.293440] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   49.297590] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.297593] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.297607] [drm:verify_single_dpll_state] PORT PLL B
>[   49.301830] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   49.322432] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   49.326638] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   49.326641] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.326643] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.326661] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   49.326670] [drm:intel_disable_pipe] disabling pipe C
>[   49.333399] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   49.333406] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   49.333409] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   49.341366] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.341368] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.341369] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.341371] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.341371] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.341372] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.341373] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.341374] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.341375] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.341376] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.341377] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.341378] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.341379] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.341380] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.341381] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.341383] [drm:verify_single_dpll_state] PORT PLL A
>[   49.341384] [drm:verify_single_dpll_state] PORT PLL B
>[   49.341385] [drm:verify_single_dpll_state] PORT PLL C
>[   49.341388] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   49.341389] [drm:intel_power_well_disable] disabling power well 2
>[   49.341392] [drm:skl_set_power_well] Disabling power well 2
>[   49.341394] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.341396] [drm:intel_power_well_disable] disabling DC off
>[   49.341397] [drm:gen9_enable_dc5] Enabling DC5
>[   49.341398] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   49.341400] [drm:intel_power_well_disable] disabling always-on
>[   49.343109] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.343427] [drm:drm_mode_addfb2] [FB:96]
>[   49.347481] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.347485] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   49.347492] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   49.347493] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.347502] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   49.347504] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   49.347505] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   49.347507] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.347514] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a837000 for pipe C
>[   49.347515] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   49.347516] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.347517] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.347518] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   49.347519] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.347520] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   49.347521] [drm:intel_dump_pipe_config] requested mode:
>[   49.347522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   49.347523] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.347525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   49.347526] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   49.347527] [drm:intel_dump_pipe_config] port clock: 162000
>[   49.347528] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   49.347529] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   49.347530] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.347530] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.347531] [drm:intel_dump_pipe_config] ips: 0
>[   49.347532] [drm:intel_dump_pipe_config] double wide: 0
>[   49.347533] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.347535] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.347536] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   49.347536] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   49.347537] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   49.347540] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   49.347542] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.347545] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   49.347546] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   49.347547] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.347630] [drm:intel_power_well_enable] enabling always-on
>[   49.347631] [drm:intel_power_well_enable] enabling DC off
>[   49.347694] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   49.347697] [drm:intel_power_well_enable] enabling power well 2
>[   49.347698] [drm:skl_set_power_well] Enabling power well 2
>[   49.347701] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   49.347702] [drm:intel_power_well_enable] enabling dpio-common-a
>[   49.357351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   49.357362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   49.365350] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.365351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.365360] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.365361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.365362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.365363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.365363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.365364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.365365] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.365366] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.365367] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.365368] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.365369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.365370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.365371] [drm:verify_single_dpll_state] PORT PLL A
>[   49.365373] [drm:verify_single_dpll_state] PORT PLL B
>[   49.365374] [drm:verify_single_dpll_state] PORT PLL C
>[   49.365380] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   49.365381] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   49.366117] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.366118] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.369866] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   49.369868] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.370092] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.370620] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   49.370621] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   49.373441] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.373481] [drm:skylake_pfit_enable] for crtc_state = ffff88046a837000
>[   49.373526] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   49.373528] [drm:intel_enable_pipe] enabling pipe C
>[   49.377686] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.377689] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.377702] [drm:verify_single_dpll_state] PORT PLL C
>[   49.381911] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   49.402509] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   49.406712] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   49.406715] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.406717] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.406736] [drm:intel_disable_pipe] disabling pipe C
>[   49.413398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   49.413404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   49.413407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   49.421349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.421351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.421359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.421360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.421361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.421362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.421363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.421364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.421364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.421365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.421366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.421367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.421368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.421370] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.421371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.421372] [drm:verify_single_dpll_state] PORT PLL A
>[   49.421373] [drm:verify_single_dpll_state] PORT PLL B
>[   49.421374] [drm:verify_single_dpll_state] PORT PLL C
>[   49.421377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   49.421378] [drm:intel_power_well_disable] disabling power well 2
>[   49.421381] [drm:skl_set_power_well] Disabling power well 2
>[   49.421383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.421385] [drm:intel_power_well_disable] disabling DC off
>[   49.421386] [drm:gen9_enable_dc5] Enabling DC5
>[   49.421387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   49.421389] [drm:intel_power_well_disable] disabling always-on
>[   49.422956] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.423276] [drm:drm_mode_addfb2] [FB:96]
>[   49.427554] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.427557] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   49.427564] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   49.427565] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.427567] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   49.427569] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   49.427569] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   49.427571] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.427572] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835000 for pipe C
>[   49.427573] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   49.427574] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.427575] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.427576] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   49.427577] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.427578] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   49.427579] [drm:intel_dump_pipe_config] requested mode:
>[   49.427581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   49.427581] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.427591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   49.427592] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   49.427593] [drm:intel_dump_pipe_config] port clock: 162000
>[   49.427594] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   49.427595] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   49.427596] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.427597] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.427597] [drm:intel_dump_pipe_config] ips: 0
>[   49.427598] [drm:intel_dump_pipe_config] double wide: 0
>[   49.427600] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.427600] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.427601] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   49.427602] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   49.427603] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   49.427606] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   49.427608] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.427610] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   49.427611] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   49.427612] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.427695] [drm:intel_power_well_enable] enabling always-on
>[   49.427696] [drm:intel_power_well_enable] enabling DC off
>[   49.427760] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   49.427762] [drm:intel_power_well_enable] enabling power well 2
>[   49.427764] [drm:skl_set_power_well] Enabling power well 2
>[   49.427767] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   49.427768] [drm:intel_power_well_enable] enabling dpio-common-a
>[   49.437351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   49.437362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   49.445367] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.445368] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.445370] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.445371] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.445372] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.445373] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.445374] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.445375] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.445375] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.445376] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.445377] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.445378] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.445380] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.445381] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.445382] [drm:verify_single_dpll_state] PORT PLL A
>[   49.445383] [drm:verify_single_dpll_state] PORT PLL B
>[   49.445384] [drm:verify_single_dpll_state] PORT PLL C
>[   49.445389] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   49.445390] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   49.446126] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.446127] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.449865] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   49.449866] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.450091] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.450618] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   49.450619] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   49.453438] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.453478] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   49.453523] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   49.453525] [drm:intel_enable_pipe] enabling pipe C
>[   49.457684] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.457687] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.457700] [drm:verify_single_dpll_state] PORT PLL C
>[   49.461909] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   49.482507] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   49.486712] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   49.486715] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.486717] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.486726] [drm:intel_disable_pipe] disabling pipe C
>[   49.493398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   49.493403] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   49.493406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   49.501349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.501351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.501359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.501360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.501361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.501362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.501362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.501364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.501364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.501365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.501366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.501367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.501368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.501369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.501371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.501372] [drm:verify_single_dpll_state] PORT PLL A
>[   49.501373] [drm:verify_single_dpll_state] PORT PLL B
>[   49.501374] [drm:verify_single_dpll_state] PORT PLL C
>[   49.501377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   49.501378] [drm:intel_power_well_disable] disabling power well 2
>[   49.501381] [drm:skl_set_power_well] Disabling power well 2
>[   49.501383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.501384] [drm:intel_power_well_disable] disabling DC off
>[   49.501386] [drm:gen9_enable_dc5] Enabling DC5
>[   49.501387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   49.501389] [drm:intel_power_well_disable] disabling always-on
>[   49.502641] kms_pipe_crc_basic: exiting, ret=0
>[   49.502756] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   49.502757] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.502758] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   49.502759] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   49.502761] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   49.502762] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   49.502763] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.502764] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a835000 for pipe A
>[   49.502764] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   49.502765] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.502765] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.502766] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   49.502767] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.502767] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   49.502768] [drm:intel_dump_pipe_config] requested mode:
>[   49.502769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   49.502769] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.502770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   49.502771] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   49.502772] [drm:intel_dump_pipe_config] port clock: 270000
>[   49.502772] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   49.502773] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   49.502773] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.502774] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.502774] [drm:intel_dump_pipe_config] ips: 0
>[   49.502774] [drm:intel_dump_pipe_config] double wide: 0
>[   49.502775] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.502776] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.502778] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   49.502778] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   49.502778] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   49.502779] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   49.502779] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   49.502780] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   49.502781] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   49.502781] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.502782] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   49.502783] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   49.502784] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   49.502784] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.502785] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88046a835800 for pipe B
>[   49.502785] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   49.502786] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.502786] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.502787] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   49.502788] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.502788] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   49.502789] [drm:intel_dump_pipe_config] requested mode:
>[   49.502790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   49.502790] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.502791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   49.502792] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   49.502792] [drm:intel_dump_pipe_config] port clock: 162000
>[   49.502793] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   49.502793] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   49.502794] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.502794] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.502794] [drm:intel_dump_pipe_config] ips: 0
>[   49.502795] [drm:intel_dump_pipe_config] double wide: 0
>[   49.502796] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.502796] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.502797] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   49.502798] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   49.502798] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   49.502799] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   49.502799] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   49.502800] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   49.502800] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   49.502801] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.502801] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   49.502802] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   49.502803] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   49.502803] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.502804] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467356000 for pipe C
>[   49.502804] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   49.502805] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.502805] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.502806] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   49.502807] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.502807] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   49.502807] [drm:intel_dump_pipe_config] requested mode:
>[   49.502808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   49.502809] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.502810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   49.502811] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   49.502811] [drm:intel_dump_pipe_config] port clock: 162000
>[   49.502811] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   49.502812] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   49.502812] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.502813] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.502813] [drm:intel_dump_pipe_config] ips: 0
>[   49.502813] [drm:intel_dump_pipe_config] double wide: 0
>[   49.502815] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.502815] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.502815] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   49.502816] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   49.502816] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   49.502817] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   49.502819] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   49.502820] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   49.502821] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.502822] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   49.502823] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   49.502823] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   49.502824] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   49.502825] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   49.502825] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   49.502826] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   49.502826] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   49.502827] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.502837] [drm:intel_power_well_enable] enabling always-on
>[   49.502838] [drm:intel_power_well_enable] enabling DC off
>[   49.502901] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   49.502904] [drm:intel_power_well_enable] enabling dpio-common-a
>[   49.509365] [drm:intel_power_well_enable] enabling power well 2
>[   49.509366] [drm:skl_set_power_well] Enabling power well 2
>[   49.513350] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   49.517360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   49.525347] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   49.525348] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   49.525349] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   49.525349] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   49.525350] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   49.525350] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   49.525351] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   49.525352] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   49.525352] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   49.525358] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   49.525359] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   49.525361] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   49.525362] [drm:verify_single_dpll_state] PORT PLL A
>[   49.525363] [drm:verify_single_dpll_state] PORT PLL B
>[   49.525363] [drm:verify_single_dpll_state] PORT PLL C
>[   49.525368] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   49.525369] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   49.525391] [drm:edp_panel_on] Turn eDP port A panel power on
>[   49.525392] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   49.665348] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   49.665348] [drm:wait_panel_status] Wait complete
>[   49.665349] [drm:wait_panel_on] Wait for panel power on
>[   49.665350] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   49.692012] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   49.692013] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   49.692014] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   49.692017] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   49.725345] [drm:wait_panel_status] Wait complete
>[   49.725348] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   49.725350] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   49.726060] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.726061] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.726279] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.726793] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.726829] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835000
>[   49.726874] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   49.726877] [drm:intel_enable_pipe] enabling pipe A
>[   49.726885] [drm:intel_edp_backlight_on] 
>[   49.726886] [drm:intel_panel_enable_backlight] pipe A
>[   49.726886] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   49.733347] [drm:intel_psr_enable] PSR not supported on this platform
>[   49.733347] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   49.733364] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   49.733365] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   49.734097] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.734097] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.737572] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.745346] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.745384] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835800
>[   49.745432] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   49.745433] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   49.745435] [drm:intel_enable_pipe] enabling pipe B
>[   49.745447] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   49.745448] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   49.745506] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   49.745507] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   49.746237] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   49.746238] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.749787] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   49.749788] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   49.750011] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   49.750537] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   49.750538] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   49.753347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   49.753385] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   49.753437] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   49.753438] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   49.753439] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   49.753441] [drm:intel_enable_pipe] enabling pipe C
>[   49.757588] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   49.757590] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   49.757604] [drm:verify_single_dpll_state] PORT PLL A
>[   49.757611] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   49.757613] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   49.757622] [drm:verify_single_dpll_state] PORT PLL B
>[   49.757627] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   49.757629] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   49.757638] [drm:verify_single_dpll_state] PORT PLL C
>[   49.762626] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.762642] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   49.762701] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.762703] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   49.762715] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.762717] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   49.762726] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.762728] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   49.763196] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   49.763199] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   49.763200] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.983944] kms_pipe_crc_basic: executing
>[   49.984135] [drm:i915_gem_open] 
>[   49.984265] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.984267] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   49.984328] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.984330] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   49.984342] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.984343] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   49.984356] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   49.984357] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   49.984666] [drm:i915_gem_open] 
>[   49.984820] [drm:i915_gem_open] 
>[   49.986244] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[   49.987097] [drm:drm_mode_addfb2] [FB:96]
>[   49.990927] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   49.990931] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   49.990939] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   49.990940] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   49.990942] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.990943] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   49.990946] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   49.990947] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   49.990948] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   49.990949] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467355800 for pipe C
>[   49.990950] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   49.990951] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   49.990952] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   49.990953] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   49.990954] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   49.990955] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   49.990965] [drm:intel_dump_pipe_config] requested mode:
>[   49.990966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   49.990967] [drm:intel_dump_pipe_config] adjusted mode:
>[   49.990969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   49.990970] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   49.990971] [drm:intel_dump_pipe_config] port clock: 270000
>[   49.990971] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   49.990972] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   49.990973] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   49.990974] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   49.990975] [drm:intel_dump_pipe_config] ips: 0
>[   49.990976] [drm:intel_dump_pipe_config] double wide: 0
>[   49.990977] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   49.990978] [drm:intel_dump_pipe_config] planes on this crtc
>[   49.990979] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   49.990981] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   49.990982] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[   49.990983] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   49.990984] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   49.990985] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   49.990988] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   49.990989] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   49.990990] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   49.990992] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   49.990993] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   49.990994] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   49.991089] [drm:intel_edp_backlight_off] 
>[   50.193348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   50.193360] [drm:intel_disable_pipe] disabling pipe A
>[   50.197457] [drm:edp_panel_off] Turn eDP port A panel power off
>[   50.197459] [drm:wait_panel_off] Wait for panel power off time
>[   50.197461] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   50.210599] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   50.210602] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   50.210603] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   50.210613] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   50.221346] [drm:wait_panel_status] Wait complete
>[   50.221350] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   50.221362] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   50.221367] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   50.221369] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   50.221374] [drm:intel_disable_pipe] disabling pipe C
>[   50.225511] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   50.225516] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   50.225519] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   50.225520] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   50.225521] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   50.225522] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   50.225523] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   50.225524] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   50.225525] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   50.225526] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   50.225527] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   50.225528] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   50.225529] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   50.225530] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   50.225532] [drm:verify_single_dpll_state] PORT PLL A
>[   50.225533] [drm:verify_single_dpll_state] PORT PLL B
>[   50.225537] [drm:verify_single_dpll_state] PORT PLL C
>[   50.225541] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   50.225552] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   50.225553] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   50.225575] [drm:edp_panel_on] Turn eDP port A panel power on
>[   50.225576] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   50.701349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   50.701352] [drm:wait_panel_status] Wait complete
>[   50.701359] [drm:wait_panel_on] Wait for panel power on
>[   50.701361] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   50.728010] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   50.728013] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   50.728014] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   50.728024] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   50.761345] [drm:wait_panel_status] Wait complete
>[   50.761350] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   50.761358] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   50.762068] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   50.762069] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   50.762288] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   50.762804] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   50.762843] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   50.762892] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   50.762893] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   50.762896] [drm:intel_enable_pipe] enabling pipe C
>[   50.762899] [drm:intel_edp_backlight_on] 
>[   50.762900] [drm:intel_panel_enable_backlight] pipe C
>[   50.762902] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   50.769350] [drm:intel_psr_enable] PSR not supported on this platform
>[   50.769352] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   50.771188] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   50.771195] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   50.771197] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   50.771210] [drm:verify_single_dpll_state] PORT PLL A
>[   50.775439] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   50.796009] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   50.800218] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   50.800237] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   50.800239] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   50.800249] [drm:intel_edp_backlight_off] 
>[   51.001349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   51.001360] [drm:intel_disable_pipe] disabling pipe C
>[   51.005507] [drm:edp_panel_off] Turn eDP port A panel power off
>[   51.005510] [drm:wait_panel_off] Wait for panel power off time
>[   51.005512] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   51.018648] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   51.018650] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   51.018651] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   51.018661] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   51.029348] [drm:wait_panel_status] Wait complete
>[   51.029352] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   51.029363] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   51.029367] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.029370] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.029372] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.029373] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.029374] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.029375] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.029375] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.029377] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.029377] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.029378] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.029379] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.029381] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.029382] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.029383] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.029385] [drm:verify_single_dpll_state] PORT PLL A
>[   51.029386] [drm:verify_single_dpll_state] PORT PLL B
>[   51.029390] [drm:verify_single_dpll_state] PORT PLL C
>[   51.029393] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.029396] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.029406] [drm:intel_power_well_disable] disabling dpio-common-a
>[   51.029409] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.034180] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.036721] [drm:drm_mode_addfb2] [FB:96]
>[   51.040400] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.040403] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   51.040410] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   51.040411] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   51.040413] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.040414] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   51.040417] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   51.040418] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   51.040419] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   51.040421] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a834000 for pipe C
>[   51.040422] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   51.040422] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   51.040423] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   51.040425] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   51.040435] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   51.040436] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   51.040436] [drm:intel_dump_pipe_config] requested mode:
>[   51.040438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   51.040439] [drm:intel_dump_pipe_config] adjusted mode:
>[   51.040440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   51.040442] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   51.040442] [drm:intel_dump_pipe_config] port clock: 270000
>[   51.040443] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   51.040444] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   51.040445] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   51.040446] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   51.040447] [drm:intel_dump_pipe_config] ips: 0
>[   51.040447] [drm:intel_dump_pipe_config] double wide: 0
>[   51.040449] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   51.040450] [drm:intel_dump_pipe_config] planes on this crtc
>[   51.040451] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   51.040452] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   51.040453] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   51.040454] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   51.040456] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   51.040458] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   51.040459] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   51.040460] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.040550] [drm:intel_power_well_enable] enabling dpio-common-a
>[   51.045359] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.045361] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.045362] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.045363] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.045364] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.045364] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.045366] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.045367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.045368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.045369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.045371] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.045372] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.045373] [drm:verify_single_dpll_state] PORT PLL A
>[   51.045374] [drm:verify_single_dpll_state] PORT PLL B
>[   51.045378] [drm:verify_single_dpll_state] PORT PLL C
>[   51.045382] [drm:skl_wm_flush_pipe] flush pipe B (pass 1)
>[   51.048892] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.048903] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   51.048903] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   51.048926] [drm:edp_panel_on] Turn eDP port A panel power on
>[   51.048927] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   51.509349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   51.509351] [drm:wait_panel_status] Wait complete
>[   51.509358] [drm:wait_panel_on] Wait for panel power on
>[   51.509360] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   51.536007] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   51.536009] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   51.536010] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   51.536021] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   51.561346] [drm:wait_panel_status] Wait complete
>[   51.561351] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   51.561360] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   51.562070] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   51.562071] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   51.562291] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   51.562807] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   51.562844] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834000
>[   51.562892] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.562894] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   51.562896] [drm:intel_enable_pipe] enabling pipe C
>[   51.562900] [drm:intel_edp_backlight_on] 
>[   51.562901] [drm:intel_panel_enable_backlight] pipe C
>[   51.562902] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   51.569349] [drm:intel_psr_enable] PSR not supported on this platform
>[   51.569351] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   51.571195] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.571198] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.571211] [drm:verify_single_dpll_state] PORT PLL A
>[   51.575421] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   51.596013] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   51.600215] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   51.600218] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   51.600220] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.600241] [drm:intel_edp_backlight_off] 
>[   51.801347] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   51.801359] [drm:intel_disable_pipe] disabling pipe C
>[   51.805401] [drm:edp_panel_off] Turn eDP port A panel power off
>[   51.805402] [drm:wait_panel_off] Wait for panel power off time
>[   51.805404] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   51.818535] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   51.818537] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   51.818539] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   51.818549] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   51.837360] [drm:wait_panel_status] Wait complete
>[   51.837362] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   51.837368] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   51.837372] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.837375] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.837377] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.837377] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.837378] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.837379] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.837380] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.837381] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.837382] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.837383] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.837384] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.837385] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.837389] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.837390] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.837391] [drm:verify_single_dpll_state] PORT PLL A
>[   51.837392] [drm:verify_single_dpll_state] PORT PLL B
>[   51.837396] [drm:verify_single_dpll_state] PORT PLL C
>[   51.837399] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.837403] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   51.837411] [drm:intel_power_well_disable] disabling dpio-common-a
>[   51.837413] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.840748] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.843634] [drm:drm_mode_addfb2] [FB:96]
>[   51.847628] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.847631] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   51.847639] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   51.847640] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   51.847642] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   51.847644] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   51.847645] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   51.847646] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   51.847648] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a834000 for pipe C
>[   51.847649] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   51.847650] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   51.847651] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   51.847652] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   51.847653] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   51.847654] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   51.847655] [drm:intel_dump_pipe_config] requested mode:
>[   51.847656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   51.847657] [drm:intel_dump_pipe_config] adjusted mode:
>[   51.847666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   51.847668] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   51.847669] [drm:intel_dump_pipe_config] port clock: 162000
>[   51.847669] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   51.847670] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   51.847671] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   51.847672] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   51.847673] [drm:intel_dump_pipe_config] ips: 0
>[   51.847674] [drm:intel_dump_pipe_config] double wide: 0
>[   51.847675] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   51.847676] [drm:intel_dump_pipe_config] planes on this crtc
>[   51.847677] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   51.847678] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   51.847679] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   51.847680] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   51.847683] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   51.847684] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   51.847686] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   51.847687] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   51.847688] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   51.847689] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.847787] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   51.847837] [drm:intel_disable_pipe] disabling pipe B
>[   51.853398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   51.853403] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   51.853408] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.853409] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.853410] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.853411] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.853411] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.853412] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.853413] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.853414] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.853415] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.853416] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.853417] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.853418] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.853419] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.853420] [drm:verify_single_dpll_state] PORT PLL A
>[   51.853421] [drm:verify_single_dpll_state] PORT PLL B
>[   51.853422] [drm:verify_single_dpll_state] PORT PLL C
>[   51.853426] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   51.853427] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   51.854159] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   51.854160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   51.857881] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   51.865347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   51.865387] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834000
>[   51.865432] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   51.865434] [drm:intel_enable_pipe] enabling pipe C
>[   51.865439] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   51.865440] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   51.869597] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   51.869602] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   51.869604] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.869615] [drm:verify_single_dpll_state] PORT PLL B
>[   51.873826] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   51.894439] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   51.898647] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   51.898649] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   51.898652] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.898660] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   51.898678] [drm:intel_disable_pipe] disabling pipe C
>[   51.905398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   51.905403] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   51.905407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   51.913349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   51.913351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.913358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.913360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.913361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.913361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.913362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.913363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.913364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.913365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.913366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.913367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   51.913368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.913369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.913370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.913372] [drm:verify_single_dpll_state] PORT PLL A
>[   51.913373] [drm:verify_single_dpll_state] PORT PLL B
>[   51.913374] [drm:verify_single_dpll_state] PORT PLL C
>[   51.913377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   51.913378] [drm:intel_power_well_disable] disabling power well 2
>[   51.913381] [drm:skl_set_power_well] Disabling power well 2
>[   51.913383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.913385] [drm:intel_power_well_disable] disabling DC off
>[   51.913386] [drm:gen9_enable_dc5] Enabling DC5
>[   51.913387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   51.913389] [drm:intel_power_well_disable] disabling always-on
>[   51.915042] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.915359] [drm:drm_mode_addfb2] [FB:96]
>[   51.919650] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.919654] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   51.919660] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   51.919661] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   51.919663] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   51.919666] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   51.919667] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   51.919677] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   51.919685] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a836000 for pipe C
>[   51.919686] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   51.919686] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   51.919688] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   51.919689] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   51.919690] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   51.919691] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   51.919691] [drm:intel_dump_pipe_config] requested mode:
>[   51.919693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   51.919694] [drm:intel_dump_pipe_config] adjusted mode:
>[   51.919695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   51.919697] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   51.919697] [drm:intel_dump_pipe_config] port clock: 162000
>[   51.919698] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   51.919699] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   51.919700] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   51.919701] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   51.919702] [drm:intel_dump_pipe_config] ips: 0
>[   51.919702] [drm:intel_dump_pipe_config] double wide: 0
>[   51.919704] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   51.919705] [drm:intel_dump_pipe_config] planes on this crtc
>[   51.919706] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   51.919707] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   51.919708] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   51.919710] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   51.919712] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   51.919715] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   51.919716] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   51.919717] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.919808] [drm:intel_power_well_enable] enabling always-on
>[   51.919809] [drm:intel_power_well_enable] enabling DC off
>[   51.919872] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   51.919875] [drm:intel_power_well_enable] enabling power well 2
>[   51.919876] [drm:skl_set_power_well] Enabling power well 2
>[   51.919880] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   51.919880] [drm:intel_power_well_enable] enabling dpio-common-a
>[   51.929351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   51.929362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   51.937349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   51.937351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.937359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.937360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.937361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.937362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.937362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.937364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.937364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.937365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.937366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.937367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.937368] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.937370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.937371] [drm:verify_single_dpll_state] PORT PLL A
>[   51.937372] [drm:verify_single_dpll_state] PORT PLL B
>[   51.937373] [drm:verify_single_dpll_state] PORT PLL C
>[   51.937378] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   51.937379] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   51.938116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   51.938117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   51.941863] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   51.949347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   51.949388] [drm:skylake_pfit_enable] for crtc_state = ffff88046a836000
>[   51.949432] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   51.949435] [drm:intel_enable_pipe] enabling pipe C
>[   51.949439] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   51.949441] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   51.953590] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   51.953593] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.953607] [drm:verify_single_dpll_state] PORT PLL B
>[   51.957816] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   51.978432] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   51.982637] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   51.982640] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   51.982642] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   51.982650] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   51.982669] [drm:intel_disable_pipe] disabling pipe C
>[   51.989398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   51.989405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   51.989408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   51.997349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   51.997351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   51.997358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   51.997359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   51.997360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   51.997361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   51.997362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   51.997363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   51.997364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   51.997365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   51.997366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   51.997367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   51.997368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   51.997369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   51.997370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   51.997371] [drm:verify_single_dpll_state] PORT PLL A
>[   51.997372] [drm:verify_single_dpll_state] PORT PLL B
>[   51.997373] [drm:verify_single_dpll_state] PORT PLL C
>[   51.997377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   51.997378] [drm:intel_power_well_disable] disabling power well 2
>[   51.997381] [drm:skl_set_power_well] Disabling power well 2
>[   51.997383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   51.997385] [drm:intel_power_well_disable] disabling DC off
>[   51.997386] [drm:gen9_enable_dc5] Enabling DC5
>[   51.997387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   51.997389] [drm:intel_power_well_disable] disabling always-on
>[   51.999084] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   51.999401] [drm:drm_mode_addfb2] [FB:96]
>[   52.003641] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   52.003644] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   52.003660] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   52.003661] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   52.003663] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   52.003665] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   52.003666] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   52.003667] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   52.003675] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467356000 for pipe C
>[   52.003676] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   52.003677] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.003678] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.003679] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   52.003680] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   52.003681] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   52.003681] [drm:intel_dump_pipe_config] requested mode:
>[   52.003683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   52.003684] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.003685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   52.003687] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   52.003688] [drm:intel_dump_pipe_config] port clock: 162000
>[   52.003688] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   52.003689] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   52.003690] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.003691] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.003692] [drm:intel_dump_pipe_config] ips: 0
>[   52.003693] [drm:intel_dump_pipe_config] double wide: 0
>[   52.003694] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   52.003695] [drm:intel_dump_pipe_config] planes on this crtc
>[   52.003696] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   52.003697] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   52.003698] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   52.003700] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   52.003702] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.003705] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   52.003706] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   52.003707] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.003790] [drm:intel_power_well_enable] enabling always-on
>[   52.003791] [drm:intel_power_well_enable] enabling DC off
>[   52.003854] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   52.003857] [drm:intel_power_well_enable] enabling power well 2
>[   52.003858] [drm:skl_set_power_well] Enabling power well 2
>[   52.003862] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   52.003863] [drm:intel_power_well_enable] enabling dpio-common-a
>[   52.013351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   52.013362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   52.021349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   52.021351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   52.021359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   52.021360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   52.021361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   52.021362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   52.021363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   52.021363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   52.021364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   52.021365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   52.021366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   52.021367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   52.021368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   52.021369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   52.021371] [drm:verify_single_dpll_state] PORT PLL A
>[   52.021372] [drm:verify_single_dpll_state] PORT PLL B
>[   52.021373] [drm:verify_single_dpll_state] PORT PLL C
>[   52.021378] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   52.021379] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   52.022115] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   52.022116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.026071] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   52.026073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.026297] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   52.026824] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   52.026825] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   52.029438] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   52.029479] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   52.029523] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   52.029526] [drm:intel_enable_pipe] enabling pipe C
>[   52.033678] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   52.033680] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   52.033693] [drm:verify_single_dpll_state] PORT PLL C
>[   52.037899] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   52.058501] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   52.062709] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   52.062711] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.062713] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.062723] [drm:intel_disable_pipe] disabling pipe C
>[   52.069398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   52.069403] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   52.069406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   52.077349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   52.077351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   52.077353] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   52.077360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   52.077361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   52.077362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   52.077362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   52.077363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   52.077364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   52.077365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   52.077366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   52.077367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   52.077368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   52.077369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   52.077371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   52.077372] [drm:verify_single_dpll_state] PORT PLL A
>[   52.077373] [drm:verify_single_dpll_state] PORT PLL B
>[   52.077374] [drm:verify_single_dpll_state] PORT PLL C
>[   52.077377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   52.077378] [drm:intel_power_well_disable] disabling power well 2
>[   52.077381] [drm:skl_set_power_well] Disabling power well 2
>[   52.077384] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   52.077385] [drm:intel_power_well_disable] disabling DC off
>[   52.077386] [drm:gen9_enable_dc5] Enabling DC5
>[   52.077387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   52.077389] [drm:intel_power_well_disable] disabling always-on
>[   52.078937] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   52.079255] [drm:drm_mode_addfb2] [FB:96]
>[   52.083215] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   52.083219] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   52.083225] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   52.083226] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   52.083228] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   52.083230] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   52.083231] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   52.083232] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   52.083234] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467357800 for pipe C
>[   52.083234] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   52.083235] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.083236] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.083238] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   52.083239] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   52.083239] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   52.083240] [drm:intel_dump_pipe_config] requested mode:
>[   52.083242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   52.083243] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.083244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   52.083245] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   52.083246] [drm:intel_dump_pipe_config] port clock: 162000
>[   52.083247] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   52.083256] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   52.083257] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.083257] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.083258] [drm:intel_dump_pipe_config] ips: 0
>[   52.083259] [drm:intel_dump_pipe_config] double wide: 0
>[   52.083260] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   52.083261] [drm:intel_dump_pipe_config] planes on this crtc
>[   52.083262] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   52.083263] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   52.083264] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   52.083267] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   52.083269] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.083271] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   52.083272] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   52.083273] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.083356] [drm:intel_power_well_enable] enabling always-on
>[   52.083357] [drm:intel_power_well_enable] enabling DC off
>[   52.083420] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   52.083423] [drm:intel_power_well_enable] enabling power well 2
>[   52.083424] [drm:skl_set_power_well] Enabling power well 2
>[   52.083428] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   52.083429] [drm:intel_power_well_enable] enabling dpio-common-a
>[   52.093351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   52.093362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   52.101349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   52.101351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   52.101359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   52.101360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   52.101361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   52.101362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   52.101363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   52.101364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   52.101364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   52.101365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   52.101366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   52.101367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   52.101369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   52.101370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   52.101371] [drm:verify_single_dpll_state] PORT PLL A
>[   52.101372] [drm:verify_single_dpll_state] PORT PLL B
>[   52.101373] [drm:verify_single_dpll_state] PORT PLL C
>[   52.101378] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   52.101379] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   52.102115] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   52.102116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.106069] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   52.106070] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.106295] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   52.106822] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   52.106823] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   52.109436] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   52.109476] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   52.109521] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   52.109523] [drm:intel_enable_pipe] enabling pipe C
>[   52.113675] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   52.113678] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   52.113690] [drm:verify_single_dpll_state] PORT PLL C
>[   52.117899] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   52.138498] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   52.142701] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   52.142703] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.142705] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.142725] [drm:intel_disable_pipe] disabling pipe C
>[   52.149409] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   52.149415] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   52.149418] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   52.157349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   52.157351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   52.157358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   52.157360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   52.157361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   52.157361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   52.157362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   52.157363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   52.157364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   52.157365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   52.157366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   52.157367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   52.157368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   52.157369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   52.157370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   52.157372] [drm:verify_single_dpll_state] PORT PLL A
>[   52.157373] [drm:verify_single_dpll_state] PORT PLL B
>[   52.157374] [drm:verify_single_dpll_state] PORT PLL C
>[   52.157377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   52.157378] [drm:intel_power_well_disable] disabling power well 2
>[   52.157381] [drm:skl_set_power_well] Disabling power well 2
>[   52.157383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   52.157384] [drm:intel_power_well_disable] disabling DC off
>[   52.157386] [drm:gen9_enable_dc5] Enabling DC5
>[   52.157387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   52.157389] [drm:intel_power_well_disable] disabling always-on
>[   52.158625] kms_pipe_crc_basic: exiting, ret=0
>[   52.158733] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   52.158734] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   52.158736] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   52.158737] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   52.158739] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   52.158739] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   52.158740] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   52.158741] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834800 for pipe A
>[   52.158742] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   52.158742] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.158743] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.158744] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   52.158744] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   52.158745] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   52.158745] [drm:intel_dump_pipe_config] requested mode:
>[   52.158746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   52.158747] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.158748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   52.158749] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   52.158749] [drm:intel_dump_pipe_config] port clock: 270000
>[   52.158749] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   52.158750] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   52.158750] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.158751] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.158751] [drm:intel_dump_pipe_config] ips: 0
>[   52.158752] [drm:intel_dump_pipe_config] double wide: 0
>[   52.158753] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   52.158753] [drm:intel_dump_pipe_config] planes on this crtc
>[   52.158755] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   52.158756] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   52.158756] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   52.158756] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   52.158757] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   52.158757] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   52.158758] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   52.158758] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   52.158759] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   52.158761] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   52.158761] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   52.158762] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   52.158762] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88046a837000 for pipe B
>[   52.158763] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   52.158763] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.158764] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.158765] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   52.158765] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   52.158766] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   52.158766] [drm:intel_dump_pipe_config] requested mode:
>[   52.158767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   52.158767] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.158768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   52.158769] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   52.158770] [drm:intel_dump_pipe_config] port clock: 162000
>[   52.158770] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   52.158770] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   52.158771] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.158771] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.158772] [drm:intel_dump_pipe_config] ips: 0
>[   52.158772] [drm:intel_dump_pipe_config] double wide: 0
>[   52.158773] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   52.158773] [drm:intel_dump_pipe_config] planes on this crtc
>[   52.158775] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   52.158776] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   52.158776] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   52.158776] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   52.158777] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   52.158777] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   52.158778] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   52.158778] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   52.158779] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   52.158780] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   52.158780] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   52.158781] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   52.158781] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a836000 for pipe C
>[   52.158782] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   52.158782] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.158783] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.158783] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   52.158784] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   52.158784] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   52.158785] [drm:intel_dump_pipe_config] requested mode:
>[   52.158786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   52.158786] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.158787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   52.158788] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   52.158788] [drm:intel_dump_pipe_config] port clock: 162000
>[   52.158789] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   52.158789] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   52.158790] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.158790] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.158791] [drm:intel_dump_pipe_config] ips: 0
>[   52.158791] [drm:intel_dump_pipe_config] double wide: 0
>[   52.158792] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   52.158792] [drm:intel_dump_pipe_config] planes on this crtc
>[   52.158793] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   52.158793] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   52.158794] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   52.158795] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   52.158796] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   52.158797] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   52.158798] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.158799] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   52.158800] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   52.158801] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   52.158801] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   52.158802] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   52.158802] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   52.158803] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   52.158803] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   52.158804] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.158815] [drm:intel_power_well_enable] enabling always-on
>[   52.158815] [drm:intel_power_well_enable] enabling DC off
>[   52.158878] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   52.158881] [drm:intel_power_well_enable] enabling dpio-common-a
>[   52.165365] [drm:intel_power_well_enable] enabling power well 2
>[   52.165366] [drm:skl_set_power_well] Enabling power well 2
>[   52.169349] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   52.173359] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   52.181347] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   52.181348] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   52.181348] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   52.181349] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   52.181350] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   52.181350] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   52.181351] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   52.181351] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   52.181358] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   52.181358] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   52.181359] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   52.181360] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   52.181361] [drm:verify_single_dpll_state] PORT PLL A
>[   52.181362] [drm:verify_single_dpll_state] PORT PLL B
>[   52.181362] [drm:verify_single_dpll_state] PORT PLL C
>[   52.181368] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   52.181368] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   52.181390] [drm:edp_panel_on] Turn eDP port A panel power on
>[   52.181391] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   52.313347] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   52.313348] [drm:wait_panel_status] Wait complete
>[   52.313349] [drm:wait_panel_on] Wait for panel power on
>[   52.313350] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[   52.339989] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   52.339990] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   52.339991] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   52.339995] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   52.373360] [drm:wait_panel_status] Wait complete
>[   52.373362] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   52.373363] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   52.374073] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   52.374074] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.374292] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   52.374806] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   52.374842] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   52.374888] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   52.374890] [drm:intel_enable_pipe] enabling pipe A
>[   52.374898] [drm:intel_edp_backlight_on] 
>[   52.374899] [drm:intel_panel_enable_backlight] pipe A
>[   52.374900] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   52.381346] [drm:intel_psr_enable] PSR not supported on this platform
>[   52.381347] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   52.381364] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   52.381365] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   52.382097] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   52.382097] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.385573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   52.393346] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   52.393385] [drm:skylake_pfit_enable] for crtc_state = ffff88046a837000
>[   52.393432] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   52.393433] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   52.393435] [drm:intel_enable_pipe] enabling pipe B
>[   52.393447] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   52.393448] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   52.393507] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   52.393507] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   52.394241] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   52.394241] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.397789] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   52.397789] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   52.398013] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   52.398539] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   52.398540] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   52.401346] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   52.401384] [drm:skylake_pfit_enable] for crtc_state = ffff88046a836000
>[   52.401435] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   52.401436] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   52.401437] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   52.401439] [drm:intel_enable_pipe] enabling pipe C
>[   52.405591] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   52.405593] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   52.405607] [drm:verify_single_dpll_state] PORT PLL A
>[   52.405614] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   52.405615] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   52.405625] [drm:verify_single_dpll_state] PORT PLL B
>[   52.405630] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   52.405632] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   52.405642] [drm:verify_single_dpll_state] PORT PLL C
>[   52.410621] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.410637] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   52.410696] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.410698] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   52.410711] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.410712] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   52.410723] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.410724] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   52.411226] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   52.411228] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   52.411229] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.887796] kms_pipe_crc_basic: executing
>[   52.887989] [drm:i915_gem_open] 
>[   52.888099] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.888110] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   52.888176] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.888178] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   52.888190] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.888191] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   52.888201] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   52.888203] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   52.888502] [drm:i915_gem_open] 
>[   52.888657] [drm:i915_gem_open] 
>[   52.890085] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[   52.890945] [drm:drm_mode_addfb2] [FB:96]
>[   52.894782] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   52.894785] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   52.894801] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   52.894802] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   52.894810] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.894812] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   52.894815] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   52.894815] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   52.894817] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   52.894818] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835800 for pipe C
>[   52.894819] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   52.894820] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.894821] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.894822] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   52.894823] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   52.894824] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   52.894825] [drm:intel_dump_pipe_config] requested mode:
>[   52.894827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   52.894827] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.894829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   52.894830] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   52.894831] [drm:intel_dump_pipe_config] port clock: 270000
>[   52.894832] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   52.894833] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   52.894834] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.894835] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.894835] [drm:intel_dump_pipe_config] ips: 0
>[   52.894836] [drm:intel_dump_pipe_config] double wide: 0
>[   52.894838] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   52.894838] [drm:intel_dump_pipe_config] planes on this crtc
>[   52.894839] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   52.894841] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   52.894842] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[   52.894843] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   52.894844] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   52.894846] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   52.894848] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   52.894849] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   52.894851] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   52.894852] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   52.894853] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   52.894854] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   52.894951] [drm:intel_edp_backlight_off] 
>[   53.097348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   53.097362] [drm:intel_disable_pipe] disabling pipe A
>[   53.101466] [drm:edp_panel_off] Turn eDP port A panel power off
>[   53.101468] [drm:wait_panel_off] Wait for panel power off time
>[   53.101470] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   53.114603] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   53.114605] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   53.114606] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   53.114618] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   53.125347] [drm:wait_panel_status] Wait complete
>[   53.125351] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   53.125363] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   53.125369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.125371] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   53.125376] [drm:intel_disable_pipe] disabling pipe C
>[   53.129479] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   53.129484] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   53.129486] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   53.129487] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   53.129488] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   53.129489] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   53.129490] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   53.129491] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   53.129492] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   53.129493] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   53.129493] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   53.129494] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   53.129496] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   53.129497] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   53.129499] [drm:verify_single_dpll_state] PORT PLL A
>[   53.129500] [drm:verify_single_dpll_state] PORT PLL B
>[   53.129504] [drm:verify_single_dpll_state] PORT PLL C
>[   53.129508] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.129518] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   53.129519] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   53.129541] [drm:edp_panel_on] Turn eDP port A panel power on
>[   53.129542] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   53.605360] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   53.605362] [drm:wait_panel_status] Wait complete
>[   53.605363] [drm:wait_panel_on] Wait for panel power on
>[   53.605365] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   53.632013] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   53.632015] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   53.632017] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   53.632026] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   53.665346] [drm:wait_panel_status] Wait complete
>[   53.665351] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   53.665359] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   53.666069] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   53.666070] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   53.666289] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   53.666807] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   53.666844] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835800
>[   53.666893] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.666894] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   53.666896] [drm:intel_enable_pipe] enabling pipe C
>[   53.666900] [drm:intel_edp_backlight_on] 
>[   53.666901] [drm:intel_panel_enable_backlight] pipe C
>[   53.666902] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   53.673349] [drm:intel_psr_enable] PSR not supported on this platform
>[   53.673351] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   53.675193] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   53.675198] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   53.675201] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   53.675214] [drm:verify_single_dpll_state] PORT PLL A
>[   53.679420] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   53.700012] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   53.704219] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   53.704222] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   53.704224] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   53.704248] [drm:intel_edp_backlight_off] 
>[   53.905349] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   53.905361] [drm:intel_disable_pipe] disabling pipe C
>[   53.909511] [drm:edp_panel_off] Turn eDP port A panel power off
>[   53.909513] [drm:wait_panel_off] Wait for panel power off time
>[   53.909515] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   53.922652] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   53.922654] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   53.922655] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   53.922666] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   53.933346] [drm:wait_panel_status] Wait complete
>[   53.933350] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   53.933363] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   53.933367] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.933370] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   53.933371] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   53.933372] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   53.933373] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   53.933374] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   53.933375] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   53.933376] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   53.933376] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   53.933377] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   53.933378] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   53.933380] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   53.933381] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   53.933382] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   53.933384] [drm:verify_single_dpll_state] PORT PLL A
>[   53.933385] [drm:verify_single_dpll_state] PORT PLL B
>[   53.933389] [drm:verify_single_dpll_state] PORT PLL C
>[   53.933392] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.933395] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.933405] [drm:intel_power_well_disable] disabling dpio-common-a
>[   53.933408] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   53.938655] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   53.941271] [drm:drm_mode_addfb2] [FB:96]
>[   53.944927] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   53.944931] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   53.944937] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   53.944938] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   53.944940] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   53.944942] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   53.944944] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   53.944945] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   53.944946] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   53.944948] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e9800 for pipe C
>[   53.944949] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   53.944950] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   53.944951] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   53.944952] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   53.944953] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   53.944954] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   53.944954] [drm:intel_dump_pipe_config] requested mode:
>[   53.944956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   53.944957] [drm:intel_dump_pipe_config] adjusted mode:
>[   53.944958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   53.944960] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   53.944968] [drm:intel_dump_pipe_config] port clock: 270000
>[   53.944969] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   53.944970] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   53.944971] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   53.944972] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   53.944973] [drm:intel_dump_pipe_config] ips: 0
>[   53.944973] [drm:intel_dump_pipe_config] double wide: 0
>[   53.944975] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   53.944976] [drm:intel_dump_pipe_config] planes on this crtc
>[   53.944977] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   53.944978] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   53.944978] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   53.944980] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   53.944982] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   53.944984] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   53.944985] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   53.944986] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   53.945075] [drm:intel_power_well_enable] enabling dpio-common-a
>[   53.949360] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   53.949362] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   53.949363] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   53.949364] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   53.949365] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   53.949365] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   53.949367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   53.949368] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   53.949369] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   53.949370] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   53.949372] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   53.949373] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   53.949374] [drm:verify_single_dpll_state] PORT PLL A
>[   53.949375] [drm:verify_single_dpll_state] PORT PLL B
>[   53.949379] [drm:verify_single_dpll_state] PORT PLL C
>[   53.949383] [drm:skl_wm_flush_pipe] flush pipe B (pass 1)
>[   53.953769] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   53.953780] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   53.953781] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   53.953803] [drm:edp_panel_on] Turn eDP port A panel power on
>[   53.953804] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   54.413348] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   54.413350] [drm:wait_panel_status] Wait complete
>[   54.413358] [drm:wait_panel_on] Wait for panel power on
>[   54.413359] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   54.440012] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   54.440014] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   54.440015] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   54.440025] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   54.473345] [drm:wait_panel_status] Wait complete
>[   54.473349] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   54.473357] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   54.474068] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   54.474069] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   54.474288] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   54.474804] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   54.474841] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   54.474888] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   54.474889] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   54.474892] [drm:intel_enable_pipe] enabling pipe C
>[   54.474895] [drm:intel_edp_backlight_on] 
>[   54.474896] [drm:intel_panel_enable_backlight] pipe C
>[   54.474897] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   54.481349] [drm:intel_psr_enable] PSR not supported on this platform
>[   54.481351] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   54.483182] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.483185] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.483198] [drm:verify_single_dpll_state] PORT PLL A
>[   54.487430] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   54.508004] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   54.512209] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   54.512212] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.512213] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.512239] [drm:intel_edp_backlight_off] 
>[   54.713347] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   54.713358] [drm:intel_disable_pipe] disabling pipe C
>[   54.717399] [drm:edp_panel_off] Turn eDP port A panel power off
>[   54.717401] [drm:wait_panel_off] Wait for panel power off time
>[   54.717403] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060
>[   54.730527] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   54.730529] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   54.730531] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   54.730541] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   54.749359] [drm:wait_panel_status] Wait complete
>[   54.749362] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   54.749368] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   54.749372] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   54.749374] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.749376] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.749377] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.749377] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.749378] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.749379] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.749380] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.749381] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.749382] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.749383] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.749384] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.749388] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.749389] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.749390] [drm:verify_single_dpll_state] PORT PLL A
>[   54.749391] [drm:verify_single_dpll_state] PORT PLL B
>[   54.749395] [drm:verify_single_dpll_state] PORT PLL C
>[   54.749398] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   54.749402] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   54.749409] [drm:intel_power_well_disable] disabling dpio-common-a
>[   54.749412] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.754221] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.756430] [drm:drm_mode_addfb2] [FB:96]
>[   54.760466] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.760470] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   54.760477] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   54.760478] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   54.760480] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   54.760483] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   54.760484] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   54.760485] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   54.760487] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e9800 for pipe C
>[   54.760488] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   54.760488] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   54.760489] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   54.760498] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   54.760500] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   54.760500] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   54.760501] [drm:intel_dump_pipe_config] requested mode:
>[   54.760503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   54.760503] [drm:intel_dump_pipe_config] adjusted mode:
>[   54.760505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   54.760512] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   54.760513] [drm:intel_dump_pipe_config] port clock: 162000
>[   54.760514] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   54.760515] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   54.760516] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   54.760516] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   54.760517] [drm:intel_dump_pipe_config] ips: 0
>[   54.760518] [drm:intel_dump_pipe_config] double wide: 0
>[   54.760519] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   54.760520] [drm:intel_dump_pipe_config] planes on this crtc
>[   54.760521] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   54.760522] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   54.760523] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   54.760524] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   54.760527] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   54.760528] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.760530] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   54.760531] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   54.760532] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   54.760533] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.760626] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   54.760676] [drm:intel_disable_pipe] disabling pipe B
>[   54.765398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   54.765403] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   54.765407] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.765409] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.765410] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.765410] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.765411] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.765412] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.765413] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.765414] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.765415] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.765416] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.765417] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.765418] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.765419] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.765420] [drm:verify_single_dpll_state] PORT PLL A
>[   54.765421] [drm:verify_single_dpll_state] PORT PLL B
>[   54.765422] [drm:verify_single_dpll_state] PORT PLL C
>[   54.765426] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   54.765427] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   54.766159] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   54.766160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   54.770124] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   54.777347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   54.777387] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9800
>[   54.777432] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   54.777434] [drm:intel_enable_pipe] enabling pipe C
>[   54.777438] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   54.777439] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   54.781591] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   54.781596] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   54.781599] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.781609] [drm:verify_single_dpll_state] PORT PLL B
>[   54.785819] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   54.806433] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   54.810642] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   54.810644] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.810646] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.810654] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   54.810674] [drm:intel_disable_pipe] disabling pipe C
>[   54.817398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   54.817403] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   54.817406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   54.825349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   54.825351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.825358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.825359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.825360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.825361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.825362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.825363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.825364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.825364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.825365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.825366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   54.825368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.825369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.825370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.825371] [drm:verify_single_dpll_state] PORT PLL A
>[   54.825372] [drm:verify_single_dpll_state] PORT PLL B
>[   54.825373] [drm:verify_single_dpll_state] PORT PLL C
>[   54.825376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   54.825377] [drm:intel_power_well_disable] disabling power well 2
>[   54.825380] [drm:skl_set_power_well] Disabling power well 2
>[   54.825383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.825384] [drm:intel_power_well_disable] disabling DC off
>[   54.825386] [drm:gen9_enable_dc5] Enabling DC5
>[   54.825387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   54.825388] [drm:intel_power_well_disable] disabling always-on
>[   54.827048] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.827366] [drm:drm_mode_addfb2] [FB:96]
>[   54.831971] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.831975] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   54.831982] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   54.831983] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   54.831985] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   54.831987] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   54.831988] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   54.831989] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   54.831991] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e9000 for pipe C
>[   54.831992] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   54.831993] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   54.831994] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   54.831995] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   54.831996] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   54.831997] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   54.831998] [drm:intel_dump_pipe_config] requested mode:
>[   54.831999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   54.832000] [drm:intel_dump_pipe_config] adjusted mode:
>[   54.832002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   54.832003] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   54.832004] [drm:intel_dump_pipe_config] port clock: 162000
>[   54.832004] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   54.832005] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   54.832006] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   54.832007] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   54.832008] [drm:intel_dump_pipe_config] ips: 0
>[   54.832009] [drm:intel_dump_pipe_config] double wide: 0
>[   54.832018] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   54.832019] [drm:intel_dump_pipe_config] planes on this crtc
>[   54.832020] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   54.832021] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   54.832021] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   54.832024] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   54.832026] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.832029] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   54.832030] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   54.832031] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.832122] [drm:intel_power_well_enable] enabling always-on
>[   54.832123] [drm:intel_power_well_enable] enabling DC off
>[   54.832186] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   54.832189] [drm:intel_power_well_enable] enabling power well 2
>[   54.832190] [drm:skl_set_power_well] Enabling power well 2
>[   54.832193] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   54.832194] [drm:intel_power_well_enable] enabling dpio-common-a
>[   54.841351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   54.841361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   54.849349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   54.849351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.849359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.849360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.849361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.849361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.849362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.849363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.849364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.849365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.849366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.849367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.849368] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.849369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.849371] [drm:verify_single_dpll_state] PORT PLL A
>[   54.849372] [drm:verify_single_dpll_state] PORT PLL B
>[   54.849373] [drm:verify_single_dpll_state] PORT PLL C
>[   54.849378] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   54.849379] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   54.850116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   54.850117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   54.854105] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   54.861358] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   54.861398] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9000
>[   54.861443] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   54.861446] [drm:intel_enable_pipe] enabling pipe C
>[   54.861455] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   54.861456] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   54.865735] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   54.865739] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.865753] [drm:verify_single_dpll_state] PORT PLL B
>[   54.869830] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   54.890446] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   54.894645] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   54.894648] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.894650] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.894658] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   54.894677] [drm:intel_disable_pipe] disabling pipe C
>[   54.901398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   54.901404] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   54.901407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   54.909349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   54.909351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.909359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.909360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.909361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.909362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.909362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.909364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.909364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.909365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.909366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.909367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   54.909368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.909369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.909371] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.909372] [drm:verify_single_dpll_state] PORT PLL A
>[   54.909373] [drm:verify_single_dpll_state] PORT PLL B
>[   54.909374] [drm:verify_single_dpll_state] PORT PLL C
>[   54.909377] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   54.909378] [drm:intel_power_well_disable] disabling power well 2
>[   54.909381] [drm:skl_set_power_well] Disabling power well 2
>[   54.909384] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.909385] [drm:intel_power_well_disable] disabling DC off
>[   54.909387] [drm:gen9_enable_dc5] Enabling DC5
>[   54.909388] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   54.909390] [drm:intel_power_well_disable] disabling always-on
>[   54.911112] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.911437] [drm:drm_mode_addfb2] [FB:96]
>[   54.915639] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.915643] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   54.915650] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   54.915651] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   54.915653] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   54.915655] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   54.915655] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   54.915657] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   54.915658] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467356000 for pipe C
>[   54.915659] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   54.915660] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   54.915661] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   54.915662] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   54.915663] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   54.915664] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   54.915665] [drm:intel_dump_pipe_config] requested mode:
>[   54.915667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   54.915667] [drm:intel_dump_pipe_config] adjusted mode:
>[   54.915669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   54.915670] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   54.915671] [drm:intel_dump_pipe_config] port clock: 162000
>[   54.915672] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   54.915680] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   54.915681] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   54.915682] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   54.915683] [drm:intel_dump_pipe_config] ips: 0
>[   54.915684] [drm:intel_dump_pipe_config] double wide: 0
>[   54.915685] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   54.915686] [drm:intel_dump_pipe_config] planes on this crtc
>[   54.915687] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   54.915688] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   54.915689] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   54.915691] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   54.915693] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.915696] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   54.915697] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   54.915698] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.915781] [drm:intel_power_well_enable] enabling always-on
>[   54.915782] [drm:intel_power_well_enable] enabling DC off
>[   54.915846] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   54.915849] [drm:intel_power_well_enable] enabling power well 2
>[   54.915850] [drm:skl_set_power_well] Enabling power well 2
>[   54.915853] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   54.915854] [drm:intel_power_well_enable] enabling dpio-common-a
>[   54.925351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   54.925361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   54.933349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   54.933351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.933359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.933360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.933361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.933362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.933363] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.933364] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.933364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.933365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.933366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.933367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   54.933368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.933370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.933371] [drm:verify_single_dpll_state] PORT PLL A
>[   54.933372] [drm:verify_single_dpll_state] PORT PLL B
>[   54.933373] [drm:verify_single_dpll_state] PORT PLL C
>[   54.933379] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   54.933380] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   54.934116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   54.934117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   54.937856] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   54.937858] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   54.938082] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   54.938610] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   54.938611] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   54.941439] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   54.941479] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   54.941524] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   54.941526] [drm:intel_enable_pipe] enabling pipe C
>[   54.945676] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.945679] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.945691] [drm:verify_single_dpll_state] PORT PLL C
>[   54.949900] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   54.970499] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   54.974705] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   54.974708] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.974710] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.974730] [drm:intel_disable_pipe] disabling pipe C
>[   54.981398] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   54.981404] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   54.981407] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   54.989349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   54.989350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   54.989358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   54.989359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   54.989360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   54.989361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   54.989362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   54.989363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   54.989363] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   54.989364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   54.989365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   54.989366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   54.989367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   54.989369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   54.989370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   54.989371] [drm:verify_single_dpll_state] PORT PLL A
>[   54.989372] [drm:verify_single_dpll_state] PORT PLL B
>[   54.989373] [drm:verify_single_dpll_state] PORT PLL C
>[   54.989376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   54.989377] [drm:intel_power_well_disable] disabling power well 2
>[   54.989380] [drm:skl_set_power_well] Disabling power well 2
>[   54.989383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   54.989384] [drm:intel_power_well_disable] disabling DC off
>[   54.989386] [drm:gen9_enable_dc5] Enabling DC5
>[   54.989387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   54.989388] [drm:intel_power_well_disable] disabling always-on
>[   54.990962] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.991280] [drm:drm_mode_addfb2] [FB:96]
>[   54.995554] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   54.995557] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   54.995564] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   54.995565] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   54.995567] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   54.995569] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   54.995570] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   54.995571] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   54.995573] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467357800 for pipe C
>[   54.995581] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   54.995582] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   54.995583] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   54.995584] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   54.995585] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   54.995592] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   54.995593] [drm:intel_dump_pipe_config] requested mode:
>[   54.995594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   54.995595] [drm:intel_dump_pipe_config] adjusted mode:
>[   54.995597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   54.995598] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   54.995599] [drm:intel_dump_pipe_config] port clock: 162000
>[   54.995600] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   54.995601] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   54.995602] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   54.995602] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   54.995603] [drm:intel_dump_pipe_config] ips: 0
>[   54.995604] [drm:intel_dump_pipe_config] double wide: 0
>[   54.995605] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   54.995606] [drm:intel_dump_pipe_config] planes on this crtc
>[   54.995607] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   54.995608] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   54.995609] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   54.995611] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   54.995614] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   54.995616] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   54.995617] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   54.995618] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   54.995701] [drm:intel_power_well_enable] enabling always-on
>[   54.995702] [drm:intel_power_well_enable] enabling DC off
>[   54.995766] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   54.995768] [drm:intel_power_well_enable] enabling power well 2
>[   54.995770] [drm:skl_set_power_well] Enabling power well 2
>[   54.995773] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   54.995774] [drm:intel_power_well_enable] enabling dpio-common-a
>[   55.005350] [drm:intel_power_well_disable] disabling dpio-common-a
>[   55.005361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   55.013349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   55.013351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   55.013359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   55.013360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   55.013361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   55.013362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   55.013362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   55.013363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   55.013364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   55.013365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   55.013366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   55.013367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   55.013368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   55.013369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   55.013371] [drm:verify_single_dpll_state] PORT PLL A
>[   55.013372] [drm:verify_single_dpll_state] PORT PLL B
>[   55.013373] [drm:verify_single_dpll_state] PORT PLL C
>[   55.013378] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   55.013379] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   55.014115] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   55.014116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   55.017865] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   55.017866] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   55.018091] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   55.018618] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   55.018619] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   55.021428] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   55.021468] [drm:skylake_pfit_enable] for crtc_state = ffff880467357800
>[   55.021513] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   55.021516] [drm:intel_enable_pipe] enabling pipe C
>[   55.025672] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   55.025675] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   55.025688] [drm:verify_single_dpll_state] PORT PLL C
>[   55.029897] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   55.050495] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   55.054699] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   55.054702] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   55.054704] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   55.054713] [drm:intel_disable_pipe] disabling pipe C
>[   55.061409] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   55.061415] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   55.061418] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   55.069349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   55.069350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   55.069358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   55.069359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   55.069360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   55.069361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   55.069362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   55.069363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   55.069364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   55.069364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   55.069365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   55.069366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   55.069368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   55.069369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   55.069370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   55.069371] [drm:verify_single_dpll_state] PORT PLL A
>[   55.069372] [drm:verify_single_dpll_state] PORT PLL B
>[   55.069373] [drm:verify_single_dpll_state] PORT PLL C
>[   55.069376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   55.069377] [drm:intel_power_well_disable] disabling power well 2
>[   55.069380] [drm:skl_set_power_well] Disabling power well 2
>[   55.069383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   55.069384] [drm:intel_power_well_disable] disabling DC off
>[   55.069386] [drm:gen9_enable_dc5] Enabling DC5
>[   55.069387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   55.069388] [drm:intel_power_well_disable] disabling always-on
>[   55.070638] kms_pipe_crc_basic: exiting, ret=0
>[   55.070744] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   55.070745] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   55.070747] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   55.070748] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   55.070750] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   55.070750] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   55.070751] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   55.070753] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8804694eb800 for pipe A
>[   55.070753] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   55.070753] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   55.070754] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   55.070755] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   55.070756] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   55.070756] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   55.070756] [drm:intel_dump_pipe_config] requested mode:
>[   55.070758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   55.070758] [drm:intel_dump_pipe_config] adjusted mode:
>[   55.070759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   55.070760] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   55.070760] [drm:intel_dump_pipe_config] port clock: 270000
>[   55.070761] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   55.070761] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   55.070762] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   55.070762] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   55.070763] [drm:intel_dump_pipe_config] ips: 0
>[   55.070763] [drm:intel_dump_pipe_config] double wide: 0
>[   55.070764] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   55.070764] [drm:intel_dump_pipe_config] planes on this crtc
>[   55.070766] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   55.070767] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   55.070767] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   55.070768] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   55.070768] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   55.070768] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   55.070769] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   55.070770] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   55.070770] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   55.070772] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   55.070772] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   55.070773] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   55.070774] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8804694e8800 for pipe B
>[   55.070774] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   55.070774] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   55.070775] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   55.070776] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   55.070777] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   55.070777] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   55.070777] [drm:intel_dump_pipe_config] requested mode:
>[   55.070778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   55.070779] [drm:intel_dump_pipe_config] adjusted mode:
>[   55.070780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   55.070781] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   55.070781] [drm:intel_dump_pipe_config] port clock: 162000
>[   55.070781] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   55.070782] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   55.070782] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   55.070783] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   55.070783] [drm:intel_dump_pipe_config] ips: 0
>[   55.070783] [drm:intel_dump_pipe_config] double wide: 0
>[   55.070785] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   55.070785] [drm:intel_dump_pipe_config] planes on this crtc
>[   55.070786] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   55.070787] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   55.070787] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   55.070787] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   55.070788] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   55.070788] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   55.070789] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   55.070789] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   55.070790] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   55.070791] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   55.070791] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   55.070792] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   55.070793] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8804694e9000 for pipe C
>[   55.070793] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   55.070793] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   55.070794] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   55.070795] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   55.070795] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   55.070796] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   55.070796] [drm:intel_dump_pipe_config] requested mode:
>[   55.070797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   55.070797] [drm:intel_dump_pipe_config] adjusted mode:
>[   55.070798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   55.070799] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   55.070800] [drm:intel_dump_pipe_config] port clock: 162000
>[   55.070800] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   55.070801] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   55.070801] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   55.070802] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   55.070802] [drm:intel_dump_pipe_config] ips: 0
>[   55.070802] [drm:intel_dump_pipe_config] double wide: 0
>[   55.070803] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   55.070804] [drm:intel_dump_pipe_config] planes on this crtc
>[   55.070804] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   55.070805] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   55.070805] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   55.070806] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   55.070808] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   55.070809] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   55.070809] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   55.070811] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   55.070811] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   55.070812] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   55.070813] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   55.070813] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   55.070814] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   55.070814] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   55.070815] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   55.070815] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   55.070826] [drm:intel_power_well_enable] enabling always-on
>[   55.070827] [drm:intel_power_well_enable] enabling DC off
>[   55.070890] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   55.070893] [drm:intel_power_well_enable] enabling dpio-common-a
>[   55.077365] [drm:intel_power_well_enable] enabling power well 2
>[   55.077366] [drm:skl_set_power_well] Enabling power well 2
>[   55.081349] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   55.085360] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   55.093347] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   55.093347] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   55.093348] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   55.093349] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   55.093350] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   55.093350] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   55.093351] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   55.093351] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   55.093352] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   55.093352] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   55.093359] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   55.093360] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   55.093361] [drm:verify_single_dpll_state] PORT PLL A
>[   55.093362] [drm:verify_single_dpll_state] PORT PLL B
>[   55.093363] [drm:verify_single_dpll_state] PORT PLL C
>[   55.093368] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   55.093368] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   55.093390] [drm:edp_panel_on] Turn eDP port A panel power on
>[   55.093391] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   55.225349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   55.225349] [drm:wait_panel_status] Wait complete
>[   55.225350] [drm:wait_panel_on] Wait for panel power on
>[   55.225357] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   55.252005] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   55.252006] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   55.252006] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   55.252010] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   55.281345] [drm:wait_panel_status] Wait complete
>[   55.281349] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   55.281350] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   55.282061] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   55.282061] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   55.282279] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   55.282794] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   55.282830] [drm:skylake_pfit_enable] for crtc_state = ffff8804694eb800
>[   55.282875] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   55.282877] [drm:intel_enable_pipe] enabling pipe A
>[   55.282886] [drm:intel_edp_backlight_on] 
>[   55.282886] [drm:intel_panel_enable_backlight] pipe A
>[   55.282887] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   55.289346] [drm:intel_psr_enable] PSR not supported on this platform
>[   55.289347] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   55.289365] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   55.289365] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   55.290097] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   55.290098] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   55.293572] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   55.301367] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   55.301406] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e8800
>[   55.301453] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   55.301454] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   55.301456] [drm:intel_enable_pipe] enabling pipe B
>[   55.301460] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   55.301461] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   55.301517] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   55.301517] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   55.302247] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   55.302248] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   55.305840] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   55.305841] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   55.306065] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   55.306594] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   55.306594] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   55.309357] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   55.309399] [drm:skylake_pfit_enable] for crtc_state = ffff8804694e9000
>[   55.309450] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   55.309451] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   55.309452] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   55.309454] [drm:intel_enable_pipe] enabling pipe C
>[   55.313606] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   55.313608] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   55.313624] [drm:verify_single_dpll_state] PORT PLL A
>[   55.313631] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   55.313633] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   55.313641] [drm:verify_single_dpll_state] PORT PLL B
>[   55.313647] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   55.313650] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   55.313660] [drm:verify_single_dpll_state] PORT PLL C
>[   55.318646] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.318662] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   55.318723] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.318724] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   55.318736] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.318738] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   55.318748] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.318749] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   55.319257] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   55.319259] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   55.319260] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   55.328453] kms_pipe_crc_basic: executing
>[   55.328638] [drm:i915_gem_open] 
>[   55.328747] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.328749] [drm:i915_pages_create_for_stolen] offset=0x8da000, size=16384
>[   55.328850] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.328852] [drm:i915_pages_create_for_stolen] offset=0x8de000, size=16384
>[   55.328864] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.328865] [drm:i915_pages_create_for_stolen] offset=0x8e2000, size=16384
>[   55.328876] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   55.328877] [drm:i915_pages_create_for_stolen] offset=0x8e6000, size=16384
>[   55.329181] [drm:i915_gem_open] 
>[   55.329329] [drm:i915_gem_open] 
>[   55.330744] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[   55.331600] [drm:drm_mode_addfb2] [FB:96]
>[   55.335431] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   55.335435] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   55.335442] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   55.335443] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   55.335445] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   55.335447] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   55.335449] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   55.335450] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   55.335451] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   55.335453] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a837000 for pipe C
>[   55.335454] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   55.335455] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   55.335456] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   55.335457] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   55.335458] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   55.335459] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   55.335459] [drm:intel_dump_pipe_config] requested mode:
>[   55.335469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   55.335470] [drm:intel_dump_pipe_config] adjusted mode:
>[   55.335471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   55.335472] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   55.335473] [drm:intel_dump_pipe_config] port clock: 270000
>[   55.335474] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   55.335475] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   55.335476] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   55.335477] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   55.335477] [drm:intel_dump_pipe_config] ips: 0
>[   55.335478] [drm:intel_dump_pipe_config] double wide: 0
>[   55.335480] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   55.335481] [drm:intel_dump_pipe_config] planes on this crtc
>[   55.335482] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled
>[   55.335483] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   55.335485] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[   55.335485] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   55.335486] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   55.335488] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   55.335490] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   55.335492] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   55.335493] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   55.335495] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   55.335496] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   55.335497] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   55.335593] [drm:intel_edp_backlight_off] 
>[   55.537348] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   55.537360] [drm:intel_disable_pipe] disabling pipe A
>[   55.541463] [drm:edp_panel_off] Turn eDP port A panel power off
>[   55.541464] [drm:wait_panel_off] Wait for panel power off time
>[   55.541466] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   55.554601] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   55.554603] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   55.554604] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   55.554614] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   55.565346] [drm:wait_panel_status] Wait complete
>[   55.565350] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[   55.565364] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   55.565370] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   55.565372] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   55.565377] [drm:intel_disable_pipe] disabling pipe C
>[   55.569492] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   55.569497] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   55.569500] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   55.569501] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   55.569502] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   55.569503] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   55.569503] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   55.569504] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   55.569505] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   55.569506] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   55.569507] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   55.569508] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   55.569510] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   55.569511] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   55.569512] [drm:verify_single_dpll_state] PORT PLL A
>[   55.569513] [drm:verify_single_dpll_state] PORT PLL B
>[   55.569517] [drm:verify_single_dpll_state] PORT PLL C
>[   55.569521] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   55.569531] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   55.569532] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   55.569557] [drm:edp_panel_on] Turn eDP port A panel power on
>[   55.569558] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   56.045348] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   56.045350] [drm:wait_panel_status] Wait complete
>[   56.045358] [drm:wait_panel_on] Wait for panel power on
>[   56.045359] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   56.072008] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   56.072010] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   56.072012] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   56.072022] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   56.101359] [drm:wait_panel_status] Wait complete
>[   56.101363] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   56.101364] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   56.102077] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   56.102078] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   56.102298] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   56.102815] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   56.102853] [drm:skylake_pfit_enable] for crtc_state = ffff88046a837000
>[   56.102902] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   56.102903] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   56.102906] [drm:intel_enable_pipe] enabling pipe C
>[   56.102909] [drm:intel_edp_backlight_on] 
>[   56.102910] [drm:intel_panel_enable_backlight] pipe C
>[   56.102912] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   56.109349] [drm:intel_psr_enable] PSR not supported on this platform
>[   56.109357] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   56.111199] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   56.111204] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   56.111206] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   56.111222] [drm:verify_single_dpll_state] PORT PLL A
>[   56.115452] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   56.136020] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   56.140233] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   56.140254] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   56.140256] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   56.140266] [drm:intel_edp_backlight_off] 
>[   56.341347] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   56.341358] [drm:intel_disable_pipe] disabling pipe C
>[   56.345422] [drm:edp_panel_off] Turn eDP port A panel power off
>[   56.345423] [drm:wait_panel_off] Wait for panel power off time
>[   56.345425] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   56.358556] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   56.358558] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   56.358559] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   56.358569] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   56.369346] [drm:wait_panel_status] Wait complete
>[   56.369349] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   56.369361] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   56.369368] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   56.369370] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   56.369372] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   56.369373] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   56.369374] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   56.369375] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   56.369375] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   56.369376] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   56.369377] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   56.369378] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   56.369379] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   56.369380] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   56.369382] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   56.369383] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   56.369384] [drm:verify_single_dpll_state] PORT PLL A
>[   56.369385] [drm:verify_single_dpll_state] PORT PLL B
>[   56.369389] [drm:verify_single_dpll_state] PORT PLL C
>[   56.369393] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   56.369396] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   56.369404] [drm:intel_power_well_disable] disabling dpio-common-a
>[   56.369406] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   56.375266] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   56.377662] [drm:drm_mode_addfb2] [FB:96]
>[   56.381247] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   56.381251] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[   56.381265] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   56.381266] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   56.381268] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   56.381269] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   56.381278] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   56.381279] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   56.381280] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   56.381282] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a834800 for pipe C
>[   56.381283] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   56.381284] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   56.381285] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   56.381286] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   56.381287] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   56.381288] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   56.381288] [drm:intel_dump_pipe_config] requested mode:
>[   56.381290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   56.381291] [drm:intel_dump_pipe_config] adjusted mode:
>[   56.381292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   56.381294] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   56.381294] [drm:intel_dump_pipe_config] port clock: 270000
>[   56.381295] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   56.381296] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   56.381297] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   56.381298] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   56.381299] [drm:intel_dump_pipe_config] ips: 0
>[   56.381299] [drm:intel_dump_pipe_config] double wide: 0
>[   56.381301] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   56.381302] [drm:intel_dump_pipe_config] planes on this crtc
>[   56.381303] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   56.381304] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   56.381304] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   56.381306] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   56.381308] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   56.381310] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A
>[   56.381311] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C
>[   56.381312] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   56.382340] [drm:intel_power_well_enable] enabling dpio-common-a
>[   56.389366] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   56.389367] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   56.389368] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   56.389369] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   56.389370] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   56.389371] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   56.389372] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   56.389373] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   56.389374] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   56.389375] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   56.389377] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   56.389378] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   56.389379] [drm:verify_single_dpll_state] PORT PLL A
>[   56.389380] [drm:verify_single_dpll_state] PORT PLL B
>[   56.389385] [drm:verify_single_dpll_state] PORT PLL C
>[   56.389388] [drm:skl_wm_flush_pipe] flush pipe B (pass 1)
>[   56.389728] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   56.389738] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36
>[   56.389739] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   56.389761] [drm:edp_panel_on] Turn eDP port A panel power on
>[   56.389762] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   56.849349] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   56.849360] [drm:wait_panel_status] Wait complete
>[   56.849361] [drm:wait_panel_on] Wait for panel power on
>[   56.849362] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   56.876015] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   56.876019] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   56.876020] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   56.876029] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   56.909345] [drm:wait_panel_status] Wait complete
>[   56.909350] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   56.909358] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   56.910067] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   56.910068] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   56.910286] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   56.910804] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   56.910841] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   56.910890] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   56.910892] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   56.910894] [drm:intel_enable_pipe] enabling pipe C
>[   56.910898] [drm:intel_edp_backlight_on] 
>[   56.910899] [drm:intel_panel_enable_backlight] pipe C
>[   56.910900] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   56.917349] [drm:intel_psr_enable] PSR not supported on this platform
>[   56.917357] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   56.919190] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   56.919192] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   56.919207] [drm:verify_single_dpll_state] PORT PLL A
>[   56.923418] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   56.944010] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   56.948217] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   56.948220] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   56.948239] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   56.948250] [drm:intel_edp_backlight_off] 
>[   57.149347] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   57.149358] [drm:intel_disable_pipe] disabling pipe C
>[   57.153401] [drm:edp_panel_off] Turn eDP port A panel power off
>[   57.153405] [drm:wait_panel_off] Wait for panel power off time
>[   57.153407] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060
>[   57.166555] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   57.166558] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   57.166559] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   57.166569] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   57.177346] [drm:wait_panel_status] Wait complete
>[   57.177349] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36
>[   57.177362] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[   57.177366] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   57.177368] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.177370] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.177371] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.177372] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.177373] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.177373] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.177374] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.177375] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.177376] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.177377] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.177378] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.177380] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.177381] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.177382] [drm:verify_single_dpll_state] PORT PLL A
>[   57.177384] [drm:verify_single_dpll_state] PORT PLL B
>[   57.177388] [drm:verify_single_dpll_state] PORT PLL C
>[   57.177391] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   57.177394] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   57.177402] [drm:intel_power_well_disable] disabling dpio-common-a
>[   57.177404] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.181985] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.184447] [drm:drm_mode_addfb2] [FB:96]
>[   57.188457] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.188461] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   57.188468] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   57.188470] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.188472] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   57.188474] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   57.188475] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   57.188476] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.188478] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835800 for pipe C
>[   57.188479] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   57.188480] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.188481] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.188482] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   57.188483] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.188484] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   57.188485] [drm:intel_dump_pipe_config] requested mode:
>[   57.188486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   57.188495] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.188496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   57.188498] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   57.188499] [drm:intel_dump_pipe_config] port clock: 162000
>[   57.188499] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   57.188500] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   57.188501] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.188502] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.188503] [drm:intel_dump_pipe_config] ips: 0
>[   57.188504] [drm:intel_dump_pipe_config] double wide: 0
>[   57.188505] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.188506] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.188507] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   57.188508] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   57.188509] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   57.188510] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   57.188513] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   57.188514] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.188515] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   57.188517] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   57.188518] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   57.188519] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.188616] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[   57.188667] [drm:intel_disable_pipe] disabling pipe B
>[   57.193398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31
>[   57.193403] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   57.193407] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.193409] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.193410] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.193410] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.193411] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.193412] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.193413] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.193414] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.193415] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.193416] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.193417] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.193418] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.193419] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.193420] [drm:verify_single_dpll_state] PORT PLL A
>[   57.193421] [drm:verify_single_dpll_state] PORT PLL B
>[   57.193422] [drm:verify_single_dpll_state] PORT PLL C
>[   57.193426] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   57.193427] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   57.194159] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.194160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.198124] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.205347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.205387] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835800
>[   57.205431] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   57.205434] [drm:intel_enable_pipe] enabling pipe C
>[   57.205438] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   57.205439] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   57.209589] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   57.209594] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.209597] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.209607] [drm:verify_single_dpll_state] PORT PLL B
>[   57.213817] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   57.234433] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   57.238642] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   57.238645] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.238647] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.238654] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   57.238662] [drm:intel_disable_pipe] disabling pipe C
>[   57.245411] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   57.245416] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   57.245419] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   57.253349] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.253350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.253358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.253359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.253360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.253361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.253362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.253363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.253363] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.253364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.253365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.253366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.253367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.253369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.253370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.253371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.253372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.253373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.253376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   57.253377] [drm:intel_power_well_disable] disabling power well 2
>[   57.253380] [drm:skl_set_power_well] Disabling power well 2
>[   57.253383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.253384] [drm:intel_power_well_disable] disabling DC off
>[   57.253386] [drm:gen9_enable_dc5] Enabling DC5
>[   57.253387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   57.253388] [drm:intel_power_well_disable] disabling always-on
>[   57.255031] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.255347] [drm:drm_mode_addfb2] [FB:96]
>[   57.259814] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.259817] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1]
>[   57.259824] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   57.259825] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.259827] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   57.259830] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   57.259831] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   57.259832] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.259833] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a834800 for pipe C
>[   57.259834] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   57.259835] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.259836] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.259837] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   57.259839] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.259839] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   57.259848] [drm:intel_dump_pipe_config] requested mode:
>[   57.259850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   57.259850] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.259852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   57.259853] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   57.259854] [drm:intel_dump_pipe_config] port clock: 162000
>[   57.259855] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   57.259856] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   57.259857] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.259858] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.259858] [drm:intel_dump_pipe_config] ips: 0
>[   57.259859] [drm:intel_dump_pipe_config] double wide: 0
>[   57.259861] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.259861] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.259862] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   57.259863] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   57.259864] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   57.259867] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   57.259869] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.259871] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B
>[   57.259872] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C
>[   57.259873] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.259965] [drm:intel_power_well_enable] enabling always-on
>[   57.259966] [drm:intel_power_well_enable] enabling DC off
>[   57.260029] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   57.260032] [drm:intel_power_well_enable] enabling power well 2
>[   57.260033] [drm:skl_set_power_well] Enabling power well 2
>[   57.260036] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   57.260037] [drm:intel_power_well_enable] enabling dpio-common-a
>[   57.269351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   57.269361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   57.277349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.277351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.277358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.277359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.277360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.277361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.277362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.277363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.277364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.277365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.277366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.277367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.277368] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.277369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.277371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.277372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.277373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.277378] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36
>[   57.277379] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   57.278115] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.278116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.281857] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.289347] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.289387] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   57.289431] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   57.289434] [drm:intel_enable_pipe] enabling pipe C
>[   57.289439] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   57.289441] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD
>[   57.293590] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.293593] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.293607] [drm:verify_single_dpll_state] PORT PLL B
>[   57.297816] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   57.318432] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   57.322640] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   57.322643] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.322645] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.322653] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C
>[   57.322672] [drm:intel_disable_pipe] disabling pipe C
>[   57.329398] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36
>[   57.329405] [drm:intel_disable_shared_dpll] disabling PORT PLL B
>[   57.329408] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   57.337348] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.337350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.337358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.337359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.337360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.337361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.337362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.337363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.337364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.337364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.337365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.337366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.337368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.337369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.337370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.337371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.337372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.337373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.337376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   57.337378] [drm:intel_power_well_disable] disabling power well 2
>[   57.337381] [drm:skl_set_power_well] Disabling power well 2
>[   57.337383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.337384] [drm:intel_power_well_disable] disabling DC off
>[   57.337386] [drm:gen9_enable_dc5] Enabling DC5
>[   57.337387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   57.337389] [drm:intel_power_well_disable] disabling always-on
>[   57.339123] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.339444] [drm:drm_mode_addfb2] [FB:96]
>[   57.343576] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.343580] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   57.343593] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   57.343595] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.343597] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   57.343599] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   57.343599] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   57.343601] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.343602] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a835800 for pipe C
>[   57.343603] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   57.343604] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.343605] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.343613] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   57.343614] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.343615] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   57.343616] [drm:intel_dump_pipe_config] requested mode:
>[   57.343617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   57.343618] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.343619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   57.343621] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   57.343622] [drm:intel_dump_pipe_config] port clock: 162000
>[   57.343622] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   57.343623] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   57.343624] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.343625] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.343626] [drm:intel_dump_pipe_config] ips: 0
>[   57.343627] [drm:intel_dump_pipe_config] double wide: 0
>[   57.343628] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.343629] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.343630] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   57.343631] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   57.343632] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   57.343634] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   57.343636] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.343639] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   57.343640] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   57.343641] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.343724] [drm:intel_power_well_enable] enabling always-on
>[   57.343725] [drm:intel_power_well_enable] enabling DC off
>[   57.343788] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   57.343791] [drm:intel_power_well_enable] enabling power well 2
>[   57.343793] [drm:skl_set_power_well] Enabling power well 2
>[   57.343796] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   57.343797] [drm:intel_power_well_enable] enabling dpio-common-a
>[   57.353351] [drm:intel_power_well_disable] disabling dpio-common-a
>[   57.353362] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   57.361349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.361351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.361359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.361360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.361361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.361362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.361362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.361363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.361364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.361365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.361366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.361367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.361368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.361369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.361371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.361372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.361373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.361379] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   57.361380] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   57.362116] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.362117] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.366072] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   57.366073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.366297] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.366824] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   57.366825] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   57.369438] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.369478] [drm:skylake_pfit_enable] for crtc_state = ffff88046a835800
>[   57.369523] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   57.369525] [drm:intel_enable_pipe] enabling pipe C
>[   57.373677] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.373680] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.373693] [drm:verify_single_dpll_state] PORT PLL C
>[   57.377900] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   57.398501] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   57.402709] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   57.402712] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.402714] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.402733] [drm:intel_disable_pipe] disabling pipe C
>[   57.409397] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   57.409403] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   57.409406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   57.417348] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.417350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.417357] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.417359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.417360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.417360] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.417361] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.417362] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.417363] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.417364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.417365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.417366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.417367] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.417368] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.417369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.417371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.417372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.417373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.417375] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   57.417377] [drm:intel_power_well_disable] disabling power well 2
>[   57.417380] [drm:skl_set_power_well] Disabling power well 2
>[   57.417382] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.417383] [drm:intel_power_well_disable] disabling DC off
>[   57.417385] [drm:gen9_enable_dc5] Enabling DC5
>[   57.417386] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   57.417388] [drm:intel_power_well_disable] disabling always-on
>[   57.418941] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.419259] [drm:drm_mode_addfb2] [FB:96]
>[   57.423549] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[   57.423553] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2]
>[   57.423559] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   57.423560] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.423562] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   57.423572] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   57.423573] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   57.423574] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.423576] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88046a834800 for pipe C
>[   57.423583] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   57.423584] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.423585] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.423586] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   57.423587] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.423588] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   57.423588] [drm:intel_dump_pipe_config] requested mode:
>[   57.423590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   57.423591] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.423592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   57.423594] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   57.423594] [drm:intel_dump_pipe_config] port clock: 162000
>[   57.423595] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   57.423596] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   57.423597] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.423598] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.423599] [drm:intel_dump_pipe_config] ips: 0
>[   57.423599] [drm:intel_dump_pipe_config] double wide: 0
>[   57.423601] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.423602] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.423603] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   57.423604] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   57.423605] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   57.423607] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   57.423609] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.423612] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   57.423613] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   57.423614] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.423697] [drm:intel_power_well_enable] enabling always-on
>[   57.423698] [drm:intel_power_well_enable] enabling DC off
>[   57.423762] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   57.423765] [drm:intel_power_well_enable] enabling power well 2
>[   57.423766] [drm:skl_set_power_well] Enabling power well 2
>[   57.423769] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   57.423770] [drm:intel_power_well_enable] enabling dpio-common-a
>[   57.433350] [drm:intel_power_well_disable] disabling dpio-common-a
>[   57.433361] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   57.441349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.441351] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.441359] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.441360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.441361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.441362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.441362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.441363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.441364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.441365] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.441366] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.441367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.441368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.441369] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.441371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.441372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.441373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.441378] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   57.441379] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   57.442114] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.442116] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.446072] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   57.446073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.446297] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.446825] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   57.446826] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   57.449439] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.449479] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834800
>[   57.449524] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   57.449526] [drm:intel_enable_pipe] enabling pipe C
>[   57.453678] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.453681] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.453694] [drm:verify_single_dpll_state] PORT PLL C
>[   57.457903] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf
>[   57.478501] [drm:pipe_crc_set_source] stopping CRCs for pipe C
>[   57.482699] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000
>[   57.482702] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.482704] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.482713] [drm:intel_disable_pipe] disabling pipe C
>[   57.489397] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36
>[   57.489403] [drm:intel_disable_shared_dpll] disabling PORT PLL C
>[   57.489406] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[   57.497348] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.497350] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.497358] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.497359] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.497360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.497361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.497362] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.497363] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.497364] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.497364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.497365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.497366] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.497368] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.497369] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.497370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.497371] [drm:verify_single_dpll_state] PORT PLL A
>[   57.497372] [drm:verify_single_dpll_state] PORT PLL B
>[   57.497373] [drm:verify_single_dpll_state] PORT PLL C
>[   57.497376] [drm:intel_power_well_disable] disabling dpio-common-bc
>[   57.497378] [drm:intel_power_well_disable] disabling power well 2
>[   57.497380] [drm:skl_set_power_well] Disabling power well 2
>[   57.497383] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.497384] [drm:intel_power_well_disable] disabling DC off
>[   57.497386] [drm:gen9_enable_dc5] Enabling DC5
>[   57.497387] [drm:gen9_set_dc_state] Setting DC state from 00 to 01
>[   57.497388] [drm:intel_power_well_disable] disabling always-on
>[   57.498627] kms_pipe_crc_basic: exiting, ret=0
>[   57.498737] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[   57.498738] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.498740] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   57.498741] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[   57.498743] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   57.498743] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[   57.498744] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.498745] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a834000 for pipe A
>[   57.498746] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   57.498746] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.498747] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.498748] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[   57.498748] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.498749] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   57.498749] [drm:intel_dump_pipe_config] requested mode:
>[   57.498750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   57.498751] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.498752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[   57.498753] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[   57.498753] [drm:intel_dump_pipe_config] port clock: 270000
>[   57.498753] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   57.498754] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   57.498755] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.498755] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.498755] [drm:intel_dump_pipe_config] ips: 0
>[   57.498756] [drm:intel_dump_pipe_config] double wide: 0
>[   57.498757] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.498757] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.498759] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   57.498760] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   57.498760] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   57.498760] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   57.498761] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   57.498761] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[   57.498762] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[   57.498762] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.498763] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[   57.498765] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   57.498765] [drm:intel_dp_compute_config] DP link bw required 369600 available 518400
>[   57.498766] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.498766] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff880467355800 for pipe B
>[   57.498767] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   57.498767] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.498768] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.498769] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   57.498769] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.498770] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   57.498770] [drm:intel_dump_pipe_config] requested mode:
>[   57.498771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   57.498771] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.498772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   57.498773] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   57.498774] [drm:intel_dump_pipe_config] port clock: 162000
>[   57.498774] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   57.498775] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   57.498775] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.498775] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.498776] [drm:intel_dump_pipe_config] ips: 0
>[   57.498776] [drm:intel_dump_pipe_config] double wide: 0
>[   57.498777] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.498778] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.498779] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled
>[   57.498780] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   57.498780] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[   57.498780] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1
>[   57.498781] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[   57.498781] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[   57.498782] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[   57.498782] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   57.498783] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   57.498784] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   57.498784] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[   57.498785] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   57.498785] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff880467356000 for pipe C
>[   57.498786] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   57.498786] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   57.498787] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   57.498787] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   57.498788] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   57.498789] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   57.498789] [drm:intel_dump_pipe_config] requested mode:
>[   57.498790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   57.498790] [drm:intel_dump_pipe_config] adjusted mode:
>[   57.498791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   57.498792] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   57.498792] [drm:intel_dump_pipe_config] port clock: 162000
>[   57.498793] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   57.498793] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   57.498794] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   57.498794] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   57.498795] [drm:intel_dump_pipe_config] ips: 0
>[   57.498795] [drm:intel_dump_pipe_config] double wide: 0
>[   57.498796] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   57.498796] [drm:intel_dump_pipe_config] planes on this crtc
>[   57.498797] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[   57.498797] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1
>[   57.498798] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[   57.498799] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[   57.498801] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   57.498801] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   57.498802] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   57.498804] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[   57.498804] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[   57.498805] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   57.498806] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[   57.498806] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B
>[   57.498806] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[   57.498807] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[   57.498808] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C
>[   57.498808] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[   57.498819] [drm:intel_power_well_enable] enabling always-on
>[   57.498819] [drm:intel_power_well_enable] enabling DC off
>[   57.498883] [drm:gen9_set_dc_state] Setting DC state from 01 to 00
>[   57.498885] [drm:intel_power_well_enable] enabling dpio-common-a
>[   57.505365] [drm:intel_power_well_enable] enabling power well 2
>[   57.505366] [drm:skl_set_power_well] Enabling power well 2
>[   57.509349] [drm:intel_power_well_enable] enabling dpio-common-bc
>[   57.513359] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[   57.521347] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[   57.521348] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[   57.521349] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[   57.521349] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[   57.521350] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[   57.521351] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[   57.521351] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[   57.521357] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[   57.521358] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[   57.521358] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[   57.521359] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[   57.521360] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[   57.521361] [drm:verify_single_dpll_state] PORT PLL A
>[   57.521362] [drm:verify_single_dpll_state] PORT PLL B
>[   57.521363] [drm:verify_single_dpll_state] PORT PLL C
>[   57.521368] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[   57.521368] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[   57.521390] [drm:edp_panel_on] Turn eDP port A panel power on
>[   57.521391] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   57.661359] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[   57.661360] [drm:wait_panel_status] Wait complete
>[   57.661360] [drm:wait_panel_on] Wait for panel power on
>[   57.661361] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063
>[   57.688006] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[   57.688007] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   57.688008] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 2
>[   57.688013] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   57.721345] [drm:wait_panel_status] Wait complete
>[   57.721348] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   57.721349] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[   57.722066] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.722066] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.722284] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.722799] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.722835] [drm:skylake_pfit_enable] for crtc_state = ffff88046a834000
>[   57.722880] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   57.722882] [drm:intel_enable_pipe] enabling pipe A
>[   57.722890] [drm:intel_edp_backlight_on] 
>[   57.722891] [drm:intel_panel_enable_backlight] pipe A
>[   57.722892] [drm:intel_panel_actually_set_backlight] set backlight PWM = 92160
>[   57.729346] [drm:intel_psr_enable] PSR not supported on this platform
>[   57.729346] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   57.729363] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31
>[   57.729364] [drm:intel_enable_shared_dpll] enabling PORT PLL B
>[   57.730096] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.730096] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.733573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.741346] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.741384] [drm:skylake_pfit_enable] for crtc_state = ffff880467355800
>[   57.741431] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   57.741432] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   57.741434] [drm:intel_enable_pipe] enabling pipe B
>[   57.741447] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[   57.741448] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[   57.741507] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36
>[   57.741507] [drm:intel_enable_shared_dpll] enabling PORT PLL C
>[   57.742238] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   57.742238] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.745787] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   57.745788] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   57.746013] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   57.746538] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   57.746539] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   57.749346] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   57.749384] [drm:skylake_pfit_enable] for crtc_state = ffff880467356000
>[   57.749435] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   57.749436] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   57.749437] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[   57.749439] [drm:intel_enable_pipe] enabling pipe C
>[   57.753590] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[   57.753592] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   57.753605] [drm:verify_single_dpll_state] PORT PLL A
>[   57.753612] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1]
>[   57.753614] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   57.753623] [drm:verify_single_dpll_state] PORT PLL B
>[   57.753629] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2]
>[   57.753631] [drm:verify_crtc_state] [CRTC:36:pipe C]
>[   57.753640] [drm:verify_single_dpll_state] PORT PLL C
>[   57.758615] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   57.758617] [drm:i915_pages_create_for_stolen] offset=0x8ea000, size=16384
>[   57.758689] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   57.758691] [drm:i915_pages_create_for_stolen] offset=0x8ee000, size=16384
>[   57.758704] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   57.758706] [drm:i915_pages_create_for_stolen] offset=0x8f2000, size=16384
>[   57.758715] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   57.758717] [drm:i915_pages_create_for_stolen] offset=0x8f6000, size=16384
>[   57.759219] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   57.759221] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[   57.759222] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[   60.229349] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[   60.229358] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067

Actions: View

Attachments on bug 86365: 109583 | 119905 | 124702 | 124747

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.