Attachment 126148 Details for Bug 97553 – register dump with blank tty1 screen (after blind login)

regs.bad.0.5.102.txt (text/plain), 18.88 KB, created by Max Rus on 2016-08-31 19:16:49 UTC

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Creator: Max Rus

Created: 2016-08-31 19:16:49 UTC

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patch

obsolete

>via-chrome-tool (C) 2009 by VIA Technologies, Inc.
>This is FREE SOFTWARE with ABSOLUTELY NO WARRANTY
>
>Sequencer register dump (IO Port address: 0x3c4): 
>   3c5.00 = 0x01 (Reset)
>   3c5.01 = 0x21 (Clocking Mode)
>   3c5.02 = 0x0f (Map Mask)
>   3c5.03 = 0x00 (Character Map Select)
>   3c5.04 = 0x0e (Memory Mode)
>   3c5.10 = 0x01 (Extended Register Unlock)
>   3c5.11 = 0x78 (Configuration 0)
>   3c5.12 = 0x00 (Configuration 1)
>   3c5.13 = 0x00 (Configuration 2 (DVP1 strapping))
>   3c5.14 = 0x00 (Frame Buffer Size Control)
>   3c5.15 = 0xae (Display Mode Control)
>   3c5.16 = 0x13 (Display FIFO Threshold Control)
>   3c5.17 = 0x2f (Display FIFO Control)
>   3c5.18 = 0x53 (Display Arbiter Control 0)
>   3c5.19 = 0x5f (Power Management)
>       0x01 CPU Interface Clock Control: 0x01
>       0x02 Display Interface Clock Control: 0x02
>       0x04 MC Interface Clock Control: 0x04
>       0x08 Typical Arbiter Interface Clock Control: 0x08
>       0x10 AGP Interface Clock Control: 0x10
>       0x20 P-Arbiter Interface Clock Control: 0x00
>       0x40 MIU/AGP Interface Clock Control: 0x40
>   3c5.1a = 0x7a (PCI Bus Control)
>       0x01 LUT Shadow Access: 0x00
>       0x04 PCI Burst Write Wait State Select (0: 0 Wait state, 1: 1 Wait state): 0x00
>       0x08 Extended Mode Memory Access Enable (0: Disable, 1: Enable): 0x08
>       0x40 Software Reset (0: Default value, 1: Reset): 0x40
>       0x80 Read Cache Enable (0: Disable, 1: Enable): 0x00
>   3c5.1b = 0x30 (Power Management Control 0)
>       0x01 Primary Display's LUT Off: 0x00
>       0x18 Primary Display Engine VCK Gating: 0x10
>       0x60 Secondary Display Engine LCK Gating: 0x20
>   3c5.1c = 0xe4 (Horizontal Display Fetch Count Data)
>   3c5.1d = 0x01 (Horizontal Display Fetch Count Control)
>   3c5.1e = 0x01 (Power Management Control)
>       0x01 ROC ECK: 0x01
>       0x02 Replace ECK by MCK: 0x00
>       0x08 Spread Spectrum: 0x00
>       0x30 DVP1 Power Control: 0x00
>       0xc0 VCP Power Control: 0x00
>   3c5.20 = 0x40 (Typical Arbiter Control 0)
>   3c5.21 = 0x40 (Typical Arbiter Control 1)
>   3c5.22 = 0x08 (Display Arbiter Control 1)
>   3c5.26 = 0x3d (IIC Serial Port Control 0)
>   3c5.2a = 0x00 (Power Management Control 5)
>       0x03 LVDS Channel 1 Pad Control: 0x00
>       0x0c LVDS Channel 2 Pad Control: 0x00
>       0x40 Spread Spectrum Type FIFO: 0x00
>   3c5.2b = 0x00 (LVDS Interrupt Control)
>       0x01 MSI Pending IRQ Re-trigger: 0x00
>       0x02 CRT Hot Plug Detect Enable: 0x00
>       0x04 CRT Sense IRQ status: 0x00
>       0x08 CRT Sense IRQ enable: 0x00
>       0x10 LVDS Sense IRQ status: 0x00
>       0x20 LVDS Sense IRQ enable: 0x00
>   3c5.2c = 0xd4 (General Purpose I/O Port)
>   3c5.2d = 0xff (Power Management Control 1)
>       0x03 ECK Pll Power Control: 0x03
>       0x0c LCK PLL Power Control: 0x0c
>       0x30 VCK PLL Power Control: 0x30
>       0xc0 E3_ECK_N Selection: 0xc0
>   3c5.2e = 0xfb (Power Management Control 2)
>       0x03 Video Playback Engine V3/V4 Gated Clock VCK: 0x03
>       0x0c PCI Master / DMA Gated Clock ECK/CPUCK: 0x08
>       0x30 Video Processor Gated Clock ECK: 0x30
>       0xc0 Capturer Gated Clock ECK: 0xc0
>   3c5.31 = 0x3d (IIC Serial Port Control 1)
>   3c5.35 = 0x43 (Subsystem Vendor ID Low)
>   3c5.36 = 0x10 (Subsystem Vendor ID High)
>   3c5.37 = 0xb5 (Subsystem ID Low)
>   3c5.38 = 0x81 (Subsystem ID High)
>   3c5.39 = 0x10 (BIOS Reserved Register 0)
>   3c5.3a = 0x00 (BIOS Reserved Register 1)
>   3c5.3b = 0x02 (PCI Revision ID Back Door)
>   3c5.3c = 0x01 (Miscellaneous)
>       0x01 AGP Bus Pack Door AGP3 Enable: 0x01
>       0x02 Switch 3 PLLs to Prime Output: 0x00
>       0x04 LCDCK PLL Locked Detect: 0x00
>       0x08 VCK PLL Locked Detect: 0x00
>       0x10 ECL PLL Locked Detect: 0x00
>       0x60 PLL Frequency Division Select for Testing: 0x00
>   3c5.3d = 0x00 (General Purpose I/O Port)
>   3c5.3e = 0x00 (Miscellaneous Register for AGP Mux)
>   3c5.3f = 0xff (Power Management Control 2)
>       0x03 Video Clock Control (Gated ECK): 0x03
>       0x0c 2D Clock Control (Gated ECK/CPUCK): 0x0c
>       0x30 3D Clock Control (Gated ECK): 0x30
>       0xc0 CR Clock Control (Gated ECK): 0xc0
>   3c5.40 = 0x08 (PLL Control)
>       0x01 Reset ECK PLL: 0x00
>       0x02 Reset VCK PLL: 0x00
>       0x04 Reset LCDCK PLL: 0x00
>       0x08 LVDS Interrupt Method: 0x08
>       0x30 Free Run ECK Frequency within Idle Mode: 0x00
>       0x80 CRT Sense Enable: 0x00
>   3c5.41 = 0x40 (Typical Arbiter Control 1)
>   3c5.42 = 0x30 (Typical Arbiter Control 2)
>   3c5.43 = 0x00 (Graphics Bonding Option)
>       0x01 Notebook Used Flag: 0x00
>       0x04 Typical Channel 1 Arbiter Read Back Data Overwrite Flag: 0x00
>       0x08 Typical Channel 0 Arbiter Read Back Data Overwrite Flag: 0x00
>       0x10 IGA1 Display FIFO Underflow Flag: 0x00
>       0x20 IGA2 Display FIFO Underflow Flag: 0x00
>       0x40 Windows Media Video Enable Flag: 0x00
>       0x80 Advance Video Enable Flag: 0x00
>   3c5.44 = 0x77 (VCK Clock Synthesizer Value 0)
>   3c5.45 = 0x04 (VCK Clock Synthesizer Value 1)
>   3c5.46 = 0x03 (VCK Clock Synthesizer Value 2)
>   3c5.47 = 0x8a (ECK Clock Synthesizer Value 0)
>   3c5.48 = 0x04 (ECK Clock Synthesizer Value 1)
>   3c5.49 = 0x03 (ECK Clock Synthesizer Value 2)
>   3c5.4a = 0x52 (LDCK Clock Synthesizer Value 0)
>   3c5.4b = 0x90 (LDCK Clock Synthesizer Value 1)
>   3c5.4c = 0x01 (LDCK Clock Synthesizer Value 2)
>   3c5.4d = 0x00 (Preemptive Arbiter Control)
>   3c5.4e = 0x00 (Software Reset Control)
>       0x01 HQV/Video/Capture Engine Reset: 0x00
>       0x02 HQV/Video/Capture Register Reset: 0x00
>       0x04 2D Engine Reset: 0x00
>       0x08 2D Register Reset: 0x00
>       0x10 3D Engine Reset: 0x00
>       0x20 3D Register Reset: 0x00
>       0x40 CR Engine Reset: 0x00
>       0x80 CR Register Reset: 0x00
>   3c5.4f = 0x1f (CR Gating Clock Control)
>   3c5.50 = 0x1f (AGP Control)
>   3c5.51 = 0x00 (Display FIFO Control 1)
>   3c5.52 = 0x00 (Integrated TV Shadow Register Control)
>   3c5.53 = 0x00 (DAC Sense Control 1)
>   3c5.54 = 0x00 (DAC Sense Control 2)
>   3c5.55 = 0x00 (DAC Sense Control 3)
>   3c5.56 = 0x00 (DAC Sense Control 4)
>   3c5.57 = 0x00 (Display FIFO Control 2)
>   3c5.58 = 0x00 (GFX Power Control 1)
>   3c5.59 = 0x00 (GFX Power Control 2)
>       0x01 GFX-NM AGP Dynamic Clock Enable: 0x00
>       0x02 GFX-NM GMINT Channel 0 Dynamic Clock Enable: 0x00
>       0x04 GFX-NM GMINT Channel 1 Dynamic Clock Enable: 0x00
>       0x08 GFX-NM PCIC Dynamic Clock Enable: 0x00
>       0x10 GFX-NM IGA Dynamic Clock Enable: 0x00
>       0x20 IGA Low Threshold Enable: 0x00
>       0x80 IGA1 Enable: 0x00
>   3c5.5a = 0x00 (PCI Bus Control 2)
>   3c5.5b = 0x00 (Device Used Status 0)
>       0x01 LVDS1 Used IGA2 Source: 0x00
>       0x02 LBDS1 Used IGA1 Source: 0x00
>       0x04 LVDS0 Used IGA2 Source: 0x00
>       0x08 LVDS1 Used IGA1 Source: 0x00
>       0x10 DAC0 Used IGA2 Source: 0x00
>       0x20 DAC0 Used IGA1 Source: 0x00
>       0x40 DAC0 User is TV: 0x00
>       0x80 DCVI Source Selection is TV: 0x00
>   3c5.5c = 0x00 (Device Used Status 1)
>       0x01 DVP1 Used IGA2 Source: 0x00
>       0x02 DVP1 Used IGA1 Source: 0x00
>       0x10 DAC1 Used IGA2 Source: 0x00
>       0x20 DAC1 Used IGA1 Source: 0x00
>       0x40 DAC1 User is TV: 0x00
>   3c5.5d = 0x00 (Timer Control)
>   3c5.5e = 0x00 (DAC Control 2)
>   3c5.60 = 0x00 (I2C Mode Control)
>   3c5.61 = 0x00 (I2C Host Address)
>   3c5.62 = 0x00 (I2C Host Data)
>   3c5.63 = 0x00 (I2C Host Control)
>   3c5.64 = 0x00 (I2C Status)
>   3c5.65 = 0x00 (Power Management Control 6)
>   3c5.66 = 0x00 (GTI Control 0)
>   3c5.67 = 0x00 (GTI Control 1)
>   3c5.68 = 0x00 (GTI Control 2)
>   3c5.69 = 0x00 (GTI Control 3)
>   3c5.6a = 0x00 (GTI Control 4)
>   3c5.6b = 0x00 (GTI Control 5)
>   3c5.6c = 0x00 (GTI Control 6)
>   3c5.6d = 0x00 (GTI Control 7)
>   3c5.6e = 0x00 (GTI Control 8)
>   3c5.6f = 0x00 (GTI Control 9)
>   3c5.70 = 0x00 (GARB Control 0)
>   3c5.71 = 0x00 (Typical Arbiter Control 2)
>   3c5.72 = 0x00 (Typical Arbiter Control 3)
>   3c5.73 = 0x00 (Typical Arbiter Control 4)
>   3c5.74 = 0x00 (Typical Arbiter Control 5)
>   3c5.75 = 0x00 (Typical Arbiter Control 6)
>   3c5.76 = 0x00 (Backlight Control 1)
>       0x01 Backlight Control Enable: 0x00
>   3c5.77 = 0x00 (Backlight Control 2)
>   3c5.78 = 0x00 (Backlight Control 3)
>
>Graphic Controller register dump (IO Port address: 0x3ce): 
>   3cf.00 = 0x00 (Set / Reset)
>   3cf.01 = 0x00 (Enable Set / Reset)
>   3cf.02 = 0x00 (Color Compare)
>   3cf.03 = 0x00 (Data Rotate)
>   3cf.04 = 0x00 (Read Map Select)
>   3cf.05 = 0x00 (Mode)
>   3cf.06 = 0x05 (Miscellaneous)
>   3cf.07 = 0x0f (Color Don't Care)
>   3cf.08 = 0xff (Bit Mask)
>   3cf.20 = 0x00 (Offset Register Control)
>   3cf.21 = 0x00 (Offset Register A)
>   3cf.22 = 0x00 (Offset Register B)
>
>CRT controller register dump (IO Port address: 0x3d4): 
>   3d5.00 = 0x3d (Horizontal Total)
>   3d5.01 = 0xef (Horizontal Display End)
>   3d5.02 = 0xef (Start Horizontal Blank)
>   3d5.03 = 0x81 (End Horizontal Blank)
>   3d5.04 = 0x00 (Start Horizontal Retrace)
>   3d5.05 = 0x19 (End Horizontal Retrace)
>   3d5.06 = 0x5e (Vertical Total)
>   3d5.07 = 0x00 (Overflow)
>   3d5.08 = 0x00 (Preset Row Scan)
>   3d5.09 = 0x00 (Max Scan Line)
>   3d5.0a = 0x1e (Cursor Start)
>   3d5.0b = 0x00 (Cursor End)
>   3d5.0c = 0x00 (Start Address High)
>   3d5.0d = 0x00 (Start Address Low)
>   3d5.0e = 0x00 (Cursor Location High)
>   3d5.0f = 0x00 (Cursor Location Low)
>   3d5.10 = 0x3a (Vertical Retrace Start)
>   3d5.11 = 0x0f (Vertical Retrace End)
>   3d5.12 = 0x37 (Vertical Display End)
>   3d5.13 = 0xc0 (Offset)
>   3d5.14 = 0x00 (Underline Location)
>   3d5.15 = 0x37 (Start Vertical Blank)
>   3d5.16 = 0x5f (End Vertical Blank)
>   3d5.17 = 0xe3 (CRTC Mode Control)
>   3d5.18 = 0xff (Line Compare)
>   3d5.30 = 0x08 (Display Fetch Blocking Control)
>   3d5.31 = 0x00 (Half Line Position)
>   3d5.32 = 0x11 (Mode Control)
>       0x01 Real-Time Flipping: 0x01
>       0x02 Digital Video Port (DVP) Grammar Correction: 0x00
>       0x04 Display End Blanking Enable: 0x00
>       0x08 CRT SYNC Driving Selection (0: Low, 1: High): 0x00
>       0xe0 HSYNC Delay Number by VCLK: 0x00
>   3d5.33 = 0x36 (Hsync Adjuster)
>   3d5.34 = 0x00 (Starting Address Overflow, Bits [23:16])
>   3d5.35 = 0x7f (Extended Overflow)
>   3d5.36 = 0x09 (Power Management Control 3)
>   3d5.37 = 0x00 (DAC Control)
>   3d5.38 = 0xfe (Signature Data B0)
>   3d5.39 = 0xff (Signature Data B1)
>   3d5.3a = 0xff (Signature Data B2)
>   3d5.3b = 0x01 (Scratch Pad 2)
>   3d5.3c = 0x08 (Scratch Pad 3)
>   3d5.3d = 0x74 (Scratch Pad 4)
>   3d5.3e = 0x00 (Scratch Pad 5)
>   3d5.3f = 0x02 (Scratch Pad 6)
>   3d5.40 = 0x00 (Test Mode Control 0)
>   3d5.43 = 0x90 (IGA1 Display Control)
>   3d5.45 = 0x00 (Power Now Indicator Control 3)
>   3d5.46 = 0x00 (Test Mode Control 1)
>   3d5.47 = 0x00 (Test Mode Control 2)
>   3d5.48 = 0x00 (Starting Address Overflow)
>   3d5.50 = 0xb8 (Second CRTC Horizontal Total Period)
>   3d5.51 = 0xea (Second CRTC Horizontal Active Data Period)
>   3d5.52 = 0x20 (Second CRTC Horizontal Blanking Start)
>   3d5.53 = 0x01 (Second CRTC Horizontal Blanking End)
>   3d5.54 = 0x0c (Second CRTC Horizontal Blanking Overflow)
>   3d5.55 = 0x00 (Second CRTC Horizontal Period Overflow)
>   3d5.56 = 0x41 (Second CRTC Horizontal Retrace Start)
>   3d5.57 = 0x4a (Second CRTC Horizontal Retrace End)
>   3d5.58 = 0x00 (Second CRTC Vertical Total Period)
>   3d5.59 = 0x50 (Second CRTC Vertical Active Data Period)
>   3d5.5a = 0x58 (Second CRTC Vertical Blanking Start)
>   3d5.5b = 0x40 (Second CRTC Vertical Blanking End)
>   3d5.5c = 0x80 (Second CRTC Vertical Blanking Overflow)
>   3d5.5d = 0x85 (Second CRTC Vertical Period Overflow)
>   3d5.5e = 0x00 (Second CRTC Vertical Retrace Start)
>   3d5.5f = 0x18 (Second CRTC Vertical Retrace End)
>   3d5.60 = 0x00 (Second CRTC Vertical Status 1)
>   3d5.61 = 0x20 (Second CRTC Vertical Status 2)
>   3d5.62 = 0x00 (Second Display Starting Address Low)
>   3d5.63 = 0x00 (Second Display Starting Address Middle)
>   3d5.64 = 0x00 (Second Display Starting Address High)
>   3d5.65 = 0x54 (Second Display Horizontal Quadword Count)
>   3d5.66 = 0x08 (Second Display Horizontal Offset)
>   3d5.67 = 0x00 (Second Display Color Depth and Horizontal Overflow)
>   3d5.68 = 0x00 (Second Display Queue Depth and Read Threshold)
>   3d5.69 = 0x00 (Second Display Interrupt Enable and Status)
>   3d5.6a = 0x40 (Second Display Channel and LCD Enable)
>   3d5.6b = 0x04 (Channel 1 and 2 Clock Mode Selection)
>   3d5.6c = 0x00 (TV Clock Control)
>   3d5.6d = 0x48 (Horizontal Total Shadow)
>   3d5.6e = 0x40 (End Horizontal Blanking Shadow)
>   3d5.6f = 0x81 (Vertical Total Shadow)
>   3d5.70 = 0x00 (Vertical Display Enable End Shadow)
>   3d5.71 = 0x51 (Vertical Display Overflow Shadow)
>   3d5.72 = 0x21 (Start Vertical Blank Shadow)
>   3d5.73 = 0x06 (End Vertical Blank Shadow)
>   3d5.74 = 0x00 (Vertical Blank Overflow Shadow)
>   3d5.75 = 0x04 (Vertical Retrace Start Shadow)
>   3d5.76 = 0x14 (Vertical Retrace End Shadow)
>   3d5.77 = 0x00 (LCD Horizontal Scaling Factor)
>   3d5.78 = 0x00 (LCD Vertical Scaling Factor)
>   3d5.79 = 0x00 (LCD Scaling Control)
>   3d5.7a = 0x00 (LCD Scaling Parameter 1)
>   3d5.7b = 0x02 (LCD Scaling Parameter 2)
>   3d5.7c = 0x01 (LCD Scaling Parameter 3)
>   3d5.7d = 0x18 (LCD Scaling Parameter 4)
>   3d5.7e = 0x1a (LCD Scaling Parameter 5)
>   3d5.7f = 0x00 (LCD Scaling Parameter 6)
>   3d5.80 = 0x12 (LCD Scaling Parameter 7)
>   3d5.81 = 0x19 (LCD Scaling Parameter 8)
>   3d5.82 = 0x00 (LCD Scaling Parameter 9)
>   3d5.83 = 0x10 (LCD Scaling Parameter 10)
>   3d5.84 = 0x02 (LCD Scaling Parameter 11)
>   3d5.85 = 0x04 (LCD Scaling Parameter 12)
>   3d5.86 = 0x10 (LCD Scaling Parameter 13)
>   3d5.87 = 0x06 (LCD Scaling Parameter 14)
>   3d5.88 = 0x20 (LCD Panel Type)
>   3d5.8a = 0x00 (LCD Timing Control 1)
>   3d5.8b = 0xca (LCD Power Sequence Control 0)
>   3d5.8c = 0xca (LCD Power Sequence Control 1)
>   3d5.8d = 0xca (LCD Power Sequence Control 2)
>   3d5.8e = 0xca (LCD Power Sequence Control 3)
>   3d5.8f = 0x11 (LCD Power Sequence Control 4)
>   3d5.90 = 0x11 (LCD Power Sequence Control 5)
>   3d5.91 = 0x00 (Software Control Power Sequence)
>   3d5.92 = 0x00 (Read Threshold 2)
>   3d5.94 = 0x00 (Expire Number and Display Queue Extend)
>   3d5.95 = 0x00 (Extend Threshold Bit)
>   3d5.97 = 0x00 (LVDS Channel 2 Function Select 0)
>   3d5.98 = 0x00 (LVDS Channel 2 Function Select 1)
>   3d5.99 = 0x00 (LVDS Channel 1 Function Select 0)
>   3d5.9a = 0x00 (LVDS Channel 1 Function Select 1)
>   3d5.9b = 0x00 (Digital Video Port 1 Function Select 0)
>   3d5.9c = 0x00 (Digital Video Port 1 Function Select 1)
>   3d5.9d = 0x00 (Power Now Control 2)
>   3d5.9e = 0x00 (Power Now Control 3)
>   3d5.9f = 0x00 (Power Now Control 4)
>   3d5.a0 = 0x00 (Horizontal Scaling Initial Value)
>   3d5.a1 = 0x00 (Vertical Scaling Initial Value)
>   3d5.a2 = 0x00 (Horizontal and Vertical Scaling Enable)
>   3d5.a3 = 0x00 (Second Display Starting Address Extended)
>   3d5.a5 = 0x00 (Second LCD Vertical Scaling Factor)
>   3d5.a6 = 0x00 (Second LCD Vertical Scaling Factor)
>   3d5.a7 = 0x00 (Expected IGA1 Vertical Display End)
>   3d5.a8 = 0x00 (Expected IGA1 Vertical Display End)
>   3d5.a9 = 0x00 (Hardware Gamma Control)
>   3d5.aa = 0x00 (FIFO Depth + Threshold Overflow)
>   3d5.ab = 0x00 (IGA2 Interlace Half Line)
>   3d5.ac = 0x00 (IGA2 Interlace Half Line)
>   3d5.af = 0x00 (P-Arbiter Write Expired Number)
>   3d5.b0 = 0x00 (IGA2 Pack Circuit Request Threshold)
>   3d5.b1 = 0x00 (IGA2 Pack Circuit Request High Threshold)
>   3d5.b2 = 0x00 (IGA2 Pack Circuit Request Expire Threshold)
>   3d5.b3 = 0x00 (IGA2 Pack Circuit Control)
>   3d5.b4 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>   3d5.b5 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>   3d5.b6 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>   3d5.b7 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
>   3d5.b8 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
>   3d5.b9 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
>   3d5.ba = 0x00 (V Counter Set Pointer)
>   3d5.bb = 0x00 (V Counter Set Pointer)
>   3d5.bc = 0x00 (V Counter Reset Value)
>   3d5.bd = 0x00 (V Counter Reset Value)
>   3d5.be = 0x00 (Frame Buffer Limit Value)
>   3d5.bf = 0x00 (Frame Buffer Limit Value)
>   3d5.c0 = 0x00 (Expected IGA1 Vertical Display End 1)
>   3d5.c1 = 0x00 (Expected IGA1 Vertical Display End 1)
>   3d5.c2 = 0x00 (Third LCD Vertical Scaling Factor)
>   3d5.c3 = 0x00 (Third LCD Vertical Scaling Factor)
>   3d5.c4 = 0x00 (Expected IGA1 Vertical Display End 2)
>   3d5.c5 = 0x00 (Expected IGA1 Vertical Display End 2)
>   3d5.c7 = 0x00 (Fourth LCD Vertical Scaling Factor)
>   3d5.c8 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>   3d5.c9 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>   3d5.ca = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>   3d5.cb = 0x00 (IGA2 Pack Circuit Target Base Address 1)
>   3d5.d0 = 0x00 (LVDS PLL1 Control)
>   3d5.d1 = 0x00 (LVDS PLL2 Control)
>   3d5.d2 = 0x00 (LVDS Control)
>   3d5.d3 = 0x00 (LVDS Second Power Sequence Control 0)
>   3d5.d4 = 0x00 (LVDS Second Power Sequence Control 1)
>   3d5.d5 = 0x00 (LVDS Texting Mode Control)
>   3d5.d6 = 0x00 (DCVI Control Register 0)
>   3d5.d7 = 0x00 (DCVI Control Register 1)
>   3d5.d9 = 0x00 (Scaling Down Source Data Offset Control)
>   3d5.da = 0x00 (Scaling Down Source Data Offset Control)
>   3d5.db = 0x00 (Scaling Down Source Data Offset Control)
>   3d5.dc = 0x00 (Scaling Down Vertical Scale Control)
>   3d5.dd = 0x00 (Scaling Down Vertical Scale Control)
>   3d5.de = 0x00 (Scaling Down Vertical Scale Control)
>   3d5.df = 0x00 (Scaling Down Vertical Scale Control)
>   3d5.e0 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>   3d5.e1 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>   3d5.e2 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>   3d5.e3 = 0x00 (Scaling Down Destination FB Starting Addr 0)
>   3d5.e4 = 0x00 (Scaling Down SW Source FB Stride)
>   3d5.e5 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>   3d5.e6 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>   3d5.e7 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>   3d5.e8 = 0x00 (Scaling Down Destination FB Starting Addr 1)
>   3d5.e9 = 0x00 (Scaling Down Destination FB Starting Addr 2)
>   3d5.ea = 0x00 (Scaling Down Destination FB Starting Addr 2)
>   3d5.eb = 0x00 (Scaling Down Destination FB Starting Addr 2)
>   3d5.ec = 0x00 (IGA1 Down Scaling Destination Control)
>   3d5.f0 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
>   3d5.f1 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
>   3d5.f2 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
>   3d5.f3 = 0x00 (Snapshot Mode Control)
>   3d5.f4 = 0x00 (Snapshot Mode Control)
>   3d5.f5 = 0x00 (Snapshot Mode Control)
>   3d5.f6 = 0x00 (Snapshot Mode Control)
>
>SL in System memory: 0x0, RTSF in SL: 0x0
>Primary Display:
>    H total=2576, active=1920, blank (1920-528), sync(2048-200)
>    V total=1120, active=1080, blank (1080-96), sync(1082-15)
>base_addr=0x00000000, bpp=32
>
>Secondary Display:
>    H total=185, active=235, blank (1057-4354), sync(3137-74)
>    V total=1281, active=81, blank (89-65), sync(0-24)
>base_addr=0x00000000, bpp=8
>
>Panel Scaling disabled
>
>LVDS Seq Mode: LVDS1 + LVDS2
>LVDS CRT Mode: LVDS1 + LVDS2
>LVDS Channel 1 Format SPWG, Power Up
>LVDS Channel 2 Format SPWG, Power Up
>
>VCK PLL: dm=119, dtx=2, dr=0, dn=1 VCK Fvco=577492 kHz, Fout=0 kHz
>ECK PLL: dm=138, dtx=2, dr=0, dn=1 ECK Fvco=668173 kHz, Fout=0 kHz
>LDCK PLL: dm=594, dtx=2, dr=2, dn=0 LDCK Fvco=4266764 kHz, Fout=1066691 kHz

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Attachments on bug 97553: 126147 | 126148 | 126149

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