Attachment 126154 Details for Bug 97557 – dmesg

dmesg

dmesg (text/plain), 6.48 KB, created by Luis Botello on 2016-09-01 02:04:08 UTC

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Creator: Luis Botello

Created: 2016-09-01 02:04:08 UTC

Size: 6.48 KB

patch

obsolete

>[ 6554.979902] gem_sync: executing
>[ 6554.980036] [drm:i915_gem_open] 
>[ 6554.980552] [drm:i915_gem_open] 
>[ 6554.980867] gem_sync: starting subtest forked-render
>[ 6564.994593] gem_sync: exiting, ret=0
>[ 6564.994699] [drm:connected_sink_compute_bpp] [CONNECTOR:50:DP-2] checking for sink bpp constrains
>[ 6564.994700] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[ 6564.994702] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 6564.994704] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 6564.994704] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[ 6564.994706] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
>[ 6564.994706] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 6564.994708] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8807f775d800 for pipe A
>[ 6564.994708] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 6564.994709] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 6564.994710] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[ 6564.994711] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 6564.994711] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 6564.994712] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 6564.994712] [drm:intel_dump_pipe_config] requested mode:
>[ 6564.994714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 6564.994714] [drm:intel_dump_pipe_config] adjusted mode:
>[ 6564.994715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 6564.994716] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 6564.994717] [drm:intel_dump_pipe_config] port clock: 162000
>[ 6564.994717] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 6564.994718] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[ 6564.994719] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 6564.994719] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 6564.994720] [drm:intel_dump_pipe_config] ips: 0
>[ 6564.994720] [drm:intel_dump_pipe_config] double wide: 0
>[ 6564.994721] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x10c09, fp1: 0x10c09
>[ 6564.994722] [drm:intel_dump_pipe_config] planes on this crtc
>[ 6564.994723] [drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[ 6564.994724] [drm:intel_dump_pipe_config] 	FB:67, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 6564.994725] [drm:intel_dump_pipe_config] 	scaler:0 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 6564.994725] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[ 6564.994726] [drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[ 6564.994732] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated PCH DPLL A
>[ 6564.994733] [drm:intel_reference_shared_dpll] using PCH DPLL A for pipe A
>[ 6564.994742] [drm:intel_power_well_enable] enabling always-on
>[ 6564.994746] [drm:verify_encoder_state] [ENCODER:37:CRT]
>[ 6564.994748] [drm:verify_encoder_state] [ENCODER:38:HDMI B]
>[ 6564.994750] [drm:verify_encoder_state] [ENCODER:43:DP B]
>[ 6564.994752] [drm:verify_encoder_state] [ENCODER:45:HDMI C]
>[ 6564.994753] [drm:verify_encoder_state] [ENCODER:47:HDMI D]
>[ 6564.994754] [drm:verify_encoder_state] [ENCODER:49:DP C]
>[ 6564.994755] [drm:verify_encoder_state] [ENCODER:51:DP D]
>[ 6564.994757] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1]
>[ 6564.994759] [drm:intel_connector_verify_state] [CONNECTOR:39:HDMI-A-1]
>[ 6564.994760] [drm:intel_connector_verify_state] [CONNECTOR:44:DP-1]
>[ 6564.994762] [drm:intel_connector_verify_state] [CONNECTOR:46:HDMI-A-2]
>[ 6564.994763] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-3]
>[ 6564.994765] [drm:intel_connector_verify_state] [CONNECTOR:52:DP-3]
>[ 6564.994766] [drm:verify_single_dpll_state] PCH DPLL A
>[ 6564.994770] [drm:verify_single_dpll_state] PCH DPLL B
>[ 6564.994778] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[ 6564.995313] [drm:intel_enable_pipe] enabling pipe A
>[ 6564.995468] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0
>[ 6564.995475] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100
>[ 6564.995476] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0.
>[ 6564.995483] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600
>[ 6564.995484] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0.
>[ 6564.995485] [drm:ivb_manual_fdi_link_train] FDI train done.
>[ 6564.995488] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 1, on? 0) for crtc 26
>[ 6564.995488] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[ 6564.996854] [drm:_intel_dp_set_link_train] Using DP training pattern TPS1
>[ 6564.999440] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[ 6564.999441] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[ 6564.999442] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[ 6564.999444] [drm:_intel_dp_set_link_train] Using DP training pattern TPS1
>[ 6565.003215] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[ 6565.003217] [drm:_intel_dp_set_link_train] Using DP training pattern TPS2
>[ 6565.005188] [drm:intel_dp_set_signal_levels] Using signal levels 00400000
>[ 6565.005189] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[ 6565.005190] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[ 6565.007162] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[ 6565.040593] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2]
>[ 6565.040598] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[ 6565.040615] [drm:verify_single_dpll_state] PCH DPLL A
>[ 6571.668467] gem_sync: executing
>[ 6571.668597] [drm:i915_gem_open] 
>[ 6571.669091] [drm:i915_gem_open] 
>[ 6571.669350] gem_sync: starting subtest forked-render
>[ 6581.725315] gem_sync: exiting, ret=0
>[ 6586.614761] gem_sync: executing
>[ 6586.614875] [drm:i915_gem_open] 
>[ 6586.615359] [drm:i915_gem_open] 
>[ 6586.615617] gem_sync: starting subtest forked-render
>[ 6596.631750] gem_sync: exiting, ret=99

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Attachments on bug 97557: 126154 | 126155

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