Attachment 126253 Details for Bug 97363 – drm-debug-opregion_panel_type_stuff

drm-debug-opregion_panel_type_stuff

drm-debug-opregion_panel_type_stuff (text/plain), 701.26 KB, created by Robin Müller on 2016-09-06 19:22:29 UTC

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Creator: Robin Müller

Created: 2016-09-06 19:22:29 UTC

Size: 701.26 KB

patch

obsolete

>[drm:drm_core_init] Initialized drm 1.1.0 20060810
>[drm:intel_detect_pch] Found PantherPoint PCH
>[drm:get_allowed_dc_mask] Allowed DC state mask 00
>[drm:intel_device_info_dump] i915 device info: gen=7, pciid=0x0166 rev=0x09 flags=is_mobile,need_gfx_hws,is_ivybridge,has_fbc,has_hotplug,has_llc,
>[drm:intel_device_info_runtime_init] slice mask: 0000
>[drm:intel_device_info_runtime_init] slice total: 0
>[drm:intel_device_info_runtime_init] subslice total: 0
>[drm:intel_device_info_runtime_init] subslice mask 0000
>[drm:intel_device_info_runtime_init] subslice per slice: 0
>[drm:intel_device_info_runtime_init] EU total: 0
>[drm:intel_device_info_runtime_init] EU per subslice: 0
>[drm:intel_device_info_runtime_init] has slice power gating: n
>[drm:intel_device_info_runtime_init] has subslice power gating: n
>[drm:intel_device_info_runtime_init] has EU power gating: n
>[drm:intel_sanitize_options] ppgtt mode: 1
>[drm:intel_sanitize_options] use GPU sempahores? yes
>[drm:i915_ggtt_probe_hw] Memory usable by graphics device = 2048M
>[drm:i915_ggtt_probe_hw] GMADR size = 256M
>[drm:i915_ggtt_probe_hw] GTT stolen size = 64M
>fb: switching to inteldrmfb from VESA VGA
>[drm:i915_kick_out_vgacon] Replacing VGA console driver
>[drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K
>[drm:intel_opregion_setup] graphic opregion physical addr: 0xdaf75018
>[drm:intel_opregion_setup] Public ACPI methods supported
>[drm:intel_opregion_setup] SWSCI supported
>[drm:swsci_setup] SWSCI GBDA callbacks 00000cf3, SBCB callbacks 00000241
>[drm:intel_opregion_setup] ASLE supported
>[drm:intel_opregion_setup] ASLE extension supported
>[drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[drm:drm_vblank_init] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[drm:drm_vblank_init] Driver supports precise vblank timestamp query.
>[drm:init_vbt_defaults] Set default to SSC at 120000 kHz
>[drm:intel_bios_init] VBT signature "$VBT SNB/IVB-MOBILE ", BDB version 165
>[drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 1 lvds_use_ssc 1 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[drm:parse_general_definitions] crt_ddc_bus_pin: 2
>[drm:swsci] GBDA get panel details 0x00000020 0x00520100
>[drm:parse_lfp_panel_data] Panel type: 0 (OpRegion)
>[drm:parse_lfp_panel_data] DRRS supported mode is static
>[drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:parse_lfp_panel_data] VBT initial LVDS value 300
>[drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 10000 Hz, active high, min brightness 0, level 255
>[drm:parse_sdvo_panel_data] Found SDVO panel mode in BIOS VBT tables:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[drm:parse_sdvo_device_mapping] No SDVO device info is found in VBT
>[drm:parse_driver_features] DRRS State Enabled:1
>[drm:intel_dsm_pci_probe] no _DSM method for intel device
>[drm:intel_update_rawclk] rawclk rate: 125000 kHz
>[drm:intel_power_well_enable] enabling always-on
>[drm:drm_irq_install] irq=24
>[drm:intel_fbc_init] Sanitized enable_fbc value: 0
>[drm:intel_print_wm_latency] Primary WM0 latency 12 (1.2 usec)
>[drm:intel_print_wm_latency] Primary WM1 latency 4 (2.0 usec)
>[drm:intel_print_wm_latency] Primary WM2 latency 16 (8.0 usec)
>[drm:intel_print_wm_latency] Primary WM3 latency 32 (16.0 usec)
>[drm:intel_print_wm_latency] Sprite WM0 latency 12 (1.2 usec)
>[drm:intel_print_wm_latency] Sprite WM1 latency 4 (2.0 usec)
>[drm:intel_print_wm_latency] Sprite WM2 latency 16 (8.0 usec)
>[drm:intel_print_wm_latency] Sprite WM3 latency 32 (16.0 usec)
>[drm:intel_print_wm_latency] Cursor WM0 latency 12 (1.2 usec)
>[drm:intel_print_wm_latency] Cursor WM1 latency 4 (2.0 usec)
>[drm:intel_print_wm_latency] Cursor WM2 latency 16 (8.0 usec)
>[drm:intel_print_wm_latency] Cursor WM3 latency 64 (32.0 usec)
>[drm:intel_modeset_init] 3 display pipes available.
>[drm:intel_update_cdclk] Current CD clock rate: 400000 kHz
>[drm:intel_update_max_cdclk] Max CD clock rate: 400000 kHz
>[drm:intel_update_max_cdclk] Max dotclock rate: 360000 kHz
>[drm:intel_lvds_pps_get_hw_state] LVDS PPS:t1+t2 400 t3 300 t4 4000 t5 2000 tx 2000 divider 6249 port 0 powerdown_on_reset 1
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[drm:intel_lvds_init] using mode from VBT: 
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_panel_setup_backlight] Connector LVDS-1 backlight initialized, enabled, brightness 4648/4648
>[drm:intel_lvds_init] detected dual-link lvds configuration
>[drm:intel_crt_reset] crt adpa set to 0xf40000
>[drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus dpb. force bit now 1
>[drm:intel_sdvo_read_byte] i2c transfer returned -6
>[drm:intel_sdvo_init] No SDVO device found on SDVOB
>[drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus dpb. force bit now 0
>[drm:intel_hdmi_init_connector] Adding HDMI connector on port B
>[drm:intel_dp_init_connector] Adding DP connector on port B
>[drm:ironlake_init_pch_refclk] has_panel 1 has_lvds 1 has_ck505 0 using_ssc_source 1
>[drm:ironlake_init_pch_refclk] Using SSC on panel
>[drm:intel_modeset_readout_hw_state] [CRTC:26:pipe A] hw state readout: enabled
>[drm:intel_modeset_readout_hw_state] [CRTC:30:pipe B] hw state readout: disabled
>[drm:intel_modeset_readout_hw_state] [CRTC:34:pipe C] hw state readout: disabled
>[drm:intel_modeset_readout_hw_state] PCH DPLL A hw state readout: crtc_mask 0x00000001, on 1
>[drm:intel_modeset_readout_hw_state] PCH DPLL B hw state readout: crtc_mask 0x00000000, on 0
>[drm:intel_modeset_readout_hw_state] [ENCODER:37:LVDS] hw state readout: enabled, pipe A
>[drm:intel_modeset_readout_hw_state] [ENCODER:41:CRT] hw state readout: disabled, pipe A
>[drm:intel_modeset_readout_hw_state] [ENCODER:42:HDMI B] hw state readout: disabled, pipe A
>[drm:intel_modeset_readout_hw_state] [ENCODER:47:DP B] hw state readout: disabled, pipe A
>[drm:intel_modeset_readout_hw_state] [CONNECTOR:36:LVDS-1] hw state readout: enabled
>[drm:intel_modeset_readout_hw_state] [CONNECTOR:40:VGA-1] hw state readout: disabled
>[drm:intel_modeset_readout_hw_state] [CONNECTOR:43:HDMI-A-1] hw state readout: disabled
>[drm:intel_modeset_readout_hw_state] [CONNECTOR:48:DP-1] hw state readout: disabled
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1600x900] for CRTC state ffff8802142cf000
>[drm:drm_calc_timestamping_constants] crtc 26: hwmode: htotal 1792, vtotal 932, vdisplay 900
>[drm:drm_calc_timestamping_constants] crtc 26: clock 100714 kHz framedur 16583037 linedur 17792
>[drm:drm_vblank_on] crtc 0, vblank enabled 0, inmodeset 1
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,67)@ 2.721668 -> 2.720476 [e 2 us, 0 rep]
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][setup_hw_state] config ffff8802142cf000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 4, gmch_m: 2339489, gmch_n: 8388608, link_m: 194957, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 100714 1600 1648 1680 1792 900 902 907 932 0x40 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 100714 1600 1648 1680 1792 900 902 907 932 0x40 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 100714 1600 1648 1680 1792 900 902 907 932, type: 0x40 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 100714
>[drm:intel_dump_pipe_config] pipe src size: 1600x900
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x06400384, enabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [CRTC:30:pipe B][setup_hw_state] config ffff880214300000 for pipe B
>[drm:intel_dump_pipe_config] cpu_transcoder: B
>[drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0
>[drm:intel_dump_pipe_config] pipe src size: 0x0
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x0, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:28:primary B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:29:cursor B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:31:sprite B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [CRTC:34:pipe C][setup_hw_state] config ffff880214301000 for pipe C
>[drm:intel_dump_pipe_config] cpu_transcoder: C
>[drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0
>[drm:intel_dump_pipe_config] pipe src size: 0x0
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x0, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:32:primary C] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:33:cursor C] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:35:sprite C] disabled, scaler_id = 0
>[drm:drm_mode_object_reference] OBJ ID: 36 (1)
>[drm:ironlake_get_initial_plane_config] pipe A with fb: size=1600x900@32, offset=0, pitch 6400, size 0x57e400
>[drm:i915_gem_object_create_stolen_for_preallocated] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=57f000
>[drm:i915_pages_create_for_stolen] offset=0x0, size=5763072
>[drm:intel_alloc_initial_plane_obj] initial plane fb obj ffff880213f18000
>[drm:drm_mode_object_reference] OBJ ID: 50 (1)
>[drm:drm_atomic_state_init] Allocated atomic state ffff880214304000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff880214304800 state to ffff880214304000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff880214305000 state to ffff880214304000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff880214305800 state to ffff880214304000
>[drm:drm_mode_object_reference] OBJ ID: 50 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880213dd6780 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880213dd6840 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:27:sprite A] ffff880213dd6900 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880213dd69c0 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff880213dd6a80 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite B] ffff880213dd6b40 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880213dd6c00 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff880213dd6cc0 state to ffff880214304000
>[drm:drm_atomic_get_plane_state] Added [PLANE:35:sprite C] ffff880213dd6d80 state to ffff880214304000
>[drm:drm_mode_object_reference] OBJ ID: 36 (2)
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880213dd8e80 state to ffff880214304000
>[drm:drm_mode_object_reference] OBJ ID: 40 (1)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:40] ffff880213dd8ea0 state to ffff880214304000
>[drm:drm_mode_object_reference] OBJ ID: 43 (1)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:43] ffff880213dd8ec0 state to ffff880214304000
>[drm:drm_mode_object_reference] OBJ ID: 48 (1)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:48] ffff880213dd8ee0 state to ffff880214304000
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:update_connector_routing] Updating routing for [CONNECTOR:40:VGA-1]
>[drm:update_connector_routing] Disabling [CONNECTOR:40:VGA-1]
>[drm:update_connector_routing] Updating routing for [CONNECTOR:43:HDMI-A-1]
>[drm:update_connector_routing] Disabling [CONNECTOR:43:HDMI-A-1]
>[drm:update_connector_routing] Updating routing for [CONNECTOR:48:DP-1]
>[drm:update_connector_routing] Disabling [CONNECTOR:48:DP-1]
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880214304000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 40 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 43 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 48 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880214304000
>[drm:i915_gem_init_ggtt] clearing unused GTT space: [57f000, 7ffff000]
>[drm:gen6_ppgtt_init] Allocated pde space (2M) at GTT entry: 7fdf0
>[drm:gen6_ppgtt_init] Adding PPGTT at offset 7fdf0000
>[drm:i915_gem_context_init] HW context support initialized
>[drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[drm:i915_pages_create_for_stolen] offset=0x57f000, size=131072
>[drm:init_status_page] render ring hws offset: 0x7fff0000
>[drm:i915_gem_object_create_stolen] creating stolen object: size=1000
>[drm:i915_pages_create_for_stolen] offset=0x59f000, size=4096
>[drm:intel_engine_create_scratch] render ring pipe control offset: 0x7fffe000
>[drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[drm:i915_pages_create_for_stolen] offset=0x5a0000, size=131072
>[drm:init_status_page] blitter ring hws offset: 0x0059f000
>[drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[drm:i915_pages_create_for_stolen] offset=0x5c0000, size=131072
>[drm:init_status_page] bsd ring hws offset: 0x005c0000
>[drm:intel_guc_setup] GuC fw status: path (null), fetch NONE, load NONE
>[drm:intel_init_gt_powersave] Overclocking supported, max: 1050MHz, overclock: 1050MHz
>[drm:intel_update_cdclk] Current CD clock rate: 400000 kHz
>[drm:intel_fbdev_init_bios] found possible fb from plane A
>[drm:intel_fbdev_init_bios] pipe B not active or no fb, skipping
>[drm:intel_fbdev_init_bios] pipe C not active or no fb, skipping
>[drm:intel_fbdev_init_bios] checking plane A for BIOS fb
>[drm:intel_fbdev_init_bios] pipe A area: 1600x900, bpp: 32, size: 5760000
>[drm:intel_fbdev_init_bios] fb big enough for plane A (5763072 >= 5760000)
>[drm:intel_fbdev_init_bios] pipe B not active, skipping
>[drm:intel_fbdev_init_bios] pipe C not active, skipping
>[drm:drm_mode_object_reference] OBJ ID: 50 (2)
>[drm:intel_fbdev_init_bios] using BIOS fb for initial console
>[drm:drm_mode_object_reference] OBJ ID: 36 (2)
>[drm:drm_mode_object_reference] OBJ ID: 40 (1)
>[drm:drm_mode_object_reference] OBJ ID: 43 (1)
>[drm:drm_mode_object_reference] OBJ ID: 48 (1)
>[drm:drm_minor_register] 
>[drm:drm_minor_register] new minor registered 64
>[drm:drm_minor_register] 
>[drm:drm_minor_register] new minor registered 128
>[drm:drm_minor_register] 
>[drm:drm_minor_register] new minor registered 0
>[drm:drm_sysfs_connector_add] adding "LVDS-1" to sysfs
>[drm:drm_sysfs_hotplug_event] generating hotplug event
>[drm:intel_backlight_device_register] Connector LVDS-1 backlight sysfs interface registered
>[drm:drm_sysfs_connector_add] adding "VGA-1" to sysfs
>[drm:drm_sysfs_hotplug_event] generating hotplug event
>[drm:drm_sysfs_connector_add] adding "HDMI-A-1" to sysfs
>[drm:drm_sysfs_hotplug_event] generating hotplug event
>[drm:drm_sysfs_connector_add] adding "DP-1" to sysfs
>[drm:drm_sysfs_hotplug_event] generating hotplug event
>[drm:intel_dp_connector_register] registering DPDDC-B bus for card0-DP-1
>[drm:drm_dp_aux_register_devnode] drm_dp_aux_dev: aux [DPDDC-B] registered as minor 0
>[drm:intel_didl_outputs] 8 outputs detected
>[drm:i915_driver_load] Initialized i915 1.6.0 20160902 for 0000:00:02.0 on minor 0
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1]
>[drm:intel_lvds_detect] [CONNECTOR:36:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1] status updated from unknown to connected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1] probed modes :
>[drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1]
>[drm:intel_crt_detect] [CONNECTOR:40:VGA-1] force=1
>[drm:intel_ironlake_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[drm:intel_ironlake_crt_detect_hotplug] ironlake hotplug adpa=0xf40000, result 0
>[drm:intel_crt_detect] CRT not detected via hotplug
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1] status updated from unknown to disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1] disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] HDMI live status down
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1] status updated from unknown to disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1] disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[drm:intel_dp_detect] [CONNECTOR:48:DP-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[drm:drm_setup_crtcs] 
>[drm:drm_enable_connectors] connector 36 enabled? yes
>[drm:drm_enable_connectors] connector 40 enabled? no
>[drm:drm_enable_connectors] connector 43 enabled? no
>[drm:drm_enable_connectors] connector 48 enabled? no
>[drm:intel_fb_initial_config] looking for cmdline mode on connector LVDS-1
>[drm:intel_fb_initial_config] looking for preferred mode on connector LVDS-1 0
>[drm:intel_fb_initial_config] connector LVDS-1 on [CRTC:26:pipe A]: 640x480
>[drm:intel_fb_initial_config] connector VGA-1 not enabled, skipping
>[drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
>[drm:drm_setup_crtcs] desired mode 640x480 set on crtc 26 (0,0)
>[drm:intelfb_create] re-using BIOS fb
>[drm:drm_sysfs_hotplug_event] generating hotplug event
>[drm:intelfb_create] allocated 1600x900 fb: 0x00000000
>[drm:drm_fb_helper_hotplug_event] 
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1]
>[drm:intel_lvds_detect] [CONNECTOR:36:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1] probed modes :
>[drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1]
>[drm:intel_crt_detect] [CONNECTOR:40:VGA-1] force=1
>[drm:intel_ironlake_crt_detect_hotplug] ironlake hotplug adpa=0xf40000, result 0
>[drm:intel_crt_detect] CRT not detected via hotplug
>fbcon: inteldrmfb (fb0) is primary device
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1] disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] HDMI live status down
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1] disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[drm:intel_dp_detect] [CONNECTOR:48:DP-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[drm:drm_setup_crtcs] 
>[drm:drm_enable_connectors] connector 36 enabled? yes
>[drm:drm_enable_connectors] connector 40 enabled? no
>[drm:drm_enable_connectors] connector 43 enabled? no
>[drm:drm_enable_connectors] connector 48 enabled? no
>[drm:intel_fb_initial_config] looking for cmdline mode on connector LVDS-1
>[drm:intel_fb_initial_config] looking for preferred mode on connector LVDS-1 0
>[drm:intel_fb_initial_config] connector LVDS-1 on [CRTC:26:pipe A]: 640x480
>[drm:intel_fb_initial_config] connector VGA-1 not enabled, skipping
>[drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
>[drm:drm_setup_crtcs] desired mode 640x480 set on crtc 26 (0,0)
>[drm:drm_atomic_state_init] Allocated atomic state ffff880214335000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880214315e40 state to ffff880214335000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff880214335800 state to ffff880214335000
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880214315f00 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315f00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315f00
>[drm:drm_atomic_get_plane_state] Added [PLANE:27:sprite A] ffff880214315cc0 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315cc0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315cc0
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880214315c00 state to ffff880214335000
>[drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff8802143159c0 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143159c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143159c0
>[drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite B] ffff880214315a80 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315a80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315a80
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880214315840 state to ffff880214335000
>[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff880214315900 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315900
>[drm:drm_atomic_get_plane_state] Added [PLANE:35:sprite C] ffff880214315780 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315780
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff880214335800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315e40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff880214315e40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880214335000
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880214d36fa0 state to ffff880214335000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880214d36fa0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880214d36fa0 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff880214336000 state to ffff880214335000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880214336000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315c00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315c00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff880214335000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff880214336800 state to ffff880214335000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880214336800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214315840 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214315840
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff880214335000
>[drm:drm_atomic_check_only] checking ffff880214335000
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880214335000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880214335000
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880214335800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880214335000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880214335000
>[drm:drm_atomic_state_init] Allocated atomic state ffff880215bb5000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802143fb540 state to ffff880215bb5000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff880215bb5800 state to ffff880215bb5000
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802143fb600 state to ffff880215bb5000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb600 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb600
>[drm:drm_atomic_get_plane_state] Added [PLANE:27:sprite A] ffff8802143fb6c0 state to ffff880215bb5000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb6c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb6c0
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802143fb780 state to ffff880215bb5000
>[drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff8802143fb840 state to ffff880215bb5000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb840 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb840
>[drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite B] ffff8802143fb900 state to ffff880215bb5000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb900
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802143fb9c0 state to ffff880215bb5000
>[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff8802143fba80 state to ffff880215bb5000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fba80
>[drm:drm_atomic_get_plane_state] Added [PLANE:35:sprite C] ffff8802143fbb40 state to ffff880215bb5000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fbb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fbb40
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff880215bb5800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb540 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802143fb540
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880215bb5000
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215bc0860 state to ffff880215bb5000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215bc0860 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215bc0860 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff880215bb6000 state to ffff880215bb5000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215bb6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff880215bb5000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff880215bb6800 state to ffff880215bb5000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215bb6800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb9c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb9c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff880215bb5000
>[drm:drm_atomic_check_only] checking ffff880215bb5000
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880215bb5000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880215bb5000
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880215bb5800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880215bb5000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880215bb5000
>[drm:drm_sysfs_hotplug_event] generating hotplug event
>[drm:drm_fb_helper_hotplug_event] 
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1]
>[drm:intel_lvds_detect] [CONNECTOR:36:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1] probed modes :
>[drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1]
>[drm:intel_crt_detect] [CONNECTOR:40:VGA-1] force=1
>[drm:intel_ironlake_crt_detect_hotplug] ironlake hotplug adpa=0xf40000, result 0
>[drm:intel_crt_detect] CRT not detected via hotplug
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1] disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] HDMI live status down
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1] disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[drm:intel_dp_detect] [CONNECTOR:48:DP-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[drm:drm_setup_crtcs] 
>[drm:drm_enable_connectors] connector 36 enabled? yes
>[drm:drm_enable_connectors] connector 40 enabled? no
>[drm:drm_enable_connectors] connector 43 enabled? no
>[drm:drm_enable_connectors] connector 48 enabled? no
>[drm:intel_fb_initial_config] looking for cmdline mode on connector LVDS-1
>[drm:intel_fb_initial_config] looking for preferred mode on connector LVDS-1 0
>[drm:intel_fb_initial_config] connector LVDS-1 on [CRTC:26:pipe A]: 640x480
>[drm:intel_fb_initial_config] connector VGA-1 not enabled, skipping
>[drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
>[drm:drm_setup_crtcs] desired mode 640x480 set on crtc 26 (0,0)
>[drm:drm_atomic_state_init] Allocated atomic state ffff880214335000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880213ca70c0 state to ffff880214335000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff880214336800 state to ffff880214335000
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880213ca7180 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca7180 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca7180
>[drm:drm_atomic_get_plane_state] Added [PLANE:27:sprite A] ffff880213ca7240 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca7240 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca7240
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880213ca7300 state to ffff880214335000
>[drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff880213ca73c0 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca73c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca73c0
>[drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite B] ffff880213ca7480 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca7480 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca7480
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880213ca7540 state to ffff880214335000
>[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff880213ca7600 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca7600 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca7600
>[drm:drm_atomic_get_plane_state] Added [PLANE:35:sprite C] ffff880213ca76c0 state to ffff880214335000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca76c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca76c0
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff880214336800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca70c0 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff880213ca70c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880214335000
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880214d36f60 state to ffff880214335000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880214d36f60 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880214d36f60 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff880214336000 state to ffff880214335000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880214336000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca7300 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca7300
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff880214335000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff880214335800 state to ffff880214335000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880214335800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880213ca7540 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880213ca7540
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff880214335000
>[drm:drm_atomic_check_only] checking ffff880214335000
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880214335000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880214335000
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880214336800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880214335000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880214335000
>[drm:drm_atomic_state_init] Allocated atomic state ffff880215bb5000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff880215bb6800 state to ffff880215bb5000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802143fbb40 state to ffff880215bb5000
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff880215bb6800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fbb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802143fbb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880215bb5000
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215bc0860 state to ffff880215bb5000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215bc0860 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215bc0860 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff880215bb6000 state to ffff880215bb5000
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802143fb9c0 state to ffff880215bb5000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215bb6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb9c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb9c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff880215bb5000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff880215bb5800 state to ffff880215bb5000
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802143fb900 state to ffff880215bb5000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215bb5800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802143fb900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802143fb900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff880215bb5000
>[drm:drm_atomic_check_only] checking ffff880215bb5000
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880215bb5000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff880215bb5000
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880215bb6800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880215bb5000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880215bb5000
>i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[drm:intel_print_rc6_info] Enabling RC6 states: RC6 on RC6p on RC6pp off
>[drm:sandybridge_pcode_write] warning: pcode (write) mailbox access failed: -75
>[drm:gen6_enable_rps] Failed to set the min frequency
>[drm:intel_backlight_device_update_status] updating intel_backlight, brightness=232/4648
>[drm:intel_panel_actually_set_backlight] set backlight PWM = 232
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 1219, minor = 0
>[drm:i915_gem_open] 
>[drm:drm_setup] 
>[drm:drm_ioctl] pid=1219, dev=0xe200, auth=1, DRM_IOCTL_SET_MASTER
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_GET_APERTURE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_REG_READ
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GET_RESET_STATS
>[drm:drm_ioctl] ret = -1
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CONTEXT_CREATE
>[drm:i915_gem_context_create_ioctl] HW context 1 created
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CONTEXT_DESTROY
>[drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CONTEXT_CREATE
>[drm:i915_gem_context_create_ioctl] HW context 1 created
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1]
>[drm:intel_lvds_detect] [CONNECTOR:36:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:36:LVDS-1] probed modes :
>[drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1]
>[drm:intel_crt_detect] [CONNECTOR:40:VGA-1] force=1
>[drm:intel_ironlake_crt_detect_hotplug] ironlake hotplug adpa=0xf40000, result 0
>[drm:intel_crt_detect] CRT not detected via hotplug
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:VGA-1] disconnected
>[drm:drm_mode_object_unreference] OBJ ID: 40 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_mode_object_unreference] OBJ ID: 40 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[drm:intel_hdmi_detect] HDMI live status down
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:43:HDMI-A-1] disconnected
>[drm:drm_mode_object_unreference] OBJ ID: 43 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_mode_object_unreference] OBJ ID: 43 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[drm:intel_dp_detect] [CONNECTOR:48:DP-1]
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[drm:drm_mode_object_unreference] OBJ ID: 48 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[drm:drm_mode_object_unreference] OBJ ID: 48 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETENCODER
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETENCODER
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETENCODER
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETENCODER
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETENCODER
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_SETPROPERTY
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b537000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880214f4e0c0 state to ffff88020b537000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b537800 state to ffff88020b537000
>[drm:drm_atomic_check_only] checking ffff88020b537000
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_commit] commiting ffff88020b537000
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,605)@ 16.96021 -> 16.85256 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1, diff=804, hw=1797 hw_last=993
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,605)@ 16.96034 -> 16.85270 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=805, diff=0, hw=1797 hw_last=1797
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,606)@ 16.96050 -> 16.85268 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=805, diff=0, hw=1797 hw_last=1797
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-30)@ 16.101328 -> 16.101861 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=805, diff=1, hw=1798 hw_last=1797
>[drm:drm_handle_vblank_events] vblank event on 805, current 806
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-28)@ 16.101361 -> 16.101859 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=806, diff=0, hw=1798 hw_last=1798
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b537000
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b537000
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 2217, minor = 0
>[drm:i915_gem_open] 
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=0, DRM_IOCTL_GET_MAGIC
>[drm:drm_getmagic] 1
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_AUTH_MAGIC
>[drm:drm_authmagic] 1
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_GET_APERTURE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_REG_READ
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GET_RESET_STATS
>[drm:drm_ioctl] ret = -1
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CONTEXT_CREATE
>[drm:i915_gem_context_create_ioctl] HW context 1 created
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CREATE_DUMB
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_MAP_DUMB
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR2
>[drm:drm_atomic_state_init] Allocated atomic state ffff880215bb0000
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff88020a031000 state to ffff880215bb0000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020c86e800 state to ffff880215bb0000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031000 to [CRTC:26:pipe A]
>[drm:drm_mode_object_reference] OBJ ID: 53 (1)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff88020a031000
>[drm:drm_atomic_check_only] checking ffff880215bb0000
>[drm:drm_atomic_helper_crtc_normalize_zpos] [CRTC:26:pipe A] calculating normalized zpos values
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff88020a031a80 state to ffff880215bb0000
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:23:primary A] processing zpos value 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:25:cursor A] processing zpos value 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:23:primary A] normalized zpos value 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:25:cursor A] normalized zpos value 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[drm:drm_atomic_commit] commiting ffff880215bb0000
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,331)@ 16.938936 -> 16.933047 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=806, diff=50, hw=1848 hw_last=1798
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,331)@ 16.938947 -> 16.933058 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=856, diff=0, hw=1848 hw_last=1848
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880215bb0000
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880215bb0000
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_state_init] Allocated atomic state ffff880215bb0000
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff88020a0319c0 state to ffff880215bb0000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88021681c800 state to ffff880215bb0000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a0319c0 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff88020a0319c0
>[drm:drm_atomic_check_only] checking ffff880215bb0000
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_commit] commiting ffff880215bb0000
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,336)@ 16.939027 -> 16.933049 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=856, diff=0, hw=1848 hw_last=1848
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,336)@ 16.939037 -> 16.933059 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=856, diff=0, hw=1848 hw_last=1848
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880215bb0000
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880215bb0000
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 2217, minor = 0
>[drm:i915_gem_open] 
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=0, DRM_IOCTL_GET_MAGIC
>[drm:drm_getmagic] 2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_AUTH_MAGIC
>[drm:drm_authmagic] 2
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_THROTTLE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GEM_GET_APERTURE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_THROTTLE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_REG_READ
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GET_RESET_STATS
>[drm:drm_ioctl] ret = -1
>[drm:drm_ioctl] pid=2293, dev=0xe200, auth=1, I915_GETPARAM
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9402800
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9402800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9403000 state to ffff8801f9402800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff880201b5ba80
>[drm:drm_atomic_check_only] checking ffff8801f9402800
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_commit] commiting ffff8801f9402800
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,709)@ 18.458444 -> 18.445829 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=856, diff=91, hw=1939 hw_last=1848
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,710)@ 18.458453 -> 18.445820 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=947, diff=0, hw=1939 hw_last=1939
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9402800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9402800
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c02e0 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c02e0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c02e0 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5be40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5be40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5be40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5be40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_PAGE_FLIP
>[drm:check_src_coords] Invalid source coordinates 1600.000000x900.000000+0.000000+0.000000
>WARNING: CPU: 1 PID: 2180 at drivers/gpu/drm/drm_irq.c:1168 drm_vblank_put+0xb4/0xc0 [drm]
> tpm sch_fq_codel ip_tables x_tables ext4 crc16 jbd2 mbcache sd_mod ahci libahci xhci_pci xhci_hcd libata ehci_pci ehci_hcd scsi_mod usbcore usb_common i915 button video intel_gtt i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm
> [<ffffffffa0007774>] drm_vblank_put+0xb4/0xc0 [drm]
> [<ffffffffa0007797>] drm_crtc_vblank_put+0x17/0x20 [drm]
> [<ffffffffa0011432>] drm_mode_page_flip_ioctl+0x162/0x480 [drm]
> [<ffffffffa000600c>] drm_ioctl+0x39c/0x4e0 [drm]
> [<ffffffffa00112d0>] ? drm_mode_gamma_get_ioctl+0xe0/0xe0 [drm]
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_ioctl] ret = -28
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c02e0 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c02e0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c02e0 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5be40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5be40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5be40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_state_init] Allocated atomic state ffff880215bb0000
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff88020a031840 state to ffff880215bb0000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f38e8000 state to ffff880215bb0000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031840 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff88020a031840
>[drm:drm_atomic_check_only] checking ffff880215bb0000
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_commit] commiting ffff880215bb0000
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,665)@ 18.524138 -> 18.512305 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=947, diff=4, hw=1943 hw_last=1939
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,665)@ 18.524150 -> 18.512318 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=951, diff=0, hw=1943 hw_last=1943
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880215bb0000
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff880215bb0000
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:55]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f38e9000 state to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff88020a0319c0 state to ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f38e9000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a0319c0 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:55] for plane state ffff88020a0319c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff88020ffc38a0 state to ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020ffc38a0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020ffc38a0 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff88020a031b40 state to ffff8801f38e8800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f38e9000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 55
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 57 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f38e9000 state to ffff8801f38e8800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff88020a031b40 state to ffff8801f38e8800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f38e9000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031b40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020a031b40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f38e8800
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_commit] commiting ffff8801f38e8800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f38e9800 state to ffff8801f38e8800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff88020a0319c0 state to ffff8801f38e8800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f38e9800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a0319c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020a0319c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f38e8800
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_commit] commiting ffff8801f38e8800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0300 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0300 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0300 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 57 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 55 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_SETPROPERTY
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,783)@ 18.725726 -> 18.711794 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=951, diff=12, hw=1955 hw_last=1943
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,783)@ 18.725738 -> 18.711806 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=963, diff=0, hw=1955 hw_last=1955
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,784)@ 18.725748 -> 18.711798 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=963, diff=0, hw=1955 hw_last=1955
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-32)@ 18.727823 -> 18.728392 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=963, diff=1, hw=1956 hw_last=1955
>[drm:drm_handle_vblank_events] vblank event on 963, current 964
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-31)@ 18.727839 -> 18.728391 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=964, diff=0, hw=1956 hw_last=1956
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:55]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:55] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0320 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0320 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0320 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5be40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 55
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 57 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5be40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5be40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5be40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bcc0 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 57 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bcc0 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bcc0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bcc0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5be40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5be40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5be40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 55 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:55]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f97c0800 state to ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880214f4a180 state to ffff8801f97c0000
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f97c0800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214f4a180 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:55] for plane state ffff880214f4a180
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95dcca0 state to ffff8801f97c0000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95dcca0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95dcca0 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f97c0000
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880214f4a300 state to ffff8801f97c0000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f97c0000
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f97c0800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 55
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f97c0000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 57 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f97c0000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f97c0800 state to ffff8801f97c0000
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880214f4a300 state to ffff8801f97c0000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f97c0800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214f4a300 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214f4a300
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f97c0000
>[drm:drm_atomic_check_only] checking ffff8801f97c0000
>[drm:drm_atomic_commit] commiting ffff8801f97c0000
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f97c0000
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f97c0000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f97c1000 state to ffff8801f97c0000
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880214f4a180 state to ffff8801f97c0000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f97c1000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880214f4a180 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880214f4a180
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f97c0000
>[drm:drm_atomic_check_only] checking ffff8801f97c0000
>[drm:drm_atomic_commit] commiting ffff8801f97c0000
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f97c0000
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f97c0000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f38ea000 state to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff88020a0316c0 state to ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f38ea000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a0316c0 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff88020a0316c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff88020ffc35c0 state to ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020ffc35c0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020ffc35c0 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff88020a031000 state to ffff8801f38e8800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f38ea000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 57 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f38ea000 state to ffff8801f38e8800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff88020a031000 state to ffff8801f38e8800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f38ea000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031000 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020a031000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f38e8800
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_commit] commiting ffff8801f38e8800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f38ea800 state to ffff8801f38e8800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff88020a0316c0 state to ffff8801f38e8800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f38ea800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a0316c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020a0316c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f38e8800
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_commit] commiting ffff8801f38e8800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 55 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETGAMMA
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETGAMMA
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,873)@ 18.827088 -> 18.811555 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=964, diff=5, hw=1961 hw_last=1956
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,874)@ 18.827097 -> 18.811546 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=969, diff=0, hw=1961 hw_last=1961
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,876)@ 18.827141 -> 18.811555 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=969, diff=0, hw=1961 hw_last=1961
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-32)@ 18.827565 -> 18.828135 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=969, diff=1, hw=1962 hw_last=1961
>[drm:drm_handle_vblank_events] vblank event on 969, current 970
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-31)@ 18.827583 -> 18.828135 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=970, diff=0, hw=1962 hw_last=1962
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0340 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0340 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406800 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f38eb000 state to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff88020a031d80 state to ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f38eb000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031d80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff88020a031d80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff88020ffc35c0 state to ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020ffc35c0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020ffc35c0 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff88020a031000 state to ffff8801f38e8800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f38e8800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f38eb000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f38eb000 state to ffff8801f38e8800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff88020a031000 state to ffff8801f38e8800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f38eb000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031000 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020a031000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f38e8800
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_commit] commiting ffff8801f38e8800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f38e8800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f38eb800 state to ffff8801f38e8800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff88020a031d80 state to ffff8801f38e8800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f38eb800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020a031d80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020a031d80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f38e8800
>[drm:drm_atomic_check_only] checking ffff8801f38e8800
>[drm:drm_atomic_commit] commiting ffff8801f38e8800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f38e8800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f38e8800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9405000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b780 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9407000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9405000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bf00 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:56]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5b900 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b900 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 56 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:56] for plane state ffff880201b5b900
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c0360 state to ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c0360 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9403800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9406000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 56
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9406000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5ba80 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9406000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5ba80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5ba80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9403800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9407000 state to ffff8801f9403800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5bb40 state to ffff8801f9403800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9407000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5bb40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9403800
>[drm:drm_atomic_check_only] checking ffff8801f9403800
>[drm:drm_atomic_commit] commiting ffff8801f9403800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9403800
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9403800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fe240 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f5800 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe240 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff8802040fe240
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_commit] commiting ffff88020b7f7800
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,42)@ 20.308381 -> 20.307634 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=970, diff=89, hw=2051 hw_last=1962
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,43)@ 20.308396 -> 20.307631 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1059, diff=0, hw=2051 hw_last=2051
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB
>[drm:drm_mode_addfb2] [FB:54]
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[drm:drm_mode_setcrtc] [CONNECTOR:36:LVDS-1]
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f4800 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802040fe3c0 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff88020b7f4800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe3c0 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 54 (2)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:54] for plane state ffff8802040fe3c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215adcc80 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [CRTC:26:pipe A]
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fe0c0 state to ffff88020b7f7800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88020b7f4800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 54
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (6)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 58 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_ioctl] ret = -22
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:30:pipe B]
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff88020b7f4800 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802040fe0c0 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f4800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe0c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe0c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff88020b7f7800
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_commit] commiting ffff88020b7f7800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[drm:drm_mode_setcrtc] [CRTC:34:pipe C]
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff88020b7f4000 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802040fe3c0 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f4000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe3c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe3c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff88020b7f7800
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_commit] commiting ffff88020b7f7800
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[drm:drm_mode_object_unreference] OBJ ID: 56 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_PWRITE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SW_FINISH
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fea80 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f3800 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fea80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_mode_object_reference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff8802040fea80
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[drm:drm_atomic_commit] commiting ffff88020b7f7800
>[drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,749)@ 20.321005 -> 20.307678 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1059, diff=0, hw=2051 hw_last=2051
>[drm:vblank_disable_fn] disabling vblank on crtc 0
>[drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,751)@ 20.321024 -> 20.307662 [e 0 us, 0 rep]
>[drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1059, diff=0, hw=2051 hw_last=2051
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_ioctl] pid=1219, dev=0xe200, auth=1, DRM_IOCTL_DROP_MASTER
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802040fe240 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f5800 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fe300 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe300 to [NOCRTC]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe300
>[drm:drm_atomic_get_plane_state] Added [PLANE:27:sprite A] ffff8802040fe480 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe480 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe480
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802040fe9c0 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff8802040fe780 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe780
>[drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite B] ffff8802040fe540 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe540 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe540
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802040fe6c0 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff8802040feb40 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040feb40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040feb40
>[drm:drm_atomic_get_plane_state] Added [PLANE:35:sprite C] ffff8802040fed80 state to ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fed80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fed80
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff88020b7f5800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe240 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802040fe240
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215adcc80 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff88020b7f3000 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f3000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe9c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe9c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff88020b7f7800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff88020b7f2800 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f2800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe6c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe6c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff88020b7f7800
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88020b7f5800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [CRTC:26:pipe A] calculating normalized zpos values
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:23:primary A] processing zpos value 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:23:primary A] normalized zpos value 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb -1
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f2800 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802040fed80 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff88020b7f2800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fed80 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802040fed80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215adcc80 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff88020b7f3000 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802040fe6c0 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f3000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe6c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe6c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff88020b7f7800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff88020b7f5800 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802040fe540 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f5800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe540 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe540
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff88020b7f7800
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fe780 state to ffff88020b7f7800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88020b7f2800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f5800 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802040fe540 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff88020b7f5800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe540 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802040fe540
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215adcc80 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adcc80 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff88020b7f3000 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802040fe780 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f3000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff88020b7f7800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff88020b7f2800 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802040fed80 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f2800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fed80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fed80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff88020b7f7800
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040feb40 state to ffff88020b7f7800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88020b7f5800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_atomic_state_init] Allocated atomic state ffff8801f9400800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8801f9403800 state to ffff8801f9400800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff880201b5bf00 state to ffff8801f9400800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff8801f9403800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5bf00 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff880201b5bf00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9400800
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff8801f95c03a0 state to ffff8801f9400800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c03a0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f95c03a0 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff8801f9405000 state to ffff8801f9400800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff880201b5b780 state to ffff8801f9400800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9405000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5b780 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5b780
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff8801f9400800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff8801f9403000 state to ffff8801f9400800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff880201b5be40 state to ffff8801f9400800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9403000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201b5be40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201b5be40
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff8801f9400800
>[drm:drm_atomic_check_only] checking ffff8801f9400800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9400800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff880201b5bcc0 state to ffff8801f9400800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8801f9400800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8801f9403800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f9400800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff8801f9400800
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_CREATE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_BUSY
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_TILING
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_MMAP_GTT
>[drm:drm_ioctl] pid=2180, dev=0xe200, auth=1, I915_GEM_SET_DOMAIN
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_ioctl] pid=2217, dev=0xe200, auth=1, I915_GEM_MADVISE
>[drm:drm_release] open_count = 3
>[drm:drm_release] pid = 2293, device = 0xe200, open_count = 3
>[drm:drm_release] open_count = 2
>[drm:drm_release] pid = 2217, device = 0xe200, open_count = 2
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f3000 state to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802040fe9c0 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff88020b7f3000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe9c0 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802040fe9c0
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215adc520 state to ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adc520 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adc520 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff88020b7f0000 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802040fef00 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f0000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fef00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fef00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff88020b7f7800
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff88020b7f6800 state to ffff88020b7f7800
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802040fed80 state to ffff88020b7f7800
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f6800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fed80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fed80
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff88020b7f7800
>[drm:drm_atomic_check_only] checking ffff88020b7f7800
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fe300 state to ffff88020b7f7800
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f7800
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88020b7f3000 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 53
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f7800
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 56 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f7800
>[drm:drm_release] open_count = 1
>[drm:drm_release] pid = 1219, device = 0xe200, open_count = 1
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_lastclose] 
>[drm:drm_atomic_state_init] Allocated atomic state ffff88020b7f6000
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff8802040fe240 state to ffff88020b7f6000
>[drm:drm_mode_object_reference] OBJ ID: 49 (1)
>[drm:drm_mode_object_reference] OBJ ID: 55 (2)
>[drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff88020b7f7800 state to ffff88020b7f6000
>[drm:drm_mode_object_reference] OBJ ID: 53 (2)
>[drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff8802040fe900 state to ffff88020b7f6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe900 to [NOCRTC]
>[drm:drm_mode_object_unreference] OBJ ID: 53 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe900
>[drm:drm_atomic_get_plane_state] Added [PLANE:27:sprite A] ffff8802040fe6c0 state to ffff88020b7f6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe6c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe6c0
>[drm:drm_atomic_get_plane_state] Added [PLANE:28:primary B] ffff8802040fec00 state to ffff88020b7f6000
>[drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff8802040fee40 state to ffff88020b7f6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fee40 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fee40
>[drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite B] ffff8802040fecc0 state to ffff88020b7f6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fecc0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fecc0
>[drm:drm_atomic_get_plane_state] Added [PLANE:32:primary C] ffff8802040fe480 state to ffff88020b7f6000
>[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff8802040fed80 state to ffff88020b7f6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fed80 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fed80
>[drm:drm_atomic_get_plane_state] Added [PLANE:35:sprite C] ffff8802040fe9c0 state to ffff88020b7f6000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe9c0 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe9c0
>[drm:drm_mode_object_unreference] OBJ ID: 49 (2)
>[drm:drm_atomic_set_mode_for_crtc] Set [MODE:640x480] for CRTC state ffff88020b7f7800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe240 to [CRTC:26:pipe A]
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_mode_object_reference] OBJ ID: 50 (3)
>[drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8802040fe240
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f6000
>[drm:drm_mode_object_reference] OBJ ID: 36 (3)
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_get_connector_state] Added [CONNECTOR:36] ffff880215adc4c0 state to ffff88020b7f6000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adc4c0 to [NOCRTC]
>[drm:drm_mode_object_reference] OBJ ID: 36 (4)
>[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880215adc4c0 to [CRTC:26:pipe A]
>[drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff88020b7f6800 state to ffff88020b7f6000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f6800
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fec00 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fec00
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff88020b7f6000
>[drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff88020b7f0000 state to ffff88020b7f6000
>[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020b7f0000
>[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802040fe480 to [NOCRTC]
>[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802040fe480
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff88020b7f6000
>[drm:drm_atomic_check_only] checking ffff88020b7f6000
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
>[drm:update_connector_routing] Updating routing for [CONNECTOR:36:LVDS-1]
>[drm:update_connector_routing] [CONNECTOR:36:LVDS-1] keeps [ENCODER:37:LVDS], now on [CRTC:26:pipe A]
>[drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f6000
>[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff88020b7f6000
>[drm:connected_sink_compute_bpp] [CONNECTOR:36:LVDS-1] checking for sink bpp constrains
>[drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88020b7f7800 for pipe A
>[drm:intel_dump_pipe_config] cpu_transcoder: A
>[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 1173473, gmch_n: 4194304, link_m: 48894, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 63 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 25180 640 648 744 784 480 482 484 509 0x8 0xa
>[drm:intel_dump_crtc_timings] crtc timings: 25180 640 648 744 784 480 482 484 509, type: 0x8 flags: 0xa
>[drm:intel_dump_pipe_config] port clock: 25180
>[drm:intel_dump_pipe_config] pipe src size: 640x480
>[drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0
>[drm:intel_dump_pipe_config] double wide: 0
>[drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x20f07, fp1: 0x30d07
>[drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[drm:intel_dump_pipe_config]         FB:50, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+1600+900 dst 0x0+1600+900
>[drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[drm:intel_dump_pipe_config]         FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[drm:intel_dump_pipe_config]         scaler:0 src 0x0+256+256 dst 316x236+256+256
>[drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [CRTC:26:pipe A] calculating normalized zpos values
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:23:primary A] processing zpos value 0
>[drm:drm_atomic_helper_crtc_normalize_zpos] [PLANE:23:primary A] normalized zpos value 0
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 50
>[drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb -1
>[drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[drm:ironlake_crtc_compute_clock] using SSC reference clock of 120000 kHz
>[drm:ironlake_crtc_compute_clock] *ERROR* Couldn't find PLL settings for mode!
>[drm:drm_atomic_helper_check_planes] [CRTC:26:pipe A] atomic driver check failed
>[drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020b7f6000
>[drm:drm_mode_object_unreference] OBJ ID: 36 (5)
>[drm:drm_mode_object_unreference] OBJ ID: 36 (4)
>[drm:drm_mode_object_unreference] OBJ ID: 54 (1)
>[drm:drm_mode_object_unreference] OBJ ID: 55 (3)
>[drm:drm_mode_object_unreference] OBJ ID: 50 (4)
>[drm:drm_atomic_state_free] Freeing atomic state ffff88020b7f6000
>[drm:intel_fbdev_restore_mode] failed to restore crtc mode
>[drm:drm_lastclose] driver lastclose completed

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Attachments on bug 97363: 125813 | 125814 | 126020 | 126021 | 126253

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