Attachment 126983 Details for Bug 98036 – dmesg

dmesg

dmesglog (text/plain), 248.79 KB, created by Luis Botello on 2016-10-03 22:04:03 UTC

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Description:

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Creator: Luis Botello

Created: 2016-10-03 22:04:03 UTC

Size: 248.79 KB

patch

obsolete

>[   33.987998] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   33.990455] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   33.992899] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   33.992905] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   33.992910] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   33.992964] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   33.992969] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   34.005564] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   34.005567] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   34.006107] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   34.006164] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   34.006180] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   34.006184] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.006187] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   34.006190] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   34.006193] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   34.006196] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   34.006199] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   34.006202] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   34.006204] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   34.006207] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   34.006210] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   34.006213] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   34.006216] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   34.006910] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   34.006914] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   34.006920] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   34.006924] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   34.006926] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   34.006928] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   34.007834] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   34.008691] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   34.009590] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   34.009597] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   34.009601] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   34.010113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   34.010116] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   34.010122] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   34.015759] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   34.015762] [drm:intel_crt_detect] CRT not detected via hotplug
>[   34.015914] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   34.015916] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   34.016060] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   34.016064] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   34.016065] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   34.016067] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   34.016617] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   34.016618] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   34.016620] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   34.016622] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   34.016654] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   34.016656] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   34.019115] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.021566] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.024019] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.026471] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.028920] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.031372] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.033826] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.036275] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.038809] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.041290] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.043781] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.046311] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.048759] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.051232] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.053679] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.056210] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.058684] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.061192] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.063686] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.066136] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.068574] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.071014] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.073453] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.075900] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.078342] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.080778] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.083305] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.085752] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.088190] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.090632] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.093069] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.095515] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.095520] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   34.095525] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   34.095584] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   34.095588] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   34.108234] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   34.108237] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   34.108383] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   34.108426] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   34.108441] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   34.108445] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.108448] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   34.108451] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   34.108455] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   34.108458] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   34.108461] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   34.108464] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   34.108468] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   34.108471] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   34.108474] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   34.108477] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   34.108480] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   34.433176] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   34.433180] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   34.433190] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   34.433193] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   34.433195] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   34.433197] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   34.434087] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   34.435251] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   34.436178] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   34.436185] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   34.436190] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   34.436667] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   34.436671] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   34.436676] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   34.443896] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   34.443899] [drm:intel_crt_detect] CRT not detected via hotplug
>[   34.444053] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   34.444056] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   34.444200] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   34.444204] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   34.444206] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   34.444207] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   34.444756] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   34.444758] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   34.444759] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   34.444763] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   34.444802] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   34.444805] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   34.447270] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.449723] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.452175] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.454628] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.457075] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.459528] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.461976] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.464423] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.466919] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.469359] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.471808] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.474251] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.476689] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.479133] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.481573] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.484011] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.486450] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.488887] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.491327] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.493763] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.496200] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.498662] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.501108] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.503566] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.506019] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.508467] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.510918] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.513363] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.515822] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.518306] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.520779] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.523257] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   34.523267] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   34.523271] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   34.523321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   34.523325] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   34.536151] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   34.536154] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   34.536306] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   34.536349] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   34.536363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   34.536367] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   34.536370] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   34.536372] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   34.536375] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   34.536378] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   34.536381] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   34.536384] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   34.536387] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   34.536390] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   34.536393] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   34.536395] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   34.536398] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   37.674815] [drm:edp_panel_vdd_off_sync] Turning eDP port B VDD off
>[   37.674820] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   39.509106] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   39.509119] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   39.509131] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   39.509141] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   39.509151] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   39.509161] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   48.634637] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   48.634649] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   48.634661] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   48.634670] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   48.634680] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   48.634690] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   57.776913] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   57.776925] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   57.776937] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   57.776946] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   57.776956] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   57.776965] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   65.567963] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[   65.567973] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   66.766522] [drm:i915_gem_open] 
>[   66.856692] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[   66.861441] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[   66.878683] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   66.878694] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   66.878704] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   66.878712] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   66.878721] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   66.878730] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   69.375199] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   69.375203] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   69.375210] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   69.375214] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   69.375215] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   69.375217] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   69.375224] [drm:edp_panel_vdd_on] Turning eDP port B VDD on
>[   69.375228] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   69.376096] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   69.376947] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   69.377844] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   69.377849] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   69.377853] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   69.378290] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   69.378293] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   69.378298] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   69.384181] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   69.384183] [drm:intel_crt_detect] CRT not detected via hotplug
>[   69.384337] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   69.384339] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   69.384489] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   69.384492] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   69.384493] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   69.384495] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   69.385089] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   69.385091] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   69.385092] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   69.385095] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   69.385135] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   69.385137] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   69.387762] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.390201] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.392647] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.395111] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.397549] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.400045] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.402485] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.404934] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.407379] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.409831] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.412280] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.414720] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.417156] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.419617] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.422054] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.424599] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.427138] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.429578] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.432100] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.434537] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.437007] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.439451] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.441891] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.444338] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.446778] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.449769] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.452237] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.454686] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.457123] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.459805] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.462273] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.466200] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   69.466212] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   69.466216] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   69.466274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   69.466278] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   69.479178] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   69.479181] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   69.479329] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   69.479370] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   69.479384] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   69.479388] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   69.479391] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   69.479394] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   69.479397] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   69.479400] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   69.479403] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   69.479406] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   69.479409] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   69.479412] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   69.479414] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   69.479417] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   69.479420] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   69.674242] [drm:i915_gem_open] 
>[   69.697154] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[   69.699714] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[   69.736927] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-1] checking for sink bpp constrains
>[   69.736930] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 24
>[   69.736934] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[   69.736935] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[   69.736938] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[   69.736941] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff992b730b5000 for pipe B
>[   69.736943] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   69.736944] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   69.736946] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   69.736948] [drm:intel_dump_pipe_config] dp: 0, lanes: 4, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   69.736950] [drm:intel_dump_pipe_config] dp: 0, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   69.736951] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   69.736952] [drm:intel_dump_pipe_config] requested mode:
>[   69.736955] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x0 0x9
>[   69.736956] [drm:intel_dump_pipe_config] adjusted mode:
>[   69.736959] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x0 0x9
>[   69.736962] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x0 flags: 0x9
>[   69.736963] [drm:intel_dump_pipe_config] port clock: 154000
>[   69.736964] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   69.736966] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[   69.736968] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   69.736969] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   69.736970] [drm:intel_dump_pipe_config] ips: 0
>[   69.736971] [drm:intel_dump_pipe_config] double wide: 0
>[   69.736973] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xf0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[   69.736974] [drm:intel_dump_pipe_config] planes on this crtc
>[   69.736978] [drm:intel_dump_pipe_config] [PLANE:29:primary B] enabled
>[   69.736981] [drm:intel_dump_pipe_config] 	FB:54, fb = 3286x1200 format = XR24 little-endian (0x34325258)
>[   69.736983] [drm:intel_dump_pipe_config] 	scaler:0 src 1366x0+1920+1200 dst 0x0+1920+1200
>[   69.736985] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] enabled
>[   69.736987] [drm:intel_dump_pipe_config] 	FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[   69.736989] [drm:intel_dump_pipe_config] 	scaler:0 src 0x0+256+256 dst 270x596+256+256
>[   69.736991] [drm:intel_dump_pipe_config] [PLANE:32:sprite C] disabled, scaler_id = 0
>[   69.736993] [drm:intel_dump_pipe_config] [PLANE:33:sprite D] disabled, scaler_id = 0
>[   69.736996] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[   69.737037] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   69.742919] [drm:intel_disable_pipe] disabling pipe B
>[   69.761081] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[   69.761089] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=937, cursor=0 level=0 cxsr=1
>[   69.761092] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[   69.761097] [drm:verify_encoder_state] [ENCODER:35:CRT]
>[   69.761101] [drm:verify_encoder_state] [ENCODER:36:DP B]
>[   69.761103] [drm:verify_encoder_state] [ENCODER:44:DP C]
>[   69.761105] [drm:verify_encoder_state] [ENCODER:46:HDMI C]
>[   69.761107] [drm:intel_connector_verify_state] [CONNECTOR:34:VGA-1]
>[   69.761110] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[   69.761117] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-1]
>[   69.761120] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   69.762061] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   69.762067] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=425, cursor=0, sprite0=0, sprite1=0, SR: plane=937, cursor=0 level=0 cxsr=1
>[   69.763022] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   69.763030] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=425, cursor=63, sprite0=0, sprite1=0, SR: plane=937, cursor=0 level=0 cxsr=1
>[   69.763175] [drm:drm_mode_addfb2] [FB:74]
>[   69.766502] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   69.766509] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   69.799907] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[   69.799933] [drm:verify_encoder_state] [ENCODER:35:CRT]
>[   69.799938] [drm:verify_encoder_state] [ENCODER:36:DP B]
>[   69.799939] [drm:verify_encoder_state] [ENCODER:44:DP C]
>[   69.799942] [drm:verify_encoder_state] [ENCODER:46:HDMI C]
>[   69.799946] [drm:intel_connector_verify_state] [CONNECTOR:34:VGA-1]
>[   69.799948] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[   69.799950] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-1]
>[   69.799956] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[   69.801074] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   69.801082] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=425, cursor=0, sprite0=0, sprite1=0, SR: plane=937, cursor=0 level=0 cxsr=1
>[   69.816551] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   69.816560] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-1]
>[   69.816581] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-1] checking for sink bpp constrains
>[   69.816583] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 24
>[   69.816585] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[   69.816587] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[   69.816589] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[   69.816592] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff992b770fb800 for pipe A
>[   69.816594] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   69.816595] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   69.816597] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   69.816599] [drm:intel_dump_pipe_config] dp: 0, lanes: 4, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   69.816601] [drm:intel_dump_pipe_config] dp: 0, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   69.816602] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   69.816603] [drm:intel_dump_pipe_config] requested mode:
>[   69.816606] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x0 0x9
>[   69.816607] [drm:intel_dump_pipe_config] adjusted mode:
>[   69.816610] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x0 0x9
>[   69.816613] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x0 flags: 0x9
>[   69.816614] [drm:intel_dump_pipe_config] port clock: 154000
>[   69.816615] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   69.816617] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[   69.816619] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   69.816620] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   69.816621] [drm:intel_dump_pipe_config] ips: 0
>[   69.816622] [drm:intel_dump_pipe_config] double wide: 0
>[   69.816624] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xf0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[   69.816625] [drm:intel_dump_pipe_config] planes on this crtc
>[   69.816627] [drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[   69.816631] [drm:intel_dump_pipe_config] 	FB:74, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[   69.816633] [drm:intel_dump_pipe_config] 	scaler:0 src 0x0+1366+768 dst 0x0+1366+768
>[   69.816634] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   69.816637] [drm:intel_dump_pipe_config] 	FB:54, fb = 256x256 format = AR24 little-endian (0x34325241)
>[   69.816639] [drm:intel_dump_pipe_config] 	scaler:0 src 0x0+8+172 dst 1358x596+8+172
>[   69.816641] [drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[   69.816642] [drm:intel_dump_pipe_config] [PLANE:28:sprite B] disabled, scaler_id = 0
>[   69.816645] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[   69.816691] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   69.833278] [drm:intel_edp_backlight_off] 
>[   70.038897] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   70.039339] [drm:edp_panel_off] Turn eDP port B panel power off
>[   70.039342] [drm:wait_panel_off] Wait for panel power off time
>[   70.039348] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   70.078727] [drm:wait_panel_status] Wait complete
>[   70.078741] [drm:intel_disable_pipe] disabling pipe A
>[   70.084851] [drm:intel_dp_link_down] 
>[   70.146757] [drm:verify_encoder_state] [ENCODER:35:CRT]
>[   70.146762] [drm:verify_encoder_state] [ENCODER:36:DP B]
>[   70.146765] [drm:verify_encoder_state] [ENCODER:44:DP C]
>[   70.146767] [drm:verify_encoder_state] [ENCODER:46:HDMI C]
>[   70.146769] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
>[   70.146771] [drm:intel_connector_verify_state] [CONNECTOR:34:VGA-1]
>[   70.146774] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[   70.149062] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   70.149068] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[   70.149070] [drm:intel_enable_pipe] enabling pipe A
>[   70.165807] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-1]
>[   70.165816] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[   70.199305] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   70.199310] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   70.199316] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   70.199319] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   70.199321] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   70.199323] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   70.199330] [drm:edp_panel_vdd_on] Turning eDP port B VDD on
>[   70.199332] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   70.675390] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   70.675395] [drm:wait_panel_status] Wait complete
>[   70.675399] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   70.675401] [drm:edp_panel_vdd_on] eDP port B panel power wasn't enabled
>[   70.884292] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   70.885149] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   70.886050] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   70.886058] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   70.886062] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   70.886565] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   70.886570] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   70.886575] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   70.892537] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   70.892539] [drm:intel_crt_detect] CRT not detected via hotplug
>[   70.892692] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   70.892694] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   70.892838] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   70.892841] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   70.892843] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   70.892844] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   70.893394] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   70.893396] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   70.893397] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   70.893400] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   70.893425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   70.893427] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   70.895874] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.898310] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.900755] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.903196] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.905636] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.908078] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.910519] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.912963] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.915422] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.917858] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.920303] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.922756] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.925210] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.927662] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.930108] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.932558] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.935009] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.937446] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.939888] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.942326] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.944773] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.947224] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.949672] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.952122] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.954570] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.957023] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.959489] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.961927] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.964369] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.966806] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.969249] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.971695] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   70.971700] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   70.971704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   70.971752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   70.971756] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   70.985529] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   70.985532] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   70.985678] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   70.985720] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   70.985735] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   70.985740] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   70.985743] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   70.985746] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   70.985750] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   70.985753] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   70.985756] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   70.985759] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   70.985762] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   70.985766] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   70.985769] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   70.985772] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   70.985775] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   70.997244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   70.997249] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   70.997258] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   70.997262] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   70.997264] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   70.997266] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   70.998753] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   71.001358] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   71.002290] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.002297] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   71.002301] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   71.002898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   71.002902] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   71.002908] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   71.009235] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   71.009238] [drm:intel_crt_detect] CRT not detected via hotplug
>[   71.009392] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.009393] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   71.009538] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.009541] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.009543] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   71.009545] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   71.010095] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.010097] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   71.010098] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   71.010101] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   71.010142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   71.010145] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   71.012666] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.015110] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.017548] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.020132] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.022602] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.026297] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.028757] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.031198] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.033637] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.036077] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.038514] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.041038] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.043648] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.046114] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.048567] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.051006] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.053442] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.055883] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.058318] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.060756] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.063196] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.065635] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.068073] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.070509] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.072953] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.075394] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.077831] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.080272] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.082710] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.085155] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.087608] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.090059] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.090063] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   71.090067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   71.090118] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   71.090122] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   71.104922] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.104931] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   71.105246] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.105289] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.105305] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   71.105310] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   71.105313] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   71.105316] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   71.105319] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   71.105323] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   71.105326] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   71.105329] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   71.105332] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   71.105335] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   71.105339] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   71.105342] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   71.105345] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   71.120963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   71.120967] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   71.120974] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   71.120977] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   71.120980] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   71.120982] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   71.121864] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   71.122718] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   71.123620] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.123626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   71.123630] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   71.124007] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   71.124010] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   71.124014] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   71.130986] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   71.130988] [drm:intel_crt_detect] CRT not detected via hotplug
>[   71.131139] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.131141] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   71.131286] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.131289] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.131290] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   71.131292] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   71.131841] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.131843] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   71.131845] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   71.131847] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   71.131876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   71.131878] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   71.134326] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.136772] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.139212] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.141650] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.144090] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.146530] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.148987] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.151431] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.153886] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.156341] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.158780] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.161227] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.163670] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.166109] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.168558] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.171006] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.173445] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.175887] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.178323] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.180771] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.183216] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.185653] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.188110] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.190551] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.192992] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.195435] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.197876] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.200321] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.202759] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.205205] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.207652] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.210100] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.210107] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   71.210112] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   71.210164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   71.210168] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   71.222763] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.222765] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   71.222912] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.222949] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.222962] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   71.222966] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   71.222969] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   71.222972] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   71.222974] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   71.222977] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   71.222980] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   71.222983] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   71.222986] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   71.222989] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   71.223021] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   71.223029] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   71.223037] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   71.224144] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   71.224148] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   71.224154] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   71.224157] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   71.224159] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   71.224161] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   71.225055] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   71.225908] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   71.226820] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.226826] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   71.226830] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   71.227191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   71.227194] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   71.227199] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   71.233046] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   71.233049] [drm:intel_crt_detect] CRT not detected via hotplug
>[   71.233202] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.233204] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   71.233348] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.233351] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.233353] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   71.233356] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   71.233905] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.233907] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   71.233908] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   71.233911] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   71.233947] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   71.233949] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   71.236401] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.238840] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.241289] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.243763] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.246251] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.248729] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.251185] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.253650] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.256090] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.258532] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.260998] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.263465] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.265924] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.268395] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.270841] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.273293] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.275738] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.278174] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.280618] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.283058] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.285498] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.287946] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.290385] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.292828] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.295281] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.297718] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.300162] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.302598] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.305047] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.307544] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.310020] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.315061] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.315073] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   71.315080] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   71.315134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   71.315137] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   71.327818] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.327820] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   71.327965] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.328000] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.328014] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   71.328018] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   71.328021] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   71.328024] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   71.328027] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   71.328030] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   71.328033] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   71.328036] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   71.328039] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   71.328042] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   71.328044] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   71.328047] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   71.328050] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   71.335266] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   71.335274] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=903, cursor=0 level=0 cxsr=1
>[   71.335277] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[   71.444108] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   71.444113] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   71.444120] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   71.444123] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   71.444125] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   71.444127] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   71.445049] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   71.446152] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   71.449145] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.449152] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   71.449157] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   71.449494] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   71.449497] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   71.449503] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   71.455153] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   71.455156] [drm:intel_crt_detect] CRT not detected via hotplug
>[   71.457310] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.457314] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   71.457479] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   71.457484] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.457486] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   71.457489] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   71.458651] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   71.458657] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   71.458659] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   71.458664] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   71.458709] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   71.458711] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   71.461237] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.463986] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.466749] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.470295] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.473478] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.476344] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.479053] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.483121] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.485848] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.488465] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.491409] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.493926] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.497454] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.500588] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.503294] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.505821] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.509049] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.511562] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.515302] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.517803] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.520602] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.523837] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.528057] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.530849] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.533728] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.536524] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.541099] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.544194] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.549148] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.557383] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.559903] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.562665] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   71.562677] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   71.562681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   71.562732] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   71.562736] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   71.577023] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.577028] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   71.579733] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   71.579775] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.579788] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   71.579793] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   71.579796] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   71.579799] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   71.579801] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   71.579805] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   71.579807] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   71.579810] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   71.579813] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   71.579816] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   71.579819] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   71.579822] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   71.579825] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   71.594305] [drm:i915_gem_open] 
>[   71.755581] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[   71.823652] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[   73.225591] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   73.225595] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   73.225602] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   73.225605] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   73.225607] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   73.225609] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   73.226629] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   73.228216] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   73.231788] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   73.231796] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   73.231801] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   73.232124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   73.232127] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   73.232131] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   73.237748] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   73.237751] [drm:intel_crt_detect] CRT not detected via hotplug
>[   73.237909] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   73.237910] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   73.238062] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   73.238065] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   73.238067] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   73.238069] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   73.238618] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   73.238620] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   73.238621] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   73.238624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   73.238656] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   73.238659] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   73.241156] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.243607] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.246053] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.248600] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.251929] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.255206] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.257704] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.260242] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.263731] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.266180] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.268618] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.271058] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.273503] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.275944] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.278380] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.280827] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.283323] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.285770] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.288213] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.290659] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.293158] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.295618] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.298065] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.300523] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.302967] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.305413] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.307864] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.310311] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.312780] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.315229] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.317682] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.320137] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.320142] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   73.320146] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   73.320206] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   73.320211] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   73.332798] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   73.332801] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   73.332948] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   73.332986] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   73.333001] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   73.333005] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   73.333008] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   73.333011] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   73.333014] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   73.333017] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   73.333020] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   73.333022] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   73.333025] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   73.333028] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   73.333031] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   73.333034] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   73.333037] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   73.504687] [drm:i915_gem_open] 
>[   73.524591] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[   73.529983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   73.529987] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   73.529994] [drm:intel_dp_long_pulse] Display Port TPS3 support: source no, sink no
>[   73.529997] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[   73.529999] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[   73.530000] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[   73.530882] [drm:intel_dp_probe_oui] Sink OUI: 00e04c
>[   73.531759] [drm:intel_dp_probe_oui] Branch OUI: 00e04c
>[   73.532689] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   73.532695] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   73.532700] [drm:drm_mode_debug_printmodeline] Modeline 38:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[   73.533003] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1]
>[   73.533006] [drm:intel_crt_detect] [CONNECTOR:34:VGA-1] force=1
>[   73.533039] [drm:valleyview_crt_detect_hotplug] trigger hotplug detect cycle: adpa=0xf40000
>[   73.539006] [drm:valleyview_crt_detect_hotplug] valleyview hotplug adpa=0xf40000, result 0
>[   73.539011] [drm:intel_crt_detect] CRT not detected via hotplug
>[   73.539180] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   73.539182] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK on first message, retry
>[   73.539346] [drm:do_gmbus_xfer] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
>[   73.539352] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   73.539354] [drm:intel_crt_get_edid] CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   73.539356] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus vga. force bit now 1
>[   73.540052] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
>[   73.540056] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus vga. force bit now 0
>[   73.540058] [drm:intel_crt_detect_ddc] CRT not detected via DDC:0x50 [no valid EDID found]
>[   73.540061] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:34:VGA-1] disconnected
>[   73.540108] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
>[   73.540110] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
>[   73.542727] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.546153] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.548712] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.551179] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.553985] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.556467] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.558919] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.561369] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.563818] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.566263] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.568727] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.571190] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.573708] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.576165] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.578612] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.581467] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.583956] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.586412] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.588873] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.591334] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.593808] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.596264] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.598710] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.601157] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.603623] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.606088] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.608553] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.611007] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.613456] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.615903] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.618414] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.621401] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[   73.621413] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[   73.621418] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] disconnected
>[   73.621476] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1]
>[   73.621481] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-1]
>[   73.634909] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   73.634912] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   73.635066] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   73.635109] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   73.635123] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:HDMI-A-1] probed modes :
>[   73.635127] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   73.635130] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   73.635133] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   73.635136] [drm:drm_mode_debug_printmodeline] Modeline 56:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   73.635139] [drm:drm_mode_debug_printmodeline] Modeline 64:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[   73.635142] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   73.635145] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   73.635148] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   73.635151] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   73.635154] [drm:drm_mode_debug_printmodeline] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   73.635157] [drm:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   73.635160] [drm:drm_mode_debug_printmodeline] Modeline 62:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   76.004798] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   76.004811] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   76.004823] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   76.004832] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   76.004841] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   76.004850] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   76.596370] [drm:edp_panel_vdd_off_sync] Turning eDP port B VDD off
>[   76.596378] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
>[   81.873839] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   81.873849] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=903, cursor=0 level=0 cxsr=1
>[   82.919518] [drm:drm_mode_addfb2] [FB:80]
>[   82.988442] [drm:drm_mode_addfb2] [FB:74]
>[   83.141232] [drm:drm_mode_addfb2] [FB:80]
>[   83.304516] [drm:drm_mode_addfb2] [FB:74]
>[   83.372132] [drm:drm_mode_addfb2] [FB:80]
>[   83.406716] [drm:drm_mode_addfb2] [FB:74]
>[   83.415304] [drm:drm_mode_addfb2] [FB:80]
>[   83.473698] [drm:drm_mode_addfb2] [FB:74]
>[   83.480258] [drm:drm_mode_addfb2] [FB:81]
>[   83.496947] [drm:drm_mode_addfb2] [FB:80]
>[   83.513621] [drm:drm_mode_addfb2] [FB:74]
>[   83.530293] [drm:drm_mode_addfb2] [FB:81]
>[   83.547004] [drm:drm_mode_addfb2] [FB:80]
>[   83.563850] [drm:drm_mode_addfb2] [FB:74]
>[   83.580377] [drm:drm_mode_addfb2] [FB:81]
>[   83.597086] [drm:drm_mode_addfb2] [FB:80]
>[   83.613749] [drm:drm_mode_addfb2] [FB:74]
>[   83.630404] [drm:drm_mode_addfb2] [FB:81]
>[   83.647129] [drm:drm_mode_addfb2] [FB:80]
>[   83.663813] [drm:drm_mode_addfb2] [FB:74]
>[   83.680773] [drm:drm_mode_addfb2] [FB:81]
>[   83.697333] [drm:drm_mode_addfb2] [FB:80]
>[   83.713851] [drm:drm_mode_addfb2] [FB:74]
>[   83.730632] [drm:drm_mode_addfb2] [FB:81]
>[   83.747334] [drm:drm_mode_addfb2] [FB:80]
>[   84.024484] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.024507] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.032487] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.032512] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.040481] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.040503] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.048498] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.048522] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.056473] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.056496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.064494] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.064518] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.072495] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.072520] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.080493] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.080517] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.088496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.088520] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.096496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.096520] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.104488] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.104513] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.112496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.112521] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.136496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.136519] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.144568] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.144593] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.152627] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.152654] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.161799] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.161824] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.168457] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.168482] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.171975] [drm:drm_mode_addfb2] [FB:74]
>[   84.176518] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.176534] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.184506] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.184529] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.187474] [drm:drm_mode_addfb2] [FB:80]
>[   84.192523] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.192538] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.316249] [drm:drm_mode_addfb2] [FB:74]
>[   84.320463] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.320477] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.368509] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.368533] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.380032] [drm:drm_mode_addfb2] [FB:80]
>[   84.472617] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.472643] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.480624] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.480648] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.488626] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.488651] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.496624] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.496649] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.504630] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.504655] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.520628] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.520654] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.528618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.528723] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.536649] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.536673] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.544640] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.544664] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.552630] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.552654] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.640668] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.640693] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.644788] [drm:drm_mode_addfb2] [FB:74]
>[   84.704613] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.704634] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.716464] [drm:drm_mode_addfb2] [FB:80]
>[   84.743493] [drm:drm_mode_addfb2] [FB:74]
>[   84.762680] [drm:drm_mode_addfb2] [FB:80]
>[   84.800597] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.800620] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.808601] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.808624] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.816613] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.816637] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.824689] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.824712] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.832641] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.832669] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.856602] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.856626] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.864636] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.864659] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.872946] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.873006] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.880781] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.880806] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.888735] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.888834] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.896713] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.896741] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.904693] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.904718] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.912722] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.912745] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.928693] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.928716] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.936702] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.936732] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.944709] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.944733] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.952710] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   84.952734] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.112780] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.112809] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.120797] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.120827] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.128879] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.128904] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.131274] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   85.131286] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   85.131297] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   85.131306] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   85.131315] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   85.131324] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   85.136910] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.136934] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.144728] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.144752] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.153351] [drm:drm_mode_addfb2] [FB:74]
>[   85.160775] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.160790] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.168714] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.168741] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.168956] [drm:drm_mode_addfb2] [FB:80]
>[   85.176754] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.176768] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.184741] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.184764] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.192759] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.192782] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.200812] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.200837] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.208766] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.208790] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.216789] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.216814] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.232771] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.232804] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.240771] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.240794] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.248768] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.248792] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.256769] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.256791] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.264788] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.264811] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.268516] [drm:drm_mode_addfb2] [FB:74]
>[   85.312784] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.312806] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.324475] [drm:drm_mode_addfb2] [FB:80]
>[   85.384849] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.384872] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.392864] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.392897] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.400895] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.400926] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.408830] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.408855] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.448849] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.449098] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.456929] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.456993] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.464808] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.464835] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.472842] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.472866] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.480836] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.480861] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.616897] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.616920] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.625949] [drm:drm_mode_addfb2] [FB:74]
>[   85.647676] [drm:drm_mode_addfb2] [FB:80]
>[   85.657971] [drm:drm_mode_addfb2] [FB:74]
>[   85.665396] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.665413] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.673075] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.673099] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.675369] [drm:drm_mode_addfb2] [FB:80]
>[   85.680926] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.680941] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.688923] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.688947] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.691942] [drm:drm_mode_addfb2] [FB:74]
>[   85.709046] [drm:drm_mode_addfb2] [FB:80]
>[   85.725769] [drm:drm_mode_addfb2] [FB:74]
>[   85.752930] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.752955] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.760930] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.760954] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.768943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.768967] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.777116] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.777152] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.784950] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.784974] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.792890] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.792912] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.800892] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.800915] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.841431] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.841456] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.848858] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.848881] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.856823] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.856847] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.864840] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.864862] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.872822] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.872845] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.884647] [drm:drm_mode_addfb2] [FB:80]
>[   85.888850] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.888863] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.928927] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.928949] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.932365] [drm:drm_mode_addfb2] [FB:74]
>[   85.936981] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.936997] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   85.954591] [drm:drm_mode_addfb2] [FB:80]
>[   86.000831] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.000852] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.016850] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.016871] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.024859] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.024881] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.032923] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.032947] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.044633] [drm:drm_mode_addfb2] [FB:74]
>[   86.055458] [drm:drm_mode_addfb2] [FB:80]
>[   86.071411] [drm:drm_mode_addfb2] [FB:74]
>[   86.088067] [drm:drm_mode_addfb2] [FB:80]
>[   86.088926] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.088940] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.096981] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.096996] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.104952] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.104981] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.105189] [drm:drm_mode_addfb2] [FB:74]
>[   86.112957] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.112971] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.120968] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.120994] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.121825] [drm:drm_mode_addfb2] [FB:80]
>[   86.152510] [drm:drm_mode_addfb2] [FB:74]
>[   86.160952] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.160966] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.168307] [drm:drm_mode_addfb2] [FB:80]
>[   86.168932] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.168945] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.176992] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.177007] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.188435] [drm:drm_mode_addfb2] [FB:74]
>[   86.232923] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.232946] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.236613] [drm:drm_mode_addfb2] [FB:80]
>[   86.240931] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.240943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.257525] [drm:drm_mode_addfb2] [FB:74]
>[   86.277395] [drm:drm_mode_addfb2] [FB:80]
>[   86.294382] [drm:drm_mode_addfb2] [FB:74]
>[   86.308144] [drm:drm_mode_addfb2] [FB:80]
>[   86.313051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.313066] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.321112] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.321139] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.321952] [drm:drm_mode_addfb2] [FB:74]
>[   86.329030] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.329043] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.337065] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.337090] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.339300] [drm:drm_mode_addfb2] [FB:80]
>[   86.355438] [drm:drm_mode_addfb2] [FB:74]
>[   86.370899] [drm:drm_mode_addfb2] [FB:80]
>[   86.387674] [drm:drm_mode_addfb2] [FB:74]
>[   86.393039] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.393054] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.401028] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.401050] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.409017] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.409039] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.417025] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.417048] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.425035] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.425057] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.433044] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.433067] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.457048] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.457072] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.465028] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.465050] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.473051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.473076] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.481032] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.481054] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.497046] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.497068] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.500961] [drm:drm_mode_addfb2] [FB:80]
>[   86.537030] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.537052] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.548534] [drm:drm_mode_addfb2] [FB:74]
>[   86.553089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.553102] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.570050] [drm:drm_mode_addfb2] [FB:80]
>[   86.588998] [drm:drm_mode_addfb2] [FB:74]
>[   86.601012] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.601033] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.602345] [drm:drm_mode_addfb2] [FB:80]
>[   86.617145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.617166] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.617282] [drm:drm_mode_addfb2] [FB:81]
>[   86.625108] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.625123] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.633229] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.633247] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.633815] [drm:drm_mode_addfb2] [FB:74]
>[   86.650610] [drm:drm_mode_addfb2] [FB:80]
>[   86.667124] [drm:drm_mode_addfb2] [FB:81]
>[   86.681056] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.681071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.689135] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.689158] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.697110] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.697133] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.705133] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.705156] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.713126] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.713148] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.721121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.721144] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.729135] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.729158] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.737134] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.737158] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.745163] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.745185] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.753134] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.753157] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.761124] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.761147] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.769147] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.769170] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.777120] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.777142] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.785145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.785169] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.793151] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   86.793173] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   87.153148] [drm:drm_mode_addfb2] [FB:74]
>[   87.169047] [drm:drm_mode_addfb2] [FB:80]
>[   88.152924] [drm:drm_mode_addfb2] [FB:74]
>[   88.169075] [drm:drm_mode_addfb2] [FB:80]
>[   88.527562] [drm:drm_mode_addfb2] [FB:74]
>[   88.555060] [drm:drm_mode_addfb2] [FB:80]
>[   88.569130] [drm:drm_mode_addfb2] [FB:81]
>[   88.586427] [drm:drm_mode_addfb2] [FB:74]
>[   88.602455] [drm:drm_mode_addfb2] [FB:80]
>[   88.619156] [drm:drm_mode_addfb2] [FB:81]
>[   88.635827] [drm:drm_mode_addfb2] [FB:74]
>[   89.160699] [drm:drm_mode_addfb2] [FB:80]
>[   89.173214] [drm:drm_mode_addfb2] [FB:74]
>[   90.057933] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.057955] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.081961] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.081984] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.153431] [drm:drm_mode_addfb2] [FB:80]
>[   90.170818] [drm:drm_mode_addfb2] [FB:81]
>[   90.394065] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.394089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.402020] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.402053] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.409981] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.410006] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.417977] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.418001] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.425974] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.425997] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.433961] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.433984] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.554117] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.554139] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.690118] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.690141] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.698165] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.698189] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.706186] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.706210] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.714183] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.714206] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.722185] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.722209] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.770165] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.770188] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.778170] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.778193] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.786179] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.786202] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.794191] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.794215] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.802183] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.802206] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.866172] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.866194] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.874175] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.874197] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.994244] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   90.994267] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.002238] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.002261] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.010229] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.010251] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.082214] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.082235] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.090305] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.090328] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.098257] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.098280] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.106266] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.106288] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.114243] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.114265] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.122247] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.122271] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.130257] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.130280] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.154508] [drm:drm_mode_addfb2] [FB:74]
>[   91.171959] [drm:drm_mode_addfb2] [FB:80]
>[   91.522301] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.522334] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.578240] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.578263] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   91.729670] [drm:drm_mode_addfb2] [FB:74]
>[   91.746672] [drm:drm_mode_addfb2] [FB:80]
>[   91.763556] [drm:drm_mode_addfb2] [FB:74]
>[   91.780519] [drm:drm_mode_addfb2] [FB:80]
>[   92.154140] [drm:drm_mode_addfb2] [FB:74]
>[   92.173040] [drm:drm_mode_addfb2] [FB:81]
>[   92.606476] [drm:drm_mode_addfb2] [FB:74]
>[   92.623541] [drm:drm_mode_addfb2] [FB:80]
>[   92.640682] [drm:drm_mode_addfb2] [FB:74]
>[   92.658034] [drm:drm_mode_addfb2] [FB:80]
>[   92.674064] [drm:drm_mode_addfb2] [FB:74]
>[   92.690623] [drm:drm_mode_addfb2] [FB:80]
>[   92.754631] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.754654] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.758610] [drm:drm_mode_addfb2] [FB:74]
>[   92.846116] [drm:drm_mode_addfb2] [FB:80]
>[   92.850603] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.850618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.862319] [drm:drm_mode_addfb2] [FB:74]
>[   92.886429] [drm:drm_mode_addfb2] [FB:80]
>[   92.902668] [drm:drm_mode_addfb2] [FB:74]
>[   92.915938] [drm:drm_mode_addfb2] [FB:80]
>[   92.922605] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.922618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.929918] [drm:drm_mode_addfb2] [FB:74]
>[   92.930704] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.930716] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.938702] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.938719] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.949788] [drm:drm_mode_addfb2] [FB:80]
>[   92.964046] [drm:drm_mode_addfb2] [FB:74]
>[   92.980848] [drm:drm_mode_addfb2] [FB:80]
>[   92.986687] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.986700] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.994665] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.994685] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   92.997006] [drm:drm_mode_addfb2] [FB:74]
>[   93.002678] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.002691] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.010686] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.010708] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.013385] [drm:drm_mode_addfb2] [FB:80]
>[   93.018690] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.018703] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.026679] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.026702] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.042671] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.042694] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.050701] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.050726] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.058687] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.058711] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.066640] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.066665] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.074710] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.074733] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.155357] [drm:drm_mode_addfb2] [FB:74]
>[   93.174137] [drm:drm_mode_addfb2] [FB:81]
>[   93.194823] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.194845] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.202748] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.202771] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.210749] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.210773] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.234756] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.234778] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.242737] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.242759] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.250745] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.250767] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.258755] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.258779] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.282775] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.282800] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.290765] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.290787] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.298754] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.298776] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.322783] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.322806] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.326616] [drm:drm_mode_addfb2] [FB:74]
>[   93.354714] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.354738] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.366287] [drm:drm_mode_addfb2] [FB:80]
>[   93.426804] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.426826] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.434824] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.434847] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.442833] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.442856] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.450805] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.450827] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.458826] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.458857] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.482771] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.482792] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.490793] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.490816] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.514922] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.514946] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.650881] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.650904] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.659030] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.659065] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.666866] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.666889] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.674867] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.674892] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.682855] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.682877] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.762887] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.762911] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.842868] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.842888] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.851481] [drm:drm_mode_addfb2] [FB:74]
>[   93.870867] [drm:drm_mode_addfb2] [FB:80]
>[   93.882120] [drm:drm_mode_addfb2] [FB:74]
>[   93.882922] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.882937] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.898551] [drm:drm_mode_addfb2] [FB:80]
>[   93.915283] [drm:drm_mode_addfb2] [FB:74]
>[   93.932811] [drm:drm_mode_addfb2] [FB:80]
>[   93.938957] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.938972] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   93.949401] [drm:drm_mode_addfb2] [FB:74]
>[   93.965537] [drm:drm_mode_addfb2] [FB:80]
>[   94.010934] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.010959] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.018924] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.018948] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.026949] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.026974] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.034929] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.034951] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.042949] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.042975] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.066899] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.066923] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.074909] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.074943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.082976] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.082999] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.090962] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.090985] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.098979] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.099004] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.154682] [drm:drm_mode_addfb2] [FB:74]
>[   94.171213] [drm:drm_mode_addfb2] [FB:80]
>[   94.253580] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[   94.253592] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[   94.253603] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[   94.253611] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[   94.253619] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[   94.253628] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[   94.258943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.258966] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.266941] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.266963] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.274957] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.274980] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.307046] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.307067] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.314965] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.314989] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.322954] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.322978] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.330935] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.330957] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.338943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.338964] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.346966] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.346991] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.371904] [drm:drm_mode_addfb2] [FB:74]
>[   94.390442] [drm:drm_mode_addfb2] [FB:80]
>[   94.395075] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.395100] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.403033] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.403058] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.407079] [drm:drm_mode_addfb2] [FB:74]
>[   94.418749] [drm:drm_mode_addfb2] [FB:80]
>[   94.434397] [drm:drm_mode_addfb2] [FB:74]
>[   94.451051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.451078] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.451760] [drm:drm_mode_addfb2] [FB:80]
>[   94.467954] [drm:drm_mode_addfb2] [FB:74]
>[   94.483824] [drm:drm_mode_addfb2] [FB:80]
>[   94.499054] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.499076] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.507041] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.507064] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.515013] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.515037] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.523106] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.523130] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.531093] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.531116] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.539061] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.539082] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.547039] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.547063] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.563089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.563113] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.571131] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.571155] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.579138] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.579163] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.587143] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.587167] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.619071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.619095] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.635836] [drm:drm_mode_addfb2] [FB:74]
>[   94.651089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.651113] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.655579] [drm:drm_mode_addfb2] [FB:80]
>[   94.673506] [drm:drm_mode_addfb2] [FB:74]
>[   94.675137] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.675151] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.683402] [drm:drm_mode_addfb2] [FB:80]
>[   94.700434] [drm:drm_mode_addfb2] [FB:74]
>[   94.715107] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.715128] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.717640] [drm:drm_mode_addfb2] [FB:80]
>[   94.734478] [drm:drm_mode_addfb2] [FB:74]
>[   94.750663] [drm:drm_mode_addfb2] [FB:80]
>[   94.779126] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.779149] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.787163] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.787198] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.835114] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.835145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.843069] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.843094] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.851111] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.851137] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.859067] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.859134] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.867136] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.867163] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.875220] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.875244] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.907168] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.907196] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   94.925166] [drm:drm_mode_addfb2] [FB:74]
>[   94.942646] [drm:drm_mode_addfb2] [FB:81]
>[   94.959423] [drm:drm_mode_addfb2] [FB:80]
>[   94.975998] [drm:drm_mode_addfb2] [FB:74]
>[   94.992690] [drm:drm_mode_addfb2] [FB:81]
>[   95.009385] [drm:drm_mode_addfb2] [FB:80]
>[   95.019122] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.019137] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.027198] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.027219] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.035225] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.035248] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.043108] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.043131] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.051175] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.051198] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.059129] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.059151] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.083095] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.083118] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.091267] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.091291] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.099152] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.099175] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.107165] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.107190] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.115458] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.115486] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.154433] [drm:drm_mode_addfb2] [FB:74]
>[   95.169725] [drm:drm_mode_addfb2] [FB:80]
>[   95.211171] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.211195] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.219215] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.219239] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.227206] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.227230] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.267231] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.267254] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.275231] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.275253] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.283241] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.283263] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.291235] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.291256] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.299240] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.299262] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.323234] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.323256] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.331265] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.331288] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.339266] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.339289] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.347247] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.347269] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.387280] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.387303] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.395869] [drm:drm_mode_addfb2] [FB:74]
>[   95.414136] [drm:drm_mode_addfb2] [FB:80]
>[   95.419355] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.419373] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.427280] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.427304] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.431221] [drm:drm_mode_addfb2] [FB:74]
>[   95.443400] [drm:drm_mode_addfb2] [FB:81]
>[   95.459936] [drm:drm_mode_addfb2] [FB:80]
>[   95.476654] [drm:drm_mode_addfb2] [FB:74]
>[   95.483303] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.483316] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.493244] [drm:drm_mode_addfb2] [FB:81]
>[   95.509918] [drm:drm_mode_addfb2] [FB:80]
>[   95.555214] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.555235] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.563346] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.563370] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.571337] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.571360] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.579338] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.579361] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.587371] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.587394] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.603346] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.603369] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.611349] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.611372] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.619368] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.619391] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.763429] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.763458] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.771389] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.771412] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.779395] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.779418] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.787381] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.787402] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.795398] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.795421] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.803393] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.803416] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.811454] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.811494] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.851361] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.851383] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.859406] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.859429] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.867391] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.867414] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.875385] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.875406] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.883400] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.883423] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.899402] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.899425] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.924286] [drm:drm_mode_addfb2] [FB:74]
>[   95.939430] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.939455] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.942425] [drm:drm_mode_addfb2] [FB:80]
>[   95.947458] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.947474] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.955551] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.955568] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   95.960490] [drm:drm_mode_addfb2] [FB:81]
>[   95.977249] [drm:drm_mode_addfb2] [FB:74]
>[   95.993772] [drm:drm_mode_addfb2] [FB:80]
>[   96.010597] [drm:drm_mode_addfb2] [FB:81]
>[   96.027266] [drm:drm_mode_addfb2] [FB:74]
>[   96.027357] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.027374] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.043888] [drm:drm_mode_addfb2] [FB:80]
>[   96.075405] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.075428] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.083410] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.083433] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.091395] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.091418] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.099532] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.099556] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.107452] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.107476] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.115485] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.115510] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.123453] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.123475] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.131483] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.131508] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.155171] [drm:drm_mode_addfb2] [FB:74]
>[   96.170656] [drm:drm_mode_addfb2] [FB:80]
>[   96.171456] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.171468] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.179460] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.179480] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.187468] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.187491] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.196014] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.196047] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.203481] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.203504] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.307543] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.307568] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.315543] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.315568] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.331432] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.331453] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.339469] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.339492] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.379477] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.379502] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.416426] [drm:drm_mode_addfb2] [FB:74]
>[   96.555622] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.555647] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.563601] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.563627] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.569921] [drm:drm_mode_addfb2] [FB:80]
>[   96.571508] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.571519] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.579503] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.579523] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.587503] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.587525] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.595520] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.595544] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.603524] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.603548] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.627496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.627518] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.631476] [drm:drm_mode_addfb2] [FB:74]
>[   96.707621] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.707644] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.711128] [drm:drm_mode_addfb2] [FB:80]
>[   96.715630] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.715644] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.732598] [drm:drm_mode_addfb2] [FB:74]
>[   96.751106] [drm:drm_mode_addfb2] [FB:80]
>[   96.765235] [drm:drm_mode_addfb2] [FB:74]
>[   96.779174] [drm:drm_mode_addfb2] [FB:80]
>[   96.779653] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.779666] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.787637] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.787651] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.798992] [drm:drm_mode_addfb2] [FB:74]
>[   96.813970] [drm:drm_mode_addfb2] [FB:80]
>[   96.830336] [drm:drm_mode_addfb2] [FB:74]
>[   96.846500] [drm:drm_mode_addfb2] [FB:80]
>[   96.851646] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.851660] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.859634] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.859648] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.863722] [drm:drm_mode_addfb2] [FB:74]
>[   96.867674] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.867689] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.875670] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.875685] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.880087] [drm:drm_mode_addfb2] [FB:80]
>[   96.907661] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.907683] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.915653] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.915675] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.923691] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.923715] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.931659] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.931682] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   96.943210] [drm:drm_mode_addfb2] [FB:74]
>[   97.003667] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.003689] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.007259] [drm:drm_mode_addfb2] [FB:80]
>[   97.067674] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.067700] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.075710] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.075735] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.131624] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.131647] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.139675] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.139697] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.147670] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.147694] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.155046] [drm:drm_mode_addfb2] [FB:74]
>[   97.155670] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.155683] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.170781] [drm:drm_mode_addfb2] [FB:80]
>[   97.203747] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.203770] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.208003] [drm:drm_mode_addfb2] [FB:74]
>[   97.275746] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.275769] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.288002] [drm:drm_mode_addfb2] [FB:80]
>[   97.347758] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.347779] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.355800] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.355831] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.411750] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.411971] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.419802] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.419826] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.427795] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.427817] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.435769] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.435791] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.475798] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.475821] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.483783] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.483813] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.491761] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.491784] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.499794] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.499818] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.507794] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.507817] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.511646] [drm:drm_mode_addfb2] [FB:74]
>[   97.603828] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.603850] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.615287] [drm:drm_mode_addfb2] [FB:80]
>[   97.627858] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.627873] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.636277] [drm:drm_mode_addfb2] [FB:74]
>[   97.656155] [drm:drm_mode_addfb2] [FB:80]
>[   97.672070] [drm:drm_mode_addfb2] [FB:74]
>[   97.683394] [drm:drm_mode_addfb2] [FB:80]
>[   97.683828] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.683841] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.691784] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.691797] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.703378] [drm:drm_mode_addfb2] [FB:74]
>[   97.718156] [drm:drm_mode_addfb2] [FB:80]
>[   97.734376] [drm:drm_mode_addfb2] [FB:74]
>[   97.750757] [drm:drm_mode_addfb2] [FB:80]
>[   97.767275] [drm:drm_mode_addfb2] [FB:74]
>[   97.771957] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.771970] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.779877] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.779900] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.784832] [drm:drm_mode_addfb2] [FB:80]
>[   97.787885] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.787896] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.795818] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.795837] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.843926] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.843950] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.851850] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.851875] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.859930] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.859953] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.867917] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.867941] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.879945] [drm:drm_mode_addfb2] [FB:74]
>[   97.947912] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.947934] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.951372] [drm:drm_mode_addfb2] [FB:80]
>[   97.955964] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.955980] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   97.972429] [drm:drm_mode_addfb2] [FB:74]
>[   97.990673] [drm:drm_mode_addfb2] [FB:80]
>[   98.004136] [drm:drm_mode_addfb2] [FB:74]
>[   98.011869] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.011884] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.017668] [drm:drm_mode_addfb2] [FB:80]
>[   98.019867] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.019878] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.027924] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.027938] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.036893] [drm:drm_mode_addfb2] [FB:74]
>[   98.051096] [drm:drm_mode_addfb2] [FB:80]
>[   98.068995] [drm:drm_mode_addfb2] [FB:74]
>[   98.084912] [drm:drm_mode_addfb2] [FB:80]
>[   98.091953] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.091967] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.100091] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.100126] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.101669] [drm:drm_mode_addfb2] [FB:74]
>[   98.107997] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.108013] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.115960] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.115979] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.123965] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.123988] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.131986] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.132008] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.155795] [drm:drm_mode_addfb2] [FB:80]
>[   98.171932] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.171956] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.172165] [drm:drm_mode_addfb2] [FB:74]
>[   98.179966] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.179987] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.188025] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.188049] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.195989] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.196196] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.207490] [drm:drm_mode_addfb2] [FB:80]
>[   98.268023] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.268046] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.280863] [drm:drm_mode_addfb2] [FB:74]
>[   98.308025] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.308049] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.317079] [drm:drm_mode_addfb2] [FB:80]
>[   98.332983] [drm:drm_mode_addfb2] [FB:74]
>[   98.340025] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.340039] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.346402] [drm:drm_mode_addfb2] [FB:81]
>[   98.348010] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.348021] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.356084] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.356103] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.366213] [drm:drm_mode_addfb2] [FB:74]
>[   98.380998] [drm:drm_mode_addfb2] [FB:80]
>[   98.398074] [drm:drm_mode_addfb2] [FB:74]
>[   98.414401] [drm:drm_mode_addfb2] [FB:80]
>[   98.420056] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.420071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.428051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.428066] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.431690] [drm:drm_mode_addfb2] [FB:74]
>[   98.436056] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.436071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.444054] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.444069] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.449206] [drm:drm_mode_addfb2] [FB:80]
>[   98.452053] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.452074] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.460010] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.460028] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.492080] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.492104] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.500076] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.500099] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.508098] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.508121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.516111] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.516141] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.527887] [drm:drm_mode_addfb2] [FB:74]
>[   98.628091] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.628113] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.639755] [drm:drm_mode_addfb2] [FB:80]
>[   98.660061] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.660086] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.672214] [drm:drm_mode_addfb2] [FB:74]
>[   98.690817] [drm:drm_mode_addfb2] [FB:80]
>[   98.692234] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.692247] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.700354] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.700380] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.700778] [drm:drm_mode_addfb2] [FB:74]
>[   98.708059] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.708076] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.716112] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.716138] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.717666] [drm:drm_mode_addfb2] [FB:80]
>[   98.734189] [drm:drm_mode_addfb2] [FB:74]
>[   98.751206] [drm:drm_mode_addfb2] [FB:80]
>[   98.767868] [drm:drm_mode_addfb2] [FB:74]
>[   98.780158] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.780177] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.788135] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.788158] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.796138] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.796160] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.804170] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.804193] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.812151] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.812174] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.844112] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.844133] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.852135] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.852158] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.860159] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.860183] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.868168] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.868191] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.871683] [drm:drm_mode_addfb2] [FB:80]
>[   98.932180] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.932208] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   98.944375] [drm:drm_mode_addfb2] [FB:74]
>[   99.156069] [drm:drm_mode_addfb2] [FB:80]
>[   99.172218] [drm:drm_mode_addfb2] [FB:74]
>[   99.204458] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.204489] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.208526] [drm:drm_mode_addfb2] [FB:80]
>[   99.228200] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.228224] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.232132] [drm:drm_mode_addfb2] [FB:74]
>[   99.260274] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.260297] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.272026] [drm:drm_mode_addfb2] [FB:80]
>[   99.295799] [drm:drm_mode_addfb2] [FB:74]
>[   99.312334] [drm:drm_mode_addfb2] [FB:80]
>[   99.326525] [drm:drm_mode_addfb2] [FB:74]
>[   99.332181] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.332200] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.340273] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.340300] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.340523] [drm:drm_mode_addfb2] [FB:80]
>[   99.348204] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.348223] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.362510] [drm:drm_mode_addfb2] [FB:74]
>[   99.375010] [drm:drm_mode_addfb2] [FB:80]
>[   99.391287] [drm:drm_mode_addfb2] [FB:74]
>[   99.407729] [drm:drm_mode_addfb2] [FB:80]
>[   99.424238] [drm:drm_mode_addfb2] [FB:74]
>[   99.428313] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.428326] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.436300] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.436320] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.441032] [drm:drm_mode_addfb2] [FB:80]
>[   99.444358] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.444378] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.452368] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.452395] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.460347] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.460372] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.508335] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.508359] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.524262] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.524288] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.532247] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.532271] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.540339] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.540364] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.548332] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.548355] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.551888] [drm:drm_mode_addfb2] [FB:74]
>[   99.628323] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.628343] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.631927] [drm:drm_mode_addfb2] [FB:80]
>[   99.656680] [drm:drm_mode_addfb2] [FB:74]
>[   99.672462] [drm:drm_mode_addfb2] [FB:80]
>[   99.686282] [drm:drm_mode_addfb2] [FB:74]
>[   99.699548] [drm:drm_mode_addfb2] [FB:80]
>[   99.700390] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.700406] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.708339] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.708353] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.716372] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.716397] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.719491] [drm:drm_mode_addfb2] [FB:74]
>[   99.724393] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.724406] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.732463] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.732489] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.733063] [drm:drm_mode_addfb2] [FB:80]
>[   99.749523] [drm:drm_mode_addfb2] [FB:74]
>[   99.766083] [drm:drm_mode_addfb2] [FB:80]
>[   99.782364] [drm:drm_mode_addfb2] [FB:74]
>[   99.798183] [drm:drm_mode_addfb2] [FB:80]
>[   99.815605] [drm:drm_mode_addfb2] [FB:74]
>[   99.820426] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.820442] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.828392] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.828407] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.836387] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.836406] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.844390] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.844413] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.852361] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.852386] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.860401] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.860424] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.908394] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.908415] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.924386] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.924411] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.932420] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.932443] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.940398] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.940421] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.948469] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.948492] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.956454] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.956482] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[   99.960209] [drm:drm_mode_addfb2] [FB:80]
>[  100.028476] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.028499] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.032363] [drm:drm_mode_addfb2] [FB:74]
>[  100.053984] [drm:drm_mode_addfb2] [FB:80]
>[  100.072920] [drm:drm_mode_addfb2] [FB:74]
>[  100.088702] [drm:drm_mode_addfb2] [FB:80]
>[  100.102812] [drm:drm_mode_addfb2] [FB:74]
>[  100.108461] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.108477] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.116601] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.116629] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.116870] [drm:drm_mode_addfb2] [FB:80]
>[  100.124490] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.124506] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.137296] [drm:drm_mode_addfb2] [FB:74]
>[  100.151663] [drm:drm_mode_addfb2] [FB:80]
>[  100.168159] [drm:drm_mode_addfb2] [FB:74]
>[  100.183058] [drm:drm_mode_addfb2] [FB:80]
>[  100.200231] [drm:drm_mode_addfb2] [FB:74]
>[  100.204487] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.204500] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.212572] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.212591] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.220505] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.220527] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.228474] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.228496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.236501] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.236525] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.244498] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.244522] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.252477] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.252500] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.260478] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.260500] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.268442] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.268465] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.316484] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.316504] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.332525] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.332549] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.340516] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.340538] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.348741] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.348772] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.356500] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.356532] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.364594] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.364625] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.376217] [drm:drm_mode_addfb2] [FB:80]
>[  100.444557] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.444580] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.448048] [drm:drm_mode_addfb2] [FB:74]
>[  100.452580] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.452595] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.469476] [drm:drm_mode_addfb2] [FB:80]
>[  100.487791] [drm:drm_mode_addfb2] [FB:74]
>[  100.503504] [drm:drm_mode_addfb2] [FB:80]
>[  100.520104] [drm:drm_mode_addfb2] [FB:74]
>[  100.532119] [drm:drm_mode_addfb2] [FB:81]
>[  100.540525] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.540539] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.548544] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.548622] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.548981] [drm:drm_mode_addfb2] [FB:80]
>[  100.556584] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.556600] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.564587] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.564603] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.567849] [drm:drm_mode_addfb2] [FB:74]
>[  100.582080] [drm:drm_mode_addfb2] [FB:81]
>[  100.598838] [drm:drm_mode_addfb2] [FB:74]
>[  100.615462] [drm:drm_mode_addfb2] [FB:80]
>[  100.632334] [drm:drm_mode_addfb2] [FB:74]
>[  100.644560] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.644575] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.649961] [drm:drm_mode_addfb2] [FB:80]
>[  100.652623] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.652636] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.660605] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.660620] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.668610] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.668630] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.676621] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.676645] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.716618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.716638] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.724626] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.724650] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.732631] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.732655] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.740674] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.740698] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.752195] [drm:drm_mode_addfb2] [FB:74]
>[  100.820680] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.820703] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.824647] [drm:drm_mode_addfb2] [FB:80]
>[  100.852670] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.852695] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.868995] [drm:drm_mode_addfb2] [FB:74]
>[  100.882931] [drm:drm_mode_addfb2] [FB:80]
>[  100.884585] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.884596] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.892598] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.892614] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.900596] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.900618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  100.902184] [drm:drm_mode_addfb2] [FB:74]
>[  100.916290] [drm:drm_mode_addfb2] [FB:80]
>[  100.933435] [drm:drm_mode_addfb2] [FB:74]
>[  100.950739] [drm:drm_mode_addfb2] [FB:81]
>[  100.967857] [drm:drm_mode_addfb2] [FB:74]
>[  100.984807] [drm:drm_mode_addfb2] [FB:80]
>[  101.010582] [drm:drm_mode_addfb2] [FB:74]
>[  101.116740] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.116764] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.124753] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.124776] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.132758] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.132782] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.139628] [drm:drm_mode_addfb2] [FB:80]
>[  101.140667] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.140694] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.148665] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.148681] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.156728] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.156753] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.156965] [drm:drm_mode_addfb2] [FB:74]
>[  101.172227] [drm:drm_mode_addfb2] [FB:80]
>[  101.204767] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.204787] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.209130] [drm:drm_mode_addfb2] [FB:74]
>[  101.268772] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.268796] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.272532] [drm:drm_mode_addfb2] [FB:80]
>[  101.300773] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.300797] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.304643] [drm:drm_mode_addfb2] [FB:74]
>[  101.328453] [drm:drm_mode_addfb2] [FB:80]
>[  101.345062] [drm:drm_mode_addfb2] [FB:74]
>[  101.358388] [drm:drm_mode_addfb2] [FB:80]
>[  101.364944] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.364958] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.372510] [drm:drm_mode_addfb2] [FB:74]
>[  101.372810] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.372823] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.380809] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.380824] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.392285] [drm:drm_mode_addfb2] [FB:80]
>[  101.406595] [drm:drm_mode_addfb2] [FB:74]
>[  101.423351] [drm:drm_mode_addfb2] [FB:80]
>[  101.439191] [drm:drm_mode_addfb2] [FB:74]
>[  101.455925] [drm:drm_mode_addfb2] [FB:80]
>[  101.460808] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.460821] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.468793] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.468813] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.472767] [drm:drm_mode_addfb2] [FB:74]
>[  101.476832] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.476847] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.484798] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.484818] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.492802] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.492824] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.564875] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.564899] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.572833] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.572857] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.580905] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.580928] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.588865] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.588890] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.596860] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.596885] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.608403] [drm:drm_mode_addfb2] [FB:80]
>[  101.692912] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.692937] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.697030] [drm:drm_mode_addfb2] [FB:74]
>[  101.700883] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.700902] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.717600] [drm:drm_mode_addfb2] [FB:80]
>[  101.736827] [drm:drm_mode_addfb2] [FB:74]
>[  101.750976] [drm:drm_mode_addfb2] [FB:80]
>[  101.764931] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.764948] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.766834] [drm:drm_mode_addfb2] [FB:81]
>[  101.772863] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.772876] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.780910] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.780926] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.784801] [drm:drm_mode_addfb2] [FB:74]
>[  101.800135] [drm:drm_mode_addfb2] [FB:80]
>[  101.816789] [drm:drm_mode_addfb2] [FB:81]
>[  101.833551] [drm:drm_mode_addfb2] [FB:74]
>[  101.850162] [drm:drm_mode_addfb2] [FB:80]
>[  101.866863] [drm:drm_mode_addfb2] [FB:81]
>[  101.884903] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.884923] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.892947] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.892971] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.900955] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.900978] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.908970] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.908996] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.916919] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.916943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.924926] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.924948] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.980974] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.980999] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.988940] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.988962] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.996987] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  101.997012] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.004985] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.005017] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.012988] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.013014] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.016716] [drm:drm_mode_addfb2] [FB:74]
>[  102.100979] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.101002] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.104543] [drm:drm_mode_addfb2] [FB:80]
>[  102.108991] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.109004] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.125599] [drm:drm_mode_addfb2] [FB:74]
>[  102.145499] [drm:drm_mode_addfb2] [FB:80]
>[  102.160595] [drm:drm_mode_addfb2] [FB:74]
>[  102.175590] [drm:drm_mode_addfb2] [FB:80]
>[  102.189089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.189116] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.189396] [drm:drm_mode_addfb2] [FB:74]
>[  102.197027] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.197043] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.209249] [drm:drm_mode_addfb2] [FB:80]
>[  102.212936] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.212950] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.223239] [drm:drm_mode_addfb2] [FB:74]
>[  102.239546] [drm:drm_mode_addfb2] [FB:80]
>[  102.255797] [drm:drm_mode_addfb2] [FB:74]
>[  102.272389] [drm:drm_mode_addfb2] [FB:80]
>[  102.289443] [drm:drm_mode_addfb2] [FB:74]
>[  102.305934] [drm:drm_mode_addfb2] [FB:80]
>[  102.317056] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.317302] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.325052] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.325075] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.333068] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.333091] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.341064] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.341089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.349071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.349095] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.357071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.357095] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.413051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.413075] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.420972] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.420997] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.428967] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.428989] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.437097] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.437121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.445054] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.445077] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.453047] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.453069] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.464631] [drm:drm_mode_addfb2] [FB:74]
>[  102.549120] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.549145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.557078] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.557103] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.561163] [drm:drm_mode_addfb2] [FB:80]
>[  102.586183] [drm:drm_mode_addfb2] [FB:74]
>[  102.602009] [drm:drm_mode_addfb2] [FB:80]
>[  102.620128] [drm:drm_mode_addfb2] [FB:74]
>[  102.634434] [drm:drm_mode_addfb2] [FB:81]
>[  102.637151] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.637168] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.645072] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.645088] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.651047] [drm:drm_mode_addfb2] [FB:80]
>[  102.653094] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.653110] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.661156] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.661171] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.667729] [drm:drm_mode_addfb2] [FB:74]
>[  102.669097] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.669108] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.684540] [drm:drm_mode_addfb2] [FB:81]
>[  102.701332] [drm:drm_mode_addfb2] [FB:80]
>[  102.717815] [drm:drm_mode_addfb2] [FB:74]
>[  102.734536] [drm:drm_mode_addfb2] [FB:81]
>[  102.751302] [drm:drm_mode_addfb2] [FB:80]
>[  102.781220] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.781245] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.789204] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.789229] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.797218] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.797241] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.805187] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.805212] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.813194] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.813219] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.821188] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.821213] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.829145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.829169] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.885201] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.885226] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.893237] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.893261] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.901239] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.901263] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.909241] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.909265] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.917201] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.917228] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  102.921656] [drm:drm_mode_addfb2] [FB:74]
>[  103.013205] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.013228] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.016710] [drm:drm_mode_addfb2] [FB:80]
>[  103.029246] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.029263] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.040633] [drm:drm_mode_addfb2] [FB:74]
>[  103.055940] [drm:drm_mode_addfb2] [FB:80]
>[  103.075597] [drm:drm_mode_addfb2] [FB:74]
>[  103.093608] [drm:drm_mode_addfb2] [FB:80]
>[  103.103989] [drm:drm_mode_addfb2] [FB:74]
>[  103.109331] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.109347] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.117328] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.117344] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.125204] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.125228] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.127451] [drm:drm_mode_addfb2] [FB:80]
>[  103.140567] [drm:drm_mode_addfb2] [FB:74]
>[  103.158441] [drm:drm_mode_addfb2] [FB:80]
>[  103.173709] [drm:drm_mode_addfb2] [FB:74]
>[  103.190660] [drm:drm_mode_addfb2] [FB:80]
>[  103.208033] [drm:drm_mode_addfb2] [FB:74]
>[  103.224414] [drm:drm_mode_addfb2] [FB:80]
>[  103.237234] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.237255] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.245290] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.245314] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.253311] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.253336] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.261303] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.261328] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.269300] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.269325] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.317321] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.317345] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.333328] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.333352] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.341330] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.341421] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.349332] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.349357] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.357319] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.357344] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.365338] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.365362] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.369681] [drm:drm_mode_addfb2] [FB:74]
>[  103.375880] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[  103.375891] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[  103.375902] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[  103.375911] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[  103.375919] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[  103.375928] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[  103.437355] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.437379] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.451223] [drm:drm_mode_addfb2] [FB:80]
>[  103.453328] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.453351] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.477338] [drm:drm_mode_addfb2] [FB:74]
>[  103.492226] [drm:drm_mode_addfb2] [FB:80]
>[  103.506007] [drm:drm_mode_addfb2] [FB:74]
>[  103.509315] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.509331] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.517298] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.517317] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.520192] [drm:drm_mode_addfb2] [FB:80]
>[  103.525380] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.525397] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.533371] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.533386] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.540912] [drm:drm_mode_addfb2] [FB:74]
>[  103.554360] [drm:drm_mode_addfb2] [FB:80]
>[  103.570620] [drm:drm_mode_addfb2] [FB:74]
>[  103.586437] [drm:drm_mode_addfb2] [FB:80]
>[  103.603736] [drm:drm_mode_addfb2] [FB:74]
>[  103.621017] [drm:drm_mode_addfb2] [FB:80]
>[  103.629401] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.629418] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.637334] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.637354] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.645399] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.645423] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.653407] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.653431] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.661411] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.661435] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.709404] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.709430] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.725426] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.725450] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.733421] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.733445] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.741421] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.741446] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.749416] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.749440] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.757365] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.757388] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.760990] [drm:drm_mode_addfb2] [FB:74]
>[  103.837447] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.837471] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.841360] [drm:drm_mode_addfb2] [FB:80]
>[  103.845450] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.845467] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.866128] [drm:drm_mode_addfb2] [FB:74]
>[  103.882313] [drm:drm_mode_addfb2] [FB:80]
>[  103.901032] [drm:drm_mode_addfb2] [FB:74]
>[  103.917411] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.917428] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.919022] [drm:drm_mode_addfb2] [FB:81]
>[  103.925461] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.925476] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.933431] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.933446] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  103.935755] [drm:drm_mode_addfb2] [FB:80]
>[  103.952474] [drm:drm_mode_addfb2] [FB:74]
>[  103.969163] [drm:drm_mode_addfb2] [FB:81]
>[  103.985846] [drm:drm_mode_addfb2] [FB:80]
>[  104.002514] [drm:drm_mode_addfb2] [FB:74]
>[  104.019374] [drm:drm_mode_addfb2] [FB:81]
>[  104.021533] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.021550] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.029531] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.029548] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.035956] [drm:drm_mode_addfb2] [FB:80]
>[  104.037496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.037512] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.045490] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.045506] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.053587] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.053613] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.109529] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.109557] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.117519] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.117543] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.125467] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.125490] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.133607] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.133631] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.141496] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.141520] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.149618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.149641] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.159594] [drm:drm_mode_addfb2] [FB:74]
>[  104.174729] [drm:drm_mode_addfb2] [FB:80]
>[  104.221544] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.221568] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.234739] [drm:drm_mode_addfb2] [FB:74]
>[  104.253550] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.253576] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.271618] [drm:drm_mode_addfb2] [FB:80]
>[  104.291550] [drm:drm_mode_addfb2] [FB:74]
>[  104.306204] [drm:drm_mode_addfb2] [FB:80]
>[  104.317449] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.317465] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.319762] [drm:drm_mode_addfb2] [FB:81]
>[  104.325573] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.325591] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.333575] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.333590] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.338568] [drm:drm_mode_addfb2] [FB:74]
>[  104.353504] [drm:drm_mode_addfb2] [FB:80]
>[  104.370271] [drm:drm_mode_addfb2] [FB:81]
>[  104.386604] [drm:drm_mode_addfb2] [FB:74]
>[  104.403241] [drm:drm_mode_addfb2] [FB:80]
>[  104.420606] [drm:drm_mode_addfb2] [FB:81]
>[  104.429593] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.429609] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.437550] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.437570] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.445579] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.445602] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.453591] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.453615] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.461593] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.461616] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.469547] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.469570] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.501594] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.501618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.509563] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.509586] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.517615] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.517639] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.525621] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.525646] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.533618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.533642] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.537906] [drm:drm_mode_addfb2] [FB:74]
>[  104.597615] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.597638] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.609751] [drm:drm_mode_addfb2] [FB:80]
>[  104.841631] [drm:drm_mode_addfb2] [FB:74]
>[  104.845708] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.845724] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.901670] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.901693] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.905229] [drm:drm_mode_addfb2] [FB:80]
>[  104.957718] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.957742] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  104.965826] [drm:drm_mode_addfb2] [FB:74]
>[  104.986606] [drm:drm_mode_addfb2] [FB:80]
>[  105.004875] [drm:drm_mode_addfb2] [FB:74]
>[  105.022861] [drm:drm_mode_addfb2] [FB:80]
>[  105.036974] [drm:drm_mode_addfb2] [FB:81]
>[  105.045746] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.045763] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.053682] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.053704] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.053832] [drm:drm_mode_addfb2] [FB:74]
>[  105.070311] [drm:drm_mode_addfb2] [FB:80]
>[  105.087079] [drm:drm_mode_addfb2] [FB:81]
>[  105.103676] [drm:drm_mode_addfb2] [FB:74]
>[  105.158777] [drm:drm_mode_addfb2] [FB:80]
>[  105.165773] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.165789] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.173746] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.173773] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.174058] [drm:drm_mode_addfb2] [FB:74]
>[  105.182886] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.182902] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.189779] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.189803] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.197784] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.197808] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.205784] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.205809] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.213785] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.213809] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.221789] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.221814] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.237778] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.237802] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.245746] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.245770] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.253795] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.253821] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.265438] [drm:drm_mode_addfb2] [FB:80]
>[  105.341871] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.341895] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.349824] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.349848] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.354027] [drm:drm_mode_addfb2] [FB:74]
>[  105.378947] [drm:drm_mode_addfb2] [FB:80]
>[  105.396684] [drm:drm_mode_addfb2] [FB:74]
>[  105.411345] [drm:drm_mode_addfb2] [FB:80]
>[  105.421834] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.421858] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.424657] [drm:drm_mode_addfb2] [FB:74]
>[  105.429851] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.429867] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.444219] [drm:drm_mode_addfb2] [FB:80]
>[  105.457608] [drm:drm_mode_addfb2] [FB:74]
>[  105.474490] [drm:drm_mode_addfb2] [FB:80]
>[  105.490285] [drm:drm_mode_addfb2] [FB:74]
>[  105.507743] [drm:drm_mode_addfb2] [FB:80]
>[  105.517872] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.517888] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.524404] [drm:drm_mode_addfb2] [FB:74]
>[  105.525840] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.525853] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.533881] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.533898] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.541869] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.541894] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.549879] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.549903] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.589883] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.589907] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.597889] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.597913] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.605899] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.605923] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.613893] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.613917] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.617687] [drm:drm_mode_addfb2] [FB:80]
>[  105.693900] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.693925] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.698078] [drm:drm_mode_addfb2] [FB:74]
>[  105.717924] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.717950] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  105.725411] [drm:drm_mode_addfb2] [FB:80]
>[  105.751150] [drm:drm_mode_addfb2] [FB:74]
>[  105.761808] [drm:drm_mode_addfb2] [FB:80]
>[  105.779555] [drm:drm_mode_addfb2] [FB:74]
>[  105.792369] [drm:drm_mode_addfb2] [FB:80]
>[  105.809387] [drm:drm_mode_addfb2] [FB:74]
>[  105.826037] [drm:drm_mode_addfb2] [FB:80]
>[  105.842619] [drm:drm_mode_addfb2] [FB:74]
>[  106.088008] [drm:drm_mode_addfb2] [FB:80]
>[  106.104805] [drm:drm_mode_addfb2] [FB:81]
>[  106.121409] [drm:drm_mode_addfb2] [FB:74]
>[  106.139232] [drm:drm_mode_addfb2] [FB:80]
>[  106.156562] [drm:drm_mode_addfb2] [FB:74]
>[  106.166036] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.166051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.171515] [drm:drm_mode_addfb2] [FB:81]
>[  106.173984] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.173997] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.182036] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.182052] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.188959] [drm:drm_mode_addfb2] [FB:74]
>[  106.190041] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.190058] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.204962] [drm:drm_mode_addfb2] [FB:80]
>[  106.221617] [drm:drm_mode_addfb2] [FB:81]
>[  106.238322] [drm:drm_mode_addfb2] [FB:74]
>[  106.254939] [drm:drm_mode_addfb2] [FB:80]
>[  106.271706] [drm:drm_mode_addfb2] [FB:81]
>[  106.286068] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.286084] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.294072] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.294096] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.302061] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.302085] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.310009] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.310032] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.318099] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.318123] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.358020] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.358043] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.361898] [drm:drm_mode_addfb2] [FB:74]
>[  106.433820] [drm:drm_mode_addfb2] [FB:80]
>[  106.438092] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.438107] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.462043] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.462076] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.473615] [drm:drm_mode_addfb2] [FB:74]
>[  106.497244] [drm:drm_mode_addfb2] [FB:80]
>[  106.513194] [drm:drm_mode_addfb2] [FB:74]
>[  106.526857] [drm:drm_mode_addfb2] [FB:80]
>[  106.540226] [drm:drm_mode_addfb2] [FB:74]
>[  106.541991] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.542003] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.550017] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.550032] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.559976] [drm:drm_mode_addfb2] [FB:80]
>[  106.573649] [drm:drm_mode_addfb2] [FB:74]
>[  106.591155] [drm:drm_mode_addfb2] [FB:80]
>[  106.607224] [drm:drm_mode_addfb2] [FB:74]
>[  106.623759] [drm:drm_mode_addfb2] [FB:80]
>[  106.640472] [drm:drm_mode_addfb2] [FB:74]
>[  106.654145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.654159] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.662097] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.662120] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.670119] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.670144] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.678110] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.678135] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.686121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.686143] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.694144] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.694169] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.742116] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.742139] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.750137] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.750162] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.758145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.758168] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.766165] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.766190] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.774126] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.774148] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.777683] [drm:drm_mode_addfb2] [FB:80]
>[  106.862172] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.862196] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.865605] [drm:drm_mode_addfb2] [FB:74]
>[  106.870175] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.870190] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.881988] [drm:drm_mode_addfb2] [FB:80]
>[  106.905256] [drm:drm_mode_addfb2] [FB:74]
>[  106.922349] [drm:drm_mode_addfb2] [FB:81]
>[  106.934157] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.934171] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.939111] [drm:drm_mode_addfb2] [FB:80]
>[  106.942178] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.942192] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.950242] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.950258] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  106.955725] [drm:drm_mode_addfb2] [FB:74]
>[  106.972391] [drm:drm_mode_addfb2] [FB:81]
>[  106.989106] [drm:drm_mode_addfb2] [FB:80]
>[  107.005783] [drm:drm_mode_addfb2] [FB:74]
>[  107.022759] [drm:drm_mode_addfb2] [FB:81]
>[  107.038145] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.038162] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.039149] [drm:drm_mode_addfb2] [FB:80]
>[  107.046175] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.046190] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.054148] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.054163] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.062253] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.062276] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.070164] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.070189] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.078212] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.078237] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.086193] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.086215] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.150246] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.150269] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.158371] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.158398] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.158646] [drm:drm_mode_addfb2] [FB:74]
>[  107.166209] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.166225] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.174392] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.174417] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.174657] [drm:drm_mode_addfb2] [FB:80]
>[  107.182229] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.182244] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.193650] [drm:drm_mode_addfb2] [FB:74]
>[  107.262199] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.262222] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.274110] [drm:drm_mode_addfb2] [FB:80]
>[  107.278219] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.278233] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.297516] [drm:drm_mode_addfb2] [FB:74]
>[  107.312875] [drm:drm_mode_addfb2] [FB:80]
>[  107.330259] [drm:drm_mode_addfb2] [FB:74]
>[  107.341271] [drm:drm_mode_addfb2] [FB:80]
>[  107.350215] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.350230] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.358229] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.358249] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.358303] [drm:drm_mode_addfb2] [FB:74]
>[  107.366243] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.366258] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.377425] [drm:drm_mode_addfb2] [FB:80]
>[  107.392554] [drm:drm_mode_addfb2] [FB:74]
>[  107.408499] [drm:drm_mode_addfb2] [FB:80]
>[  107.424453] [drm:drm_mode_addfb2] [FB:74]
>[  107.441669] [drm:drm_mode_addfb2] [FB:80]
>[  107.458411] [drm:drm_mode_addfb2] [FB:74]
>[  107.462298] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.462311] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.470302] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.470316] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.478309] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.478331] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.486243] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.486266] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.494326] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.494349] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.502323] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.502346] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.510315] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.510338] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.518324] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.518348] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.526327] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.526350] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.582305] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.582329] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.590306] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.590337] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.598332] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.598355] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.606268] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.606290] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.614262] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.614285] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.622268] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.622291] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.633960] [drm:drm_mode_addfb2] [FB:80]
>[  107.702281] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.702304] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.706285] [drm:drm_mode_addfb2] [FB:74]
>[  107.718378] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.718397] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.723646] [drm:drm_mode_addfb2] [FB:80]
>[  107.746329] [drm:drm_mode_addfb2] [FB:74]
>[  107.761676] [drm:drm_mode_addfb2] [FB:80]
>[  107.778340] [drm:drm_mode_addfb2] [FB:74]
>[  107.789973] [drm:drm_mode_addfb2] [FB:81]
>[  107.798336] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.798351] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.806392] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.806472] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.806989] [drm:drm_mode_addfb2] [FB:74]
>[  107.827218] [drm:drm_mode_addfb2] [FB:80]
>[  107.841653] [drm:drm_mode_addfb2] [FB:74]
>[  107.857555] [drm:drm_mode_addfb2] [FB:80]
>[  107.874438] [drm:drm_mode_addfb2] [FB:74]
>[  107.886317] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.886330] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.891666] [drm:drm_mode_addfb2] [FB:80]
>[  107.894382] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.894398] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.902340] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.902354] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.910329] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.910348] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.926333] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.926357] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.934343] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.934365] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.942346] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.942369] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.950431] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  107.950454] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.006458] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.006480] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.014460] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.014484] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.022445] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.022467] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.030400] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.030424] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.042653] [drm:drm_mode_addfb2] [FB:74]
>[  108.118561] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.118586] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.130925] [drm:drm_mode_addfb2] [FB:80]
>[  108.134466] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.134478] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.154262] [drm:drm_mode_addfb2] [FB:74]
>[  108.172761] [drm:drm_mode_addfb2] [FB:80]
>[  108.190288] [drm:drm_mode_addfb2] [FB:81]
>[  108.198531] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.198548] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.206404] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.206418] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.206974] [drm:drm_mode_addfb2] [FB:74]
>[  108.214437] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.214457] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.222427] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.222442] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.223647] [drm:drm_mode_addfb2] [FB:80]
>[  108.240391] [drm:drm_mode_addfb2] [FB:81]
>[  108.257020] [drm:drm_mode_addfb2] [FB:74]
>[  108.273787] [drm:drm_mode_addfb2] [FB:80]
>[  108.290474] [drm:drm_mode_addfb2] [FB:81]
>[  108.307137] [drm:drm_mode_addfb2] [FB:74]
>[  108.310547] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.310562] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.318507] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.318524] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.323960] [drm:drm_mode_addfb2] [FB:80]
>[  108.326565] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.326584] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.334480] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.334495] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.342445] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.342466] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.350515] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.350538] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.358478] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.358501] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.414447] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.414470] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.422546] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.422570] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.430585] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.430609] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.438474] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.438498] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.446546] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.446569] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.454468] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.454489] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.458176] [drm:drm_mode_addfb2] [FB:74]
>[  108.526681] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.526708] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.538370] [drm:drm_mode_addfb2] [FB:80]
>[  108.542561] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.542581] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.558999] [drm:drm_mode_addfb2] [FB:74]
>[  108.579498] [drm:drm_mode_addfb2] [FB:80]
>[  108.590940] [drm:drm_mode_addfb2] [FB:74]
>[  108.598628] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.598643] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.606577] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.606592] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.608302] [drm:drm_mode_addfb2] [FB:80]
>[  108.622585] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.622600] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.627219] [drm:drm_mode_addfb2] [FB:74]
>[  108.641414] [drm:drm_mode_addfb2] [FB:80]
>[  108.657858] [drm:drm_mode_addfb2] [FB:74]
>[  108.674543] [drm:drm_mode_addfb2] [FB:80]
>[  108.691460] [drm:drm_mode_addfb2] [FB:74]
>[  108.708985] [drm:drm_mode_addfb2] [FB:80]
>[  108.718627] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.718642] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.726610] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.726630] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.734632] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.734656] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.742631] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.742654] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.750638] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.750661] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.758652] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.758674] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.806658] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.806685] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.814818] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.814845] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.830774] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.830802] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.846650] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.846677] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.854682] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.854706] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.862678] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.862750] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.870645] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.870678] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.878594] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.878618] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.886595] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  108.886617] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.158458] [drm:drm_mode_addfb2] [FB:74]
>[  109.174921] [drm:drm_mode_addfb2] [FB:81]
>[  109.742903] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.742927] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.750870] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.750892] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.758885] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.758908] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.766915] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.766937] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.774888] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.774911] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.782870] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.782893] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.790897] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.790920] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.798882] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.798904] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.806899] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.806922] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.814895] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.814918] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.822948] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.822972] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.830896] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.830919] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.838907] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.838931] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.846921] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.846943] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.854886] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.854909] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.862911] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.862935] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.870916] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  109.870939] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  110.158924] [drm:drm_mode_addfb2] [FB:74]
>[  110.175795] [drm:drm_mode_addfb2] [FB:80]
>[  110.552024] [drm:drm_mode_addfb2] [FB:74]
>[  110.569006] [drm:drm_mode_addfb2] [FB:80]
>[  110.585416] [drm:drm_mode_addfb2] [FB:74]
>[  110.602216] [drm:drm_mode_addfb2] [FB:80]
>[  110.618839] [drm:drm_mode_addfb2] [FB:74]
>[  110.635388] [drm:drm_mode_addfb2] [FB:80]
>[  110.679345] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  110.679352] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=903, cursor=0 level=0 cxsr=1
>[  110.679884] [drm:drm_mode_addfb2] [FB:74]
>[  110.941650] [drm:connected_sink_compute_bpp] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  110.941652] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 24
>[  110.941657] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 270000 pixel clock 72330KHz
>[  110.941658] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  110.941661] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 1 clock 270000 bpp 18
>[  110.941663] [drm:intel_dp_compute_config] DP link bw required 130194 available 216000
>[  110.941665] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  110.941668] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff992b73531800 for pipe A
>[  110.941669] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  110.941671] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  110.941672] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  110.941674] [drm:intel_dump_pipe_config] dp: 1, lanes: 1, gmch_m: 2528116, gmch_n: 4194304, link_m: 140450, link_n: 524288, tu: 64
>[  110.941676] [drm:intel_dump_pipe_config] dp: 1, lanes: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  110.941677] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  110.941678] [drm:intel_dump_pipe_config] requested mode:
>[  110.941681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[  110.941682] [drm:intel_dump_pipe_config] adjusted mode:
>[  110.941685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 72330 1366 1414 1446 1526 768 770 775 790 0x48 0xa
>[  110.941688] [drm:intel_dump_crtc_timings] crtc timings: 72330 1366 1414 1446 1526 768 770 775 790, type: 0x48 flags: 0xa
>[  110.941689] [drm:intel_dump_pipe_config] port clock: 270000
>[  110.941690] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[  110.941691] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  110.941692] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  110.941694] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  110.941694] [drm:intel_dump_pipe_config] ips: 0
>[  110.941695] [drm:intel_dump_pipe_config] double wide: 0
>[  110.941697] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xf0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  110.941698] [drm:intel_dump_pipe_config] planes on this crtc
>[  110.941702] [drm:intel_dump_pipe_config] [PLANE:23:primary A] enabled
>[  110.941704] [drm:intel_dump_pipe_config] 	FB:74, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  110.941705] [drm:intel_dump_pipe_config] 	scaler:0 src 0x0+1920+1200 dst 0x0+1920+1200
>[  110.941706] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
>[  110.941707] [drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
>[  110.941708] [drm:intel_dump_pipe_config] [PLANE:28:sprite B] disabled, scaler_id = 0
>[  110.941710] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-1] checking for sink bpp constrains
>[  110.941711] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 24
>[  110.941713] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  110.941715] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  110.941716] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  110.941718] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff992b73530800 for pipe B
>[  110.941719] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  110.941720] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  110.941722] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  110.941723] [drm:intel_dump_pipe_config] dp: 0, lanes: 4, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  110.941725] [drm:intel_dump_pipe_config] dp: 0, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  110.941726] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  110.941727] [drm:intel_dump_pipe_config] requested mode:
>[  110.941729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  110.941730] [drm:intel_dump_pipe_config] adjusted mode:
>[  110.941733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  110.941735] [drm:intel_dump_crtc_timings] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  110.941736] [drm:intel_dump_pipe_config] port clock: 74250
>[  110.941737] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  110.941738] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  110.941740] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  110.941741] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  110.941742] [drm:intel_dump_pipe_config] ips: 0
>[  110.941743] [drm:intel_dump_pipe_config] double wide: 0
>[  110.941744] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xf0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  110.941745] [drm:intel_dump_pipe_config] planes on this crtc
>[  110.941746] [drm:intel_dump_pipe_config] [PLANE:29:primary B] disabled, scaler_id = 0
>[  110.941749] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] enabled
>[  110.941751] [drm:intel_dump_pipe_config] 	FB:53, fb = 256x256 format = AR24 little-endian (0x34325241)
>[  110.941752] [drm:intel_dump_pipe_config] 	scaler:0 src 0x0+-270+-596 dst 270x596+-270+-596
>[  110.941753] [drm:intel_dump_pipe_config] [PLANE:32:sprite C] disabled, scaler_id = 0
>[  110.941754] [drm:intel_dump_pipe_config] [PLANE:33:sprite D] disabled, scaler_id = 0
>[  110.941757] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667
>[  110.941814] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  110.943258] [drm:intel_disable_pipe] disabling pipe A
>[  110.961061] [drm:verify_encoder_state] [ENCODER:35:CRT]
>[  110.961065] [drm:verify_encoder_state] [ENCODER:36:DP B]
>[  110.961066] [drm:verify_encoder_state] [ENCODER:44:DP C]
>[  110.961068] [drm:verify_encoder_state] [ENCODER:46:HDMI C]
>[  110.961070] [drm:intel_connector_verify_state] [CONNECTOR:34:VGA-1]
>[  110.961072] [drm:intel_connector_verify_state] [CONNECTOR:45:DP-1]
>[  110.961285] [drm:edp_panel_vdd_on] Turning eDP port B VDD on
>[  110.961287] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  110.961293] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[  110.961295] [drm:wait_panel_status] Wait complete
>[  110.961298] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  110.961299] [drm:edp_panel_vdd_on] eDP port B panel power wasn't enabled
>[  111.169123] [drm:edp_panel_on] Turn eDP port B panel power on
>[  111.169127] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  111.169134] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  111.169137] [drm:wait_panel_status] Wait complete
>[  111.169139] [drm:wait_panel_on] Wait for panel power on
>[  111.169143] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  111.321012] [drm:wait_panel_status] Wait complete
>[  111.321016] [drm:edp_panel_vdd_off_sync] Turning eDP port B VDD off
>[  111.321021] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  111.321032] [drm:edp_panel_vdd_on] Turning eDP port B VDD on
>[  111.321036] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  111.322340] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  111.322342] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  111.323744] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  111.325444] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  111.325914] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  111.325920] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=425, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  111.325921] [drm:intel_enable_pipe] enabling pipe A
>[  111.325932] [drm:intel_edp_backlight_on] 
>[  111.325933] [drm:intel_panel_enable_backlight] pipe A
>[  111.325936] [drm:intel_panel_actually_set_backlight] set backlight PWM = 6696
>[  111.333177] [drm:intel_psr_enable] PSR not supported by this panel
>[  111.335499] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  111.335505] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=431, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  111.335506] [drm:intel_enable_pipe] enabling pipe B
>[  111.352294] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
>[  111.352302] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  111.352324] [drm:intel_connector_verify_state] [CONNECTOR:47:HDMI-A-1]
>[  111.352327] [drm:verify_crtc_state] [CRTC:31:pipe B]
>[  112.498019] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[  112.498030] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[  112.498041] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[  112.498050] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[  112.498058] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[  112.498067] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[  114.493811] [drm:edp_panel_vdd_off_sync] Turning eDP port B VDD off
>[  114.493818] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  121.624302] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[  121.624313] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[  121.624324] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[  121.624332] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[  121.624341] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[  121.624349] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)
>[  130.752624] ACPI Error: [\_TZ_.THRM] Namespace lookup failure, AE_NOT_FOUND (20160422/psargs-359)
>[  130.752664] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LGPA] (Node ffff992b7b0ed1b8), AE_NOT_FOUND (20160422/psparse-542)
>[  130.752707] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.LEVN] (Node ffff992b7b0ee820), AE_NOT_FOUND (20160422/psparse-542)
>[  130.752744] ACPI Error: Method parse/execution failed [\_SB.PCI0.LPCB.ECLV] (Node ffff992b7b0ee780), AE_NOT_FOUND (20160422/psparse-542)
>[  130.752779] ACPI Error: Method parse/execution failed [\_GPE._L10] (Node ffff992b7b0ee848), AE_NOT_FOUND (20160422/psparse-542)
>[  130.752815] ACPI Exception: AE_NOT_FOUND, while evaluating GPE method [_L10] (20160422/evgpe-592)

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