Attachment 127123 Details for Bug 95306 – possible fix

[patch] possible fix

0001-drm-amdgpu-gfx8-fix-CGCG_CGLS-handling.patch (text/plain), 1.47 KB, created by Alex Deucher on 2016-10-07 20:08:55 UTC

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Creator: Alex Deucher

Created: 2016-10-07 20:08:55 UTC

Size: 1.47 KB

patch

obsolete

>From 1c22b05623e5e03ada5a767951eac3203b246be9 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Fri, 7 Oct 2016 16:00:47 -0400
>Subject: [PATCH] drm/amdgpu/gfx8: fix CGCG_CGLS handling
>
>When setting up the RLC, only disable the CGCG and
>CGLS bits rather than clearing the entire register
>to avoid losing the golden settings.
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>Cc: stable@vger.kernel.org
>---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>index 88c41be..a503ee9 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>@@ -4102,14 +4102,21 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
> static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
> {
> 	int r;
>+	u32 tmp;
> 
> 	gfx_v8_0_rlc_stop(adev);
> 
> 	/* disable CG */
>-	WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
>+	tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);
>+	tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
>+		 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
>+	WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
> 	if (adev->asic_type == CHIP_POLARIS11 ||
>-	    adev->asic_type == CHIP_POLARIS10)
>-		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
>+	    adev->asic_type == CHIP_POLARIS10) {
>+		tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
>+		tmp &= ~0x3;
>+		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
>+	}
> 
> 	/* disable PG */
> 	WREG32(mmRLC_PG_CNTL, 0);
>-- 
>2.5.5
>

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Attachments on bug 95306: 125945 | 125946 | 125947 | 125978 | 126013 | 127123 | 127827 | 127842 | 127843 | 128273 | 128781 | 128782 | 128830 | 128831 | 128840 | 128841 | 129237 | 129489 | 136007 | 136125

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