Attachment 127301 Details for Bug 98259 – dmesg

dmesg

badPixel (text/plain), 44.51 KB, created by Luis Botello on 2016-10-14 15:12:22 UTC

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Description:

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Creator: Luis Botello

Created: 2016-10-14 15:12:22 UTC

Size: 44.51 KB

patch

obsolete

>[ 2051.906469] kms_rotation_crc: executing
>[ 2051.906740] [drm:i915_gem_open [i915]] 
>[ 2051.906977] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2051.907032] [drm:_i915_gem_object_create_stolen [i915]] offset=0x11000, size=16384
>[ 2051.907435] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2051.907487] [drm:_i915_gem_object_create_stolen [i915]] offset=0x15000, size=16384
>[ 2051.907641] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2051.907692] [drm:_i915_gem_object_create_stolen [i915]] offset=0x19000, size=16384
>[ 2051.907845] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2051.907898] [drm:_i915_gem_object_create_stolen [i915]] offset=0x1d000, size=16384
>[ 2051.908841] [drm:i915_gem_open [i915]] 
>[ 2051.910312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1]
>[ 2051.910377] [drm:intel_dp_detect [i915]] [CONNECTOR:39:eDP-1]
>[ 2051.910433] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 2051.910487] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 2051.910539] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 2051.910592] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 2051.910650] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2051.910711] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2051.911106] [drm:intel_dp_detect [i915]] Sink OUI: 001cf8
>[ 2051.911483] [drm:intel_dp_detect [i915]] Branch OUI: 000000
>[ 2051.912115] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 2051.912132] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes :
>[ 2051.912143] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[ 2051.912304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[ 2051.912394] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[ 2051.912932] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[ 2051.913795] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[ 2051.913870] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 2051.913941] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 2051.914012] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 2051.914414] [drm:intel_dp_detect [i915]] sink hw revision: 2.1
>[ 2051.914822] [drm:intel_dp_detect [i915]] sink sw revision: 1.39
>[ 2051.915229] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 2051.915887] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 300000 kHz
>[ 2051.915895] [drm:drm_edid_to_eld] ELD monitor ASUS PB287Q
>[ 2051.915902] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 2051.915908] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 2051.916043] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes :
>[ 2051.916053] [drm:drm_mode_debug_printmodeline] Modeline 65:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 2051.916063] [drm:drm_mode_debug_printmodeline] Modeline 119:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 2051.916071] [drm:drm_mode_debug_printmodeline] Modeline 136:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 2051.916080] [drm:drm_mode_debug_printmodeline] Modeline 120:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 2051.916090] [drm:drm_mode_debug_printmodeline] Modeline 121:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 2051.916102] [drm:drm_mode_debug_printmodeline] Modeline 137:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 2051.916110] [drm:drm_mode_debug_printmodeline] Modeline 68:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[ 2051.916119] [drm:drm_mode_debug_printmodeline] Modeline 67:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[ 2051.916127] [drm:drm_mode_debug_printmodeline] Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 2051.916136] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 2051.916145] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 2051.916154] [drm:drm_mode_debug_printmodeline] Modeline 130:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 2051.916166] [drm:drm_mode_debug_printmodeline] Modeline 115:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 2051.916175] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 2051.916183] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 2051.916192] [drm:drm_mode_debug_printmodeline] Modeline 135:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 2051.916200] [drm:drm_mode_debug_printmodeline] Modeline 117:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 2051.916209] [drm:drm_mode_debug_printmodeline] Modeline 134:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 2051.916218] [drm:drm_mode_debug_printmodeline] Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 2051.916230] [drm:drm_mode_debug_printmodeline] Modeline 84:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 2051.916238] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 2051.916247] [drm:drm_mode_debug_printmodeline] Modeline 73:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 2051.916256] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 2051.916264] [drm:drm_mode_debug_printmodeline] Modeline 75:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 2051.916273] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 2051.916282] [drm:drm_mode_debug_printmodeline] Modeline 124:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 2051.916294] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 2051.916303] [drm:drm_mode_debug_printmodeline] Modeline 111:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[ 2051.916311] [drm:drm_mode_debug_printmodeline] Modeline 85:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 2051.916320] [drm:drm_mode_debug_printmodeline] Modeline 86:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 2051.916329] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 2051.916338] [drm:drm_mode_debug_printmodeline] Modeline 131:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 2051.916350] [drm:drm_mode_debug_printmodeline] Modeline 108:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 2051.916359] [drm:drm_mode_debug_printmodeline] Modeline 88:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 2051.916367] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 2051.916376] [drm:drm_mode_debug_printmodeline] Modeline 95:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 2051.916384] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 2051.916393] [drm:drm_mode_debug_printmodeline] Modeline 78:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 2051.916405] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 2051.916414] [drm:drm_mode_debug_printmodeline] Modeline 127:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 2051.916422] [drm:drm_mode_debug_printmodeline] Modeline 98:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 2051.916431] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 2051.916439] [drm:drm_mode_debug_printmodeline] Modeline 80:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 2051.916448] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 2051.916457] [drm:drm_mode_debug_printmodeline] Modeline 125:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 2051.916469] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 2051.916477] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 2051.916661] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1]
>[ 2051.916743] [drm:intel_hdmi_detect [i915]] [CONNECTOR:51:HDMI-A-1]
>[ 2051.917005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 2051.917077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 2051.917305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 2051.917320] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 2051.917565] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 2051.917636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 2051.917863] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 2051.917875] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected
>[ 2051.918026] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2]
>[ 2051.918100] [drm:intel_dp_detect [i915]] [CONNECTOR:54:DP-2]
>[ 2051.918635] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[ 2051.919031] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 2051.919110] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 2051.919182] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 2051.919257] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 2051.919328] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 2051.919783] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 2051.919818] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes :
>[ 2051.919838] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2051.919856] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 2051.919879] [drm:drm_mode_debug_printmodeline] Modeline 99:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 2051.919896] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 2051.919910] [drm:drm_mode_debug_printmodeline] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 2051.919933] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 2051.919949] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 2051.919965] [drm:drm_mode_debug_printmodeline] Modeline 113:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 2051.919979] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 2051.920001] [drm:drm_mode_debug_printmodeline] Modeline 110:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 2051.920012] [drm:drm_mode_debug_printmodeline] Modeline 112:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 2051.920125] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2]
>[ 2051.920199] [drm:intel_hdmi_detect [i915]] [CONNECTOR:58:HDMI-A-2]
>[ 2051.920440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 2051.920511] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 2051.920740] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 2051.920750] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 2051.920979] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 2051.921050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 2051.921278] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 2051.921290] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected
>[ 2051.921534] kms_rotation_crc: starting subtest bad-pixel-format
>[ 2051.922086] [drm:drm_mode_addfb2] [FB:60]
>[ 2051.924981] [drm:drm_mode_addfb2] [FB:103]
>[ 2051.936290] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[ 2051.936305] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[ 2051.936428] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2051.964622] [drm:drm_mode_setcrtc] [CRTC:31:pipe B]
>[ 2051.964740] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[ 2051.964829] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2051.964905] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[ 2051.964981] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[ 2051.965059] [drm:bxt_get_dpll [i915]] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[ 2051.965134] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 2051.965210] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[ 2051.965285] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[ 2051.965359] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[ 2051.965431] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 2051.965505] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[ 2051.965628] [drm:intel_edp_backlight_off [i915]] 
>[ 2052.171799] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2052.171890] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2052.182388] [drm:intel_edp_panel_off [i915]] Turn eDP port A panel power off
>[ 2052.182463] [drm:intel_edp_panel_off [i915]] Wait for panel power off time
>[ 2052.182542] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 2052.234381] [drm:wait_panel_status [i915]] Wait complete
>[ 2052.234464] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 26
>[ 2052.234605] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 2052.234714] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 2052.234795] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[ 2052.234864] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 2052.234937] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2052.235008] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2052.235121] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2052.235195] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 2052.243572] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 31
>[ 2052.243673] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 2052.244026] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 2052.256150] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 36
>[ 2052.256247] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 2052.256335] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[ 2052.259924] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[ 2052.260003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:38:DDI A]
>[ 2052.260081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 2052.260164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 2052.260238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 2052.260314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 2052.260389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DDI C]
>[ 2052.260466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST A]
>[ 2052.260539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST B]
>[ 2052.260617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST C]
>[ 2052.260691] [drm:verify_connector_state [i915]] [CONNECTOR:47:DP-1]
>[ 2052.260771] [drm:verify_connector_state [i915]] [CONNECTOR:51:HDMI-A-1]
>[ 2052.260848] [drm:verify_connector_state [i915]] [CONNECTOR:58:HDMI-A-2]
>[ 2052.260929] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL A
>[ 2052.261004] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL B
>[ 2052.261081] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL C
>[ 2052.261191] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 26
>[ 2052.261263] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 2052.261533] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2052.261606] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2052.699801] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 2052.740053] [drm:wait_panel_status [i915]] Wait complete
>[ 2052.740129] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2052.740208] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[ 2052.847565] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 2052.847641] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2052.847715] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2052.847815] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2052.942334] [drm:wait_panel_status [i915]] Wait complete
>[ 2052.942418] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2052.942497] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2052.943726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2052.943826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2052.943899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2052.944626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2052.944698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2052.945696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2052.945939] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880272be2800
>[ 2052.947046] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2052.947137] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 2052.947207] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2052.947281] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 94080
>[ 2052.951790] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[ 2052.951863] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 2052.963884] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 36
>[ 2052.963957] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 2052.965291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2052.965361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2052.965433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2052.967226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 2052.967296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2052.969098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2052.969170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2052.971260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 2052.971330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 2052.972363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2052.974630] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880272be1000
>[ 2052.975731] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 2053.009290] [drm:verify_connector_state [i915]] [CONNECTOR:39:eDP-1]
>[ 2053.009376] [drm:intel_atomic_commit_tail [i915]] [CRTC:26:pipe A]
>[ 2053.009583] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL A
>[ 2053.009735] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe B]
>[ 2053.009836] [drm:verify_connector_state [i915]] [CONNECTOR:54:DP-2]
>[ 2053.009919] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe C]
>[ 2053.010057] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL C
>[ 2053.010270] [drm:drm_mode_setcrtc] [CRTC:36:pipe C]
>[ 2053.010374] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[ 2053.010461] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2053.010537] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[ 2053.010613] [drm:bxt_get_dpll [i915]] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[ 2053.010686] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 2053.010763] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[ 2053.010838] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[ 2053.010951] [drm:intel_edp_backlight_off [i915]] 
>[ 2053.215796] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2053.215888] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2053.232232] [drm:intel_edp_panel_off [i915]] Turn eDP port A panel power off
>[ 2053.232307] [drm:intel_edp_panel_off [i915]] Wait for panel power off time
>[ 2053.232388] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[ 2053.284259] [drm:wait_panel_status [i915]] Wait complete
>[ 2053.284340] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 26
>[ 2053.284481] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 2053.284594] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 2053.284750] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 2053.284823] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2053.284896] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2053.284985] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2053.294223] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 36
>[ 2053.294320] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 2053.294439] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[ 2053.297947] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[ 2053.298025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:38:DDI A]
>[ 2053.298101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 2053.298180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 2053.298253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 2053.298327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 2053.298402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DDI C]
>[ 2053.298478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST A]
>[ 2053.298551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST B]
>[ 2053.298624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST C]
>[ 2053.298698] [drm:verify_connector_state [i915]] [CONNECTOR:47:DP-1]
>[ 2053.298775] [drm:verify_connector_state [i915]] [CONNECTOR:51:HDMI-A-1]
>[ 2053.298850] [drm:verify_connector_state [i915]] [CONNECTOR:54:DP-2]
>[ 2053.298926] [drm:verify_connector_state [i915]] [CONNECTOR:58:HDMI-A-2]
>[ 2053.299001] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL A
>[ 2053.299076] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL B
>[ 2053.299150] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL C
>[ 2053.299258] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 26
>[ 2053.299329] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 2053.299597] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2053.299671] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2053.755807] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 2053.840463] [drm:wait_panel_status [i915]] Wait complete
>[ 2053.840540] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2053.840619] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2053.947962] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 2053.948038] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2053.948113] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2053.948226] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2054.041724] [drm:wait_panel_status [i915]] Wait complete
>[ 2054.041811] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2054.041893] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2054.043113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2054.043183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2054.043258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2054.044117] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2054.044189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2054.045222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2054.045470] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880272be0800
>[ 2054.046792] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2054.046885] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 2054.046957] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2054.047031] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 94080
>[ 2054.051799] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[ 2054.051874] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 2054.080313] [drm:verify_connector_state [i915]] [CONNECTOR:39:eDP-1]
>[ 2054.080400] [drm:intel_atomic_commit_tail [i915]] [CRTC:26:pipe A]
>[ 2054.080614] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL A
>[ 2054.080749] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[ 2054.080817] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2054.080904] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 2054.080990] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe C]
>[ 2054.081904] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2054.113677] [drm:display_crc_ctl_write [i915]] collecting CRCs for pipe A, pf
>[ 2054.163655] [drm:display_crc_ctl_write [i915]] stopping CRCs for pipe A
>[ 2054.192802] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2054.213710] [drm:display_crc_ctl_write [i915]] collecting CRCs for pipe A, pf
>[ 2054.263672] [drm:display_crc_ctl_write [i915]] stopping CRCs for pipe A
>[ 2054.280961] [drm:intel_plane_atomic_check [i915]] Unsupported pixel format RG16 little-endian (0x36314752) for 90/270!
>[ 2054.281169] [drm:intel_atomic_check [i915]] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[ 2054.281243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2054.281319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 2054.281399] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 2054.281468] [drm:intel_dp_compute_config [i915]] DP link bw required 712800 available 864000
>[ 2054.281542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2054.281618] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe B][modeset] config ffff88026e7ab000 for pipe B
>[ 2054.281691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B
>[ 2054.281761] [drm:intel_dump_pipe_config [i915]] pipe bpp: 24, dithering: 0
>[ 2054.281833] [drm:intel_dump_pipe_config [i915]] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 2054.281906] [drm:intel_dump_pipe_config [i915]] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 2054.281979] [drm:intel_dump_pipe_config [i915]] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 2054.282049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 2054.282119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2054.282134] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 2054.282204] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2054.282213] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 2054.282286] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 2054.282357] [drm:intel_dump_pipe_config [i915]] port clock: 270000
>[ 2054.282428] [drm:intel_dump_pipe_config [i915]] pipe src size: 3840x2160
>[ 2054.282499] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2054.282570] [drm:intel_dump_pipe_config [i915]] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 2054.282643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2054.282714] [drm:intel_dump_pipe_config [i915]] ips: 0
>[ 2054.282784] [drm:intel_dump_pipe_config [i915]] double wide: 0
>[ 2054.282860] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 2054.282930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2054.283004] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 1B] disabled, scaler_id = -1
>[ 2054.283075] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor B] disabled, scaler_id = -1
>[ 2054.283147] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 2B] disabled, scaler_id = -1
>[ 2054.283218] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3B] disabled, scaler_id = -1
>[ 2054.283292] [drm:intel_atomic_check [i915]] [CONNECTOR:54:DP-2] checking for sink bpp constrains
>[ 2054.283365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2054.283437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 2054.283509] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 2054.283579] [drm:intel_dp_compute_config [i915]] DP link bw required 356400 available 518400
>[ 2054.283652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2054.283724] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe C][modeset] config ffff88026e7ab800 for pipe C
>[ 2054.283858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C
>[ 2054.283934] [drm:intel_dump_pipe_config [i915]] pipe bpp: 24, dithering: 0
>[ 2054.284017] [drm:intel_dump_pipe_config [i915]] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 2054.284093] [drm:intel_dump_pipe_config [i915]] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 2054.284170] [drm:intel_dump_pipe_config [i915]] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 2054.284247] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2054.284320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2054.284335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2054.284407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2054.284419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2054.284499] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 2054.284574] [drm:intel_dump_pipe_config [i915]] port clock: 162000
>[ 2054.284652] [drm:intel_dump_pipe_config [i915]] pipe src size: 1920x1080
>[ 2054.284726] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 2054.284803] [drm:intel_dump_pipe_config [i915]] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 2054.284877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2054.284955] [drm:intel_dump_pipe_config [i915]] ips: 0
>[ 2054.285028] [drm:intel_dump_pipe_config [i915]] double wide: 0
>[ 2054.285108] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 2054.285181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2054.285258] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1C] disabled, scaler_id = -1
>[ 2054.285332] [drm:intel_dump_pipe_config [i915]] [PLANE:35:cursor C] disabled, scaler_id = -1
>[ 2054.285410] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2C] disabled, scaler_id = -1
>[ 2054.285497] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 384000, actual 384000
>[ 2054.285589] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2054.285668] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[ 2054.285749] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[ 2054.285830] [drm:bxt_get_dpll [i915]] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[ 2054.285908] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 2054.285985] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[ 2054.286063] [drm:bxt_get_dpll [i915]] [CRTC:31:pipe B] using pre-allocated PORT PLL B
>[ 2054.286138] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 2054.286217] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31
>[ 2054.286292] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe C] using pre-allocated PORT PLL C
>[ 2054.286370] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 2054.286446] [drm:skl_update_scaler_crtc [i915]] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31
>[ 2054.286594] [drm:intel_edp_backlight_off [i915]] 
>[ 2054.491796] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2054.491889] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2054.498246] [drm:intel_edp_panel_off [i915]] Turn eDP port A panel power off
>[ 2054.498320] [drm:intel_edp_panel_off [i915]] Wait for panel power off time
>[ 2054.498401] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[ 2054.550440] [drm:wait_panel_status [i915]] Wait complete
>[ 2054.550520] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 26
>[ 2054.550662] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 2054.550733] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2054.550794] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 2054.550854] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 2054.550927] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2054.551000] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2054.551074] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[ 2054.551145] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2054.551265] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 384000 kHz (VCO 1152000 kHz)
>[ 2054.555391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 384000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[ 2054.555467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:38:DDI A]
>[ 2054.555541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 2054.555615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 2054.555687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 2054.555783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 2054.555856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DDI C]
>[ 2054.555928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST A]
>[ 2054.556001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST B]
>[ 2054.556075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST C]
>[ 2054.556149] [drm:verify_connector_state [i915]] [CONNECTOR:51:HDMI-A-1]
>[ 2054.556227] [drm:verify_connector_state [i915]] [CONNECTOR:58:HDMI-A-2]
>[ 2054.556302] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL A
>[ 2054.556376] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL B
>[ 2054.556449] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL C
>[ 2054.556554] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 26
>[ 2054.556627] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 2054.556890] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2054.556962] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2055.035818] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 2055.141599] [drm:wait_panel_status [i915]] Wait complete
>[ 2055.141672] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2055.141748] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2055.249057] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 2055.249130] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2055.249202] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2055.249292] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2055.341858] [drm:wait_panel_status [i915]] Wait complete
>[ 2055.341936] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2055.342017] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2055.343224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2055.343293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2055.343375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2055.344089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2055.344160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2055.345161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2055.345400] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88026e7af800
>[ 2055.346448] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2055.346533] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 2055.346604] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2055.346677] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 94080
>[ 2055.351784] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[ 2055.351853] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 2055.363278] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 31
>[ 2055.363349] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 2055.364754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2055.364823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2055.364894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2055.370156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2055.370225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 2055.372585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2055.374860] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88026e7ab000
>[ 2055.375998] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 2055.376099] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B]
>[ 2055.376172] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 2055.376381] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 36
>[ 2055.376452] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 2055.377850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2055.377918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2055.377996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2055.379811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 2055.379879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2055.381663] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2055.381732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2055.383850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 2055.383920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 2055.384951] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2055.387224] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88026e7ab800
>[ 2055.388332] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 2055.409490] [drm:verify_connector_state [i915]] [CONNECTOR:39:eDP-1]
>[ 2055.409576] [drm:intel_atomic_commit_tail [i915]] [CRTC:26:pipe A]
>[ 2055.409790] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL A
>[ 2055.409946] [drm:verify_connector_state [i915]] [CONNECTOR:47:DP-1]
>[ 2055.410027] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe B]
>[ 2055.410174] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL B
>[ 2055.410284] [drm:verify_connector_state [i915]] [CONNECTOR:54:DP-2]
>[ 2055.410365] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe C]
>[ 2055.410511] [drm:verify_single_dpll_state.isra.113 [i915]] PORT PLL C
>[ 2055.435187] kms_rotation_crc: exiting, ret=99
>[ 2055.435365] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2055.435398] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[ 2055.435430] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[ 2055.459051] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2055.459086] [drm:_i915_gem_object_create_stolen [i915]] offset=0x21000, size=16384
>[ 2055.459487] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2055.459528] [drm:_i915_gem_object_create_stolen [i915]] offset=0x25000, size=16384
>[ 2055.460323] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2055.460359] [drm:_i915_gem_object_create_stolen [i915]] offset=0x29000, size=16384
>[ 2055.460479] [drm:i915_gem_object_create_stolen [i915]] creating stolen object: size=4000
>[ 2055.460511] [drm:_i915_gem_object_create_stolen [i915]] offset=0x2d000, size=16384
>[ 2055.463600] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[ 2055.463637] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[ 2055.463671] [drm:intel_plane_atomic_calc_changes [i915]] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[ 2058.011812] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2058.011895] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067

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Attachments on bug 98259: 127301 | 127302

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