Attachment 128099 Details for Bug 98805 – dmesg

dmesg

kms_setmode.dmesg (text/plain), 292.43 KB, created by Tvrtko Ursulin on 2016-11-21 10:04:24 UTC

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Creator: Tvrtko Ursulin

Created: 2016-11-21 10:04:24 UTC

Size: 292.43 KB

patch

obsolete

>[ 1915.576076] [IGT] kms_busy: executing
>[ 1915.590335] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1]
>[ 1915.590451] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[ 1915.590517] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1915.590595] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1915.590673] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1915.590742] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 1915.590817] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1915.590876] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1915.590946] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1915.591060] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>[ 1915.591653] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[ 1915.592173] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[ 1915.592217] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1] probed modes :
>[ 1915.592273] [drm:drm_mode_debug_printmodeline [drm]] Modeline 48:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1915.592509] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1]
>[ 1915.592608] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[ 1915.592696] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1915.592792] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1915.592893] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1915.592991] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1915.593028] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1] disconnected
>[ 1915.593176] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1]
>[ 1915.593247] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[ 1915.593572] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1915.593639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1915.593995] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1915.594056] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1915.594429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1915.594542] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1915.594868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1915.594909] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 1915.594943] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] disconnected
>[ 1915.595263] [IGT] kms_busy: starting subtest basic-flip-default-C
>[ 1915.603088] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[ 1915.632473] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1915.632514] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1915.632547] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[ 1915.841735] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1915.841901] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1915.846506] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[ 1915.846639] [drm:edp_panel_off [i915]] Wait for panel power off time
>[ 1915.846795] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[ 1915.897443] [drm:wait_panel_status [i915]] Wait complete
>[ 1915.897584] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[ 1915.897676] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1915.897824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1915.897914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1915.898004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1915.898079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1915.898161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1915.898229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1915.898311] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1915.898536] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1915.898630] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1915.898747] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1915.898858] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1915.898972] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1915.899090] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1915.899198] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1915.899358] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[ 1915.899468] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1915.899596] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[ 1915.899723] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1915.899845] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1915.899946] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1915.900056] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1915.900573] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1915.900697] [drm:intel_runtime_suspend [i915]] Suspending device
>[ 1915.902059] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1915.902558] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1915.902632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[ 1915.902762] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[ 1915.902854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[ 1915.902950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[ 1915.903036] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[ 1915.903110] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[ 1915.903199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[ 1915.903284] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[ 1915.903417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[ 1915.903498] [drm:intel_runtime_suspend [i915]] Device suspended
>[ 1915.903602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[ 1915.903717] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1915.903822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1915.903903] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1915.903980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1915.904035] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1915.904108] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[ 1915.904176] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[ 1915.904244] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1915.904322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1915.904448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1915.904560] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1915.904658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1915.904762] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[ 1915.904865] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[ 1915.904941] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[ 1915.905027] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1915.905125] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[ 1915.905205] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[ 1915.927749] [drm:intel_runtime_resume [i915]] Resuming device
>[ 1915.933724] [drm:intel_runtime_resume [i915]] Device resumed
>[ 1915.935231] [drm:intel_runtime_suspend [i915]] Suspending device
>[ 1915.935248] ------------[ cut here ]------------
>[ 1915.935332] WARNING: CPU: 1 PID: 10861 at drivers/gpu/drm/i915/i915_gem.c:2022 i915_gem_runtime_suspend+0x116/0x130 [i915]
>[ 1915.935383] WARN_ON(reg->pin_count)[ 1915.935399] Modules linked in:
> snd_hda_intel i915 drm_kms_helper vgem netconsole scsi_transport_iscsi fuse vfat fat x86_pkg_temp_thermal coretemp intel_cstate intel_uncore snd_hda_codec_hdmi snd_hda_codec_generic snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd mei_me mei serio_raw intel_rapl_perf intel_pch_thermal soundcore wmi acpi_pad i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops drm r8169 mii video [last unloaded: drm_kms_helper]
>[ 1915.935785] CPU: 1 PID: 10861 Comm: kworker/1:0 Tainted: G     U  W       4.9.0-rc5+ #170
>[ 1915.935799] Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS DCCN34WW(V2.03) 12/01/2015
>[ 1915.935822] Workqueue: pm pm_runtime_work
>[ 1915.935845]  ffffc900044fbbf0 ffffffffac3220bc ffffc900044fbc40 0000000000000000
>[ 1915.935890]  ffffc900044fbc30 ffffffffac059bcb 000007e6044fbc60 ffff8801626e3198
>[ 1915.935937]  ffff8801626e0000 0000000000000002 ffffffffc05e5d4e 0000000000000000
>[ 1915.935985] Call Trace:
>[ 1915.936013]  [<ffffffffac3220bc>] dump_stack+0x4f/0x73
>[ 1915.936038]  [<ffffffffac059bcb>] __warn+0xcb/0xf0
>[ 1915.936060]  [<ffffffffac059c4f>] warn_slowpath_fmt+0x5f/0x80
>[ 1915.936158]  [<ffffffffc052d916>] i915_gem_runtime_suspend+0x116/0x130 [i915]
>[ 1915.936251]  [<ffffffffc04f1c74>] intel_runtime_suspend+0x64/0x280 [i915]
>[ 1915.936277]  [<ffffffffac0926f1>] ? dequeue_entity+0x241/0xbc0
>[ 1915.936298]  [<ffffffffac36bb85>] pci_pm_runtime_suspend+0x55/0x180
>[ 1915.936317]  [<ffffffffac36bb30>] ? pci_pm_runtime_resume+0xa0/0xa0
>[ 1915.936339]  [<ffffffffac4514e2>] __rpm_callback+0x32/0x70
>[ 1915.936356]  [<ffffffffac451544>] rpm_callback+0x24/0x80
>[ 1915.936375]  [<ffffffffac36bb30>] ? pci_pm_runtime_resume+0xa0/0xa0
>[ 1915.936392]  [<ffffffffac45222d>] rpm_suspend+0x12d/0x680
>[ 1915.936415]  [<ffffffffac69f6d7>] ? _raw_spin_unlock_irq+0x17/0x30
>[ 1915.936435]  [<ffffffffac0810b8>] ? finish_task_switch+0x88/0x220
>[ 1915.936455]  [<ffffffffac4534bf>] pm_runtime_work+0x6f/0xb0
>[ 1915.936477]  [<ffffffffac074353>] process_one_work+0x1f3/0x4d0
>[ 1915.936501]  [<ffffffffac074678>] worker_thread+0x48/0x4e0
>[ 1915.936523]  [<ffffffffac074630>] ? process_one_work+0x4d0/0x4d0
>[ 1915.936542]  [<ffffffffac074630>] ? process_one_work+0x4d0/0x4d0
>[ 1915.936559]  [<ffffffffac07a2c9>] kthread+0xd9/0xf0
>[ 1915.936580]  [<ffffffffac07a1f0>] ? kthread_park+0x60/0x60
>[ 1915.936600]  [<ffffffffac69fe62>] ret_from_fork+0x22/0x30
>[ 1915.936646] ---[ end trace f9357374d2333f67 ]---
>[ 1915.940175] [drm:intel_runtime_suspend [i915]] Device suspended
>[ 1915.963752] [drm:intel_runtime_resume [i915]] Resuming device
>[ 1915.969689] [drm:intel_runtime_resume [i915]] Device resumed
>[ 1915.969790] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1915.969864] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1915.970189] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1915.970269] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1915.970447] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1915.970585] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[ 1915.970667] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[ 1915.970787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1915.970908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1915.971021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1915.971130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1915.971234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1915.971338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1915.971472] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1915.971601] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1915.971708] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1915.971824] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1915.971952] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[ 1915.972065] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1915.972197] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1915.972314] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1916.449713] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000000
>[ 1916.490002] [drm:wait_panel_status [i915]] Wait complete
>[ 1916.490144] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1916.490292] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[ 1916.563344] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1916.563469] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1916.563558] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1916.563773] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1916.692174] [drm:wait_panel_status [i915]] Wait complete
>[ 1916.692326] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1916.692592] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[ 1916.693891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1916.693974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1916.694044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1916.694130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1916.694925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 1916.695000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 1916.695066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1916.695853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1916.695930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1916.696993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1916.697283] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016a026000
>[ 1916.697580] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1916.697603] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 1916.697621] [drm:intel_panel_enable_backlight [i915]] pipe C
>[ 1916.697690] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1916.697745] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[ 1916.697762] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1916.714397] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1916.714450] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[ 1916.714505] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1916.714566] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[ 1916.714612] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1916.714646] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 1916.714678] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1916.714710] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1916.715166] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[ 1916.715603] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:47:eDP-1] status updated from connected to connected
>[ 1916.715650] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[ 1916.715677] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:55:DP-1] status updated from disconnected to disconnected
>[ 1916.715716] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[ 1916.716032] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1916.716064] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1916.716315] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1916.716371] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1916.716657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1916.716702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1916.716989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1916.717004] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 1916.717016] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[ 1916.717059] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[ 1916.717093] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1916.717128] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 1916.717160] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1916.717201] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1916.717657] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[ 1916.718027] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:47:eDP-1] status updated from connected to connected
>[ 1916.718058] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[ 1916.718076] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:55:DP-1] status updated from disconnected to disconnected
>[ 1916.718107] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[ 1916.718402] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1916.718442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1916.718832] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1916.718862] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1916.719129] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1916.719167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1916.719462] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1916.719483] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 1916.719498] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[ 1916.740043] [drm:drm_mode_addfb2 [drm]] [FB:64]
>[ 1917.214701] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1917.214823] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1917.214918] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1917.215020] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1917.215127] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[ 1917.417449] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1917.417582] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1917.431119] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[ 1917.431254] [drm:edp_panel_off [i915]] Wait for panel power off time
>[ 1917.431506] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[ 1917.483174] [drm:wait_panel_status [i915]] Wait complete
>[ 1917.483315] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[ 1917.483559] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1917.483687] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1917.483823] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1917.483933] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1917.484120] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1917.484209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1917.484299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1917.484440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1917.484534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1917.484629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1917.484745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1917.484859] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1917.484986] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1917.485093] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1917.485205] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1917.485310] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1917.485457] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1917.485567] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1917.485679] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[ 1917.485779] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[ 1917.485903] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[ 1917.486005] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1917.486120] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1917.486220] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1917.486740] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1917.487484] [IGT] kms_busy: exiting, ret=0
>[ 1917.487834] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[ 1917.487917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[ 1917.488023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[ 1917.488107] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[ 1917.488202] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[ 1917.488251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[ 1917.488273] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[ 1917.488299] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[ 1917.488316] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[ 1917.488337] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1917.488352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1917.488370] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1917.488386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1917.488399] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1917.488416] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[ 1917.488431] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[ 1917.488450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1917.488465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1917.488484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1917.488499] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1917.488517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1917.488531] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[ 1917.488549] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[ 1917.488563] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[ 1917.488586] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1917.488611] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[ 1917.488628] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1917.488657] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1917.488672] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1917.488929] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1917.488951] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[ 1917.488966] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[ 1917.488989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1917.489005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1917.489024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1917.489038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1917.489056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1917.489071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1917.489090] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1917.489107] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1917.489125] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1917.489140] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1917.489162] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[ 1917.489178] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1917.489205] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1917.489231] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1918.081704] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[ 1918.081795] [drm:wait_panel_status [i915]] Wait complete
>[ 1918.081889] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1918.082011] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[ 1918.155081] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1918.155170] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1918.155250] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1918.155381] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1918.284195] [drm:wait_panel_status [i915]] Wait complete
>[ 1918.284311] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1918.284483] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[ 1918.285724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1918.285787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1918.285848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1918.285909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1918.286663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 1918.286722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 1918.286781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1918.287520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1918.287581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1918.288630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1918.288892] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880166944000
>[ 1918.289361] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1918.289407] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 1918.289421] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1918.289487] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1918.289539] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[ 1918.289552] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1918.306149] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1918.306170] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1918.306199] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1921.345595] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1921.349719] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[ 1921.351921] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1921.353024] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1921.354052] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[   52.684866] console [netcon0] enabled
>[   52.685009] netconsole: network logging started
>[   66.457955] [IGT] kms_busy: executing
>[   66.468389] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1]
>[   66.468510] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[   66.468594] [drm:intel_power_well_enable [i915]] enabling DC off
>[   66.468689] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[   66.468787] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   66.468889] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   66.468972] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   66.469072] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   66.469159] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   66.469500] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   66.470070] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[   66.470589] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[   66.470644] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1] probed modes :
>[   66.470705] [drm:drm_mode_debug_printmodeline [drm]] Modeline 48:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   66.470883] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1]
>[   66.470980] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[   66.471052] [drm:intel_power_well_enable [i915]] enabling power well 2
>[   66.471120] [drm:skl_set_power_well [i915]] Enabling power well 2
>[   66.471296] [drm:intel_power_well_disable [i915]] disabling power well 2
>[   66.471406] [drm:skl_set_power_well [i915]] Disabling power well 2
>[   66.471453] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1] disconnected
>[   66.471626] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1]
>[   66.471730] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[   66.472103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   66.472219] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   66.472600] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   66.472660] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[   66.473029] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   66.473104] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   66.473445] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   66.473497] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[   66.473535] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] disconnected
>[   66.473850] [IGT] kms_busy: starting subtest basic-flip-default-C
>[   66.483217] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[   66.696213] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[   66.696349] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   66.696475] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[   66.904378] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[   66.904546] [drm:intel_disable_pipe [i915]] disabling pipe A
>[   66.911477] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[   66.911612] [drm:edp_panel_off [i915]] Wait for panel power off time
>[   66.911751] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[   66.962982] [drm:wait_panel_status [i915]] Wait complete
>[   66.963124] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[   66.963217] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[   66.963340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   66.963429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   66.963508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   66.963582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   66.963653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   66.963722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   66.963806] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   66.963899] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   66.963990] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   66.964070] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[   66.964262] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   66.964379] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   66.964498] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   66.964598] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   66.964710] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   66.964803] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[   66.964876] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[   66.965055] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[   66.965148] [drm:intel_power_well_disable [i915]] disabling DC off
>[   66.965223] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[   66.965288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[   66.965738] [drm:intel_power_well_disable [i915]] disabling always-on
>[   66.965927] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[   66.966351] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[   66.966402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[   66.966506] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[   66.966584] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[   66.966670] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>[   66.966751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[   66.966833] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[   66.966933] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[   66.967064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[   66.967187] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[   66.967287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[   66.967385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[   66.967471] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   66.967544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   66.967600] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   66.967670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   66.967723] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   66.967796] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[   66.967863] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[   66.967974] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   66.968069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   66.968176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   66.968263] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[   66.968338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   66.968419] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[   66.968488] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[   66.968553] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[   66.968635] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   66.968728] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[   66.968807] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[   66.970377] [drm:intel_power_well_enable [i915]] enabling always-on
>[   66.970449] [drm:intel_power_well_enable [i915]] enabling DC off
>[   66.970755] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[   66.970829] [drm:intel_power_well_enable [i915]] enabling power well 2
>[   66.970893] [drm:skl_set_power_well [i915]] Enabling power well 2
>[   66.971061] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[   66.971149] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[   66.971255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   66.971339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   66.971419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   66.971489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   66.971557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   66.971623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   66.971701] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   66.971778] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   66.971850] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   66.971969] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   66.972102] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[   66.972198] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[   66.972321] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[   66.972412] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[   67.576048] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[   67.576176] [drm:wait_panel_status [i915]] Wait complete
>[   67.576286] [drm:edp_panel_on [i915]] Wait for panel power on
>[   67.576417] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[   67.649389] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   67.649516] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   67.649607] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[   67.649791] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   67.776551] [drm:wait_panel_status [i915]] Wait complete
>[   67.776704] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   67.776853] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   67.778163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[   67.778270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[   67.778350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   67.778428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[   67.779264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[   67.779338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[   67.779408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   67.780202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[   67.780275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[   67.781380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[   67.781687] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc800
>[   67.782366] [drm:intel_enable_pipe [i915]] enabling pipe C
>[   67.782524] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[   67.782639] [drm:intel_panel_enable_backlight [i915]] pipe C
>[   67.782793] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[   67.782926] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[   67.783026] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[   67.799333] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   67.799460] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[   67.799681] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   67.821732] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[   68.266077] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[   68.266252] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[   68.266361] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[   68.266467] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   68.266581] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[   68.471407] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[   68.471552] [drm:intel_disable_pipe [i915]] disabling pipe C
>[   68.482829] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[   68.482964] [drm:edp_panel_off [i915]] Wait for panel power off time
>[   68.483178] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[   68.534635] [drm:wait_panel_status [i915]] Wait complete
>[   68.534775] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[   68.534867] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[   68.534984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   68.535158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   68.535285] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   68.535408] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   68.535513] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[   68.535644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   68.535745] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   68.535862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   68.535965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   68.536070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   68.536207] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   68.536339] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   68.536447] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   68.536556] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   68.536655] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   68.536766] [drm:intel_power_well_disable [i915]] disabling power well 2
>[   68.536876] [drm:skl_set_power_well [i915]] Disabling power well 2
>[   68.536978] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[   68.537106] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[   68.537226] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[   68.537331] [drm:intel_power_well_disable [i915]] disabling DC off
>[   68.537433] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[   68.537532] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[   68.538010] [drm:intel_power_well_disable [i915]] disabling always-on
>[   68.538740] [IGT] kms_busy: exiting, ret=0
>[   68.539016] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[   68.539124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[   68.539234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[   68.539320] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[   68.539419] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[   68.539504] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[   68.539607] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[   68.539691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[   68.539790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[   68.539863] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   68.539956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   68.540018] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   68.540128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   68.540182] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   68.540279] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[   68.540351] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[   68.540439] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   68.540511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   68.540599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   68.540668] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[   68.540753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   68.540822] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[   68.540909] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   68.540976] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[   68.541085] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   68.541211] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[   68.541291] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[   68.541421] [drm:intel_power_well_enable [i915]] enabling always-on
>[   68.541492] [drm:intel_power_well_enable [i915]] enabling DC off
>[   68.541817] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[   68.541916] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[   68.541987] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[   68.542118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   68.542195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   68.542287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   68.542358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   68.542447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   68.542515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   68.542611] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   68.542688] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   68.542777] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   68.542849] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   68.542951] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[   68.543031] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[   68.543167] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[   68.543249] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[   69.111421] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[   69.111513] [drm:wait_panel_status [i915]] Wait complete
>[   69.111609] [drm:edp_panel_on [i915]] Wait for panel power on
>[   69.111752] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[   69.184695] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   69.184785] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   69.184863] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[   69.185092] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   69.313661] [drm:wait_panel_status [i915]] Wait complete
>[   69.313779] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   69.313899] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   69.315138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[   69.315204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[   69.315266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   69.315330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[   69.316086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[   69.316146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[   69.316205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   69.316970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[   69.317031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[   69.318077] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[   69.318339] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc800
>[   69.318905] [drm:intel_enable_pipe [i915]] enabling pipe A
>[   69.318947] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[   69.318962] [drm:intel_panel_enable_backlight [i915]] pipe A
>[   69.319028] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[   69.319080] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[   69.319094] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[   69.335689] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   69.335711] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[   69.335742] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   72.373250] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[   72.378187] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   72.380023] [drm:intel_power_well_disable [i915]] disabling DC off
>[   72.381313] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[   72.382556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[   89.236881] [IGT] kms_busy: executing
>[   89.247528] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1]
>[   89.247556] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[   89.247572] [drm:intel_power_well_enable [i915]] enabling DC off
>[   89.247588] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[   89.247609] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   89.247628] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   89.247644] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   89.247660] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   89.247684] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   89.247743] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   89.248183] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[   89.248553] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[   89.248561] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1] probed modes :
>[   89.248573] [drm:drm_mode_debug_printmodeline [drm]] Modeline 48:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   89.248611] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1]
>[   89.248627] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[   89.248642] [drm:intel_power_well_enable [i915]] enabling power well 2
>[   89.248660] [drm:skl_set_power_well [i915]] Enabling power well 2
>[   89.248718] [drm:intel_power_well_disable [i915]] disabling power well 2
>[   89.248737] [drm:skl_set_power_well [i915]] Disabling power well 2
>[   89.248743] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1] disconnected
>[   89.248770] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1]
>[   89.248787] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[   89.249099] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   89.249126] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   89.249409] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   89.249426] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[   89.249741] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   89.249764] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   89.250062] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   89.250082] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[   89.250088] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] disconnected
>[   89.250158] [IGT] kms_busy: starting subtest basic-flip-default-C
>[   89.252387] [drm:drm_mode_addfb2 [drm]] [FB:64]
>[   89.272287] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[   89.272325] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   89.272356] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[   89.479357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[   89.479503] [drm:intel_disable_pipe [i915]] disabling pipe A
>[   89.497335] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[   89.497470] [drm:edp_panel_off [i915]] Wait for panel power off time
>[   89.497604] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[   89.548715] [drm:wait_panel_status [i915]] Wait complete
>[   89.548856] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[   89.548951] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[   89.549072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   89.549232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   89.549339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   89.549434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   89.549529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   89.549628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   89.549761] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   89.549886] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   89.549995] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   89.550099] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[   89.550248] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   89.550385] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   89.550475] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   89.550570] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   89.550655] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   89.550736] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[   89.550807] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[   89.550894] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[   89.550972] [drm:intel_power_well_disable [i915]] disabling DC off
>[   89.551047] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[   89.551165] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[   89.551663] [drm:intel_power_well_disable [i915]] disabling always-on
>[   89.552247] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[   89.552638] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[   89.552687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[   89.552793] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[   89.552870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[   89.552958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[   89.553038] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[   89.553145] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[   89.553252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[   89.553341] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[   89.553445] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[   89.553558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[   89.553665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   89.553736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   89.553791] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   89.553860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   89.553912] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   89.553983] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[   89.554050] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[   89.554163] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   89.554251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   89.554322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   89.554415] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[   89.554513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   89.554622] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[   89.554722] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[   89.554799] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[   89.554886] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   89.554980] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[   89.555062] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[   89.556654] [drm:intel_power_well_enable [i915]] enabling always-on
>[   89.556726] [drm:intel_power_well_enable [i915]] enabling DC off
>[   89.557028] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[   89.557135] [drm:intel_power_well_enable [i915]] enabling power well 2
>[   89.557222] [drm:skl_set_power_well [i915]] Enabling power well 2
>[   89.557396] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[   89.557499] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[   89.557595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   89.557674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   89.557751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   89.557822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   89.557892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   89.557959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   89.558045] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   89.558168] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   89.558279] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   89.558393] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   89.558514] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[   89.558593] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[   89.558697] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[   89.558780] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[   90.159427] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[   90.159551] [drm:wait_panel_status [i915]] Wait complete
>[   90.159654] [drm:edp_panel_on [i915]] Wait for panel power on
>[   90.159783] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[   90.232764] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   90.232890] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   90.232981] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[   90.233186] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   90.360970] [drm:wait_panel_status [i915]] Wait complete
>[   90.361125] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   90.361261] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   90.362534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[   90.362618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[   90.362687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   90.362759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[   90.363524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[   90.363595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[   90.363664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   90.364468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[   90.364543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[   90.365609] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[   90.365854] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc800
>[   90.366146] [drm:intel_enable_pipe [i915]] enabling pipe C
>[   90.366187] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[   90.366205] [drm:intel_panel_enable_backlight [i915]] pipe C
>[   90.366274] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[   90.366329] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[   90.366346] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[   90.383008] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   90.383068] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[   90.383124] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   90.408319] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[   90.883247] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[   90.883368] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[   90.883445] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[   90.883546] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   90.883652] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[   91.087024] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[   91.087171] [drm:intel_disable_pipe [i915]] disabling pipe C
>[   91.100879] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[   91.101017] [drm:edp_panel_off [i915]] Wait for panel power off time
>[   91.101151] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[   91.152446] [drm:wait_panel_status [i915]] Wait complete
>[   91.152587] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[   91.152678] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[   91.152906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   91.153035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   91.153154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   91.153233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   91.153326] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   91.153414] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   91.153490] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[   91.153581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   91.153683] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   91.153815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   91.153923] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   91.154042] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   91.154135] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   91.154243] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   91.154331] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   91.154432] [drm:intel_power_well_disable [i915]] disabling power well 2
>[   91.154515] [drm:skl_set_power_well [i915]] Disabling power well 2
>[   91.154584] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[   91.154651] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[   91.154778] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[   91.154879] [drm:intel_power_well_disable [i915]] disabling DC off
>[   91.154985] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[   91.155064] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[   91.155545] [drm:intel_power_well_disable [i915]] disabling always-on
>[   91.156290] [IGT] kms_busy: exiting, ret=0
>[   91.156526] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[   91.156595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[   91.156673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[   91.156798] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[   91.156876] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[   91.156963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[   91.157046] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[   91.157124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[   91.157205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[   91.157277] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   91.157348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   91.157407] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   91.157481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   91.157533] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   91.157612] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[   91.157683] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[   91.157771] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   91.157841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   91.157910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   91.157978] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[   91.158047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   91.158115] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[   91.158183] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   91.158250] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[   91.158337] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[   91.158453] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[   91.158547] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[   91.158686] [drm:intel_power_well_enable [i915]] enabling always-on
>[   91.158765] [drm:intel_power_well_enable [i915]] enabling DC off
>[   91.159075] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[   91.159143] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[   91.159198] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[   91.159278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[   91.159343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[   91.159407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[   91.159467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[   91.159525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[   91.159581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[   91.159646] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   91.159709] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[   91.159805] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[   91.159865] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[   91.159942] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[   91.160008] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[   91.160100] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[   91.160174] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[   91.759025] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[   91.759115] [drm:wait_panel_status [i915]] Wait complete
>[   91.759209] [drm:edp_panel_on [i915]] Wait for panel power on
>[   91.759331] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[   91.832302] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   91.832392] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[   91.832469] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[   91.832600] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[   91.960743] [drm:wait_panel_status [i915]] Wait complete
>[   91.960861] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   91.960983] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   91.962268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[   91.962345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[   91.962414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   91.962480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[   91.963251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[   91.963311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[   91.963371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   91.964111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[   91.964172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[   91.965217] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[   91.965478] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc800
>[   91.966134] [drm:intel_enable_pipe [i915]] enabling pipe A
>[   91.966232] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[   91.966297] [drm:intel_panel_enable_backlight [i915]] pipe A
>[   91.966414] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[   91.966518] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[   91.966594] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[   91.983017] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[   91.983101] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[   91.983204] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[   95.022336] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[   95.027507] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   95.029033] [drm:intel_power_well_disable [i915]] disabling DC off
>[   95.030367] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[   95.031558] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  105.279123] [IGT] kms_busy: executing
>[  105.301980] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1]
>[  105.302100] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[  105.302177] [drm:intel_power_well_enable [i915]] enabling DC off
>[  105.302249] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  105.302344] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  105.302429] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  105.302504] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  105.302635] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  105.302771] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  105.302907] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  105.303482] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[  105.304009] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  105.304045] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1] probed modes :
>[  105.304098] [drm:drm_mode_debug_printmodeline [drm]] Modeline 48:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  105.304254] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1]
>[  105.304332] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[  105.304400] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  105.304469] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  105.304690] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  105.304794] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  105.304835] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1] disconnected
>[  105.304976] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1]
>[  105.305055] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  105.305465] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  105.305659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  105.306031] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  105.306106] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  105.306475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  105.306647] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  105.307021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  105.307076] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  105.307108] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] disconnected
>[  105.307341] [IGT] kms_busy: starting subtest basic-flip-default-A
>[  105.316667] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  105.346947] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  105.346963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  105.378518] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  105.378565] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  105.380703] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  105.828769] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  105.828895] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  105.829008] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  106.036760] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  106.036931] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  106.046090] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  106.046224] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  106.046358] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  106.098025] [drm:wait_panel_status [i915]] Wait complete
>[  106.098164] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  106.098256] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  106.098375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  106.098556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  106.098687] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  106.098815] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  106.098913] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  106.099048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  106.099151] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  106.099268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  106.099372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  106.099494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  106.099618] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  106.099734] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  106.099851] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  106.099954] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  106.100055] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  106.100165] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  106.100269] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  106.100383] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  106.100526] [drm:intel_power_well_disable [i915]] disabling DC off
>[  106.100642] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  106.100743] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  106.101223] [drm:intel_power_well_disable [i915]] disabling always-on
>[  106.101810] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  106.102216] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  106.102878] [IGT] kms_busy: starting subtest flip-render-A
>[  106.105134] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  106.115532] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  106.115546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  106.115582] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  106.115599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  106.115617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  106.115633] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  106.115647] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  106.115663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  106.115680] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  106.115694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  106.115709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  106.115722] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  106.115734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  106.115745] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  106.115758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  106.115767] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  106.115781] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  106.115794] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  106.115806] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  106.115818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  106.115830] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  106.115842] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  106.115853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  106.115865] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  106.115876] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  106.115888] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  106.115903] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  106.115923] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  106.115938] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  106.116247] [drm:intel_power_well_enable [i915]] enabling always-on
>[  106.116259] [drm:intel_power_well_enable [i915]] enabling DC off
>[  106.116522] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  106.116547] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  106.116565] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  106.116590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  106.116613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  106.116633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  106.116654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  106.116673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  106.116691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  106.116711] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  106.116731] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  106.116751] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  106.116770] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  106.116792] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[  106.116812] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  106.116839] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  106.116865] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  106.668669] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  106.668764] [drm:wait_panel_status [i915]] Wait complete
>[  106.668873] [drm:edp_panel_on [i915]] Wait for panel power on
>[  106.668993] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  106.741848] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  106.741973] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  106.742063] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  106.742228] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  106.869245] [drm:wait_panel_status [i915]] Wait complete
>[  106.869443] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  106.869577] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  106.870834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  106.870913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  106.870982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  106.871052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  106.871826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  106.871898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  106.871964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  106.872755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  106.872828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  106.873883] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  106.874155] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc800
>[  106.874838] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  106.874886] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  106.874904] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  106.874973] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  106.875028] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  106.875044] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  106.891637] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  106.891670] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  106.891711] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  106.908524] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  106.908667] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  106.917233] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  107.391864] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  107.391968] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  107.392063] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  107.596571] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  107.596742] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  107.610510] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  107.610644] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  107.610778] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[  107.662047] [drm:wait_panel_status [i915]] Wait complete
>[  107.662188] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  107.662374] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  107.662554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  107.662702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  107.662828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  107.662946] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  107.663064] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  107.663170] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  107.663333] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  107.663457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  107.663574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  107.663684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  107.663800] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  107.663918] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  107.664023] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  107.664126] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  107.664230] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  107.664386] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  107.664491] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  107.664606] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  107.664715] [drm:intel_power_well_disable [i915]] disabling DC off
>[  107.664820] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  107.664918] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  107.665427] [drm:intel_power_well_disable [i915]] disabling always-on
>[  107.665951] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  107.666407] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  107.666887] [IGT] kms_busy: starting subtest flip-bsd-A
>[  107.669098] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  107.679363] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  107.679377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  107.679414] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  107.679431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  107.679449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  107.679466] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  107.679480] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  107.679497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  107.679514] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  107.679528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  107.679543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  107.679556] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  107.679569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  107.679579] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  107.679592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  107.679603] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  107.679617] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  107.679630] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  107.679642] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  107.679654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  107.679666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  107.679678] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  107.679690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  107.679701] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  107.679713] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  107.679725] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  107.679741] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  107.679760] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  107.679775] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  107.680088] [drm:intel_power_well_enable [i915]] enabling always-on
>[  107.680100] [drm:intel_power_well_enable [i915]] enabling DC off
>[  107.680362] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  107.680389] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  107.680407] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  107.680432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  107.680453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  107.680475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  107.680494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  107.680509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  107.680528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  107.680548] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  107.680569] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  107.680588] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  107.680608] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  107.680631] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[  107.680651] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  107.680677] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  107.680702] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  108.268568] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  108.268694] [drm:wait_panel_status [i915]] Wait complete
>[  108.268801] [drm:edp_panel_on [i915]] Wait for panel power on
>[  108.268932] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  108.341896] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  108.342021] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  108.342112] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  108.342306] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  108.469874] [drm:wait_panel_status [i915]] Wait complete
>[  108.470042] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  108.470310] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  108.471861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  108.471964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  108.472042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  108.472115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  108.472920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  108.472991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  108.473057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  108.473880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  108.473954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  108.475064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  108.475372] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc000
>[  108.476018] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  108.476127] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  108.476262] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  108.476427] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  108.476561] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  108.476661] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  108.493028] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  108.493165] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  108.493426] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  108.509745] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  108.509914] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  108.515734] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  108.959802] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  108.959927] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  108.960044] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  109.164350] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  109.164496] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  109.178206] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  109.178341] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  109.178474] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  109.229888] [drm:wait_panel_status [i915]] Wait complete
>[  109.230028] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  109.230211] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  109.230392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  109.230522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  109.230643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  109.230759] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  109.230878] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  109.230985] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  109.231156] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  109.231282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  109.231393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  109.231493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  109.231605] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  109.231714] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  109.231820] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  109.231929] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  109.232033] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  109.232170] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  109.232289] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  109.232408] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  109.232517] [drm:intel_power_well_disable [i915]] disabling DC off
>[  109.232618] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  109.232717] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  109.233225] [drm:intel_power_well_disable [i915]] disabling always-on
>[  109.233758] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  109.234202] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  109.234803] [IGT] kms_busy: starting subtest flip-bsd1-A
>[  109.234958] [IGT] kms_busy: starting subtest flip-bsd2-A
>[  109.235130] [IGT] kms_busy: starting subtest flip-blt-A
>[  109.240102] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  109.249255] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  109.249269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  109.249306] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  109.249324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  109.249342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  109.249358] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  109.249372] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  109.249388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  109.249405] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  109.249419] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  109.249433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  109.249446] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  109.249459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  109.249469] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  109.249482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  109.249491] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  109.249505] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  109.249517] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  109.249529] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  109.249541] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  109.249553] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  109.249564] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  109.249576] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  109.249589] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  109.249601] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  109.249612] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  109.249628] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  109.249649] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  109.249663] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  109.249979] [drm:intel_power_well_enable [i915]] enabling always-on
>[  109.249992] [drm:intel_power_well_enable [i915]] enabling DC off
>[  109.250256] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  109.250278] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  109.250295] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  109.250319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  109.250339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  109.250359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  109.250378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  109.250396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  109.250414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  109.250434] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  109.250454] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  109.250473] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  109.250492] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  109.250514] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[  109.250534] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  109.250561] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  109.250587] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  109.804401] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  109.804526] [drm:wait_panel_status [i915]] Wait complete
>[  109.804633] [drm:edp_panel_on [i915]] Wait for panel power on
>[  109.804766] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  109.877728] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  109.877852] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  109.877942] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  109.878125] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  110.005307] [drm:wait_panel_status [i915]] Wait complete
>[  110.005460] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  110.005601] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  110.006927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  110.007052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  110.007132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  110.007207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  110.007957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  110.008073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  110.008189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  110.008962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  110.009079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  110.010165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  110.010442] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fe800
>[  110.010955] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  110.010995] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  110.011022] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  110.011093] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  110.011148] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  110.011165] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  110.027790] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  110.027840] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  110.027887] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  110.044566] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  110.044674] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  110.051384] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  110.528101] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  110.528219] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  110.528328] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  110.732226] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  110.732393] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  110.746103] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  110.746240] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  110.746375] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  110.797499] [drm:wait_panel_status [i915]] Wait complete
>[  110.797639] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  110.797731] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  110.797849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  110.798035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  110.798164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  110.798272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  110.798369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  110.798475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  110.798588] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  110.798708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  110.798813] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  110.798973] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  110.799102] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  110.799221] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  110.799329] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  110.799431] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  110.799533] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  110.799646] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  110.799750] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  110.799876] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  110.800008] [drm:intel_power_well_disable [i915]] disabling DC off
>[  110.800123] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  110.800226] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  110.800715] [drm:intel_power_well_disable [i915]] disabling always-on
>[  110.801300] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  110.801703] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  110.802392] [IGT] kms_busy: starting subtest flip-vebox-A
>[  110.808880] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  110.818671] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  110.818684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  110.818722] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  110.818738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  110.818757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  110.818772] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  110.818786] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  110.818802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  110.818818] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  110.818833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  110.818854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  110.818868] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  110.818880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  110.818896] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  110.818911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  110.818925] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  110.818942] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  110.818960] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  110.818982] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  110.819000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  110.819018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  110.819037] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  110.819050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  110.819061] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  110.819073] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  110.819085] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  110.819101] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  110.819120] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  110.819134] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  110.819442] [drm:intel_power_well_enable [i915]] enabling always-on
>[  110.819456] [drm:intel_power_well_enable [i915]] enabling DC off
>[  110.819706] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  110.819722] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  110.819734] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  110.819752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  110.819766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  110.819779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  110.819792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  110.819804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  110.819816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  110.819830] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  110.819853] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  110.819867] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  110.819879] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  110.819901] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[  110.819920] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  110.819948] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  110.819976] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  111.404252] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  111.404377] [drm:wait_panel_status [i915]] Wait complete
>[  111.404483] [drm:edp_panel_on [i915]] Wait for panel power on
>[  111.404615] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  111.477581] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  111.477705] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  111.477794] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  111.477988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  111.605621] [drm:wait_panel_status [i915]] Wait complete
>[  111.605819] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  111.606047] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  111.607334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  111.607430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  111.607518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  111.607595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  111.608401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  111.608478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  111.608548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  111.609344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  111.609422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  111.610484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  111.610756] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671ff000
>[  111.611106] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  111.611154] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  111.611172] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  111.611241] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  111.611296] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  111.611313] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  111.627914] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  111.627954] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  111.628004] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  111.644779] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  111.644976] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  111.653759] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  112.128176] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  112.128280] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  112.128376] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  112.332016] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  112.332162] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  112.345862] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  112.345996] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  112.346130] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  112.397537] [drm:wait_panel_status [i915]] Wait complete
>[  112.397677] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  112.397842] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  112.398010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  112.398148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  112.398265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  112.398359] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  112.398456] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  112.398531] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  112.398640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  112.398725] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  112.398878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  112.398984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  112.399108] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  112.399230] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  112.399333] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  112.399417] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  112.399497] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  112.399589] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  112.399672] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  112.399815] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  112.399922] [drm:intel_power_well_disable [i915]] disabling DC off
>[  112.400032] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  112.400133] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  112.400594] [drm:intel_power_well_disable [i915]] disabling always-on
>[  112.400805] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  112.401195] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  112.401876] [IGT] kms_busy: starting subtest basic-flip-default-B
>[  112.404734] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  112.414657] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  112.414916] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  112.414925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  112.414957] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  112.414973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  112.414992] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  112.415008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  112.415023] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  112.415037] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  112.415052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  112.415067] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  112.415081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  112.415095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  112.415109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  112.415121] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  112.415132] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  112.415144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  112.415153] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  112.415167] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  112.415179] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  112.415191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  112.415203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  112.415215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  112.415226] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  112.415238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  112.415249] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  112.415260] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  112.415272] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  112.415288] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  112.415307] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 0
>[  112.415321] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[  112.415628] [drm:intel_power_well_enable [i915]] enabling always-on
>[  112.415641] [drm:intel_power_well_enable [i915]] enabling DC off
>[  112.415898] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  112.415914] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  112.415927] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  112.415951] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  112.415983] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  112.416006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  112.416027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  112.416050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  112.416071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  112.416090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  112.416108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  112.416128] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  112.416144] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  112.416158] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  112.416171] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  112.416188] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 38
>[  112.416201] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  112.416225] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  112.416245] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  113.004043] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  113.004169] [drm:wait_panel_status [i915]] Wait complete
>[  113.004277] [drm:edp_panel_on [i915]] Wait for panel power on
>[  113.004409] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  113.077373] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  113.077500] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  113.077590] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  113.077746] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  113.205712] [drm:wait_panel_status [i915]] Wait complete
>[  113.205866] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  113.206000] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  113.207275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  113.207362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  113.207432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  113.207504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  113.208265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  113.208336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  113.208402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  113.209180] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  113.209254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  113.210315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  113.210589] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fe000
>[  113.211038] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  113.211077] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  113.211095] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  113.211163] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  113.211218] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  113.211235] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  113.227880] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  113.227930] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  113.227977] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  113.244672] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  113.251477] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  113.728100] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  113.728205] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  113.728294] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  113.728389] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  113.931885] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  113.932053] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  113.945769] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  113.945905] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  113.946040] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  113.997392] [drm:wait_panel_status [i915]] Wait complete
>[  113.997532] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 38
>[  113.997696] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  113.997856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  113.997982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  113.998113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  113.998209] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  113.998299] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  113.998373] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  113.998468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  113.998572] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  113.998708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  113.998785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  113.998873] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  113.998962] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  113.999045] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  113.999126] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  113.999202] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  113.999292] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  113.999398] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  113.999472] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  113.999555] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  113.999669] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  113.999745] [drm:intel_power_well_disable [i915]] disabling DC off
>[  113.999822] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  113.999894] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  114.000364] [drm:intel_power_well_disable [i915]] disabling always-on
>[  114.000540] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  114.001132] [IGT] kms_busy: starting subtest flip-render-B
>[  114.004680] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  114.014965] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  114.015238] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  114.015247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  114.015280] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  114.015296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  114.015315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  114.015330] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  114.015344] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  114.015360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  114.015377] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  114.015391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  114.015406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  114.015419] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  114.015431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  114.015442] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  114.015455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  114.015464] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  114.015478] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  114.015490] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  114.015513] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  114.015527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  114.015540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  114.015560] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  114.015577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  114.015602] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  114.015619] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  114.015634] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  114.015655] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  114.015682] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 0
>[  114.015703] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[  114.016013] [drm:intel_power_well_enable [i915]] enabling always-on
>[  114.016027] [drm:intel_power_well_enable [i915]] enabling DC off
>[  114.016277] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  114.016292] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  114.016305] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  114.016322] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  114.016334] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  114.016351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  114.016365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  114.016381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  114.016393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  114.016406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  114.016417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  114.016432] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  114.016446] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  114.016459] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  114.016472] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  114.016488] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 38
>[  114.016502] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  114.016534] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  114.016563] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  114.603900] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  114.604028] [drm:wait_panel_status [i915]] Wait complete
>[  114.604135] [drm:edp_panel_on [i915]] Wait for panel power on
>[  114.604266] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  114.677244] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  114.677368] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  114.677457] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  114.677616] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  114.804561] [drm:wait_panel_status [i915]] Wait complete
>[  114.804714] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  114.804844] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  114.806123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  114.806207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  114.806278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  114.806348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  114.807112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  114.807183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  114.807251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  114.808063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  114.808138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  114.809196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  114.809467] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc000
>[  114.809968] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  114.810017] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  114.810035] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  114.810104] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  114.810159] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  114.810176] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  114.826819] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  114.826892] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  114.826948] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  114.843640] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  114.852233] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  115.327071] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  115.327191] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  115.327290] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  115.327394] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  115.531726] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  115.531896] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  115.545287] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  115.545465] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  115.545636] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[  115.597200] [drm:wait_panel_status [i915]] Wait complete
>[  115.597341] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 38
>[  115.597595] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  115.597727] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  115.597862] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  115.597943] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  115.598071] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  115.598161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  115.598251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  115.598336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  115.598450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  115.598540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  115.598629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  115.598722] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  115.598813] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  115.598896] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  115.598982] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  115.599061] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  115.599157] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  115.599251] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  115.599353] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  115.599458] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  115.599564] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  115.599670] [drm:intel_power_well_disable [i915]] disabling DC off
>[  115.599778] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  115.599888] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  115.600376] [drm:intel_power_well_disable [i915]] disabling always-on
>[  115.600937] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  115.601516] [IGT] kms_busy: starting subtest flip-bsd-B
>[  115.604710] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  115.614322] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  115.614610] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  115.614624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  115.614660] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  115.614683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  115.614708] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  115.614729] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  115.614749] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  115.614770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  115.614792] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  115.614812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  115.614832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  115.614852] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  115.614870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  115.614886] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  115.614904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  115.614918] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  115.614934] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  115.614952] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  115.614971] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  115.614990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  115.615008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  115.615026] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  115.615044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  115.615062] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  115.615080] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  115.615097] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  115.615118] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  115.615142] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 0
>[  115.615162] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[  115.615482] [drm:intel_power_well_enable [i915]] enabling always-on
>[  115.615495] [drm:intel_power_well_enable [i915]] enabling DC off
>[  115.615746] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  115.615761] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  115.615774] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  115.615811] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  115.615823] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  115.615840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  115.615855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  115.615869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  115.615881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  115.615893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  115.615906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  115.615920] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  115.615935] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  115.615949] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  115.615963] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  115.615979] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 38
>[  115.615993] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  115.616015] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  115.616036] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  116.203736] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  116.203863] [drm:wait_panel_status [i915]] Wait complete
>[  116.203970] [drm:edp_panel_on [i915]] Wait for panel power on
>[  116.204100] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  116.277077] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  116.277202] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  116.277293] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  116.277482] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  116.405416] [drm:wait_panel_status [i915]] Wait complete
>[  116.405569] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  116.405712] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  116.407021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  116.407127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  116.407206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  116.407283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  116.408101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  116.408176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  116.408244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  116.409040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  116.409115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  116.410224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  116.410603] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fe000
>[  116.411306] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  116.411539] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  116.411664] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  116.411812] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  116.411960] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  116.412063] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  116.428457] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  116.428593] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  116.428723] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  116.445115] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  116.450784] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  116.895114] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  116.895218] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  116.895376] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  116.895497] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  117.099591] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  117.099759] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  117.113526] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  117.113661] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  117.113795] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[  117.165077] [drm:wait_panel_status [i915]] Wait complete
>[  117.165219] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 38
>[  117.165403] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  117.165587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  117.165736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  117.165852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  117.165968] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  117.166087] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  117.166192] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  117.166334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  117.166435] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  117.166559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  117.166668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  117.166782] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  117.166901] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  117.167007] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  117.167111] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  117.167216] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  117.167348] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  117.167479] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  117.167583] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  117.167685] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  117.167800] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  117.167903] [drm:intel_power_well_disable [i915]] disabling DC off
>[  117.168005] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  117.168103] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  117.168606] [drm:intel_power_well_disable [i915]] disabling always-on
>[  117.169136] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  117.169760] [IGT] kms_busy: starting subtest flip-bsd1-B
>[  117.169894] [IGT] kms_busy: starting subtest flip-bsd2-B
>[  117.169978] [IGT] kms_busy: starting subtest flip-blt-B
>[  117.175818] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  117.185065] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  117.185354] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  117.185367] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  117.185406] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  117.185423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  117.185442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  117.185458] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  117.185472] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  117.185488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  117.185506] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  117.185521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  117.185536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  117.185549] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  117.185562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  117.185572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  117.185586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  117.185595] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  117.185609] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  117.185622] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  117.185635] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  117.185648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  117.185660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  117.185672] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  117.185683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  117.185696] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  117.185708] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  117.185720] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  117.185736] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  117.185755] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 0
>[  117.185770] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[  117.186076] [drm:intel_power_well_enable [i915]] enabling always-on
>[  117.186089] [drm:intel_power_well_enable [i915]] enabling DC off
>[  117.186349] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  117.186369] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  117.186386] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  117.186410] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  117.186442] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  117.186465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  117.186485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  117.186500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  117.186512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  117.186525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  117.186537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  117.186558] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  117.186573] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  117.186586] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  117.186599] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  117.186616] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 38
>[  117.186630] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  117.186653] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  117.186674] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  117.739622] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  117.739751] [drm:wait_panel_status [i915]] Wait complete
>[  117.739858] [drm:edp_panel_on [i915]] Wait for panel power on
>[  117.739988] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  117.812957] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  117.813081] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  117.813172] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  117.813362] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  117.941120] [drm:wait_panel_status [i915]] Wait complete
>[  117.941326] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  117.941472] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  117.942810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  117.942915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  117.942994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  117.943069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  117.943849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  117.943925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  117.943994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  117.944793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  117.944871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  117.945929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  117.946267] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fe800
>[  117.946883] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  117.946931] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  117.946948] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  117.947016] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  117.947070] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  117.947086] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  117.963741] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  117.963787] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  117.963831] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  117.980378] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  117.986540] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  118.463983] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  118.464182] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  118.464318] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  118.464456] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  118.667396] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  118.667542] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  118.681249] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  118.681386] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  118.681523] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  118.732929] [drm:wait_panel_status [i915]] Wait complete
>[  118.733069] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 38
>[  118.733249] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  118.733439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  118.733604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  118.733730] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  118.733854] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  118.733961] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  118.734102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  118.734211] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  118.734347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  118.734425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  118.734522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  118.734612] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  118.734717] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  118.734800] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  118.734897] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  118.734976] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  118.735081] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  118.735200] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  118.735312] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  118.735413] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  118.735535] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  118.735641] [drm:intel_power_well_disable [i915]] disabling DC off
>[  118.735745] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  118.735844] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  118.736350] [drm:intel_power_well_disable [i915]] disabling always-on
>[  118.736881] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  118.737526] [IGT] kms_busy: starting subtest flip-vebox-B
>[  118.739980] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  118.750246] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  118.750517] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  118.750526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  118.750558] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  118.750575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  118.750593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  118.750608] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  118.750622] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  118.750638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  118.750654] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  118.750669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  118.750683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  118.750697] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  118.750709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  118.750720] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  118.750733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  118.750742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  118.750755] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  118.750767] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  118.750779] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  118.750791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  118.750802] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  118.750815] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  118.750826] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  118.750839] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  118.750850] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  118.750861] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  118.750877] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  118.750895] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 0
>[  118.750910] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[  118.751232] [drm:intel_power_well_enable [i915]] enabling always-on
>[  118.751251] [drm:intel_power_well_enable [i915]] enabling DC off
>[  118.751508] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  118.751530] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  118.751548] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  118.751593] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  118.751611] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  118.751634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  118.751656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  118.751676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  118.751695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  118.751714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  118.751732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  118.751753] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  118.751773] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  118.751793] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  118.751812] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  118.751835] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 38
>[  118.751854] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  118.751881] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  118.751907] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  119.339478] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  119.339603] [drm:wait_panel_status [i915]] Wait complete
>[  119.339710] [drm:edp_panel_on [i915]] Wait for panel power on
>[  119.339840] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  119.412815] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  119.412941] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  119.413033] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  119.413219] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  119.540999] [drm:wait_panel_status [i915]] Wait complete
>[  119.541212] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  119.541351] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  119.542661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  119.542766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  119.542845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  119.542921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  119.543704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  119.543780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  119.543847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  119.544640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  119.544718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  119.545780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  119.546119] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671ff000
>[  119.546792] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  119.546843] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  119.546860] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  119.546928] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  119.546992] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  119.547019] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  119.563649] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  119.563696] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  119.563739] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  119.580420] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  119.586605] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  120.063845] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  120.064041] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  120.064167] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  120.064299] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  120.267295] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  120.267465] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  120.281147] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  120.281283] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  120.281418] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[  120.332754] [drm:wait_panel_status [i915]] Wait complete
>[  120.332895] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 38
>[  120.333078] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  120.333264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  120.333413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  120.333532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  120.333649] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  120.333768] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  120.333875] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  120.334034] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  120.334157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  120.334273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  120.334387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  120.334501] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  120.334620] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  120.334727] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  120.334830] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  120.334932] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  120.335066] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  120.335191] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  120.335295] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  120.335395] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  120.335511] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  120.335617] [drm:intel_power_well_disable [i915]] disabling DC off
>[  120.335719] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  120.335820] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  120.336323] [drm:intel_power_well_disable [i915]] disabling always-on
>[  120.336860] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  120.337439] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  120.340045] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  120.350789] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  120.351076] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  120.351106] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  120.351119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  120.351158] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  120.351181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  120.351206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  120.351228] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  120.351250] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  120.351272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  120.351296] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  120.351317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  120.351338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  120.351358] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  120.351377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  120.351393] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  120.351413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  120.351427] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  120.351444] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  120.351464] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  120.351484] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  120.351503] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  120.351522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  120.351540] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  120.351558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  120.351577] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  120.351596] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  120.351614] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  120.351635] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  120.351660] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[  120.351681] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[  120.352022] [drm:intel_power_well_enable [i915]] enabling always-on
>[  120.352035] [drm:intel_power_well_enable [i915]] enabling DC off
>[  120.352286] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  120.352301] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  120.352313] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  120.352343] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  120.352362] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  120.352379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  120.352393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  120.352407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  120.352419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  120.352432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  120.352443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  120.352458] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  120.352472] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  120.352485] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  120.352498] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  120.352514] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[  120.352528] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  120.352550] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  120.352571] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  120.939314] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  120.939440] [drm:wait_panel_status [i915]] Wait complete
>[  120.939547] [drm:edp_panel_on [i915]] Wait for panel power on
>[  120.939680] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  121.012648] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  121.012773] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  121.012861] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  121.013022] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  121.140998] [drm:wait_panel_status [i915]] Wait complete
>[  121.141147] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  121.141301] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  121.142607] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  121.142711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  121.142792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  121.142868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  121.143668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  121.143741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  121.143810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  121.144587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  121.144662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  121.145752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  121.146060] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fe800
>[  121.146745] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  121.146845] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  121.146871] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  121.146946] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  121.147004] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  121.147020] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  121.163593] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  121.163642] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  121.163686] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  121.186273] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  121.663877] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  121.663999] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  121.664078] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  121.664175] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  121.664279] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  121.867109] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  121.867258] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  121.880958] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  121.881095] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  121.881228] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  121.932647] [drm:wait_panel_status [i915]] Wait complete
>[  121.932785] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[  121.932947] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  121.933108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  121.933240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  121.933372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  121.933465] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  121.933561] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  121.933636] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  121.933740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  121.933825] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  121.933976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  121.934072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  121.934195] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  121.934327] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  121.934435] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  121.934521] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  121.934607] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  121.934712] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  121.934813] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  121.934939] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  121.935039] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  121.935163] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  121.935265] [drm:intel_power_well_disable [i915]] disabling DC off
>[  121.935343] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  121.935418] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  121.935913] [drm:intel_power_well_disable [i915]] disabling always-on
>[  121.936593] [IGT] kms_busy: starting subtest flip-render-C
>[  121.939659] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  121.949249] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  121.949522] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  121.949542] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  121.949551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  121.949583] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  121.949600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  121.949617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  121.949633] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  121.949647] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  121.949662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  121.949678] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  121.949692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  121.949706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  121.949719] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  121.949731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  121.949741] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  121.949754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  121.949774] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  121.949792] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  121.949809] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  121.949828] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  121.949845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  121.949864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  121.949883] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  121.949896] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  121.949910] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  121.949925] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  121.949940] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  121.949956] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  121.949976] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[  121.949991] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[  121.950289] [drm:intel_power_well_enable [i915]] enabling always-on
>[  121.950301] [drm:intel_power_well_enable [i915]] enabling DC off
>[  121.950551] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  121.950566] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  121.950578] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  121.950596] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  121.950626] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  121.950643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  121.950657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  121.950671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  121.950684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  121.950695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  121.950707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  121.950721] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  121.950735] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  121.950748] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  121.950769] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  121.950790] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[  121.950809] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  121.950841] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  121.950866] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  122.539140] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  122.539266] [drm:wait_panel_status [i915]] Wait complete
>[  122.539372] [drm:edp_panel_on [i915]] Wait for panel power on
>[  122.539503] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  122.612503] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  122.612629] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  122.612721] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  122.612879] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  122.740850] [drm:wait_panel_status [i915]] Wait complete
>[  122.741001] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  122.741133] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  122.742385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  122.742466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  122.742536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  122.742606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  122.743393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  122.743467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  122.743533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  122.744293] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  122.744367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  122.745432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  122.745707] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671ff000
>[  122.746077] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  122.746103] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  122.746121] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  122.746189] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  122.746243] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  122.746259] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  122.762893] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  122.762942] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  122.762994] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  122.787890] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  123.263078] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  123.263188] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  123.263254] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  123.263336] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  123.263425] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  123.466790] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  123.466930] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  123.480252] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  123.480369] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  123.480491] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  123.531470] [drm:wait_panel_status [i915]] Wait complete
>[  123.531611] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[  123.531778] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  123.531940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  123.532064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  123.532179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  123.532256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  123.532330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  123.532397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  123.532479] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  123.532560] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  123.532635] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  123.532768] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  123.532884] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  123.532994] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  123.533116] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  123.533200] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  123.533322] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  123.533437] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  123.533529] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  123.533606] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  123.533717] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  123.533849] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  123.533957] [drm:intel_power_well_disable [i915]] disabling DC off
>[  123.534057] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  123.534130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  123.534584] [drm:intel_power_well_disable [i915]] disabling always-on
>[  123.534930] [IGT] kms_busy: starting subtest flip-bsd-C
>[  123.538578] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  123.548395] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  123.548677] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  123.548708] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  123.548723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  123.548756] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  123.548773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  123.548793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  123.548809] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  123.548824] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  123.548840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  123.548857] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  123.548873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  123.548887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  123.548901] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  123.548914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  123.548925] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  123.548938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  123.548948] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  123.548963] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  123.548976] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  123.548989] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  123.549002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  123.549015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  123.549027] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  123.549039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  123.549052] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  123.549064] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  123.549076] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  123.549093] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  123.549112] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[  123.549127] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[  123.549441] [drm:intel_power_well_enable [i915]] enabling always-on
>[  123.549454] [drm:intel_power_well_enable [i915]] enabling DC off
>[  123.549711] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  123.549732] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  123.549748] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  123.549788] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  123.549815] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  123.549844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  123.549866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  123.549888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  123.549906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  123.549920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  123.549933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  123.549948] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  123.549964] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  123.549978] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  123.549991] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  123.550009] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[  123.550023] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  123.550047] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  123.550068] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  124.139013] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  124.139138] [drm:wait_panel_status [i915]] Wait complete
>[  124.139241] [drm:edp_panel_on [i915]] Wait for panel power on
>[  124.139370] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  124.212358] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  124.212485] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  124.212574] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  124.212768] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  124.340710] [drm:wait_panel_status [i915]] Wait complete
>[  124.340864] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  124.340999] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  124.342273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  124.342358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  124.342429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  124.342498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  124.343260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  124.343332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  124.343397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  124.344158] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  124.344231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  124.345293] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  124.345566] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671ff800
>[  124.346024] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  124.346055] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  124.346072] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  124.346142] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  124.346197] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  124.346213] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  124.362857] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  124.362907] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  124.362953] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  124.386106] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  124.863084] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  124.863212] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  124.863290] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  124.863394] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  124.863502] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  125.066868] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  125.067037] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  125.080757] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  125.080893] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  125.081028] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  125.132344] [drm:wait_panel_status [i915]] Wait complete
>[  125.132485] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[  125.132651] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  125.132812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  125.132943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  125.133067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  125.133176] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  125.133249] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  125.133318] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  125.133458] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  125.133533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  125.133661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  125.133758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  125.133850] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  125.133959] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  125.134074] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  125.134192] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  125.134301] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  125.134395] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  125.134479] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  125.134594] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  125.134668] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  125.134792] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  125.134895] [drm:intel_power_well_disable [i915]] disabling DC off
>[  125.134968] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  125.135036] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  125.135493] [drm:intel_power_well_disable [i915]] disabling always-on
>[  125.136205] [IGT] kms_busy: starting subtest flip-bsd1-C
>[  125.136309] [IGT] kms_busy: starting subtest flip-bsd2-C
>[  125.136392] [IGT] kms_busy: starting subtest flip-blt-C
>[  125.142738] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  125.152137] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  125.152410] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  125.152429] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  125.152438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  125.152472] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  125.152488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  125.152519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  125.152543] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  125.152561] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  125.152586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  125.152605] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  125.152625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  125.152646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  125.152665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  125.152683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  125.152699] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  125.152715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  125.152729] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  125.152745] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  125.152764] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  125.152783] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  125.152801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  125.152818] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  125.152836] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  125.152854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  125.152871] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  125.152889] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  125.152906] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  125.152927] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  125.152952] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[  125.152972] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[  125.153292] [drm:intel_power_well_enable [i915]] enabling always-on
>[  125.153305] [drm:intel_power_well_enable [i915]] enabling DC off
>[  125.153566] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  125.153591] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  125.153612] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  125.153638] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  125.153666] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  125.153689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  125.153709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  125.153729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  125.153748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  125.153766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  125.153784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  125.153804] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  125.153825] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  125.153844] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  125.153864] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  125.153886] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[  125.153906] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  125.153932] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  125.153958] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  125.738884] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  125.739011] [drm:wait_panel_status [i915]] Wait complete
>[  125.739118] [drm:edp_panel_on [i915]] Wait for panel power on
>[  125.739250] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  125.812230] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  125.812355] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  125.812444] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  125.812640] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  125.940479] [drm:wait_panel_status [i915]] Wait complete
>[  125.940682] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  125.940827] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  125.942154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  125.942254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  125.942330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  125.942407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  125.943314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  125.943418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  125.943638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  125.944451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  125.944667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  125.945804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  125.946022] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671fc800
>[  125.946306] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  125.946334] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  125.946354] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  125.946423] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  125.946507] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  125.946533] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  125.963189] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  125.963268] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  125.963342] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  125.988901] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  126.463382] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  126.463543] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  126.463625] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  126.463728] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  126.463835] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  126.666684] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  126.666815] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  126.680408] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  126.680587] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  126.680723] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control abcd0000
>[  126.732234] [drm:wait_panel_status [i915]] Wait complete
>[  126.732374] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[  126.732558] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  126.732741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  126.732892] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  126.732984] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  126.733083] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  126.733235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  126.733347] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  126.733521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  126.733634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  126.733740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  126.733839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  126.733951] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  126.734062] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  126.734171] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  126.734275] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  126.734380] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  126.734516] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  126.734650] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  126.734757] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  126.734866] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  126.734981] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  126.735085] [drm:intel_power_well_disable [i915]] disabling DC off
>[  126.735189] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  126.735289] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  126.735795] [drm:intel_power_well_disable [i915]] disabling always-on
>[  126.736521] [IGT] kms_busy: starting subtest flip-vebox-C
>[  126.739730] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  126.749774] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  126.750046] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  126.750065] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  126.750074] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  126.750106] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  126.750124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  126.750142] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  126.750157] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  126.750171] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  126.750186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  126.750202] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  126.750217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  126.750231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  126.750245] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  126.750257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  126.750267] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  126.750280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  126.750289] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  126.750302] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  126.750315] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  126.750327] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  126.750338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  126.750350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  126.750374] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  126.750391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  126.750409] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  126.750430] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  126.750450] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  126.750473] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  126.750501] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[  126.750522] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[  126.750846] [drm:intel_power_well_enable [i915]] enabling always-on
>[  126.750865] [drm:intel_power_well_enable [i915]] enabling DC off
>[  126.751121] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  126.751142] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  126.751161] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  126.751199] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  126.751224] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  126.751247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  126.751268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  126.751287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  126.751307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  126.751325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  126.751344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  126.751371] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  126.751391] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  126.751414] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  126.751435] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  126.751458] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[  126.751478] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  126.751509] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  126.751533] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  127.338772] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  127.338897] [drm:wait_panel_status [i915]] Wait complete
>[  127.339002] [drm:edp_panel_on [i915]] Wait for panel power on
>[  127.339132] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  127.412085] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  127.412210] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  127.412302] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  127.412468] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  127.541378] [drm:wait_panel_status [i915]] Wait complete
>[  127.541583] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  127.541716] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  127.542974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  127.543054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  127.543124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  127.543195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  127.544008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  127.544084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  127.544151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  127.544943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  127.545018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  127.546075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  127.546346] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671ff000
>[  127.546948] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  127.546988] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  127.547006] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  127.547075] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  127.547130] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  127.547147] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  127.563790] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  127.563839] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  127.563886] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  127.587722] [drm:drm_mode_addfb2 [drm]] [FB:65]
>[  128.064008] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  128.064130] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  128.064211] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  128.064307] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  128.064506] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  128.266589] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  128.266761] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  128.280479] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  128.280614] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  128.280747] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control abcd0000
>[  128.332075] [drm:wait_panel_status [i915]] Wait complete
>[  128.332215] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[  128.332397] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  128.332578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  128.332728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  128.332847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  128.332963] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  128.333084] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  128.333191] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  128.333358] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  128.333436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  128.333521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  128.333621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  128.333710] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  128.333813] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  128.333898] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  128.333996] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  128.334071] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  128.334177] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  128.334268] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  128.334379] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  128.334455] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  128.334562] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  128.334640] [drm:intel_power_well_disable [i915]] disabling DC off
>[  128.334734] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  128.334810] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  128.335280] [drm:intel_power_well_disable [i915]] disabling always-on
>[  128.335987] [IGT] kms_busy: exiting, ret=0
>[  128.336274] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  128.336397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  128.336488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  128.336589] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  128.336668] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  128.336769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  128.336847] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  128.336871] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  128.336890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  128.336912] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  128.336930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  128.336949] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  128.336968] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  128.336984] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  128.337003] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  128.337020] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  128.337042] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  128.337059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  128.337080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  128.337097] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  128.337118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  128.337135] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  128.337155] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  128.337172] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  128.337197] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  128.337227] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  128.337256] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  128.337290] [drm:intel_power_well_enable [i915]] enabling always-on
>[  128.337306] [drm:intel_power_well_enable [i915]] enabling DC off
>[  128.337565] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  128.337589] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  128.337606] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  128.337632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  128.337652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  128.337675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  128.337693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  128.337716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  128.337733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  128.337756] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  128.337775] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  128.337798] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  128.337817] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  128.337843] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[  128.337862] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  128.337892] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  128.337922] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  128.938612] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control abcd0000
>[  128.938705] [drm:wait_panel_status [i915]] Wait complete
>[  128.938801] [drm:edp_panel_on [i915]] Wait for panel power on
>[  128.938923] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control abcd0003
>[  129.011886] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  129.011976] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  129.012056] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  129.012196] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  129.141032] [drm:wait_panel_status [i915]] Wait complete
>[  129.141150] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  129.141320] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  129.142556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  129.142621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  129.142681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  129.142743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  129.143496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  129.143554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  129.143613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  129.144351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  129.144412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  129.145455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  129.145715] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801671ff000
>[  129.146039] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  129.146082] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  129.146097] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  129.146163] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  129.146221] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  129.146236] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  129.162826] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  129.162848] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  129.162879] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  132.202298] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  132.207241] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  132.209055] [drm:intel_power_well_disable [i915]] disabling DC off
>[  132.210351] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  132.211599] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  145.912608] PM: Syncing filesystems ... done.
>[  145.928339] PM: Preparing system for sleep (mem)
>[  145.950401] Freezing user space processes ... (elapsed 0.003 seconds) done.
>[  145.958313] Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
>[  145.965703] PM: Suspending system (mem)
>[  145.970312] Suspending console(s) (use no_console_suspend to debug)
>[  149.743117] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  149.747626] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[  149.749413] [drm:intel_power_well_disable [i915]] disabling DC off
>[  149.750795] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  149.752097] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  157.118877] [IGT] kms_busy: executing
>[  157.134252] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1]
>[  157.134378] [drm:intel_dp_detect [i915]] [CONNECTOR:47:eDP-1]
>[  157.134459] [drm:intel_power_well_enable [i915]] enabling DC off
>[  157.134557] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  157.134654] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  157.134755] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  157.134833] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  157.134920] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  157.135062] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  157.135221] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>[  157.135786] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[  157.136334] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  157.136387] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:47:eDP-1] probed modes :
>[  157.136459] [drm:drm_mode_debug_printmodeline [drm]] Modeline 48:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  157.136637] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1]
>[  157.136737] [drm:intel_dp_detect [i915]] [CONNECTOR:55:DP-1]
>[  157.136837] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  157.136933] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  157.137117] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  157.137254] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  157.137293] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:55:DP-1] disconnected
>[  157.137460] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1]
>[  157.137582] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  157.137959] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  157.138103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  157.138503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  157.138577] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  157.138939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  157.139110] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  157.139446] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  157.139484] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  157.139512] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:HDMI-A-1] disconnected
>[  157.139798] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  157.149100] [drm:drm_mode_addfb2 [drm]] [FB:64]
>[  157.180211] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  157.180251] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  157.180296] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  157.383301] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  157.383469] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  157.396759] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  157.396893] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  157.397131] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[  157.448687] [drm:wait_panel_status [i915]] Wait complete
>[  157.448828] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  157.448920] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  157.449211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  157.449355] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  157.449489] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  157.449596] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  157.449750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  157.449851] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  157.449975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  157.450130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  157.450237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  157.450336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  157.450458] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  157.450570] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  157.450683] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  157.450787] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  157.450896] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  157.451011] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  157.451154] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  157.451282] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  157.451402] [drm:intel_power_well_disable [i915]] disabling DC off
>[  157.451507] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  157.451617] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  157.452130] [drm:intel_power_well_disable [i915]] disabling always-on
>[  157.452670] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  157.453123] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  157.453193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[  157.453331] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  157.453456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  157.453587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  157.453707] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  157.453812] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  157.453933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  157.454074] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  157.454201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  157.454315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  157.454426] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  157.454524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  157.454616] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  157.454716] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  157.454803] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  157.454909] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  157.455045] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  157.455167] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  157.455276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  157.455376] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  157.455483] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  157.455577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  157.455683] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  157.455778] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  157.455882] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  157.455998] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  157.456151] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[  157.456280] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[  157.457873] [drm:intel_power_well_enable [i915]] enabling always-on
>[  157.457943] [drm:intel_power_well_enable [i915]] enabling DC off
>[  157.458321] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  157.458799] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  157.458896] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  157.459084] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  157.459201] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  157.459335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  157.459445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  157.459559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  157.459659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  157.459767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  157.459865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  157.459987] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  157.460178] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  157.460293] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  157.460398] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  157.460523] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[  157.460628] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  157.460765] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  157.460875] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  157.999370] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000000
>[  158.023821] [drm:wait_panel_status [i915]] Wait complete
>[  158.023964] [drm:edp_panel_on [i915]] Wait for panel power on
>[  158.024284] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[  158.097063] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  158.097189] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  158.097278] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  158.097468] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  158.225800] [drm:wait_panel_status [i915]] Wait complete
>[  158.225954] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  158.226216] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[  158.227539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  158.227645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  158.227728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  158.227827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  158.228643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  158.228720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  158.228787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  158.229586] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  158.229663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  158.230722] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  158.231006] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016078f800
>[  158.231487] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  158.231511] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  158.231528] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  158.231596] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  158.231650] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  158.231672] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  158.248289] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  158.248329] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  158.248372] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  158.271954] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  158.748559] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[  158.748684] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[  158.748780] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[  158.748881] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  158.748987] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  158.951332] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  158.951501] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  158.967026] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  158.967203] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  158.967356] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[  159.018383] [drm:wait_panel_status [i915]] Wait complete
>[  159.018526] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[  159.018620] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  159.018739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  159.018830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  159.018911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  159.018987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  159.019155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  159.019280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  159.019385] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  159.019502] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  159.019600] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  159.019719] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  159.019802] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  159.019918] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  159.020013] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  159.020159] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  159.020272] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  159.020388] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  159.020502] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  159.020608] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  159.020709] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  159.020826] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  159.020930] [drm:intel_power_well_disable [i915]] disabling DC off
>[  159.021035] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  159.021163] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  159.021646] [drm:intel_power_well_disable [i915]] disabling always-on
>[  159.022410] [IGT] kms_busy: exiting, ret=0
>[  159.022702] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  159.022783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  159.022888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  159.022970] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  159.023099] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  159.023184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  159.023288] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  159.023372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  159.023471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  159.023547] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  159.023637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  159.023698] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  159.023793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  159.023848] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  159.023947] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  159.024027] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  159.024131] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  159.024203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  159.024293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  159.024362] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  159.024449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  159.024519] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  159.024605] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  159.024672] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  159.024776] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  159.024892] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  159.024973] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  159.025120] [drm:intel_power_well_enable [i915]] enabling always-on
>[  159.025191] [drm:intel_power_well_enable [i915]] enabling DC off
>[  159.025517] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  159.025616] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  159.025686] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  159.025794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  159.025871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  159.025964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  159.026056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  159.026143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  159.026210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  159.026287] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  159.026380] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  159.026454] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  159.026541] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  159.026630] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[  159.026723] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  159.026838] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  159.026919] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  159.599378] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[  159.599455] [drm:wait_panel_status [i915]] Wait complete
>[  159.599536] [drm:edp_panel_on [i915]] Wait for panel power on
>[  159.599647] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[  159.672657] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  159.672747] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  159.672826] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  159.672960] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  159.801834] [drm:wait_panel_status [i915]] Wait complete
>[  159.801951] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  159.802119] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[  159.803406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  159.803482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  159.803551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  159.803620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  159.804375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  159.804438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  159.804501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  159.805253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  159.805314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  159.806362] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  159.806625] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016927d000
>[  159.807272] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  159.807292] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  159.807308] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  159.807375] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[  159.807428] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[  159.807442] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  159.824035] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  159.824058] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  159.824089] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  162.863398] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  162.868299] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[  162.869795] [drm:intel_power_well_disable [i915]] disabling DC off
>[  162.871312] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  162.872651] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  791.272812] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  791.272894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[  791.272980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[  791.273053] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  791.273119] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[  791.273191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[  791.273268] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  791.273338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[  791.273427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[  791.273489] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  791.273548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  791.273597] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  791.273658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  791.273699] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[  791.273763] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[  791.273822] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  791.273879] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  791.273934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  791.273988] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  791.274043] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  791.274096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  791.274155] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:63, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  791.274210] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  791.274263] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  791.274316] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  791.274389] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[  791.274491] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[  791.274558] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  791.274655] [drm:intel_power_well_enable [i915]] enabling DC off
>[  791.274716] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  791.274803] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  791.480715] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  791.480850] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  791.494386] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  791.494563] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[  791.494847] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  791.494934] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  791.495051] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[  791.546496] [drm:wait_panel_status [i915]] Wait complete
>[  791.546604] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[  791.546684] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  791.546794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  791.546870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[  791.546942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[  791.547007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[  791.547070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[  791.547131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[  791.547206] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  791.547280] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  791.547349] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[  791.547437] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  791.547506] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[  791.547586] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  791.547651] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[  791.547732] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  791.547800] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  791.547867] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  791.547942] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[  791.548014] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  791.548084] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[  791.548153] [drm:intel_power_well_disable [i915]] disabling DC off
>[  791.548219] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  791.548283] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  791.548739] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1484.036301] [IGT] kms_setmode: executing
>[ 1484.052298] [IGT] kms_setmode: starting subtest basic
>[ 1484.052381] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1484.052452] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1484.052510] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1484.052554] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1484.052841] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1484.052884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1484.052950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1484.052988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1484.053025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1484.053066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1484.053113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1484.053159] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1484.053202] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1484.053255] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1484.053285] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1484.053312] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1484.053345] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1484.053375] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1484.053410] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1484.053437] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1484.053848] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1484.053885] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1484.053943] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1484.054387] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[ 1484.086495] [drm:drm_mode_addfb2 [drm]] [FB:64]
>[ 1484.103345] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1484.103364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[ 1484.103405] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[ 1484.103421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[ 1484.103438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[ 1484.103454] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[ 1484.103468] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[ 1484.103483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[ 1484.103498] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[ 1484.103525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[ 1484.103538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[ 1484.103551] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1484.103562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1484.103573] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1484.103585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1484.103593] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1484.103606] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[ 1484.103618] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[ 1484.103630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1484.103642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1484.103653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1484.103664] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1484.103683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1484.103694] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[ 1484.103705] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[ 1484.103715] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[ 1484.103730] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1484.103749] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[ 1484.103763] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1484.104138] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1484.104152] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1484.104407] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1484.104423] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[ 1484.104435] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[ 1484.104465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1484.104479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1484.104491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1484.104504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1484.104515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1484.104526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1484.104540] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1484.104553] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1484.104573] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1484.104585] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1484.104601] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[ 1484.104614] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1484.104636] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1484.104656] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1484.104722] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[ 1484.104747] [drm:wait_panel_status [i915]] Wait complete
>[ 1484.104781] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1484.104845] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000003
>[ 1484.178080] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1484.178206] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1484.178295] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1484.178485] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1484.305881] [drm:wait_panel_status [i915]] Wait complete
>[ 1484.306079] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1484.306235] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[ 1484.307507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1484.307586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1484.307656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1484.307726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1484.308571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 1484.308650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 1484.308717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1484.309529] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1484.309607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1484.310666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1484.310941] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016c990000
>[ 1484.311653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1484.311755] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 1484.311831] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1484.312021] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1484.312166] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[ 1484.312265] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1484.328609] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1484.328734] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1484.328861] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1486.344763] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1486.344934] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1486.345304] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[ 1486.548263] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1486.548433] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1486.561687] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[ 1486.561824] [drm:edp_panel_off [i915]] Wait for panel power off time
>[ 1486.562037] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[ 1486.613729] [drm:wait_panel_status [i915]] Wait complete
>[ 1486.613869] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 31
>[ 1486.614118] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1486.614250] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1486.614385] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1486.614472] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1486.614662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1486.614764] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1486.614885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1486.615021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1486.615134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1486.615242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1486.615338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1486.615460] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1486.615566] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1486.615676] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1486.615774] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1486.615882] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1486.616021] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[ 1486.616142] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[ 1486.616253] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1486.616367] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1486.616467] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1486.616575] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1486.617083] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1486.617561] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1486.618028] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1486.618478] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1486.619096] [drm:drm_mode_addfb2 [drm]] [FB:64]
>[ 1486.634024] [drm:drm_mode_addfb2 [drm]] [FB:66]
>[ 1486.650542] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1486.650560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[ 1486.650601] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[ 1486.650617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[ 1486.650635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[ 1486.650650] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[ 1486.650663] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[ 1486.650678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[ 1486.650693] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[ 1486.650707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[ 1486.650733] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[ 1486.650745] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1486.650757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1486.650767] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1486.650779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1486.650788] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1486.650801] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[ 1486.650813] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[ 1486.650824] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1486.650836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1486.650847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1486.650859] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1486.650923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1486.650943] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[ 1486.650961] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[ 1486.650981] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[ 1486.651004] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1486.651031] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 0
>[ 1486.651052] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[ 1486.651398] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1486.651411] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1486.651663] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1486.651678] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1486.651690] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1486.651710] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[ 1486.651726] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[ 1486.651745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1486.651759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1486.651773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1486.651785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1486.651797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1486.651808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1486.651822] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1486.651844] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1486.651857] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1486.651897] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1486.651922] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 38
>[ 1486.651957] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1486.651986] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1486.652016] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1487.204291] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000000
>[ 1487.206679] [drm:wait_panel_status [i915]] Wait complete
>[ 1487.206823] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1487.207065] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[ 1487.280034] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1487.280159] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1487.280249] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1487.280454] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1487.408386] [drm:wait_panel_status [i915]] Wait complete
>[ 1487.408543] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1487.408677] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[ 1487.410011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1487.410117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1487.410196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1487.410291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1487.411141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 1487.411269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 1487.411353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1487.412178] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1487.412259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1487.413352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1487.413627] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016927d000
>[ 1487.414322] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1487.414356] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 1487.414375] [drm:intel_panel_enable_backlight [i915]] pipe B
>[ 1487.414445] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1487.414499] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[ 1487.414523] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1487.431162] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1487.431212] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[ 1487.431259] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1489.447397] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1489.447601] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1489.447826] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[ 1489.652251] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1489.652416] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1489.665675] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[ 1489.665811] [drm:edp_panel_off [i915]] Wait for panel power off time
>[ 1489.666051] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[ 1489.717724] [drm:wait_panel_status [i915]] Wait complete
>[ 1489.717865] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 38
>[ 1489.718081] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1489.718216] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1489.718316] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1489.718471] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1489.718573] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1489.718722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1489.718832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1489.718971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1489.719080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1489.719190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1489.719293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1489.719413] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1489.719526] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1489.719640] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1489.719740] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1489.719846] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1489.719982] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1489.720111] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1489.720210] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[ 1489.720317] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[ 1489.720429] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[ 1489.720541] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1489.720641] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1489.720746] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1489.721255] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1489.721729] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1489.722202] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1489.722651] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1489.723291] [drm:drm_mode_addfb2 [drm]] [FB:66]
>[ 1489.735120] [drm:drm_mode_addfb2 [drm]] [FB:67]
>[ 1489.751556] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1489.751575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:eDP-1]
>[ 1489.751617] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[ 1489.751632] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[ 1489.751650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[ 1489.751665] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[ 1489.751678] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[ 1489.751693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[ 1489.751709] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[ 1489.751723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[ 1489.751748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[ 1489.751761] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1489.751773] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1489.751783] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1489.751796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1489.751805] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1489.751818] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[ 1489.751830] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[ 1489.751842] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1489.751886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1489.751925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1489.751943] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1489.751958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1489.751975] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[ 1489.751996] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[ 1489.752014] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[ 1489.752036] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1489.752070] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 0
>[ 1489.752089] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe C
>[ 1489.752419] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1489.752432] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1489.752684] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1489.752699] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1489.752711] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1489.752730] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[ 1489.752747] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[ 1489.752766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1489.752780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1489.752793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1489.752806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1489.752817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1489.752829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1489.752876] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1489.752913] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1489.752935] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1489.752955] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1489.752977] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 4, on? 0) for crtc 45
>[ 1489.752999] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1489.753033] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1489.753059] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1490.276273] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000000
>[ 1490.307483] [drm:wait_panel_status [i915]] Wait complete
>[ 1490.307624] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1490.307788] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[ 1490.380815] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1490.380942] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1490.381032] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1490.381225] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1490.509484] [drm:wait_panel_status [i915]] Wait complete
>[ 1490.509637] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1490.509777] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[ 1490.511066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1490.511151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1490.511222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1490.511293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1490.512098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 1490.512197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 1490.512287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1490.513080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1490.513169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1490.514246] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1490.514459] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880161508800
>[ 1490.514748] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1490.514797] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 1490.514818] [drm:intel_panel_enable_backlight [i915]] pipe C
>[ 1490.514902] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1490.514972] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[ 1490.514995] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1490.531605] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1490.531655] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[ 1490.531701] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1492.547838] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1492.548110] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1492.548329] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[ 1492.756203] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1492.756371] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1492.765690] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[ 1492.765826] [drm:edp_panel_off [i915]] Wait for panel power off time
>[ 1492.766078] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>[ 1492.817516] [drm:wait_panel_status [i915]] Wait complete
>[ 1492.817655] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 4, on? 1) for crtc 45
>[ 1492.817750] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1492.817893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1492.818064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1492.818169] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1492.818317] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1492.818430] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1492.818586] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1492.818680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1492.818758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1492.818841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1492.818947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1492.819048] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1492.819160] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1492.819286] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1492.819385] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1492.819468] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1492.819550] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1492.819644] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1492.819715] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[ 1492.819782] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[ 1492.819882] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[ 1492.819982] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1492.820070] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1492.820172] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1492.820673] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1492.821236] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1492.821619] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1492.822098] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1492.822683] [drm:drm_mode_addfb2 [drm]] [FB:67]
>[ 1492.830984] [drm:drm_mode_addfb2 [drm]] [FB:68]
>[ 1492.840043] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1492.840059] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:60:HDMI-A-1]
>[ 1492.840092] [drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[ 1492.840109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[ 1492.840112] ------------[ cut here ]------------
>[ 1492.840128] WARNING: CPU: 0 PID: 2622 at drivers/gpu/drm/i915/intel_ddi.c:2059 intel_ddi_compute_config+0xa4/0xe0 [i915]
>[ 1492.840130] compute_config() on unknown output!
>[ 1492.840132] Modules linked in: netconsole scsi_transport_iscsi fuse vfat fat x86_pkg_temp_thermal coretemp intel_cstate intel_uncore snd_hda_codec_hdmi snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd intel_rapl_perf mei_me mei intel_pch_thermal serio_raw soundcore wmi acpi_pad i915 i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops r8169 drm mii video
>[ 1492.840189] CPU: 0 PID: 2622 Comm: kms_setmode Tainted: G     U  W       4.9.0-rc5+ #170
>[ 1492.840191] Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS DCCN34WW(V2.03) 12/01/2015
>[ 1492.840318]  ffffc90001377a48 ffffffffa13220bc ffffc90001377a98 0000000000000000
>[ 1492.840324]  ffffc90001377a88 ffffffffa1059bcb 0000080b00000000 000000000000000a
>[ 1492.840330]  ffff88016d815000 ffff88015e6e0000 ffff88016025a000 ffff88016a414880
>[ 1492.840336] Call Trace:
>[ 1492.840341]  [<ffffffffa13220bc>] dump_stack+0x4f/0x73
>[ 1492.840345]  [<ffffffffa1059bcb>] __warn+0xcb/0xf0
>[ 1492.840348]  [<ffffffffa1059c4f>] warn_slowpath_fmt+0x5f/0x80
>[ 1492.840363]  [<ffffffffc02e2b24>] intel_ddi_compute_config+0xa4/0xe0 [i915]
>[ 1492.840379]  [<ffffffffc02c2138>] intel_atomic_check+0x308/0x1120 [i915]
>[ 1492.840390]  [<ffffffffc017fe98>] drm_atomic_check_only+0x328/0x5b0 [drm]
>[ 1492.840398]  [<ffffffffc017f8bc>] ? drm_atomic_set_crtc_for_connector+0xbc/0xf0 [drm]
>[ 1492.840406]  [<ffffffffc0180138>] drm_atomic_commit+0x18/0x50 [drm]
>[ 1492.840414]  [<ffffffffc0214a42>] drm_atomic_helper_set_config+0x82/0xe0 [drm_kms_helper]
>[ 1492.840423]  [<ffffffffc0174b35>] drm_mode_set_config_internal+0x65/0x110 [drm]
>[ 1492.840431]  [<ffffffffc01754dd>] drm_mode_setcrtc+0x43d/0x530 [drm]
>[ 1492.840440]  [<ffffffffc0183268>] ? drm_mode_dirtyfb_ioctl+0x78/0x1a0 [drm]
>[ 1492.840448]  [<ffffffffc016ce69>] drm_ioctl+0x1f9/0x480 [drm]
>[ 1492.840456]  [<ffffffffc01750a0>] ? drm_mode_getcrtc+0x140/0x140 [drm]
>[ 1492.840460]  [<ffffffffa11926cd>] ? vma_merge+0x22d/0x340
>[ 1492.840463]  [<ffffffffa11eefa3>] do_vfs_ioctl+0xa3/0x5e0
>[ 1492.840466]  [<ffffffffa1346e75>] ? __percpu_counter_add+0x85/0xb0
>[ 1492.840468]  [<ffffffffa11931f8>] ? do_munmap+0x338/0x460
>[ 1492.840471]  [<ffffffffa11ef521>] SyS_ioctl+0x41/0x70
>[ 1492.840474]  [<ffffffffa169fc20>] entry_SYSCALL_64_fastpath+0x13/0x94
>[ 1492.840500] ---[ end trace a271b710ff085f92 ]---
>[ 1492.840502] ------------[ cut here ]------------
>[ 1492.840518] WARNING: CPU: 0 PID: 2622 at drivers/gpu/drm/i915/intel_dp.c:146 intel_dp_max_link_bw.isra.8+0x2d/0x50 [i915]
>[ 1492.840520] invalid max DP link bw val 0, using 1.62Gbps
>[ 1492.840521] Modules linked in: netconsole scsi_transport_iscsi fuse vfat fat x86_pkg_temp_thermal coretemp intel_cstate intel_uncore snd_hda_codec_hdmi snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd intel_rapl_perf mei_me mei intel_pch_thermal serio_raw soundcore wmi acpi_pad i915 i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops r8169 drm mii video
>[ 1492.840570] CPU: 0 PID: 2622 Comm: kms_setmode Tainted: G     U  W       4.9.0-rc5+ #170
>[ 1492.840572] Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS DCCN34WW(V2.03) 12/01/2015
>[ 1492.840574]  ffffc90001377948 ffffffffa13220bc ffffc90001377998 0000000000000000
>[ 1492.840753]  ffffc90001377988 ffffffffa1059bcb 00000092a10b5ba5 0000000000000000
>[ 1492.840760]  ffff88016025a0f0 ffffffffc0318230 ffffc90001377aa0 ffff8801619ac000
>[ 1492.840766] Call Trace:
>[ 1492.840769]  [<ffffffffa13220bc>] dump_stack+0x4f/0x73
>[ 1492.840772]  [<ffffffffa1059bcb>] __warn+0xcb/0xf0
>[ 1492.840775]  [<ffffffffa1059c4f>] warn_slowpath_fmt+0x5f/0x80
>[ 1492.840779]  [<ffffffffa10b5edf>] ? vprintk_default+0x1f/0x30
>[ 1492.840793]  [<ffffffffc02e7b2d>] intel_dp_max_link_bw.isra.8+0x2d/0x50 [i915]
>[ 1492.840807]  [<ffffffffc02e9ba5>] intel_dp_common_rates+0x45/0xf0 [i915]
>[ 1492.840822]  [<ffffffffc02eb2c4>] intel_dp_compute_config+0xa4/0x6b0 [i915]
>[ 1492.840824]  [<ffffffffa1059ba6>] ? __warn+0xa6/0xf0
>[ 1492.840839]  [<ffffffffc02e2aca>] intel_ddi_compute_config+0x4a/0xe0 [i915]
>[ 1492.840854]  [<ffffffffc02c2138>] intel_atomic_check+0x308/0x1120 [i915]
>[ 1492.840864]  [<ffffffffc017fe98>] drm_atomic_check_only+0x328/0x5b0 [drm]
>[ 1492.840873]  [<ffffffffc017f8bc>] ? drm_atomic_set_crtc_for_connector+0xbc/0xf0 [drm]
>[ 1492.840881]  [<ffffffffc0180138>] drm_atomic_commit+0x18/0x50 [drm]
>[ 1492.840887]  [<ffffffffc0214a42>] drm_atomic_helper_set_config+0x82/0xe0 [drm_kms_helper]
>[ 1492.840896]  [<ffffffffc0174b35>] drm_mode_set_config_internal+0x65/0x110 [drm]
>[ 1492.840903]  [<ffffffffc01754dd>] drm_mode_setcrtc+0x43d/0x530 [drm]
>[ 1492.840913]  [<ffffffffc0183268>] ? drm_mode_dirtyfb_ioctl+0x78/0x1a0 [drm]
>[ 1492.840920]  [<ffffffffc016ce69>] drm_ioctl+0x1f9/0x480 [drm]
>[ 1492.840928]  [<ffffffffc01750a0>] ? drm_mode_getcrtc+0x140/0x140 [drm]
>[ 1492.840932]  [<ffffffffa11926cd>] ? vma_merge+0x22d/0x340
>[ 1492.840935]  [<ffffffffa11eefa3>] do_vfs_ioctl+0xa3/0x5e0
>[ 1492.840938]  [<ffffffffa1346e75>] ? __percpu_counter_add+0x85/0xb0
>[ 1492.840940]  [<ffffffffa11931f8>] ? do_munmap+0x338/0x460
>[ 1492.840943]  [<ffffffffa11ef521>] SyS_ioctl+0x41/0x70
>[ 1492.840946]  [<ffffffffa169fc20>] entry_SYSCALL_64_fastpath+0x13/0x94
>[ 1492.840975] ---[ end trace a271b710ff085f93 ]---
>[ 1492.840991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 0 max bw 162000 pixel clock 25200KHz
>[ 1492.841012] [drm:intel_atomic_check [i915]] Encoder config failure
>[ 1492.841032] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][failed]
>[ 1492.841051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1492.841069] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1492.841086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1492.841100] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x0 0xa
>[ 1492.841118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1492.841131] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x0 0xa
>[ 1492.841154] [drm:intel_dump_pipe_config [i915]] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x0 flags: 0xa
>[ 1492.841171] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 640x480
>[ 1492.841187] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1492.841204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1492.841220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1492.841234] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1492.841253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1492.841272] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[ 1492.841291] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[ 1492.841315] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[ 1492.874231] [IGT] kms_setmode: exiting, ret=99
>[ 1492.874484] [drm:intel_atomic_check [i915]] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[ 1492.874566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
>[ 1492.874652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138700KHz
>[ 1492.874726] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[ 1492.874793] [drm:intel_dp_compute_config [i915]] DP link bw required 249660 available 432000
>[ 1492.874868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[ 1492.875007] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[ 1492.875095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[ 1492.875199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4847916, gmch_n: 8388608, link_m: 269328, link_n: 524288, tu: 64
>[ 1492.875279] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1492.875320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1492.875334] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1492.875351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1492.875361] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138700 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[ 1492.875379] [drm:intel_dump_pipe_config [i915]] crtc timings: 138700 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[ 1492.875393] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[ 1492.875409] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1492.875423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1492.875439] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1492.875452] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1492.875464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1492.875481] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[ 1492.875494] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[ 1492.875510] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[ 1492.875527] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 337500, actual 337500
>[ 1492.875549] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 0
>[ 1492.875564] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1492.875595] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1492.875609] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1492.875881] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1492.875913] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[ 1492.875926] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[ 1492.875946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[ 1492.875960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DDI B]
>[ 1492.875976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST A]
>[ 1492.875989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST B]
>[ 1492.876005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST C]
>[ 1492.876017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI C]
>[ 1492.876034] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1492.876048] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 1
>[ 1492.876063] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 2
>[ 1492.876076] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 3
>[ 1492.876096] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 31
>[ 1492.876110] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1492.876133] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1492.876155] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1493.372249] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000000
>[ 1493.408194] [drm:wait_panel_status [i915]] Wait complete
>[ 1493.408299] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1493.408426] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>[ 1493.481474] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1493.481564] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1493.481644] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1493.481787] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1493.610459] [drm:wait_panel_status [i915]] Wait complete
>[ 1493.610579] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1493.610702] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[ 1493.611991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1493.612069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1493.612139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1493.612206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1493.612961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 1493.613021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 1493.613081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1493.613814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1493.613975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1493.615027] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1493.615288] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801691bd000
>[ 1493.615937] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1493.616043] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[ 1493.616109] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1493.616224] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1493.616299] [drm:intel_psr_enable [i915]] PSR not supported by this panel
>[ 1493.616314] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1493.632734] [drm:verify_connector_state.isra.80 [i915]] [CONNECTOR:47:eDP-1]
>[ 1493.632761] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1493.632795] [drm:verify_single_dpll_state.isra.116 [i915]] DPLL 0
>[ 1493.666245] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=937/937
>[ 1493.666287] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 937
>[ 1496.676207] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1496.681074] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[ 1496.682540] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1496.683836] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1496.685089] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02

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