Attachment 128190 Details for Bug 98832 – Ubuntu Linux kernel diff of 3.13

[patch] Ubuntu Linux kernel diff of 3.13

3.13.0-34.60__3.13.0-101.148.diff (text/plain), 84.06 KB, created by Jan-Marek Glogowski on 2016-11-25 18:09:11 UTC

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Creator: Jan-Marek Glogowski

Created: 2016-11-25 18:09:11 UTC

Size: 84.06 KB

patch

obsolete

>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/atombios_crtc.c linux-3.13-wanderer/drivers/gpu/drm/radeon/atombios_crtc.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/atombios_crtc.c	2016-11-25 15:12:00.565360154 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/atombios_crtc.c	2016-11-25 15:12:38.325727573 +0100
>@@ -330,8 +330,10 @@
> 		misc |= ATOM_COMPOSITESYNC;
> 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> 		misc |= ATOM_INTERLACE;
>-	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> 		misc |= ATOM_DOUBLE_CLOCK_MODE;
>+	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>+		misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
> 
> 	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
> 	args.ucCRTC = radeon_crtc->crtc_id;
>@@ -374,8 +376,10 @@
> 		misc |= ATOM_COMPOSITESYNC;
> 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> 		misc |= ATOM_INTERLACE;
>-	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> 		misc |= ATOM_DOUBLE_CLOCK_MODE;
>+	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>+		misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
> 
> 	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
> 	args.ucCRTC = radeon_crtc->crtc_id;
>@@ -857,14 +861,16 @@
> 			args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
> 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
> 				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
>-			switch (bpc) {
>-			case 8:
>-			default:
>-				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
>-				break;
>-			case 10:
>-				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
>-				break;
>+			if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
>+				switch (bpc) {
>+				case 8:
>+				default:
>+					args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
>+					break;
>+				case 10:
>+					args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
>+					break;
>+				}
> 			}
> 			args.v5.ucTransmitterID = encoder_id;
> 			args.v5.ucEncoderMode = encoder_mode;
>@@ -879,20 +885,22 @@
> 			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
> 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
> 				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
>-			switch (bpc) {
>-			case 8:
>-			default:
>-				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
>-				break;
>-			case 10:
>-				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
>-				break;
>-			case 12:
>-				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
>-				break;
>-			case 16:
>-				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
>-				break;
>+			if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
>+				switch (bpc) {
>+				case 8:
>+				default:
>+					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
>+					break;
>+				case 10:
>+					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
>+					break;
>+				case 12:
>+					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
>+					break;
>+				case 16:
>+					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
>+					break;
>+				}
> 			}
> 			args.v6.ucTransmitterID = encoder_id;
> 			args.v6.ucEncoderMode = encoder_mode;
>@@ -1295,6 +1303,9 @@
> 	       (x << 16) | y);
> 	viewport_w = crtc->mode.hdisplay;
> 	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
>+	if ((rdev->family >= CHIP_BONAIRE) &&
>+	    (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
>+		viewport_h *= 2;
> 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
> 	       (viewport_w << 16) | viewport_h);
> 
>@@ -1710,9 +1721,8 @@
> 				return pll;
> 		}
> 		/* otherwise, pick one of the plls */
>-		if ((rdev->family == CHIP_KAVERI) ||
>-		    (rdev->family == CHIP_KABINI)) {
>-			/* KB/KV has PPLL1 and PPLL2 */
>+		if ((rdev->family == CHIP_KABINI)) {
>+			/* KB has PPLL1 and PPLL2 */
> 			pll_in_use = radeon_get_pll_use_mask(crtc);
> 			if (!(pll_in_use & (1 << ATOM_PPLL2)))
> 				return ATOM_PPLL2;
>@@ -1721,7 +1731,7 @@
> 			DRM_ERROR("unable to allocate a PPLL\n");
> 			return ATOM_PPLL_INVALID;
> 		} else {
>-			/* CI has PPLL0, PPLL1, and PPLL2 */
>+			/* CI/KV has PPLL0, PPLL1, and PPLL2 */
> 			pll_in_use = radeon_get_pll_use_mask(crtc);
> 			if (!(pll_in_use & (1 << ATOM_PPLL2)))
> 				return ATOM_PPLL2;
>@@ -2009,6 +2019,7 @@
> 	case ATOM_PPLL0:
> 		/* disable the ppll */
> 		if ((rdev->family == CHIP_ARUBA) ||
>+		    (rdev->family == CHIP_KAVERI) ||
> 		    (rdev->family == CHIP_BONAIRE) ||
> 		    (rdev->family == CHIP_HAWAII))
> 			atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/atombios_dp.c linux-3.13-wanderer/drivers/gpu/drm/radeon/atombios_dp.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/atombios_dp.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/atombios_dp.c	2016-11-25 15:12:38.329727612 +0100
>@@ -123,7 +123,7 @@
> 	/* flags not zero */
> 	if (args.v1.ucReplyStatus == 2) {
> 		DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
>-		return -EBUSY;
>+		return -EIO;
> 	}
> 
> 	/* error */
>@@ -384,6 +384,19 @@
> 
> /***** radeon specific DP functions *****/
> 
>+static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
>+				       u8 dpcd[DP_DPCD_SIZE])
>+{
>+	int max_link_rate;
>+
>+	if (radeon_connector_is_dp12_capable(connector))
>+		max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
>+	else
>+		max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
>+
>+	return max_link_rate;
>+}
>+
> /* First get the min lane# when low rate is used according to pixel clock
>  * (prefer low rate), second check max lane# supported by DP panel,
>  * if the max lane# < low rate lane# then use max lane# instead.
>@@ -393,7 +406,7 @@
> 					int pix_clock)
> {
> 	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
>-	int max_link_rate = drm_dp_max_link_rate(dpcd);
>+	int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
> 	int max_lane_num = drm_dp_max_lane_count(dpcd);
> 	int lane_num;
> 	int max_dp_pix_clock;
>@@ -431,7 +444,7 @@
> 			return 540000;
> 	}
> 
>-	return drm_dp_max_link_rate(dpcd);
>+	return radeon_dp_get_max_link_rate(connector, dpcd);
> }
> 
> static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
>@@ -561,6 +574,10 @@
> 	struct radeon_connector_atom_dig *dig_connector;
> 	int dp_clock;
> 
>+	if ((mode->clock > 340000) &&
>+	    (!radeon_connector_is_dp12_capable(connector)))
>+		return MODE_CLOCK_HIGH;
>+
> 	if (!radeon_connector->con_priv)
> 		return MODE_CLOCK_HIGH;
> 	dig_connector = radeon_connector->con_priv;
>@@ -683,10 +700,8 @@
> 		radeon_write_dpcd_reg(dp_info->radeon_connector,
> 				      DP_DOWNSPREAD_CTRL, 0);
> 
>-	if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
>-	    (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
>+	if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
> 		radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
>-	}
> 
> 	/* set the lane count on the sink */
> 	tmp = dp_info->dp_lane_count;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/atombios_encoders.c linux-3.13-wanderer/drivers/gpu/drm/radeon/atombios_encoders.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/atombios_encoders.c	2016-11-25 15:12:00.573360232 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/atombios_encoders.c	2016-11-25 15:12:38.329727612 +0100
>@@ -183,7 +183,6 @@
> 	struct backlight_properties props;
> 	struct radeon_backlight_privdata *pdata;
> 	struct radeon_encoder_atom_dig *dig;
>-	u8 backlight_level;
> 	char bl_name[16];
> 
> 	/* Mac laptops with multiple GPUs use the gmux driver for backlight
>@@ -222,16 +221,22 @@
> 
> 	pdata->encoder = radeon_encoder;
> 
>-	backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
>-
> 	dig = radeon_encoder->enc_priv;
> 	dig->bl_dev = bd;
> 
> 	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
>+	/* Set a reasonable default here if the level is 0 otherwise
>+	 * fbdev will attempt to turn the backlight on after console
>+	 * unblanking and it will try and restore 0 which turns the backlight
>+	 * off again.
>+	 */
>+	if (bd->props.brightness == 0)
>+		bd->props.brightness = RADEON_MAX_BL_LEVEL;
> 	bd->props.power = FB_BLANK_UNBLANK;
> 	backlight_update_status(bd);
> 
> 	DRM_INFO("radeon atom DIG backlight initialized\n");
>+	rdev->mode_info.bl_encoder = radeon_encoder;
> 
> 	return;
> 
>@@ -890,8 +895,6 @@
> 			else
> 				args.v1.ucLaneNum = 4;
> 
>-			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
>-				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
> 			switch (radeon_encoder->encoder_id) {
> 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
> 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
>@@ -908,6 +911,10 @@
> 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
> 			else
> 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
>+
>+			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
>+				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
>+
> 			break;
> 		case 2:
> 		case 3:
>@@ -1897,8 +1904,11 @@
> 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
> 				else
> 					args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
>-			} else
>+			} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
>+				args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
>+			} else {
> 				args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
>+			}
> 			switch (radeon_encoder->encoder_id) {
> 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
> 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/ci_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/ci_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/ci_dpm.c	2016-11-25 15:12:00.577360271 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/ci_dpm.c	2016-11-25 15:12:38.337727690 +0100
>@@ -852,6 +852,9 @@
> 	WREG32_SMC(CG_THERMAL_CTRL, tmp);
> #endif
> 
>+	rdev->pm.dpm.thermal.min_temp = low_temp;
>+	rdev->pm.dpm.thermal.max_temp = high_temp;
>+
> 	return 0;
> }
> 
>@@ -923,7 +926,18 @@
> 	pi->vddc_leakage.count = 0;
> 	pi->vddci_leakage.count = 0;
> 
>-	if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
>+	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
>+		for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
>+			virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
>+			if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
>+				continue;
>+			if (vddc != 0 && vddc != virtual_voltage_id) {
>+				pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
>+				pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
>+				pi->vddc_leakage.count++;
>+			}
>+		}
>+	} else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
> 		for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
> 			virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
> 			if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
>@@ -1162,7 +1176,7 @@
> 	tmp &= ~GLOBAL_PWRMGT_EN;
> 	WREG32_SMC(GENERAL_PWRMGT, tmp);
> 
>-	tmp = RREG32(SCLK_PWRMGT_CNTL);
>+	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
> 	tmp &= ~DYNAMIC_PM_EN;
> 	WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
> 
>@@ -4727,7 +4741,7 @@
> 	ci_enable_spread_spectrum(rdev, false);
> 	ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
> 	ci_stop_dpm(rdev);
>-	ci_enable_ds_master_switch(rdev, true);
>+	ci_enable_ds_master_switch(rdev, false);
> 	ci_enable_ulv(rdev, false);
> 	ci_clear_vc(rdev);
> 	ci_reset_to_default(rdev);
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/cik.c linux-3.13-wanderer/drivers/gpu/drm/radeon/cik.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/cik.c	2016-11-25 15:12:00.577360271 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/cik.c	2016-11-25 15:12:38.345727767 +0100
>@@ -2219,6 +2219,7 @@
> 				gb_tile_moden = 0;
> 				break;
> 			}
>+			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> 		}
> 	} else if (num_pipe_configs == 8) {
>@@ -3230,6 +3231,7 @@
> 			   (rdev->pdev->device == 0x130B) ||
> 			   (rdev->pdev->device == 0x130E) ||
> 			   (rdev->pdev->device == 0x1315) ||
>+			   (rdev->pdev->device == 0x1318) ||
> 			   (rdev->pdev->device == 0x131B)) {
> 			rdev->config.cik.max_cu_per_sh = 4;
> 			rdev->config.cik.max_backends_per_se = 1;
>@@ -3511,7 +3513,21 @@
> 	struct radeon_ring *ring = &rdev->ring[fence->ring];
> 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
> 
>-	/* EVENT_WRITE_EOP - flush caches, send int */
>+	/* Workaround for cache flush problems. First send a dummy EOP
>+	 * event down the pipe with seq one below.
>+	 */
>+	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
>+	radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
>+				 EOP_TC_ACTION_EN |
>+				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
>+				 EVENT_INDEX(5)));
>+	radeon_ring_write(ring, addr & 0xfffffffc);
>+	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
>+				DATA_SEL(1) | INT_SEL(0));
>+	radeon_ring_write(ring, fence->seq - 1);
>+	radeon_ring_write(ring, 0);
>+
>+	/* Then send the real EOP event down the pipe. */
> 	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
> 	radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
> 				 EOP_TC_ACTION_EN |
>@@ -3710,11 +3726,7 @@
> 		(ib->vm ? (ib->vm->id << 24) : 0);
> 
> 	radeon_ring_write(ring, header);
>-	radeon_ring_write(ring,
>-#ifdef __BIG_ENDIAN
>-			  (2 << 0) |
>-#endif
>-			  (ib->gpu_addr & 0xFFFFFFFC));
>+	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
> 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
> 	radeon_ring_write(ring, control);
> }
>@@ -3903,8 +3915,8 @@
> 	/* init the CE partitions.  CE only used for gfx on CIK */
> 	radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
> 	radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
>-	radeon_ring_write(ring, 0xc000);
>-	radeon_ring_write(ring, 0xc000);
>+	radeon_ring_write(ring, 0x8000);
>+	radeon_ring_write(ring, 0x8000);
> 
> 	/* setup clear context state */
> 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
>@@ -4067,6 +4079,31 @@
> 	WDOORBELL32(ring->doorbell_index, ring->wptr);
> }
> 
>+static void cik_compute_stop(struct radeon_device *rdev,
>+			     struct radeon_ring *ring)
>+{
>+	u32 j, tmp;
>+
>+	cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
>+	/* Disable wptr polling. */
>+	tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
>+	tmp &= ~WPTR_POLL_EN;
>+	WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
>+	/* Disable HQD. */
>+	if (RREG32(CP_HQD_ACTIVE) & 1) {
>+		WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
>+		for (j = 0; j < rdev->usec_timeout; j++) {
>+			if (!(RREG32(CP_HQD_ACTIVE) & 1))
>+				break;
>+			udelay(1);
>+		}
>+		WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
>+		WREG32(CP_HQD_PQ_RPTR, 0);
>+		WREG32(CP_HQD_PQ_WPTR, 0);
>+	}
>+	cik_srbm_select(rdev, 0, 0, 0, 0);
>+}
>+
> /**
>  * cik_cp_compute_enable - enable/disable the compute CP MEs
>  *
>@@ -4080,6 +4117,15 @@
> 	if (enable)
> 		WREG32(CP_MEC_CNTL, 0);
> 	else {
>+		/*
>+		 * To make hibernation reliable we need to clear compute ring
>+		 * configuration before halting the compute ring.
>+		 */
>+		mutex_lock(&rdev->srbm_mutex);
>+		cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
>+		cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
>+		mutex_unlock(&rdev->srbm_mutex);
>+
> 		WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
> 		rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
> 		rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
>@@ -4325,7 +4371,7 @@
>  */
> static int cik_cp_compute_resume(struct radeon_device *rdev)
> {
>-	int r, i, idx;
>+	int r, i, j, idx;
> 	u32 tmp;
> 	bool use_doorbell = true;
> 	u64 hqd_gpu_addr;
>@@ -4444,7 +4490,7 @@
> 		mqd->queue_state.cp_hqd_pq_wptr= 0;
> 		if (RREG32(CP_HQD_ACTIVE) & 1) {
> 			WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
>-			for (i = 0; i < rdev->usec_timeout; i++) {
>+			for (j = 0; j < rdev->usec_timeout; j++) {
> 				if (!(RREG32(CP_HQD_ACTIVE) & 1))
> 					break;
> 				udelay(1);
>@@ -5118,7 +5164,7 @@
> 	 */
> 	/* set vm size, must be a multiple of 4 */
> 	WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
>-	WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
>+	WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
> 	for (i = 1; i < 16; i++) {
> 		if (i < 8)
> 			WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
>@@ -5331,12 +5377,13 @@
> void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
> {
> 	struct radeon_ring *ring = &rdev->ring[ridx];
>+	int usepfp = (ridx == RADEON_RING_TYPE_GFX_INDEX);
> 
> 	if (vm == NULL)
> 		return;
> 
> 	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>-	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
>+	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
> 				 WRITE_DATA_DST_SEL(0)));
> 	if (vm->id < 8) {
> 		radeon_ring_write(ring,
>@@ -5394,8 +5441,19 @@
> 	radeon_ring_write(ring, 0);
> 	radeon_ring_write(ring, 1 << vm->id);
> 
>+	/* wait for the invalidate to complete */
>+	radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
>+	radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
>+				 WAIT_REG_MEM_FUNCTION(0) |  /* always */
>+				 WAIT_REG_MEM_ENGINE(0))); /* me */
>+	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
>+	radeon_ring_write(ring, 0);
>+	radeon_ring_write(ring, 0); /* ref */
>+	radeon_ring_write(ring, 0); /* mask */
>+	radeon_ring_write(ring, 0x20); /* poll interval */
>+
> 	/* compute doesn't have PFP */
>-	if (ridx == RADEON_RING_TYPE_GFX_INDEX) {
>+	if (usepfp) {
> 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
> 		radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
> 		radeon_ring_write(ring, 0x0);
>@@ -5673,6 +5731,7 @@
> 		}
> 
> 		orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
>+		data |= 0x00000001;
> 		data &= 0xfffffffd;
> 		if (orig != data)
> 			WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
>@@ -5704,7 +5763,7 @@
> 		}
> 	} else {
> 		orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
>-		data |= 0x00000002;
>+		data |= 0x00000003;
> 		if (orig != data)
> 			WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
> 
>@@ -6602,7 +6661,6 @@
> 	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
> 	u32 grbm_int_cntl = 0;
> 	u32 dma_cntl, dma_cntl1;
>-	u32 thermal_int;
> 
> 	if (!rdev->irq.installed) {
> 		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
>@@ -6639,13 +6697,6 @@
> 	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
> 	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
> 
>-	if (rdev->flags & RADEON_IS_IGP)
>-		thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &
>-			~(THERM_INTH_MASK | THERM_INTL_MASK);
>-	else
>-		thermal_int = RREG32_SMC(CG_THERMAL_INT) &
>-			~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
>-
> 	/* enable CP interrupts on all rings */
> 	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
> 		DRM_DEBUG("cik_irq_set: sw int gfx\n");
>@@ -6803,14 +6854,6 @@
> 		hpd6 |= DC_HPDx_INT_EN;
> 	}
> 
>-	if (rdev->irq.dpm_thermal) {
>-		DRM_DEBUG("dpm thermal\n");
>-		if (rdev->flags & RADEON_IS_IGP)
>-			thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
>-		else
>-			thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
>-	}
>-
> 	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
> 
> 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
>@@ -6864,10 +6907,8 @@
> 	WREG32(DC_HPD5_INT_CONTROL, hpd5);
> 	WREG32(DC_HPD6_INT_CONTROL, hpd6);
> 
>-	if (rdev->flags & RADEON_IS_IGP)
>-		WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
>-	else
>-		WREG32_SMC(CG_THERMAL_INT, thermal_int);
>+	/* posting read */
>+	RREG32(SRBM_STATUS);
> 
> 	return 0;
> }
>@@ -7067,6 +7108,7 @@
> 		tmp = RREG32(IH_RB_CNTL);
> 		tmp |= IH_WPTR_OVERFLOW_CLEAR;
> 		WREG32(IH_RB_CNTL, tmp);
>+		wptr &= ~RB_OVERFLOW;
> 	}
> 	return (wptr & rdev->ih.ptr_mask);
> }
>@@ -7573,6 +7615,7 @@
> static int cik_startup(struct radeon_device *rdev)
> {
> 	struct radeon_ring *ring;
>+	u32 nop;
> 	int r;
> 
> 	/* enable pcie gen2/3 link */
>@@ -7690,10 +7733,16 @@
> 	}
> 	cik_irq_set(rdev);
> 
>+	if (rdev->family == CHIP_HAWAII) {
>+		nop = RADEON_CP_PACKET2;
>+	} else {
>+		nop = PACKET3(PACKET3_NOP, 0x3FFF);
>+	}
>+
> 	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
> 	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
> 			     CP_RB0_RPTR, CP_RB0_WPTR,
>-			     PACKET3(PACKET3_NOP, 0x3FFF));
>+			     nop);
> 	if (r)
> 		return r;
> 
>@@ -7702,7 +7751,7 @@
> 	ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
> 	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
> 			     CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
>-			     PACKET3(PACKET3_NOP, 0x3FFF));
>+			     nop);
> 	if (r)
> 		return r;
> 	ring->me = 1; /* first MEC */
>@@ -7714,7 +7763,7 @@
> 	ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
> 	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
> 			     CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
>-			     PACKET3(PACKET3_NOP, 0x3FFF));
>+			     nop);
> 	if (r)
> 		return r;
> 	/* dGPU only have 1 MEC */
>@@ -8679,6 +8728,9 @@
> 	u32 num_heads = 0, lb_size;
> 	int i;
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	for (i = 0; i < rdev->num_crtc; i++) {
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/cikd.h linux-3.13-wanderer/drivers/gpu/drm/radeon/cikd.h
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/cikd.h	2016-11-25 15:12:00.581360310 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/cikd.h	2016-11-25 15:12:38.345727767 +0100
>@@ -1734,12 +1734,12 @@
> #define		EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
> #define		EOP_TCL1_ACTION_EN                      (1 << 16)
> #define		EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
>+#define		EOP_TCL2_VOLATILE                       (1 << 24)
> #define		EOP_CACHE_POLICY(x)                     ((x) << 25)
>                 /* 0 - LRU
> 		 * 1 - Stream
> 		 * 2 - Bypass
> 		 */
>-#define		EOP_TCL2_VOLATILE                       (1 << 27)
> #define		DATA_SEL(x)                             ((x) << 29)
>                 /* 0 - discard
> 		 * 1 - send low 32bit data
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/cik_sdma.c linux-3.13-wanderer/drivers/gpu/drm/radeon/cik_sdma.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/cik_sdma.c	2016-11-25 15:12:00.577360271 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/cik_sdma.c	2016-11-25 15:12:38.345727767 +0100
>@@ -195,6 +195,17 @@
> 	}
> 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
> 	rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
>+
>+	/* FIXME use something else than big hammer but after few days can not
>+	 * seem to find good combination so reset SDMA blocks as it seems we
>+	 * do not shut them down properly. This fix hibernation and does not
>+	 * affect suspend to ram.
>+	 */
>+	WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
>+	(void)RREG32(SRBM_SOFT_RESET);
>+	udelay(50);
>+	WREG32(SRBM_SOFT_RESET, 0);
>+	(void)RREG32(SRBM_SOFT_RESET);
> }
> 
> /**
>@@ -388,13 +399,6 @@
> {
> 	int r;
> 
>-	/* Reset dma */
>-	WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
>-	RREG32(SRBM_SOFT_RESET);
>-	udelay(50);
>-	WREG32(SRBM_SOFT_RESET, 0);
>-	RREG32(SRBM_SOFT_RESET);
>-
> 	r = cik_sdma_load_microcode(rdev);
> 	if (r)
> 		return r;
>@@ -515,16 +519,19 @@
> {
> 	unsigned i;
> 	int r;
>-	void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
>+	unsigned index;
> 	u32 tmp;
>+	u64 gpu_addr;
> 
>-	if (!ptr) {
>-		DRM_ERROR("invalid vram scratch pointer\n");
>-		return -EINVAL;
>-	}
>+	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
>+		index = R600_WB_DMA_RING_TEST_OFFSET;
>+	else
>+		index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
>+
>+	gpu_addr = rdev->wb.gpu_addr + index;
> 
> 	tmp = 0xCAFEDEAD;
>-	writel(tmp, ptr);
>+	rdev->wb.wb[index/4] = cpu_to_le32(tmp);
> 
> 	r = radeon_ring_lock(rdev, ring, 5);
> 	if (r) {
>@@ -532,14 +539,14 @@
> 		return r;
> 	}
> 	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
>-	radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
>-	radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff);
>+	radeon_ring_write(ring, lower_32_bits(gpu_addr));
>+	radeon_ring_write(ring, upper_32_bits(gpu_addr));
> 	radeon_ring_write(ring, 1); /* number of DWs to follow */
> 	radeon_ring_write(ring, 0xDEADBEEF);
> 	radeon_ring_unlock_commit(rdev, ring);
> 
> 	for (i = 0; i < rdev->usec_timeout; i++) {
>-		tmp = readl(ptr);
>+		tmp = le32_to_cpu(rdev->wb.wb[index/4]);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		DRM_UDELAY(1);
>@@ -568,17 +575,20 @@
> {
> 	struct radeon_ib ib;
> 	unsigned i;
>+	unsigned index;
> 	int r;
>-	void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
> 	u32 tmp = 0;
>+	u64 gpu_addr;
> 
>-	if (!ptr) {
>-		DRM_ERROR("invalid vram scratch pointer\n");
>-		return -EINVAL;
>-	}
>+	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
>+		index = R600_WB_DMA_RING_TEST_OFFSET;
>+	else
>+		index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
>+
>+	gpu_addr = rdev->wb.gpu_addr + index;
> 
> 	tmp = 0xCAFEDEAD;
>-	writel(tmp, ptr);
>+	rdev->wb.wb[index/4] = cpu_to_le32(tmp);
> 
> 	r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
> 	if (r) {
>@@ -587,8 +597,8 @@
> 	}
> 
> 	ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
>-	ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
>-	ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff;
>+	ib.ptr[1] = lower_32_bits(gpu_addr);
>+	ib.ptr[2] = upper_32_bits(gpu_addr);
> 	ib.ptr[3] = 1;
> 	ib.ptr[4] = 0xDEADBEEF;
> 	ib.length_dw = 5;
>@@ -605,7 +615,7 @@
> 		return r;
> 	}
> 	for (i = 0; i < rdev->usec_timeout; i++) {
>-		tmp = readl(ptr);
>+		tmp = le32_to_cpu(rdev->wb.wb[index/4]);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		DRM_UDELAY(1);
>@@ -732,6 +742,8 @@
>  */
> void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
> {
>+	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
>+			  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
> 	struct radeon_ring *ring = &rdev->ring[ridx];
> 
> 	if (vm == NULL)
>@@ -777,5 +789,12 @@
> 	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
> 	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
> 	radeon_ring_write(ring, 1 << vm->id);
>+
>+	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
>+	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
>+	radeon_ring_write(ring, 0);
>+	radeon_ring_write(ring, 0); /* reference */
>+	radeon_ring_write(ring, 0); /* mask */
>+	radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
> }
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/cypress_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/cypress_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/cypress_dpm.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/cypress_dpm.c	2016-11-25 15:12:38.349727806 +0100
>@@ -1551,7 +1551,7 @@
> 
> 		table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
> 		table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
>-			cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
>+			cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
> 	}
> 
> 	return 0;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/dce6_afmt.c linux-3.13-wanderer/drivers/gpu/drm/radeon/dce6_afmt.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/dce6_afmt.c	2016-11-25 15:12:00.581360310 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/dce6_afmt.c	2016-11-25 15:12:38.349727806 +0100
>@@ -155,7 +155,7 @@
> 	struct drm_connector *connector;
> 	struct radeon_connector *radeon_connector = NULL;
> 	u32 offset, tmp;
>-	u8 *sadb;
>+	u8 *sadb = NULL;
> 	int sad_count;
> 
> 	if (!dig || !dig->afmt || !dig->afmt->pin)
>@@ -174,9 +174,9 @@
> 	}
> 
> 	sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
>-	if (sad_count <= 0) {
>-		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
>-		return;
>+	if (sad_count < 0) {
>+		DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
>+		sad_count = 0;
> 	}
> 
> 	/* program the speaker allocation */
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/evergreen.c linux-3.13-wanderer/drivers/gpu/drm/radeon/evergreen.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/evergreen.c	2016-11-25 15:12:00.581360310 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/evergreen.c	2016-11-25 15:12:38.349727806 +0100
>@@ -188,7 +188,7 @@
> 	0x8c1c, 0xffffffff, 0x00001010,
> 	0x28350, 0xffffffff, 0x00000000,
> 	0xa008, 0xffffffff, 0x00010000,
>-	0x5cc, 0xffffffff, 0x00000001,
>+	0x5c4, 0xffffffff, 0x00000001,
> 	0x9508, 0xffffffff, 0x00000002,
> 	0x913c, 0x0000000f, 0x0000000a
> };
>@@ -475,7 +475,7 @@
> 	0x8c1c, 0xffffffff, 0x00001010,
> 	0x28350, 0xffffffff, 0x00000000,
> 	0xa008, 0xffffffff, 0x00010000,
>-	0x5cc, 0xffffffff, 0x00000001,
>+	0x5c4, 0xffffffff, 0x00000001,
> 	0x9508, 0xffffffff, 0x00000002
> };
> 
>@@ -634,7 +634,7 @@
> static const u32 supersumo_golden_registers[] =
> {
> 	0x5eb4, 0xffffffff, 0x00000002,
>-	0x5cc, 0xffffffff, 0x00000001,
>+	0x5c4, 0xffffffff, 0x00000001,
> 	0x7030, 0xffffffff, 0x00000011,
> 	0x7c30, 0xffffffff, 0x00000011,
> 	0x6104, 0x01000300, 0x00000000,
>@@ -718,7 +718,7 @@
> static const u32 wrestler_golden_registers[] =
> {
> 	0x5eb4, 0xffffffff, 0x00000002,
>-	0x5cc, 0xffffffff, 0x00000001,
>+	0x5c4, 0xffffffff, 0x00000001,
> 	0x7030, 0xffffffff, 0x00000011,
> 	0x7c30, 0xffffffff, 0x00000011,
> 	0x6104, 0x01000300, 0x00000000,
>@@ -2361,6 +2361,9 @@
> 	u32 num_heads = 0, lb_size;
> 	int i;
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	for (i = 0; i < rdev->num_crtc; i++) {
>@@ -2569,6 +2572,7 @@
> 					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> 					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
> 					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
>+					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> 				}
> 			} else {
> 				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
>@@ -4542,6 +4546,9 @@
> 	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
> 	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
> 
>+	/* posting read */
>+	RREG32(SRBM_STATUS);
>+
> 	return 0;
> }
> 
>@@ -4713,6 +4720,7 @@
> 		tmp = RREG32(IH_RB_CNTL);
> 		tmp |= IH_WPTR_OVERFLOW_CLEAR;
> 		WREG32(IH_RB_CNTL, tmp);
>+		wptr &= ~RB_OVERFLOW;
> 	}
> 	return (wptr & rdev->ih.ptr_mask);
> }
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/evergreen_hdmi.c linux-3.13-wanderer/drivers/gpu/drm/radeon/evergreen_hdmi.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/evergreen_hdmi.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/evergreen_hdmi.c	2016-11-25 15:12:38.353727845 +0100
>@@ -102,7 +102,7 @@
> 	struct drm_connector *connector;
> 	struct radeon_connector *radeon_connector = NULL;
> 	u32 tmp;
>-	u8 *sadb;
>+	u8 *sadb = NULL;
> 	int sad_count;
> 
> 	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
>@@ -118,9 +118,9 @@
> 	}
> 
> 	sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
>-	if (sad_count <= 0) {
>-		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
>-		return;
>+	if (sad_count < 0) {
>+		DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
>+		sad_count = 0;
> 	}
> 
> 	/* program the speaker allocation */
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/kv_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/kv_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/kv_dpm.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/kv_dpm.c	2016-11-25 15:12:38.353727845 +0100
>@@ -1121,6 +1121,19 @@
> 	}
> }
> 
>+static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
>+{
>+	u32 thermal_int;
>+
>+	thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);
>+	if (enable)
>+		thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
>+	else
>+		thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK);
>+	WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
>+
>+}
>+
> int kv_dpm_enable(struct radeon_device *rdev)
> {
> 	struct kv_power_info *pi = kv_get_pi(rdev);
>@@ -1222,8 +1235,7 @@
> 			DRM_ERROR("kv_set_thermal_temperature_range failed\n");
> 			return ret;
> 		}
>-		rdev->irq.dpm_thermal = true;
>-		radeon_irq_set(rdev);
>+		kv_enable_thermal_int(rdev, true);
> 	}
> 
> 	ret = kv_smc_bapm_enable(rdev, false);
>@@ -1269,6 +1281,7 @@
> 	kv_stop_dpm(rdev);
> 	kv_enable_ulv(rdev, false);
> 	kv_reset_am(rdev);
>+	kv_enable_thermal_int(rdev, false);
> 
> 	kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
> }
>@@ -2620,7 +2633,11 @@
> 	if (rdev->family == CHIP_KABINI)
> 		pi->high_voltage_t = 4001;
> 
>-	pi->enable_nb_dpm = true;
>+	/* Enabling nb dpm on an asrock system prevents dpm from working */
>+	if (rdev->pdev->subsystem_vendor == 0x1849)
>+		pi->enable_nb_dpm = false;
>+	else
>+		pi->enable_nb_dpm = true;
> 
> 	pi->caps_power_containment = true;
> 	pi->caps_cac = true;
>@@ -2635,7 +2652,19 @@
> 	pi->caps_sclk_ds = true;
> 	pi->enable_auto_thermal_throttling = true;
> 	pi->disable_nb_ps3_in_battery = false;
>-	pi->bapm_enable = false;
>+	if (radeon_bapm == -1) {
>+		/* There are stability issues reported on with
>+		 * bapm enabled on an asrock system.
>+		 */
>+		if (rdev->pdev->subsystem_vendor == 0x1849)
>+			pi->bapm_enable = false;
>+		else
>+			pi->bapm_enable = true;
>+	} else if (radeon_bapm == 0) {
>+		pi->bapm_enable = false;
>+	} else {
>+		pi->bapm_enable = true;
>+	}
> 	pi->voltage_drop_t = 0;
> 	pi->caps_sclk_throttle_low_notification = false;
> 	pi->caps_fps = false; /* true? */
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/ni.c linux-3.13-wanderer/drivers/gpu/drm/radeon/ni.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/ni.c	2016-11-25 15:12:00.581360310 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/ni.c	2016-11-25 15:12:38.357727884 +0100
>@@ -1072,12 +1072,12 @@
> 
> 	if ((rdev->config.cayman.max_backends_per_se == 1) &&
> 	    (rdev->flags & RADEON_IS_IGP)) {
>-		if ((disabled_rb_mask & 3) == 1) {
>-			/* RB0 disabled, RB1 enabled */
>-			tmp = 0x11111111;
>-		} else {
>+		if ((disabled_rb_mask & 3) == 2) {
> 			/* RB1 disabled, RB0 enabled */
> 			tmp = 0x00000000;
>+		} else {
>+			/* RB0 disabled, RB1 enabled */
>+			tmp = 0x11111111;
> 		}
> 	} else {
> 		tmp = gb_addr_config & NUM_PIPES_MASK;
>@@ -1255,7 +1255,8 @@
> 	 */
> 	for (i = 1; i < 8; i++) {
> 		WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
>-		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
>+		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
>+			rdev->vm_manager.max_pfn - 1);
> 		WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
> 			rdev->gart.table_addr >> 12);
> 	}
>@@ -2433,6 +2434,16 @@
> 	radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
> 	radeon_ring_write(ring, 1 << vm->id);
> 
>+	/* wait for the invalidate to complete */
>+	radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
>+	radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
>+				 WAIT_REG_MEM_ENGINE(0))); /* me */
>+	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
>+	radeon_ring_write(ring, 0);
>+	radeon_ring_write(ring, 0); /* ref */
>+	radeon_ring_write(ring, 0); /* mask */
>+	radeon_ring_write(ring, 0x20); /* poll interval */
>+
> 	/* sync PFP to ME, otherwise we might get invalid PFP reads */
> 	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
> 	radeon_ring_write(ring, 0x0);
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/nid.h linux-3.13-wanderer/drivers/gpu/drm/radeon/nid.h
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/nid.h	2016-11-25 15:12:00.585360349 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/nid.h	2016-11-25 15:12:38.365727962 +0100
>@@ -1132,6 +1132,23 @@
> #define	PACKET3_MEM_SEMAPHORE				0x39
> #define	PACKET3_MPEG_INDEX				0x3A
> #define	PACKET3_WAIT_REG_MEM				0x3C
>+#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
>+                /* 0 - always
>+		 * 1 - <
>+		 * 2 - <=
>+		 * 3 - ==
>+		 * 4 - !=
>+		 * 5 - >=
>+		 * 6 - >
>+		 */
>+#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
>+                /* 0 - reg
>+		 * 1 - mem
>+		 */
>+#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
>+                /* 0 - me
>+		 * 1 - pfp
>+		 */
> #define	PACKET3_MEM_WRITE				0x3D
> #define	PACKET3_PFP_SYNC_ME				0x42
> #define	PACKET3_SURFACE_SYNC				0x43
>@@ -1271,6 +1288,13 @@
> 					 (1 << 21) |			\
> 					 (((n) & 0xFFFFF) << 0))
> 
>+#define DMA_SRBM_POLL_PACKET		((9 << 28) |			\
>+					 (1 << 27) |			\
>+					 (1 << 26))
>+
>+#define DMA_SRBM_READ_PACKET		((9 << 28) |			\
>+					 (1 << 27))
>+
> /* async DMA Packet types */
> #define	DMA_PACKET_WRITE				  0x2
> #define	DMA_PACKET_COPY					  0x3
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/ni_dma.c linux-3.13-wanderer/drivers/gpu/drm/radeon/ni_dma.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/ni_dma.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/ni_dma.c	2016-11-25 15:12:38.361727923 +0100
>@@ -120,12 +120,6 @@
> 	u32 reg_offset, wb_offset;
> 	int i, r;
> 
>-	/* Reset dma */
>-	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
>-	RREG32(SRBM_SOFT_RESET);
>-	udelay(50);
>-	WREG32(SRBM_SOFT_RESET, 0);
>-
> 	for (i = 0; i < 2; i++) {
> 		if (i == 0) {
> 			ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
>@@ -335,5 +329,11 @@
> 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
> 	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
> 	radeon_ring_write(ring, 1 << vm->id);
>+
>+	/* wait for invalidate to complete */
>+	radeon_ring_write(ring, DMA_SRBM_READ_PACKET);
>+	radeon_ring_write(ring, (0xff << 20) | (VM_INVALIDATE_REQUEST >> 2));
>+	radeon_ring_write(ring, 0); /* mask */
>+	radeon_ring_write(ring, 0); /* value */
> }
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/ni_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/ni_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/ni_dpm.c	2016-11-25 15:12:00.581360310 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/ni_dpm.c	2016-11-25 15:12:38.361727923 +0100
>@@ -1313,7 +1313,7 @@
> 
> 		table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
> 		table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
>-			cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
>+			cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
> 	}
> }
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/r100.c linux-3.13-wanderer/drivers/gpu/drm/radeon/r100.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/r100.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/r100.c	2016-11-25 15:12:38.365727962 +0100
>@@ -742,6 +742,10 @@
> 		tmp |= RADEON_FP2_DETECT_MASK;
> 	}
> 	WREG32(RADEON_GEN_INT_CNTL, tmp);
>+
>+	/* read back to post the write */
>+	RREG32(RADEON_GEN_INT_CNTL);
>+
> 	return 0;
> }
> 
>@@ -3190,6 +3194,9 @@
> 	uint32_t pixel_bytes1 = 0;
> 	uint32_t pixel_bytes2 = 0;
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	if (rdev->mode_info.crtcs[0]->base.enabled) {
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/r600.c linux-3.13-wanderer/drivers/gpu/drm/radeon/r600.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/r600.c	2016-11-25 15:12:00.585360349 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/r600.c	2016-11-25 15:12:38.377728079 +0100
>@@ -3559,6 +3559,9 @@
> 		WREG32(RV770_CG_THERMAL_INT, thermal_int);
> 	}
> 
>+	/* posting read */
>+	RREG32(R_000E50_SRBM_STATUS);
>+
> 	return 0;
> }
> 
>@@ -3707,6 +3710,7 @@
> 		tmp = RREG32(IH_RB_CNTL);
> 		tmp |= IH_WPTR_OVERFLOW_CLEAR;
> 		WREG32(IH_RB_CNTL, tmp);
>+		wptr &= ~RB_OVERFLOW;
> 	}
> 	return (wptr & rdev->ih.ptr_mask);
> }
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/r600_dma.c linux-3.13-wanderer/drivers/gpu/drm/radeon/r600_dma.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/r600_dma.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/r600_dma.c	2016-11-25 15:12:38.377728079 +0100
>@@ -116,15 +116,6 @@
> 	u32 rb_bufsz;
> 	int r;
> 
>-	/* Reset dma */
>-	if (rdev->family >= CHIP_RV770)
>-		WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
>-	else
>-		WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
>-	RREG32(SRBM_SOFT_RESET);
>-	udelay(50);
>-	WREG32(SRBM_SOFT_RESET, 0);
>-
> 	WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
> 	WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
> 
>@@ -236,16 +227,19 @@
> {
> 	unsigned i;
> 	int r;
>-	void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
>+	unsigned index;
> 	u32 tmp;
>+	u64 gpu_addr;
> 
>-	if (!ptr) {
>-		DRM_ERROR("invalid vram scratch pointer\n");
>-		return -EINVAL;
>-	}
>+	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
>+		index = R600_WB_DMA_RING_TEST_OFFSET;
>+	else
>+		index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
>+
>+	gpu_addr = rdev->wb.gpu_addr + index;
> 
> 	tmp = 0xCAFEDEAD;
>-	writel(tmp, ptr);
>+	rdev->wb.wb[index/4] = cpu_to_le32(tmp);
> 
> 	r = radeon_ring_lock(rdev, ring, 4);
> 	if (r) {
>@@ -253,13 +247,13 @@
> 		return r;
> 	}
> 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
>-	radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
>-	radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
>+	radeon_ring_write(ring, lower_32_bits(gpu_addr));
>+	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
> 	radeon_ring_write(ring, 0xDEADBEEF);
> 	radeon_ring_unlock_commit(rdev, ring);
> 
> 	for (i = 0; i < rdev->usec_timeout; i++) {
>-		tmp = readl(ptr);
>+		tmp = le32_to_cpu(rdev->wb.wb[index/4]);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		DRM_UDELAY(1);
>@@ -339,17 +333,17 @@
> {
> 	struct radeon_ib ib;
> 	unsigned i;
>+	unsigned index;
> 	int r;
>-	void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
> 	u32 tmp = 0;
>+	u64 gpu_addr;
> 
>-	if (!ptr) {
>-		DRM_ERROR("invalid vram scratch pointer\n");
>-		return -EINVAL;
>-	}
>+	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
>+		index = R600_WB_DMA_RING_TEST_OFFSET;
>+	else
>+		index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
> 
>-	tmp = 0xCAFEDEAD;
>-	writel(tmp, ptr);
>+	gpu_addr = rdev->wb.gpu_addr + index;
> 
> 	r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
> 	if (r) {
>@@ -358,8 +352,8 @@
> 	}
> 
> 	ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
>-	ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
>-	ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
>+	ib.ptr[1] = lower_32_bits(gpu_addr);
>+	ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
> 	ib.ptr[3] = 0xDEADBEEF;
> 	ib.length_dw = 4;
> 
>@@ -375,7 +369,7 @@
> 		return r;
> 	}
> 	for (i = 0; i < rdev->usec_timeout; i++) {
>-		tmp = readl(ptr);
>+		tmp = le32_to_cpu(rdev->wb.wb[index/4]);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		DRM_UDELAY(1);
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/r600_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/r600_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/r600_dpm.c	2016-11-25 15:12:00.585360349 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/r600_dpm.c	2016-11-25 15:12:38.381728118 +0100
>@@ -187,7 +187,7 @@
> 		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
> 			radeon_crtc = to_radeon_crtc(crtc);
> 			if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
>-				vrefresh = radeon_crtc->hw_mode.vrefresh;
>+				vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);
> 				break;
> 			}
> 		}
>@@ -1193,7 +1193,7 @@
> 					(mode_info->atom_context->bios + data_offset +
> 					 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
> 				rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
>-					ppt->usMaximumPowerDeliveryLimit;
>+					le16_to_cpu(ppt->usMaximumPowerDeliveryLimit);
> 				pt = &ppt->power_tune_table;
> 			} else {
> 				ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/r600_hdmi.c linux-3.13-wanderer/drivers/gpu/drm/radeon/r600_hdmi.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/r600_hdmi.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/r600_hdmi.c	2016-11-25 15:12:38.381728118 +0100
>@@ -326,7 +326,7 @@
> 	struct drm_connector *connector;
> 	struct radeon_connector *radeon_connector = NULL;
> 	u32 tmp;
>-	u8 *sadb;
>+	u8 *sadb = NULL;
> 	int sad_count;
> 
> 	/* XXX: setting this register causes hangs on some asics */
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_asic.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_asic.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_asic.c	2016-11-25 15:12:00.597360466 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_asic.c	2016-11-25 15:12:38.389728195 +0100
>@@ -1157,7 +1157,7 @@
> static struct radeon_asic_ring rv770_uvd_ring = {
> 	.ib_execute = &uvd_v1_0_ib_execute,
> 	.emit_fence = &uvd_v2_2_fence_emit,
>-	.emit_semaphore = &uvd_v1_0_semaphore_emit,
>+	.emit_semaphore = &uvd_v2_2_semaphore_emit,
> 	.cs_parse = &radeon_uvd_cs_parse,
> 	.ring_test = &uvd_v1_0_ring_test,
> 	.ib_test = &uvd_v1_0_ib_test,
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_asic.h linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_asic.h
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_asic.h	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_asic.h	2016-11-25 15:12:38.389728195 +0100
>@@ -813,6 +813,10 @@
> int uvd_v2_2_resume(struct radeon_device *rdev);
> void uvd_v2_2_fence_emit(struct radeon_device *rdev,
> 			 struct radeon_fence *fence);
>+bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
>+			     struct radeon_ring *ring,
>+			     struct radeon_semaphore *semaphore,
>+			     bool emit_wait);
> 
> /* uvd v3.1 */
> bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_atombios.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_atombios.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_atombios.c	2016-11-25 15:12:00.597360466 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_atombios.c	2016-11-25 15:12:38.389728195 +0100
>@@ -453,7 +453,9 @@
> 	}
> 
> 	/* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
>-	if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
>+	if (((dev->pdev->device == 0x9802) ||
>+	     (dev->pdev->device == 0x9805) ||
>+	     (dev->pdev->device == 0x9806)) &&
> 	    (dev->pdev->subsystem_vendor == 0x1734) &&
> 	    (dev->pdev->subsystem_device == 0x11bd)) {
> 		if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
>@@ -464,7 +466,6 @@
> 		}
> 	}
> 
>-
> 	return true;
> }
> 
>@@ -1963,7 +1964,7 @@
> 	"adm1032",
> 	"adm1030",
> 	"max6649",
>-	"lm64",
>+	"lm63", /* lm64 */
> 	"f75375",
> 	"asc7xxx",
> };
>@@ -1974,7 +1975,7 @@
> 	"adm1032",
> 	"adm1030",
> 	"max6649",
>-	"lm64",
>+	"lm63", /* lm64 */
> 	"f75375",
> 	"RV6xx",
> 	"RV770",
>@@ -2281,19 +2282,31 @@
> 				 (controller->ucFanParameters &
> 				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
> 			rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
>-		} else if ((controller->ucType ==
>-			    ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
>-			   (controller->ucType ==
>-			    ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
>-			   (controller->ucType ==
>-			    ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
>-			DRM_INFO("Special thermal controller config\n");
>+		} else if (controller->ucType ==
>+			   ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
>+			DRM_INFO("External GPIO thermal controller %s fan control\n",
>+				 (controller->ucFanParameters &
>+				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
>+			rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
>+		} else if (controller->ucType ==
>+			   ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
>+			DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
>+				 (controller->ucFanParameters &
>+				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
>+			rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
>+		} else if (controller->ucType ==
>+			   ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
>+			DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
>+				 (controller->ucFanParameters &
>+				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
>+			rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
> 		} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
> 			DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
> 				 pp_lib_thermal_controller_names[controller->ucType],
> 				 controller->ucI2cAddress >> 1,
> 				 (controller->ucFanParameters &
> 				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
>+			rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
> 			i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
> 			rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
> 			if (rdev->pm.i2c_bus) {
>@@ -3235,6 +3248,42 @@
> 
> 	return 0;
> }
>+
>+union get_voltage_info {
>+	struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
>+	struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
>+};
>+
>+int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
>+				u16 virtual_voltage_id,
>+				u16 *voltage)
>+{
>+	int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
>+	u32 entry_id;
>+	u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
>+	union get_voltage_info args;
>+
>+	for (entry_id = 0; entry_id < count; entry_id++) {
>+		if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
>+		    virtual_voltage_id)
>+			break;
>+	}
>+
>+	if (entry_id >= count)
>+		return -EINVAL;
>+
>+	args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
>+	args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
>+	args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
>+	args.in.ulSCLKFreq =
>+		cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
>+
>+	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
>+
>+	*voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
>+
>+	return 0;
>+}
> 
> int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
> 					  u16 voltage_level, u8 voltage_type,
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_bios.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_bios.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_bios.c	2016-11-25 15:12:00.601360505 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_bios.c	2016-11-25 15:12:38.393728235 +0100
>@@ -76,7 +76,7 @@
> 
> static bool radeon_read_bios(struct radeon_device *rdev)
> {
>-	uint8_t __iomem *bios;
>+	uint8_t __iomem *bios, val1, val2;
> 	size_t size;
> 
> 	rdev->bios = NULL;
>@@ -86,15 +86,19 @@
> 		return false;
> 	}
> 
>-	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
>+	val1 = readb(&bios[0]);
>+	val2 = readb(&bios[1]);
>+
>+	if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
> 		pci_unmap_rom(rdev->pdev, bios);
> 		return false;
> 	}
>-	rdev->bios = kmemdup(bios, size, GFP_KERNEL);
>+	rdev->bios = kzalloc(size, GFP_KERNEL);
> 	if (rdev->bios == NULL) {
> 		pci_unmap_rom(rdev->pdev, bios);
> 		return false;
> 	}
>+	memcpy_fromio(rdev->bios, bios, size);
> 	pci_unmap_rom(rdev->pdev, bios);
> 	return true;
> }
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_combios.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_combios.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_combios.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_combios.c	2016-11-25 15:12:38.393728235 +0100
>@@ -1271,10 +1271,15 @@
> 
> 			if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
> 			    (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
>+				u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
>+
>+				if (hss > lvds->native_mode.hdisplay)
>+					hss = (10 - 1) * 8;
>+
> 				lvds->native_mode.htotal = lvds->native_mode.hdisplay +
> 					(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
> 				lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
>-					(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
>+					hss;
> 				lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
> 					(RBIOS8(tmp + 23) * 8);
> 
>@@ -3398,6 +3403,14 @@
> 	    rdev->pdev->subsystem_device == 0x30ae)
> 		return;
> 
>+	/* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
>+	 * - it hangs on resume inside the dynclk 1 table.
>+	 */
>+	if (rdev->family == CHIP_RS480 &&
>+	    rdev->pdev->subsystem_vendor == 0x103c &&
>+	    rdev->pdev->subsystem_device == 0x280a)
>+		return;
>+
> 	/* DYN CLK 1 */
> 	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
> 	if (table)
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_connectors.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_connectors.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_connectors.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_connectors.c	2016-11-25 15:12:38.397728273 +0100
>@@ -80,6 +80,11 @@
> 			if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
> 				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
> 			} else if (radeon_dp_needs_link_train(radeon_connector)) {
>+				/* Don't try to start link training before we
>+				 * have the dpcd */
>+				if (!radeon_dp_getdpcd(radeon_connector))
>+					return;
>+
> 				/* set it to OFF so that drm_helper_connector_dpms()
> 				 * won't return immediately since the current state
> 				 * is ON at this point.
>@@ -1411,7 +1416,7 @@
> 	struct radeon_device *rdev = dev->dev_private;
> 
> 	if (ASIC_IS_DCE5(rdev) &&
>-	    (rdev->clock.dp_extclk >= 53900) &&
>+	    (rdev->clock.default_dispclk >= 53900) &&
> 	    radeon_connector_encoder_is_hbr2(connector)) {
> 		return true;
> 	}
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_cs.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_cs.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_cs.c	2016-11-25 15:12:00.601360505 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_cs.c	2016-11-25 15:12:38.401728312 +0100
>@@ -179,11 +179,13 @@
> 	u32 ring = RADEON_CS_RING_GFX;
> 	s32 priority = 0;
> 
>+	INIT_LIST_HEAD(&p->validated);
>+
> 	if (!cs->num_chunks) {
> 		return 0;
> 	}
>+
> 	/* get chunks */
>-	INIT_LIST_HEAD(&p->validated);
> 	p->idx = 0;
> 	p->ib.sa_bo = NULL;
> 	p->ib.semaphore = NULL;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_device.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_device.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_device.c	2016-11-25 15:12:00.601360505 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_device.c	2016-11-25 15:12:38.401728312 +0100
>@@ -1309,7 +1309,7 @@
> 
> 	r = radeon_init(rdev);
> 	if (r)
>-		return r;
>+		goto failed;
> 
> 	r = radeon_ib_ring_tests(rdev);
> 	if (r)
>@@ -1329,8 +1329,24 @@
> 		radeon_agp_disable(rdev);
> 		r = radeon_init(rdev);
> 		if (r)
>-			return r;
>+			goto failed;
> 	}
>+
>+	/*
>+	 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
>+	 * after the CP ring have chew one packet at least. Hence here we stop
>+	 * and restart DPM after the radeon_ib_ring_tests().
>+	 */
>+	if (rdev->pm.dpm_enabled &&
>+	    (rdev->pm.pm_method == PM_METHOD_DPM) &&
>+	    (rdev->family == CHIP_TURKS) &&
>+	    (rdev->flags & RADEON_IS_MOBILITY)) {
>+		mutex_lock(&rdev->pm.mutex);
>+		radeon_dpm_disable(rdev);
>+		radeon_dpm_enable(rdev);
>+		mutex_unlock(&rdev->pm.mutex);
>+	}
>+
> 	if ((radeon_testing & 1)) {
> 		if (rdev->accel_working)
> 			radeon_test_moves(rdev);
>@@ -1350,6 +1366,11 @@
> 			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
> 	}
> 	return 0;
>+
>+failed:
>+	if (runtime)
>+		vga_switcheroo_fini_domain_pm_ops(rdev->dev);
>+	return r;
> }
> 
> static void radeon_debugfs_remove_files(struct radeon_device *rdev);
>@@ -1370,6 +1391,8 @@
> 	radeon_bo_evict_vram(rdev);
> 	radeon_fini(rdev);
> 	vga_switcheroo_unregister_client(rdev->pdev);
>+	if (rdev->flags & RADEON_IS_PX)
>+		vga_switcheroo_fini_domain_pm_ops(rdev->dev);
> 	vga_client_register(rdev->pdev, NULL, NULL, NULL);
> 	if (rdev->rio_mem)
> 		pci_iounmap(rdev->pdev, rdev->rio_mem);
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_display.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_display.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_display.c	2016-11-25 15:12:00.601360505 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_display.c	2016-11-25 15:12:38.405728351 +0100
>@@ -753,6 +753,10 @@
> 	struct radeon_device *rdev = dev->dev_private;
> 	int ret = 0;
> 
>+	/* don't leak the edid if we already fetched it in detect() */
>+	if (radeon_connector->edid)
>+		goto got_edid;
>+
> 	/* on hw with routers, select right port */
> 	if (radeon_connector->router.ddc_valid)
> 		radeon_router_select_ddc_port(radeon_connector);
>@@ -792,6 +796,7 @@
> 			radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
> 	}
> 	if (radeon_connector->edid) {
>+got_edid:
> 		drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
> 		ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
> 		drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_drv.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_drv.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_drv.c	2016-11-25 15:12:00.601360505 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_drv.c	2016-11-25 15:12:38.405728351 +0100
>@@ -168,6 +168,7 @@
> int radeon_dpm = -1;
> int radeon_aspm = -1;
> int radeon_runtime_pm = -1;
>+int radeon_bapm = -1;
> 
> MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
> module_param_named(no_wb, radeon_no_wb, int, 0444);
>@@ -232,6 +233,9 @@
> MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
> module_param_named(runpm, radeon_runtime_pm, int, 0444);
> 
>+MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
>+module_param_named(bapm, radeon_bapm, int, 0444);
>+
> static struct pci_device_id pciidlist[] = {
> 	radeon_PCI_IDS
> };
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_encoders.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_encoders.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_encoders.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_encoders.c	2016-11-25 15:12:38.405728351 +0100
>@@ -179,7 +179,6 @@
> 						radeon_atom_backlight_init(radeon_encoder, connector);
> 					else
> 						radeon_legacy_backlight_init(radeon_encoder, connector);
>-					rdev->mode_info.bl_encoder = radeon_encoder;
> 				}
> 			}
> 		}
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_gart.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_gart.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_gart.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_gart.c	2016-11-25 15:12:38.405728351 +0100
>@@ -251,8 +251,10 @@
> 			}
> 		}
> 	}
>-	mb();
>-	radeon_gart_tlb_flush(rdev);
>+	if (rdev->gart.ptr) {
>+		mb();
>+		radeon_gart_tlb_flush(rdev);
>+	}
> }
> 
> /**
>@@ -294,8 +296,10 @@
> 			}
> 		}
> 	}
>-	mb();
>-	radeon_gart_tlb_flush(rdev);
>+	if (rdev->gart.ptr) {
>+		mb();
>+		radeon_gart_tlb_flush(rdev);
>+	}
> 	return 0;
> }
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon.h linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon.h
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon.h	2016-11-25 15:12:00.593360427 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon.h	2016-11-25 15:12:38.381728118 +0100
>@@ -99,6 +99,7 @@
> extern int radeon_dpm;
> extern int radeon_aspm;
> extern int radeon_runtime_pm;
>+extern int radeon_bapm;
> 
> /*
>  * Copy from radeon_drv.h so we don't have to include both and have conflicting
>@@ -289,6 +290,9 @@
> 							 u16 *vddc, u16 *vddci,
> 							 u16 virtual_voltage_id,
> 							 u16 vbios_voltage_id);
>+int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
>+				u16 virtual_voltage_id,
>+				u16 *voltage);
> int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
> 				      u8 voltage_type,
> 				      u16 nominal_voltage,
>@@ -1077,6 +1081,8 @@
> #define R600_WB_EVENT_OFFSET     3072
> #define CIK_WB_CP1_WPTR_OFFSET     3328
> #define CIK_WB_CP2_WPTR_OFFSET     3584
>+#define R600_WB_DMA_RING_TEST_OFFSET 3588
>+#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
> 
> /**
>  * struct radeon_pm - power management datas
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_irq_kms.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_irq_kms.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_irq_kms.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_irq_kms.c	2016-11-25 15:12:38.405728351 +0100
>@@ -79,10 +79,12 @@
> 	struct drm_mode_config *mode_config = &dev->mode_config;
> 	struct drm_connector *connector;
> 
>+	mutex_lock(&mode_config->mutex);
> 	if (mode_config->num_connector) {
> 		list_for_each_entry(connector, &mode_config->connector_list, head)
> 			radeon_connector_hotplug(connector);
> 	}
>+	mutex_unlock(&mode_config->mutex);
> 	/* Just fire off a uevent and let userspace tell us what to do */
> 	drm_helper_hpd_irq_event(dev);
> }
>@@ -202,6 +204,16 @@
> 	if (rdev->flags & RADEON_IS_AGP)
> 		return false;
> 
>+	/*
>+	 * Older chips have a HW limitation, they can only generate 40 bits
>+	 * of address for "64-bit" MSIs which breaks on some platforms, notably
>+	 * IBM POWER servers, so we limit them
>+	 */
>+	if (rdev->family < CHIP_BONAIRE) {
>+		dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
>+		rdev->pdev->no_64bit_msi = 1;
>+	}
>+
> 	/* force MSI on */
> 	if (radeon_msi == 1)
> 		return true;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_kms.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_kms.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_kms.c	2016-11-25 15:12:00.613360622 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_kms.c	2016-11-25 15:12:38.405728351 +0100
>@@ -254,7 +254,14 @@
> 		}
> 		break;
> 	case RADEON_INFO_ACCEL_WORKING2:
>-		*value = rdev->accel_working;
>+		if (rdev->family == CHIP_HAWAII) {
>+			if (rdev->accel_working)
>+				*value = 2;
>+			else
>+				*value = 0;
>+		} else {
>+			*value = rdev->accel_working;
>+		}
> 		break;
> 	case RADEON_INFO_TILING_CONFIG:
> 		if (rdev->family >= CHIP_BONAIRE)
>@@ -732,6 +739,8 @@
> 
> 	/* Get associated drm_crtc: */
> 	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
>+	if (!drmcrtc)
>+		return -EINVAL;
> 
> 	/* Helper routine in DRM core does all the work: */
> 	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_legacy_encoders.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_legacy_encoders.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_legacy_encoders.c	2016-11-25 15:12:38.405728351 +0100
>@@ -441,6 +441,7 @@
> 	backlight_update_status(bd);
> 
> 	DRM_INFO("radeon legacy LVDS backlight initialized\n");
>+	rdev->mode_info.bl_encoder = radeon_encoder;
> 
> 	return;
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_pm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_pm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_pm.c	2016-11-25 15:12:00.613360622 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_pm.c	2016-11-25 15:12:38.409728390 +0100
>@@ -458,10 +458,6 @@
> 	struct radeon_device *rdev = ddev->dev_private;
> 	enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
> 
>-	if  ((rdev->flags & RADEON_IS_PX) &&
>-	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
>-		return snprintf(buf, PAGE_SIZE, "off\n");
>-
> 	return snprintf(buf, PAGE_SIZE, "%s\n",
> 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
> 			(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
>@@ -475,11 +471,6 @@
> 	struct drm_device *ddev = dev_get_drvdata(dev);
> 	struct radeon_device *rdev = ddev->dev_private;
> 
>-	/* Can't set dpm state when the card is off */
>-	if  ((rdev->flags & RADEON_IS_PX) &&
>-	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
>-		return -EINVAL;
>-
> 	mutex_lock(&rdev->pm.mutex);
> 	if (strncmp("battery", buf, strlen("battery")) == 0)
> 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
>@@ -493,7 +484,12 @@
> 		goto fail;
> 	}
> 	mutex_unlock(&rdev->pm.mutex);
>-	radeon_pm_compute_clocks(rdev);
>+
>+	/* Can't set dpm state when the card is off */
>+	if (!(rdev->flags & RADEON_IS_PX) ||
>+	    (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
>+		radeon_pm_compute_clocks(rdev);
>+
> fail:
> 	return count;
> }
>@@ -922,9 +918,6 @@
> 	/* update displays */
> 	radeon_dpm_display_configuration_changed(rdev);
> 
>-	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
>-	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
>-
> 	/* wait for the rings to drain */
> 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
> 		struct radeon_ring *ring = &rdev->ring[i];
>@@ -940,6 +933,9 @@
> 
> 	radeon_dpm_post_set_power_state(rdev);
> 
>+	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
>+	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
>+
> 	if (rdev->asic->dpm.force_performance_level) {
> 		if (rdev->pm.dpm.thermal_active) {
> 			enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
>@@ -1259,8 +1255,39 @@
> 	return 0;
> }
> 
>+struct radeon_dpm_quirk {
>+	u32 chip_vendor;
>+	u32 chip_device;
>+	u32 subsys_vendor;
>+	u32 subsys_device;
>+};
>+
>+/* cards with dpm stability problems */
>+static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
>+	/* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
>+	{ PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
>+	/* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
>+	{ PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
>+	{ 0, 0, 0, 0 },
>+};
>+
> int radeon_pm_init(struct radeon_device *rdev)
> {
>+	struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
>+	bool disable_dpm = false;
>+
>+	/* Apply dpm quirks */
>+	while (p && p->chip_device != 0) {
>+		if (rdev->pdev->vendor == p->chip_vendor &&
>+		    rdev->pdev->device == p->chip_device &&
>+		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
>+		    rdev->pdev->subsystem_device == p->subsys_device) {
>+			disable_dpm = true;
>+			break;
>+		}
>+		++p;
>+	}
>+
> 	/* enable dpm on rv6xx+ */
> 	switch (rdev->family) {
> 	case CHIP_RV610:
>@@ -1271,10 +1298,6 @@
> 	case CHIP_RS780:
> 	case CHIP_RS880:
> 	case CHIP_RV770:
>-	case CHIP_BARTS:
>-	case CHIP_TURKS:
>-	case CHIP_CAICOS:
>-	case CHIP_CAYMAN:
> 	case CHIP_BONAIRE:
> 	case CHIP_KABINI:
> 	case CHIP_KAVERI:
>@@ -1302,6 +1325,10 @@
> 	case CHIP_PALM:
> 	case CHIP_SUMO:
> 	case CHIP_SUMO2:
>+	case CHIP_BARTS:
>+	case CHIP_TURKS:
>+	case CHIP_CAICOS:
>+	case CHIP_CAYMAN:
> 	case CHIP_ARUBA:
> 	case CHIP_TAHITI:
> 	case CHIP_PITCAIRN:
>@@ -1315,6 +1342,8 @@
> 			 (!(rdev->flags & RADEON_IS_IGP)) &&
> 			 (!rdev->smc_fw))
> 			rdev->pm.pm_method = PM_METHOD_PROFILE;
>+		else if (disable_dpm && (radeon_dpm == -1))
>+			rdev->pm.pm_method = PM_METHOD_PROFILE;
> 		else if (radeon_dpm == 0)
> 			rdev->pm.pm_method = PM_METHOD_PROFILE;
> 		else
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_semaphore.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_semaphore.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_semaphore.c	2016-11-25 15:12:00.617360660 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_semaphore.c	2016-11-25 15:12:38.409728390 +0100
>@@ -34,7 +34,7 @@
> int radeon_semaphore_create(struct radeon_device *rdev,
> 			    struct radeon_semaphore **semaphore)
> {
>-	uint32_t *cpu_addr;
>+	uint64_t *cpu_addr;
> 	int i, r;
> 
> 	*semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL);
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_ttm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_ttm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_ttm.c	2016-11-25 15:12:00.617360660 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_ttm.c	2016-11-25 15:12:38.409728390 +0100
>@@ -189,7 +189,7 @@
> 	rbo = container_of(bo, struct radeon_bo, tbo);
> 	switch (bo->mem.mem_type) {
> 	case TTM_PL_VRAM:
>-		if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
>+		if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
> 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
> 		else
> 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
>@@ -621,7 +621,7 @@
> 						       0, PAGE_SIZE,
> 						       PCI_DMA_BIDIRECTIONAL);
> 		if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
>-			while (--i) {
>+			while (i--) {
> 				pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
> 					       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
> 				gtt->ttm.dma_address[i] = 0;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_uvd.c linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_uvd.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/radeon_uvd.c	2016-11-25 15:12:00.629360777 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/radeon_uvd.c	2016-11-25 15:12:38.413728429 +0100
>@@ -350,6 +350,29 @@
> 	return 0;
> }
> 
>+static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
>+				     unsigned stream_type)
>+{
>+	switch (stream_type) {
>+	case 0: /* H264 */
>+	case 1: /* VC1 */
>+		/* always supported */
>+		return 0;
>+
>+	case 3: /* MPEG2 */
>+	case 4: /* MPEG4 */
>+		/* only since UVD 3 */
>+		if (p->rdev->family >= CHIP_PALM)
>+			return 0;
>+
>+		/* fall through */
>+	default:
>+		DRM_ERROR("UVD codec not supported by hardware %d!\n",
>+			  stream_type);
>+		return -EINVAL;
>+	}
>+}
>+
> static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
> 			     unsigned offset, unsigned buf_sizes[])
> {
>@@ -388,50 +411,70 @@
> 		return -EINVAL;
> 	}
> 
>-	if (msg_type == 1) {
>-		/* it's a decode msg, calc buffer sizes */
>-		r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
>-		/* calc image size (width * height) */
>-		img_size = msg[6] * msg[7];
>+	switch (msg_type) {
>+	case 0:
>+		/* it's a create msg, calc image size (width * height) */
>+		img_size = msg[7] * msg[8];
>+
>+		r = radeon_uvd_validate_codec(p, msg[4]);
> 		radeon_bo_kunmap(bo);
> 		if (r)
> 			return r;
> 
>-	} else if (msg_type == 2) {
>+		/* try to alloc a new handle */
>+		for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
>+			if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
>+				DRM_ERROR("Handle 0x%x already in use!\n", handle);
>+				return -EINVAL;
>+			}
>+
>+			if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
>+				p->rdev->uvd.filp[i] = p->filp;
>+				p->rdev->uvd.img_size[i] = img_size;
>+				return 0;
>+			}
>+		}
>+
>+		DRM_ERROR("No more free UVD handles!\n");
>+		return -EINVAL;
>+
>+	case 1:
>+		/* it's a decode msg, validate codec and calc buffer sizes */
>+		r = radeon_uvd_validate_codec(p, msg[4]);
>+		if (!r)
>+			r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
>+		radeon_bo_kunmap(bo);
>+		if (r)
>+			return r;
>+
>+		/* validate the handle */
>+		for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
>+			if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
>+				if (p->rdev->uvd.filp[i] != p->filp) {
>+					DRM_ERROR("UVD handle collision detected!\n");
>+					return -EINVAL;
>+				}
>+				return 0;
>+			}
>+		}
>+
>+		DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
>+		return -ENOENT;
>+
>+	case 2:
> 		/* it's a destroy msg, free the handle */
> 		for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
> 			atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
> 		radeon_bo_kunmap(bo);
> 		return 0;
>-	} else {
>-		/* it's a create msg, calc image size (width * height) */
>-		img_size = msg[7] * msg[8];
>-		radeon_bo_kunmap(bo);
> 
>-		if (msg_type != 0) {
>-			DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
>-			return -EINVAL;
>-		}
>+	default:
> 
>-		/* it's a create msg, no special handling needed */
>-	}
>-
>-	/* create or decode, validate the handle */
>-	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
>-		if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
>-			return 0;
>-	}
>-
>-	/* handle not found try to alloc a new one */
>-	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
>-		if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
>-			p->rdev->uvd.filp[i] = p->filp;
>-			p->rdev->uvd.img_size[i] = img_size;
>-			return 0;
>-		}
>+		DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
>+		return -EINVAL;
> 	}
> 
>-	DRM_ERROR("No more free UVD handles!\n");
>+	BUG();
> 	return -EINVAL;
> }
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/rs600.c linux-3.13-wanderer/drivers/gpu/drm/radeon/rs600.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/rs600.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/rs600.c	2016-11-25 15:12:38.413728429 +0100
>@@ -698,6 +698,10 @@
> 	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
> 	if (ASIC_IS_DCE2(rdev))
> 		WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
>+
>+	/* posting read */
>+	RREG32(R_000040_GEN_INT_CNTL);
>+
> 	return 0;
> }
> 
>@@ -888,6 +892,9 @@
> 	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
> 	/* FIXME: implement full support */
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	if (rdev->mode_info.crtcs[0]->base.enabled)
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/rs690.c linux-3.13-wanderer/drivers/gpu/drm/radeon/rs690.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/rs690.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/rs690.c	2016-11-25 15:12:38.413728429 +0100
>@@ -579,6 +579,9 @@
> 	u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
> 	u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	if (rdev->mode_info.crtcs[0]->base.enabled)
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/rv515.c linux-3.13-wanderer/drivers/gpu/drm/radeon/rv515.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/rv515.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/rv515.c	2016-11-25 15:12:38.413728429 +0100
>@@ -1271,6 +1271,9 @@
> 	struct drm_display_mode *mode0 = NULL;
> 	struct drm_display_mode *mode1 = NULL;
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	if (rdev->mode_info.crtcs[0]->base.enabled)
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/rv730_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/rv730_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/rv730_dpm.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/rv730_dpm.c	2016-11-25 15:12:38.417728468 +0100
>@@ -464,7 +464,7 @@
> 	result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
> 
> 	if (result != PPSMC_Result_OK)
>-		DRM_ERROR("Could not force DPM to low\n");
>+		DRM_DEBUG("Could not force DPM to low\n");
> 
> 	WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
> 
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/rv770d.h linux-3.13-wanderer/drivers/gpu/drm/radeon/rv770d.h
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/rv770d.h	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/rv770d.h	2016-11-25 15:12:38.417728468 +0100
>@@ -982,6 +982,9 @@
> 			 ((n) & 0x3FFF) << 16)
> 
> /* UVD */
>+#define UVD_SEMA_ADDR_LOW				0xef00
>+#define UVD_SEMA_ADDR_HIGH				0xef04
>+#define UVD_SEMA_CMD					0xef08
> #define UVD_GPCOM_VCPU_CMD				0xef0c
> #define UVD_GPCOM_VCPU_DATA0				0xef10
> #define UVD_GPCOM_VCPU_DATA1				0xef14
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/rv770_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/rv770_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/rv770_dpm.c	2016-11-25 15:12:00.629360777 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/rv770_dpm.c	2016-11-25 15:12:38.417728468 +0100
>@@ -192,7 +192,7 @@
> 	result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
> 
> 	if (result != PPSMC_Result_OK)
>-		DRM_ERROR("Could not force DPM to low.\n");
>+		DRM_DEBUG("Could not force DPM to low.\n");
> 
> 	WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
> 
>@@ -1415,7 +1415,7 @@
> int rv770_set_sw_state(struct radeon_device *rdev)
> {
> 	if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
>-		return -EINVAL;
>+		DRM_DEBUG("rv770_set_sw_state failed\n");
> 	return 0;
> }
> 
>@@ -2328,12 +2328,6 @@
> 	pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
> 						       ASIC_INTERNAL_MEMORY_SS, 0);
> 
>-	/* disable ss, causes hangs on some cayman boards */
>-	if (rdev->family == CHIP_CAYMAN) {
>-		pi->sclk_ss = false;
>-		pi->mclk_ss = false;
>-	}
>-
> 	if (pi->sclk_ss || pi->mclk_ss)
> 		pi->dynamic_ss = true;
> 	else
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/si.c linux-3.13-wanderer/drivers/gpu/drm/radeon/si.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/si.c	2016-11-25 15:12:00.629360777 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/si.c	2016-11-25 15:12:38.417728468 +0100
>@@ -2225,6 +2225,9 @@
> 	u32 num_heads = 0, lb_size;
> 	int i;
> 
>+	if (!rdev->mode_info.mode_config_initialized)
>+		return;
>+
> 	radeon_update_display_priority(rdev);
> 
> 	for (i = 0; i < rdev->num_crtc; i++) {
>@@ -3968,7 +3971,7 @@
> 	/* empty context1-15 */
> 	/* set vm size, must be a multiple of 4 */
> 	WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
>-	WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
>+	WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
> 	/* Assign the pt base to something valid for now; the pts used for
> 	 * the VMs are determined by the application and setup and assigned
> 	 * on the fly in the vm part of radeon_gart.c
>@@ -4697,7 +4700,7 @@
> 
> 	/* write new base address */
> 	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>-	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
>+	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
> 				 WRITE_DATA_DST_SEL(0)));
> 
> 	if (vm->id < 8) {
>@@ -4726,6 +4729,16 @@
> 	radeon_ring_write(ring, 0);
> 	radeon_ring_write(ring, 1 << vm->id);
> 
>+	/* wait for the invalidate to complete */
>+	radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
>+	radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
>+				 WAIT_REG_MEM_ENGINE(0))); /* me */
>+	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
>+	radeon_ring_write(ring, 0);
>+	radeon_ring_write(ring, 0); /* ref */
>+	radeon_ring_write(ring, 0); /* mask */
>+	radeon_ring_write(ring, 0x20); /* poll interval */
>+
> 	/* sync PFP to ME, otherwise we might get invalid PFP reads */
> 	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
> 	radeon_ring_write(ring, 0x0);
>@@ -5839,6 +5852,9 @@
> 
> 	WREG32(CG_THERMAL_INT, thermal_int);
> 
>+	/* posting read */
>+	RREG32(SRBM_STATUS);
>+
> 	return 0;
> }
> 
>@@ -5982,6 +5998,7 @@
> 		tmp = RREG32(IH_RB_CNTL);
> 		tmp |= IH_WPTR_OVERFLOW_CLEAR;
> 		WREG32(IH_RB_CNTL, tmp);
>+		wptr &= ~RB_OVERFLOW;
> 	}
> 	return (wptr & rdev->ih.ptr_mask);
> }
>@@ -6753,8 +6770,7 @@
> 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
> 
> 	if (!vclk || !dclk) {
>-		/* keep the Bypass mode, put PLL to sleep */
>-		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
>+		/* keep the Bypass mode */
> 		return 0;
> 	}
> 
>@@ -6770,8 +6786,7 @@
> 	/* set VCO_MODE to 1 */
> 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
> 
>-	/* toggle UPLL_SLEEP to 1 then back to 0 */
>-	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
>+	/* disable sleep mode */
> 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
> 
> 	/* deassert UPLL_RESET */
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/sid.h linux-3.13-wanderer/drivers/gpu/drm/radeon/sid.h
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/sid.h	2016-11-25 15:12:00.633360816 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/sid.h	2016-11-25 15:12:38.425728546 +0100
>@@ -1586,6 +1586,23 @@
> #define	PACKET3_MPEG_INDEX				0x3A
> #define	PACKET3_COPY_DW					0x3B
> #define	PACKET3_WAIT_REG_MEM				0x3C
>+#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
>+                /* 0 - always
>+		 * 1 - <
>+		 * 2 - <=
>+		 * 3 - ==
>+		 * 4 - !=
>+		 * 5 - >=
>+		 * 6 - >
>+		 */
>+#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
>+                /* 0 - reg
>+		 * 1 - mem
>+		 */
>+#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
>+                /* 0 - me
>+		 * 1 - pfp
>+		 */
> #define	PACKET3_MEM_WRITE				0x3D
> #define	PACKET3_COPY_DATA				0x40
> #define	PACKET3_CP_DMA					0x41
>@@ -1789,6 +1806,7 @@
> #define	DMA_PACKET_TRAP					  0x7
> #define	DMA_PACKET_SRBM_WRITE				  0x9
> #define	DMA_PACKET_CONSTANT_FILL			  0xd
>+#define	DMA_PACKET_POLL_REG_MEM				  0xe
> #define	DMA_PACKET_NOP					  0xf
> 
> #endif
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/si_dma.c linux-3.13-wanderer/drivers/gpu/drm/radeon/si_dma.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/si_dma.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/si_dma.c	2016-11-25 15:12:38.421728507 +0100
>@@ -153,6 +153,14 @@
> 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
> 	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
> 	radeon_ring_write(ring, 1 << vm->id);
>+
>+	/* wait for invalidate to complete */
>+	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
>+	radeon_ring_write(ring, VM_INVALIDATE_REQUEST);
>+	radeon_ring_write(ring, 0xff << 16); /* retry */
>+	radeon_ring_write(ring, 1 << vm->id); /* mask */
>+	radeon_ring_write(ring, 0); /* value */
>+	radeon_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
> }
> 
> /**
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/si_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/si_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/si_dpm.c	2016-11-25 15:12:00.629360777 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/si_dpm.c	2016-11-25 15:12:38.421728507 +0100
>@@ -2901,6 +2901,28 @@
> 	return ret;
> }
> 
>+struct si_dpm_quirk {
>+	u32 chip_vendor;
>+	u32 chip_device;
>+	u32 subsys_vendor;
>+	u32 subsys_device;
>+	u32 max_sclk;
>+	u32 max_mclk;
>+};
>+
>+/* cards with dpm stability problems */
>+static struct si_dpm_quirk si_dpm_quirk_list[] = {
>+	/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
>+	{ PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
>+	{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
>+	{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
>+	{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
>+	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
>+	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
>+	{ PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
>+	{ 0, 0, 0, 0 },
>+};
>+
> static void si_apply_state_adjust_rules(struct radeon_device *rdev,
> 					struct radeon_ps *rps)
> {
>@@ -2911,7 +2933,22 @@
> 	u32 mclk, sclk;
> 	u16 vddc, vddci;
> 	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
>+	u32 max_sclk = 0, max_mclk = 0;
> 	int i;
>+	struct si_dpm_quirk *p = si_dpm_quirk_list;
>+
>+	/* Apply dpm quirks */
>+	while (p && p->chip_device != 0) {
>+		if (rdev->pdev->vendor == p->chip_vendor &&
>+		    rdev->pdev->device == p->chip_device &&
>+		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
>+		    rdev->pdev->subsystem_device == p->subsys_device) {
>+			max_sclk = p->max_sclk;
>+			max_mclk = p->max_mclk;
>+			break;
>+		}
>+		++p;
>+	}
> 
> 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
> 	    ni_dpm_vblank_too_short(rdev))
>@@ -2965,6 +3002,14 @@
> 			if (ps->performance_levels[i].mclk > max_mclk_vddc)
> 				ps->performance_levels[i].mclk = max_mclk_vddc;
> 		}
>+		if (max_mclk) {
>+			if (ps->performance_levels[i].mclk > max_mclk)
>+				ps->performance_levels[i].mclk = max_mclk;
>+		}
>+		if (max_sclk) {
>+			if (ps->performance_levels[i].sclk > max_sclk)
>+				ps->performance_levels[i].sclk = max_sclk;
>+		}
> 	}
> 
> 	/* XXX validate the min clocks required for display */
>@@ -6224,7 +6269,7 @@
> 	if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
> 	    index == 0) {
> 		/* XXX disable for A0 tahiti */
>-		si_pi->ulv.supported = true;
>+		si_pi->ulv.supported = false;
> 		si_pi->ulv.pl = *pl;
> 		si_pi->ulv.one_pcie_lane_in_ulv = false;
> 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/trinity_dpm.c linux-3.13-wanderer/drivers/gpu/drm/radeon/trinity_dpm.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/trinity_dpm.c	2014-01-20 03:40:07.000000000 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/trinity_dpm.c	2016-11-25 15:12:38.425728546 +0100
>@@ -1868,7 +1868,22 @@
> 	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
> 		pi->at[i] = TRINITY_AT_DFLT;
> 
>-	pi->enable_bapm = false;
>+	if (radeon_bapm == -1) {
>+		/* There are stability issues reported on with
>+		 * bapm enabled when switching between AC and battery
>+		 * power.  At the same time, some MSI boards hang
>+		 * if it's not enabled and dpm is enabled.  Just enable
>+		 * it for MSI boards right now.
>+		 */
>+		if (rdev->pdev->subsystem_vendor == 0x1462)
>+			pi->enable_bapm = true;
>+		else
>+			pi->enable_bapm = false;
>+	} else if (radeon_bapm == 0) {
>+		pi->enable_bapm = false;
>+	} else {
>+		pi->enable_bapm = true;
>+	}
> 	pi->enable_nbps_policy = true;
> 	pi->enable_sclk_ds = true;
> 	pi->enable_gfx_power_gating = true;
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/uvd_v1_0.c linux-3.13-wanderer/drivers/gpu/drm/radeon/uvd_v1_0.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/uvd_v1_0.c	2016-11-25 15:12:00.633360816 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/uvd_v1_0.c	2016-11-25 15:12:38.425728546 +0100
>@@ -365,18 +365,8 @@
> 			     struct radeon_semaphore *semaphore,
> 			     bool emit_wait)
> {
>-	uint64_t addr = semaphore->gpu_addr;
>-
>-	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
>-	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
>-
>-	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
>-	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
>-
>-	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
>-	radeon_ring_write(ring, emit_wait ? 1 : 0);
>-
>-	return true;
>+	/* disable semaphores for UVD V1 hardware */
>+	return false;
> }
> 
> /**
>diff -urN linux-3.13-tramp/drivers/gpu/drm/radeon/uvd_v2_2.c linux-3.13-wanderer/drivers/gpu/drm/radeon/uvd_v2_2.c
>--- linux-3.13-tramp/drivers/gpu/drm/radeon/uvd_v2_2.c	2016-11-25 15:12:00.633360816 +0100
>+++ linux-3.13-wanderer/drivers/gpu/drm/radeon/uvd_v2_2.c	2016-11-25 15:12:38.425728546 +0100
>@@ -61,6 +61,35 @@
> }
> 
> /**
>+ * uvd_v2_2_semaphore_emit - emit semaphore command
>+ *
>+ * @rdev: radeon_device pointer
>+ * @ring: radeon_ring pointer
>+ * @semaphore: semaphore to emit commands for
>+ * @emit_wait: true if we should emit a wait command
>+ *
>+ * Emit a semaphore command (either wait or signal) to the UVD ring.
>+ */
>+bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
>+			     struct radeon_ring *ring,
>+			     struct radeon_semaphore *semaphore,
>+			     bool emit_wait)
>+{
>+	uint64_t addr = semaphore->gpu_addr;
>+
>+	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
>+	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
>+
>+	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
>+	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
>+
>+	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
>+	radeon_ring_write(ring, emit_wait ? 1 : 0);
>+
>+	return true;
>+}
>+
>+/**
>  * uvd_v2_2_resume - memory controller programming
>  *
>  * @rdev: radeon_device pointer

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