Attachment 128329 Details for Bug 98874 – 3rd dump

3rd dump

X_459_00000000.log (text/plain), 36.27 KB, created by Matthias Nagel on 2016-12-04 12:12:28 UTC

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Creator: Matthias Nagel

Created: 2016-12-04 12:12:28 UTC

Size: 36.27 KB

patch

obsolete

>Command: /usr/bin/X -nolisten tcp -auth /var/run/sddm/{8d13ff65-214f-4639-ae2f-5b4f4d790ad7} -background none -noreset -displayfd 18 vt1 
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD TONGA (DRM 3.3.0 / 4.8.12-gentoo, LLVM 3.9.0)
>
>Draw call sequence # = 644276
>HW reached sequence # = 644275
>Elapsed time = 2000 ms
>
>[1;33mdraw_info: [0m{indexed = 0, mode = triangle_strip, start = 0, count = 4, start_instance = 0, instance_count = 4, vertices_per_patch = 3, index_bias = 0, min_index = 0, max_index = 3, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, }
>
>[1;33mvertex_buffer 0: [0m{stride = 8, buffer_offset = 80828, buffer = 0x01c83060, user_buffer = NULL, }
>  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 524288, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 3, }
>[1;33mnum vertex elements[0m = 1
>  [1;33mvertex_element 0: [0m{src_offset = 0, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R16G16B16A16_SSCALED, }
>[1;33mnum stream output targets[0m = 0
>
>[1;32mbegin shader: VERTEX[0m
>[1;33mshader_state: [0m{tokens = "
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL SV[0], VERTEXID
>DCL OUT[0], POSITION
>DCL CONST[0]
>DCL TEMP[0..1], LOCAL
>IMM[0] INT32 {1, 2, 0, 0}
>IMM[1] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: AND TEMP[0].x, SV[0].xxxx, IMM[0].xxxx
>  1: I2F TEMP[0].x, TEMP[0].xxxx
>  2: AND TEMP[1].x, SV[0].xxxx, IMM[0].yyyy
>  3: ISHR TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
>  4: I2F TEMP[1].x, TEMP[1].xxxx
>  5: MOV TEMP[0].y, TEMP[1].xxxx
>  6: MAD TEMP[0].xy, IN[0].zwww, TEMP[0].xyyy, IN[0].xyyy
>  7: MAD TEMP[0].xy, TEMP[0].xyyy, CONST[0].xzzz, CONST[0].ywww
>  8: MOV TEMP[0].zw, IMM[1].yyxy
>  9: MOV OUT[0], TEMP[0]
> 10: END
>", }
>[1;33mconstant_buffer 0: [0m{buffer = NULL, buffer_offset = 0, buffer_size = 16, user_buffer = 0x029025c0, }
>[1;32mend shader: VERTEX[0m
>
>[1;33mviewport_state 0: [0m{scale = {960, 568.5, 0.5, }, translate = {960, 568.5, 0.5, }, }
>[1;33mscissor_state 0: [0m{minx = 0, miny = 0, maxx = 1920, maxy = 1137, }
>[1;33mrasterizer_state: [0m{flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 1, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 1, point_quad_rasterization = 1, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 65535, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 1, clip_halfz = 0, clip_plane_enable = 0, line_width = 1, point_size = 1, offset_units = 0, offset_scale = 0, offset_clamp = 0, }
>
>[1;32mbegin shader: FRAGMENT[0m
>[1;33mshader_state: [0m{tokens = "
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0]
>  0: MOV OUT[0], CONST[0]
>  1: END
>", }
>[1;33mconstant_buffer 0: [0m{buffer = NULL, buffer_offset = 0, buffer_size = 16, user_buffer = 0x02910560, }
>[1;32mend shader: FRAGMENT[0m
>
>[1;33mdepth_stencil_alpha_state: [0m{depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
>[1;33mstencil_ref: [0m{ref_value = {0, 0, }, }
>[1;33mblend_state: [0m{dither = 1, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, }
>[1;33mblend_color: [0m{color = {0, 0, 0, 0, }, }
>[1;33mmin_samples[0m = 1
>[1;33msample_mask[0m = 0xffffffff
>
>[1;33mframebuffer_state: [0m{width = 1920, height = 1137, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0x0219be80, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, }
>  [1;33mcbufs[0]:[0m
>    [1;33msurface: [0m{format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 1920, height = 1137, texture = 0x02b80fd0, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
>    [1;33mresource: [0m{target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 1920, height0 = 1137, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 4, }
>
>
>
>*****************************************************************************
>Driver-specific state:
>
>SHADER KEY
>  instance_divisors = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>
>Vertex Shader as VS - main shader part - LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32) {
>main_body:
>  %15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <16 x i8>, <16 x i8> addrspace(2)* %15, align 16, !invariant.load !0
>  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %14)
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = extractelement <4 x float> %17, i32 2
>  %21 = extractelement <4 x float> %17, i32 3
>  %22 = add i32 %10, %6
>  %23 = and i32 %22, 1
>  %24 = sitofp i32 %23 to float
>  %25 = lshr i32 %22, 1
>  %26 = and i32 %25, 1
>  %27 = sitofp i32 %26 to float
>  %28 = fmul float %20, %24
>  %29 = fadd float %28, %18
>  %30 = fmul float %21, %27
>  %31 = fadd float %30, %19
>  %32 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %33 = load <16 x i8>, <16 x i8> addrspace(2)* %32, align 16, !invariant.load !0
>  %34 = call float @llvm.SI.load.const(<16 x i8> %33, i32 0)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %33, i32 4)
>  %36 = fmul float %29, %34
>  %37 = fadd float %36, %35
>  %38 = call float @llvm.SI.load.const(<16 x i8> %33, i32 8)
>  %39 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %40 = load <16 x i8>, <16 x i8> addrspace(2)* %39, align 16, !invariant.load !0
>  %41 = call float @llvm.SI.load.const(<16 x i8> %40, i32 12)
>  %42 = fmul float %31, %38
>  %43 = fadd float %42, %41
>  %44 = bitcast i32 %12 to float
>  %45 = insertvalue <{ float, float, float }> undef, float %44, 2
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %37, float %43, float 0.000000e+00, float 1.000000e+00)
>  ret <{ float, float, float }> %45
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #0
>
>; Function Attrs: nounwind
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) #1
>
>attributes #0 = { nounwind readnone }
>attributes #1 = { nounwind }
>
>!0 = !{}
>
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s13, v3 ; 3208060D
>Shader main disassembly:
>	s_load_dwordx4 s[4:7], s[10:11], 0x0                ; C00A0105 00000000
>	s_load_dwordx4 s[0:3], s[2:3], 0x0                  ; C00A0001 00000000
>	v_add_i32_e32 v0, vcc, s12, v0                      ; 3200000C
>	v_and_b32_e32 v1, 1, v0                             ; 26020081
>	v_bfe_u32 v0, v0, 1, 1                              ; D1C80000 02050300
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	buffer_load_format_xyzw v[3:6], v4, s[4:7], 0 idxen ; E00C2000 80010304
>	s_buffer_load_dword s4, s[0:3], 0x0                 ; C0220100 00000000
>	s_buffer_load_dword s5, s[0:3], 0x4                 ; C0220140 00000004
>	s_buffer_load_dword s6, s[0:3], 0x8                 ; C0220180 00000008
>	s_buffer_load_dword s0, s[0:3], 0xc                 ; C0220000 0000000C
>	v_cvt_f32_i32_e32 v1, v1                            ; 7E020B01
>	v_cvt_f32_i32_e32 v0, v0                            ; 7E000B00
>	s_waitcnt vmcnt(0)                                  ; BF8C0F70
>	v_mad_f32 v1, v1, v5, v3                            ; D1C10001 040E0B01
>	v_mad_f32 v0, v0, v6, v4                            ; D1C10000 04120D00
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	v_mov_b32_e32 v4, s5                                ; 7E080205
>	v_mov_b32_e32 v5, s0                                ; 7E0A0200
>	v_mac_f32_e32 v5, s6, v0                            ; 2C0A0006
>	v_mov_b32_e32 v3, 1.0                               ; 7E0602F2
>	v_mac_f32_e32 v4, s4, v1                            ; 2C080204
>	v_mov_b32_e32 v0, 0                                 ; 7E000280
>	exp 15, 12, 0, 1, 0, v4, v5, v0, v3                 ; C40008CF 03000504
>	s_waitcnt expcnt(0)                                 ; BF8C0F0F
>Shader epilog disassembly:
>	s_endpgm ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 8
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Code Size: 152 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.flatshade_colors = 0
>  prolog.poly_stipple = 0
>  prolog.force_persp_sample_interp = 0
>  prolog.force_linear_sample_interp = 0
>  prolog.force_persp_center_interp = 0
>  prolog.force_linear_center_interp = 0
>  prolog.bc_optimize_for_persp = 0
>  prolog.bc_optimize_for_linear = 0
>  epilog.spi_shader_col_format = 0x4
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 7
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>
>Pixel Shader - main shader part - LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %23 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !invariant.load !0
>  %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12)
>  %29 = bitcast float %5 to i32
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %29, 10
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %30, float %25, 11
>  %32 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %31, float %26, 12
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %32, float %27, 13
>  %34 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %33, float %28, 14
>  %35 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %34, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %35
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>attributes #1 = { nounwind readnone }
>
>!0 = !{}
>
>
>Pixel Shader:
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[2:3], 0x0  ; C00A0001 00000000
>	s_nop 0                             ; BF800000
>	s_waitcnt lgkmcnt(0)                ; BF8C007F
>	s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000
>	s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004
>	s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008
>	s_buffer_load_dword s0, s[0:3], 0xc ; C0220000 0000000C
>	s_waitcnt lgkmcnt(0)                ; BF8C007F
>	v_mov_b32_e32 v0, s4                ; 7E000204
>	v_mov_b32_e32 v1, s5                ; 7E020205
>	v_mov_b32_e32 v2, s6                ; 7E040206
>	v_mov_b32_e32 v3, s0                ; 7E060200
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702
>	exp 15, 0, 1, 1, 1, v0, v1, v0, v0 ; C4001C0F 00000100
>	s_endpgm                           ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 16
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Code Size: 96 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>
>Memory-mapped registers:
>        [1;33mGRBM_STATUS[0m <- ME0PIPE0_CMDFIFO_AVAIL = 8
>                       SRBM_RQ_PENDING = 1
>                       ME0PIPE0_CF_RQ_PENDING = 0
>                       ME0PIPE0_PF_RQ_PENDING = 0
>                       GDS_DMA_RQ_PENDING = 0
>                       DB_CLEAN = 1
>                       CB_CLEAN = 1
>                       TA_BUSY = 0
>                       GDS_BUSY = 0
>                       WD_BUSY_NO_DMA = 0
>                       VGT_BUSY = 0
>                       IA_BUSY_NO_DMA = 0
>                       IA_BUSY = 0
>                       SX_BUSY = 0
>                       WD_BUSY = 0
>                       SPI_BUSY = 0
>                       BCI_BUSY = 0
>                       SC_BUSY = 0
>                       PA_BUSY = 0
>                       DB_BUSY = 0
>                       CP_COHERENCY_BUSY = 0
>                       CP_BUSY = 1
>                       CB_BUSY = 0
>                       GUI_ACTIVE = 1
>        [1;33mGRBM_STATUS2[0m <- ME0PIPE1_CMDFIFO_AVAIL = 8
>                        ME0PIPE1_CF_RQ_PENDING = 0
>                        ME0PIPE1_PF_RQ_PENDING = 0
>                        ME1PIPE0_RQ_PENDING = 0
>                        ME1PIPE1_RQ_PENDING = 0
>                        ME1PIPE2_RQ_PENDING = 0
>                        ME1PIPE3_RQ_PENDING = 0
>                        ME2PIPE0_RQ_PENDING = 0
>                        ME2PIPE1_RQ_PENDING = 0
>                        ME2PIPE2_RQ_PENDING = 0
>                        ME2PIPE3_RQ_PENDING = 0
>                        RLC_RQ_PENDING = 0
>                        RLC_BUSY = 0
>                        TC_BUSY = 0
>                        TCC_CC_RESIDENT = 0
>                        CPF_BUSY = 1
>                        CPC_BUSY = 0
>                        CPG_BUSY = 1
>        [1;33mGRBM_STATUS_SE0[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mGRBM_STATUS_SE1[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mGRBM_STATUS_SE2[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mGRBM_STATUS_SE3[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mSDMA0_STATUS_REG[0m <- IDLE = 1
>                            REG_IDLE = 1
>                            RB_EMPTY = 1
>                            RB_FULL = 0
>                            RB_CMD_IDLE = 1
>                            RB_CMD_FULL = 0
>                            IB_CMD_IDLE = 1
>                            IB_CMD_FULL = 0
>                            BLOCK_IDLE = 1
>                            INSIDE_IB = 0
>                            EX_IDLE = 1
>                            EX_IDLE_POLL_TIMER_EXPIRE = 1
>                            PACKET_READY = 0
>                            MC_WR_IDLE = 1
>                            SRBM_IDLE = 1
>                            CONTEXT_EMPTY = 1
>                            DELTA_RPTR_FULL = 0
>                            RB_MC_RREQ_IDLE = 1
>                            IB_MC_RREQ_IDLE = 1
>                            MC_RD_IDLE = 1
>                            DELTA_RPTR_EMPTY = 1
>                            MC_RD_RET_STALL = 0
>                            MC_RD_NO_POLL_IDLE = 1
>                            PREV_CMD_IDLE = 1
>                            SEM_IDLE = 1
>                            SEM_REQ_STALL = 0
>                            SEM_RESP_STATE = 0
>                            INT_IDLE = 1
>                            INT_REQ_STALL = 0
>        [1;33mSDMA1_STATUS_REG[0m <- IDLE = 1
>                            REG_IDLE = 1
>                            RB_EMPTY = 1
>                            RB_FULL = 0
>                            RB_CMD_IDLE = 1
>                            RB_CMD_FULL = 0
>                            IB_CMD_IDLE = 1
>                            IB_CMD_FULL = 0
>                            BLOCK_IDLE = 1
>                            INSIDE_IB = 0
>                            EX_IDLE = 1
>                            EX_IDLE_POLL_TIMER_EXPIRE = 1
>                            PACKET_READY = 0
>                            MC_WR_IDLE = 1
>                            SRBM_IDLE = 1
>                            CONTEXT_EMPTY = 1
>                            DELTA_RPTR_FULL = 0
>                            RB_MC_RREQ_IDLE = 1
>                            IB_MC_RREQ_IDLE = 1
>                            MC_RD_IDLE = 1
>                            DELTA_RPTR_EMPTY = 1
>                            MC_RD_RET_STALL = 0
>                            MC_RD_NO_POLL_IDLE = 1
>                            PREV_CMD_IDLE = 1
>                            SEM_IDLE = 1
>                            SEM_REQ_STALL = 0
>                            SEM_RESP_STATE = 0
>                            INT_IDLE = 1
>                            INT_REQ_STALL = 0
>        [1;33mSRBM_STATUS[0m <- UVD_RQ_PENDING = 0
>                       SAMMSP_RQ_PENDING = 0
>                       ACP_RQ_PENDING = 0
>                       SMU_RQ_PENDING = 0
>                       GRBM_RQ_PENDING = 0
>                       HI_RQ_PENDING = 1
>                       VMC_BUSY = 0
>                       MCB_BUSY = 0
>                       MCB_NON_DISPLAY_BUSY = 0
>                       MCC_BUSY = 0
>                       MCD_BUSY = 0
>                       VMC1_BUSY = 0
>                       SEM_BUSY = 0
>                       ACP_BUSY = 0
>                       IH_BUSY = 0
>                       UVD_BUSY = 0
>                       SAMMSP_BUSY = 0
>                       GCATCL2_BUSY = 0
>                       OSATCL2_BUSY = 0
>                       BIF_BUSY = 1
>        [1;33mSRBM_STATUS2[0m <- SDMA_RQ_PENDING = 0
>                        TST_RQ_PENDING = 0
>                        SDMA1_RQ_PENDING = 0
>                        VCE0_RQ_PENDING = 0
>                        VP8_BUSY = 0
>                        SDMA_BUSY = 0
>                        SDMA1_BUSY = 0
>                        VCE0_BUSY = 1
>                        XDMA_BUSY = 0
>                        CHUB_BUSY = 0
>                        SDMA2_BUSY = 0
>                        SDMA3_BUSY = 0
>                        SAMSCP_BUSY = 0
>                        ISP_BUSY = 0
>                        VCE1_BUSY = 0
>                        ODE_BUSY = 0
>                        SDMA2_RQ_PENDING = 0
>                        SDMA3_RQ_PENDING = 0
>                        SAMSCP_RQ_PENDING = 0
>                        ISP_RQ_PENDING = 0
>                        VCE1_RQ_PENDING = 0
>        [1;33mSRBM_STATUS3[0m <- MCC0_BUSY = 0
>                        MCC1_BUSY = 0
>                        MCC2_BUSY = 0
>                        MCC3_BUSY = 0
>                        MCC4_BUSY = 0
>                        MCC5_BUSY = 0
>                        MCC6_BUSY = 0
>                        MCC7_BUSY = 0
>                        MCD0_BUSY = 0
>                        MCD1_BUSY = 0
>                        MCD2_BUSY = 0
>                        MCD3_BUSY = 0
>                        MCD4_BUSY = 0
>                        MCD5_BUSY = 0
>                        MCD6_BUSY = 0
>                        MCD7_BUSY = 0
>        [1;33mCP_STAT[0m <- ROQ_RING_BUSY = 1
>                   ROQ_INDIRECT1_BUSY = 1
>                   ROQ_INDIRECT2_BUSY = 1
>                   ROQ_STATE_BUSY = 0
>                   DC_BUSY = 0
>                   ATCL2IU_BUSY = 0
>                   PFP_BUSY = 1
>                   MEQ_BUSY = 0
>                   ME_BUSY = 1
>                   QUERY_BUSY = 0
>                   SEMAPHORE_BUSY = 0
>                   INTERRUPT_BUSY = 0
>                   SURFACE_SYNC_BUSY = 0
>                   DMA_BUSY = 0
>                   RCIU_BUSY = 0
>                   SCRATCH_RAM_BUSY = 0
>                   CPC_CPG_BUSY = 0
>                   CE_BUSY = 0
>                   TCIU_BUSY = 0
>                   ROQ_CE_RING_BUSY = 0
>                   ROQ_CE_INDIRECT1_BUSY = 0
>                   ROQ_CE_INDIRECT2_BUSY = 0
>                   CP_BUSY = 1
>        [1;33mCP_STALLED_STAT1[0m <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0
>                            RBIU_TO_SEM_NOT_RDY_TO_RCV = 0
>                            RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0
>                            ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1
>                            ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1
>                            ME_STALLED_ON_TC_WR_CONFIRM = 0
>                            ME_STALLED_ON_ATOMIC_RTN_DATA = 0
>                            ME_WAITING_ON_TC_READ_DATA = 0
>                            ME_WAITING_ON_REG_READ_DATA = 0
>                            RCIU_WAITING_ON_GDS_FREE = 0
>                            RCIU_WAITING_ON_GRBM_FREE = 0
>                            RCIU_WAITING_ON_VGT_FREE = 0
>                            RCIU_STALLED_ON_ME_READ = 0
>                            RCIU_STALLED_ON_DMA_READ = 0
>                            RCIU_STALLED_ON_APPEND_READ = 0
>                            RCIU_HALTED_BY_REG_VIOLATION = 0
>        [1;33mCP_STALLED_STAT2[0m <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0
>                            PFP_TO_MEQ_NOT_RDY_TO_RCV = 0
>                            PFP_TO_RCIU_NOT_RDY_TO_RCV = 0
>                            PFP_TO_VGT_WRITES_PENDING = 0
>                            PFP_RCIU_READ_PENDING = 0
>                            PFP_WAITING_ON_BUFFER_DATA = 1
>                            ME_WAIT_ON_CE_COUNTER = 0
>                            ME_WAIT_ON_AVAIL_BUFFER = 0
>                            GFX_CNTX_NOT_AVAIL_TO_ME = 0
>                            ME_RCIU_NOT_RDY_TO_RCV = 0
>                            ME_TO_CONST_NOT_RDY_TO_RCV = 0
>                            ME_WAITING_DATA_FROM_PFP = 1
>                            ME_WAITING_ON_PARTIAL_FLUSH = 0
>                            MEQ_TO_ME_NOT_RDY_TO_RCV = 0
>                            STQ_TO_ME_NOT_RDY_TO_RCV = 0
>                            ME_WAITING_DATA_FROM_STQ = 0
>                            PFP_STALLED_ON_TC_WR_CONFIRM = 0
>                            PFP_STALLED_ON_ATOMIC_RTN_DATA = 0
>                            EOPD_FIFO_NEEDS_SC_EOP_DONE = 0
>                            EOPD_FIFO_NEEDS_WR_CONFIRM = 0
>                            STRMO_WR_OF_PRIM_DATA_PENDING = 0
>                            PIPE_STATS_WR_DATA_PENDING = 0
>                            APPEND_RDY_WAIT_ON_CS_DONE = 0
>                            APPEND_RDY_WAIT_ON_PS_DONE = 0
>                            APPEND_WAIT_ON_WR_CONFIRM = 0
>                            APPEND_ACTIVE_PARTITION = 0
>                            APPEND_WAITING_TO_SEND_MEMWRITE = 0
>                            SURF_SYNC_NEEDS_IDLE_CNTXS = 0
>                            SURF_SYNC_NEEDS_ALL_CLEAN = 0
>        [1;33mCP_STALLED_STAT3[0m <- CE_TO_CSF_NOT_RDY_TO_RCV = 0
>                            CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0
>                            CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0
>                            CE_TO_RAM_INIT_NOT_RDY = 0
>                            CE_TO_RAM_DUMP_NOT_RDY = 0
>                            CE_TO_RAM_WRITE_NOT_RDY = 0
>                            CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0
>                            CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0
>                            CE_WAITING_ON_BUFFER_DATA = 0
>                            CE_WAITING_ON_CE_BUFFER_FLAG = 0
>                            CE_WAITING_ON_DE_COUNTER = 0
>                            CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0
>                            TCIU_WAITING_ON_FREE = 0
>                            TCIU_WAITING_ON_TAGS = 0
>                            CE_STALLED_ON_TC_WR_CONFIRM = 0
>                            CE_STALLED_ON_ATOMIC_RTN_DATA = 0
>                            ATCL2IU_WAITING_ON_FREE = 0
>                            ATCL2IU_WAITING_ON_TAGS = 0
>                            ATCL1_WAITING_ON_TRANS = 0
>        [1;33mCP_CPC_STATUS[0m <- MEC1_BUSY = 0
>                         MEC2_BUSY = 0
>                         DC0_BUSY = 0
>                         DC1_BUSY = 0
>                         RCIU1_BUSY = 0
>                         RCIU2_BUSY = 0
>                         ROQ1_BUSY = 0
>                         ROQ2_BUSY = 0
>                         TCIU_BUSY = 0
>                         SCRATCH_RAM_BUSY = 0
>                         QU_BUSY = 0
>                         ATCL2IU_BUSY = 0
>                         CPG_CPC_BUSY = 0
>                         CPF_CPC_BUSY = 0
>                         CPC_BUSY = 0
>        [1;33mCP_CPC_BUSY_STAT[0m <- MEC1_LOAD_BUSY = 0
>                            MEC1_SEMAPOHRE_BUSY = 0
>                            MEC1_MUTEX_BUSY = 0
>                            MEC1_MESSAGE_BUSY = 0
>                            MEC1_EOP_QUEUE_BUSY = 0
>                            MEC1_IQ_QUEUE_BUSY = 0
>                            MEC1_IB_QUEUE_BUSY = 0
>                            MEC1_TC_BUSY = 0
>                            MEC1_DMA_BUSY = 0
>                            MEC1_PARTIAL_FLUSH_BUSY = 0
>                            MEC1_PIPE0_BUSY = 0
>                            MEC1_PIPE1_BUSY = 0
>                            MEC1_PIPE2_BUSY = 0
>                            MEC1_PIPE3_BUSY = 0
>                            MEC2_LOAD_BUSY = 0
>                            MEC2_SEMAPOHRE_BUSY = 0
>                            MEC2_MUTEX_BUSY = 0
>                            MEC2_MESSAGE_BUSY = 0
>                            MEC2_EOP_QUEUE_BUSY = 0
>                            MEC2_IQ_QUEUE_BUSY = 0
>                            MEC2_IB_QUEUE_BUSY = 0
>                            MEC2_TC_BUSY = 0
>                            MEC2_DMA_BUSY = 0
>                            MEC2_PARTIAL_FLUSH_BUSY = 0
>                            MEC2_PIPE0_BUSY = 0
>                            MEC2_PIPE1_BUSY = 0
>                            MEC2_PIPE2_BUSY = 0
>                            MEC2_PIPE3_BUSY = 0
>        [1;33mCP_CPC_STALLED_STAT1[0m <- RCIU_TX_FREE_STALL = 0
>                                RCIU_PRIV_VIOLATION = 0
>                                TCIU_TX_FREE_STALL = 0
>                                MEC1_DECODING_PACKET = 0
>                                MEC1_WAIT_ON_RCIU = 0
>                                MEC1_WAIT_ON_RCIU_READ = 0
>                                MEC1_WAIT_ON_ROQ_DATA = 0
>                                MEC2_DECODING_PACKET = 0
>                                MEC2_WAIT_ON_RCIU = 0
>                                MEC2_WAIT_ON_RCIU_READ = 0
>                                MEC2_WAIT_ON_ROQ_DATA = 0
>                                ATCL2IU_WAITING_ON_FREE = 0
>                                ATCL2IU_WAITING_ON_TAGS = 0
>                                ATCL1_WAITING_ON_TRANS = 0
>        [1;33mCP_CPF_STATUS[0m <- POST_WPTR_GFX_BUSY = 1
>                         CSF_BUSY = 1
>                         ROQ_ALIGN_BUSY = 0
>                         ROQ_RING_BUSY = 1
>                         ROQ_INDIRECT1_BUSY = 1
>                         ROQ_INDIRECT2_BUSY = 1
>                         ROQ_STATE_BUSY = 0
>                         ROQ_CE_RING_BUSY = 0
>                         ROQ_CE_INDIRECT1_BUSY = 0
>                         ROQ_CE_INDIRECT2_BUSY = 0
>                         SEMAPHORE_BUSY = 0
>                         INTERRUPT_BUSY = 0
>                         TCIU_BUSY = 0
>                         HQD_BUSY = 0
>                         PRT_BUSY = 0
>                         ATCL2IU_BUSY = 0
>                         CPF_GFX_BUSY = 1
>                         CPF_CMP_BUSY = 0
>                         GRBM_CPF_STAT_BUSY = 1
>                         CPC_CPF_BUSY = 0
>                         CPF_BUSY = 1
>        [1;33mCP_CPF_BUSY_STAT[0m <- REG_BUS_FIFO_BUSY = 0
>                            CSF_RING_BUSY = 1
>                            CSF_INDIRECT1_BUSY = 1
>                            CSF_INDIRECT2_BUSY = 0
>                            CSF_STATE_BUSY = 0
>                            CSF_CE_INDR1_BUSY = 0
>                            CSF_CE_INDR2_BUSY = 0
>                            CSF_ARBITER_BUSY = 0
>                            CSF_INPUT_BUSY = 0
>                            OUTSTANDING_READ_TAGS = 0
>                            HPD_PROCESSING_EOP_BUSY = 0
>                            HQD_DISPATCH_BUSY = 0
>                            HQD_IQ_TIMER_BUSY = 0
>                            HQD_DMA_OFFLOAD_BUSY = 0
>                            HQD_WAIT_SEMAPHORE_BUSY = 0
>                            HQD_SIGNAL_SEMAPHORE_BUSY = 0
>                            HQD_MESSAGE_BUSY = 0
>                            HQD_PQ_FETCHER_BUSY = 0
>                            HQD_IB_FETCHER_BUSY = 0
>                            HQD_IQ_FETCHER_BUSY = 0
>                            HQD_EOP_FETCHER_BUSY = 0
>                            HQD_CONSUMED_RPTR_BUSY = 0
>                            HQD_FETCHER_ARB_BUSY = 0
>                            HQD_ROQ_ALIGN_BUSY = 0
>                            HQD_ROQ_EOP_BUSY = 0
>                            HQD_ROQ_IQ_BUSY = 0
>                            HQD_ROQ_PQ_BUSY = 0
>                            HQD_ROQ_IB_BUSY = 0
>                            HQD_WPTR_POLL_BUSY = 0
>                            HQD_PQ_BUSY = 0
>                            HQD_IB_BUSY = 0
>        [1;33mCP_CPF_STALLED_STAT1[0m <- RING_FETCHING_DATA = 0
>                                INDR1_FETCHING_DATA = 1
>                                INDR2_FETCHING_DATA = 0
>                                STATE_FETCHING_DATA = 0
>                                TCIU_WAITING_ON_FREE = 0
>                                TCIU_WAITING_ON_TAGS = 0
>                                ATCL2IU_WAITING_ON_FREE = 0
>                                ATCL2IU_WAITING_ON_TAGS = 0
>                                ATCL1_WAITING_ON_TRANS = 0
>
>
>Last 60 lines of dmesg:
>
>[    1.703145] amdgpu 0000:01:00.0: fence driver on ring 12 use gpu addr 0x00000001000000c8, cpu addr 0xffff880406e1a0c8
>[    1.703179] amdgpu 0000:01:00.0: fence driver on ring 13 use gpu addr 0x00000001000000d8, cpu addr 0xffff880406e1a0d8
>[    1.778575] Adding 33554428k swap on /dev/sda4.  Priority:-1 extents:1 across:33554428k SS
>[    1.780629] [drm] ring test on 0 succeeded in 10 usecs
>[    1.780857] [drm] ring test on 1 succeeded in 26 usecs
>[    1.780891] [drm] ring test on 2 succeeded in 17 usecs
>[    1.780899] [drm] ring test on 3 succeeded in 3 usecs
>[    1.780906] [drm] ring test on 4 succeeded in 3 usecs
>[    1.780912] [drm] ring test on 5 succeeded in 2 usecs
>[    1.780920] [drm] ring test on 6 succeeded in 3 usecs
>[    1.780927] [drm] ring test on 7 succeeded in 3 usecs
>[    1.780935] [drm] ring test on 8 succeeded in 3 usecs
>[    1.780984] [drm] ring test on 9 succeeded in 5 usecs
>[    1.780990] [drm] ring test on 10 succeeded in 5 usecs
>[    1.827063] [drm] ring test on 11 succeeded in 1 usecs
>[    1.847100] [drm] UVD initialized successfully.
>[    1.949572] usb 2-1.8.1: new low-speed USB device number 5 using ehci-pci
>[    2.013169] EXT4-fs (sdb3): mounted filesystem with ordered data mode. Opts: acl,user_xattr
>[    2.044081] input: Logitech USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.8/2-1.8.1/2-1.8.1:1.0/0003:046D:C31C.0001/input/input20
>[    2.048294] [drm] ring test on 12 succeeded in 23 usecs
>[    2.048307] [drm] ring test on 13 succeeded in 4 usecs
>[    2.048308] [drm] VCE initialized successfully.
>[    2.064053] random: crng init done
>[    2.084322] [drm] fb mappable at 0xE0A9A000
>[    2.084323] [drm] vram apper at 0xE0000000
>[    2.084324] [drm] size 9216000
>[    2.084325] [drm] fb depth is 24
>[    2.084326] [drm]    pitch is 7680
>[    2.084444] fbcon: amdgpudrmfb (fb0) is primary device
>[    2.095654] hid-generic 0003:046D:C31C.0001: input,hidraw0: USB HID v1.10 Keyboard [Logitech USB Keyboard] on usb-0000:00:1d.0-1.8.1/input0
>[    2.102411] input: Logitech USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.8/2-1.8.1/2-1.8.1:1.1/0003:046D:C31C.0002/input/input21
>[    2.153661] hid-generic 0003:046D:C31C.0002: input,hidraw1: USB HID v1.10 Device [Logitech USB Keyboard] on usb-0000:00:1d.0-1.8.1/input1
>[    2.186305] Console: switching to colour frame buffer device 240x75
>[    2.195551] amdgpu 0000:01:00.0: fb0: amdgpudrmfb frame buffer device
>[    2.195903] [drm] ib test on ring 0 succeeded
>[    2.195965] [drm] ib test on ring 1 succeeded
>[    2.195982] [drm] ib test on ring 2 succeeded
>[    2.196004] [drm] ib test on ring 3 succeeded
>[    2.196025] [drm] ib test on ring 4 succeeded
>[    2.196045] [drm] ib test on ring 5 succeeded
>[    2.196065] [drm] ib test on ring 6 succeeded
>[    2.196084] [drm] ib test on ring 7 succeeded
>[    2.196103] [drm] ib test on ring 8 succeeded
>[    2.196120] [drm] ib test on ring 9 succeeded
>[    2.196135] [drm] ib test on ring 10 succeeded
>[    2.197383] [drm] ib test on ring 11 succeeded
>[    2.197509] [drm] ib test on ring 12 succeeded
>[    2.198371] [drm] Initialized amdgpu 3.3.0 20150101 for 0000:01:00.0 on minor 0
>[    2.222573] usb 2-1.8.2: new low-speed USB device number 6 using ehci-pci
>[    2.309609] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.8/2-1.8.2/2-1.8.2:1.0/0003:046D:C05A.0003/input/input22
>[    2.309762] hid-generic 0003:046D:C05A.0003: input,hidraw2: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:1d.0-1.8.2/input0
>[    2.347075] IPv6: ADDRCONF(NETDEV_UP): enp5s0: link is not ready
>[    2.392262] IPv6: ADDRCONF(NETDEV_UP): enp5s0: link is not ready
>[    2.400462] IPv6: ADDRCONF(NETDEV_UP): enp6s0: link is not ready
>[    2.446099] IPv6: ADDRCONF(NETDEV_UP): enp6s0: link is not ready
>[    2.587734] clocksource: Switched to clocksource tsc
>[    5.077061] igb 0000:06:00.0 enp6s0: igb: enp6s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
>[    5.595818] IPv6: ADDRCONF(NETDEV_CHANGE): enp6s0: link becomes ready
>[ 2330.005447] tun: Universal TUN/TAP device driver, 1.6
>[ 2330.005450] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>

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Attachments on bug 98874: 128252 | 128253 | 128261 | 128305 | 128329 | 128330 | 128728

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