Attachment 128410 Details for Bug 97529 – patch for T100HA against 9a2f9111a94a851e53bad3fd6a92f77dbd3a95e2

[patch] patch for T100HA against 9a2f9111a94a851e53bad3fd6a92f77dbd3a95e2

i915.patch (text/plain), 13.24 KB, created by Pavel on 2016-12-11 11:16:32 UTC

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Creator: Pavel

Created: 2016-12-11 11:16:32 UTC

Size: 13.24 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>index 6b63355..196b6b0 100644
>--- a/drivers/gpu/drm/i915/intel_dsi.c
>+++ b/drivers/gpu/drm/i915/intel_dsi.c
>@@ -80,7 +80,7 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
> 	}
> }
> 
>-static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>+void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
> {
> 	struct drm_encoder *encoder = &intel_dsi->base.base;
> 	struct drm_device *dev = encoder->dev;
>@@ -508,37 +508,83 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> 	}
> }
> 
>-static void intel_dsi_enable(struct intel_encoder *encoder)
>-{
>-	struct drm_device *dev = encoder->base.dev;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>-	enum port port;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	if (is_cmd_mode(intel_dsi)) {
>-		for_each_dsi_port(port, intel_dsi->ports)
>-			I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
>-	} else {
>-		msleep(20); /* XXX */
>-		for_each_dsi_port(port, intel_dsi->ports)
>-			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
>-		msleep(100);
>-
>-		drm_panel_enable(intel_dsi->panel);
>+static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>+			      struct intel_crtc_state *pipe_config);
> 
>-		for_each_dsi_port(port, intel_dsi->ports)
>-			wait_for_dsi_fifo_empty(intel_dsi, port);
>+static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> 
>-		intel_dsi_port_enable(encoder);
>-	}
>+	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
>+	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
>+		return;
> 
>-	intel_panel_enable_backlight(intel_dsi->attached_connector);
>+	msleep(msec);
> }
> 
>-static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>-			      struct intel_crtc_state *pipe_config);
>+/*
>+ * Panel enable/disable sequences from the spec:
>+ *
>+ * v2 sequence for video mode:
>+ * - power on
>+ * - wait t1+t2
>+ * - MIPIDeassertResetPin
>+ * - clk/data lines to lp-11
>+ * - MIPISendInitialDcsCmds
>+ * - turn on DPI
>+ * - MIPIDisplayOn
>+ * - wait t5
>+ * - backlight on
>+ * ...
>+ * - backlight off
>+ * - wait t6
>+ * - MIPIDisplayOff
>+ * - turn off DPI
>+ * - clk/data lines to lp-00
>+ * - MIPIAssertResetPin
>+ * - wait t3
>+ * - power off
>+ * - wait t4
>+ *
>+ * v3 sequence for video mode:
>+ * - MIPIPanelPowerOn
>+ * - MIPIDeassertResetPin
>+ * - set clk/data lines to lp-11
>+ * - MIPISendInitialDcsCmds (LP)
>+ * - turn on DPI
>+ * - MIPITearOn (command mode only) + MIPIDisplayOn (LP and HS)
>+ * - MIPIBacklightOn
>+ * ...
>+ * - MIPIBacklightOff
>+ * - turn off DPI
>+ * - MIPITearOff + MIPIDisplayOff (LP)
>+ * - clk/data lines to lp-00
>+ * - MIPIAssertResetPin
>+ * - MIPIPanelPowerOff
>+ *
>+ * sequence for command mode:
>+ * - power on
>+ * - wait t1+t2
>+ * - MIPIDeassertResetPin
>+ * - clk/data lines to lp-11
>+ * - MIPISendInitialDcsCmds
>+ * - MIPITearOn
>+ * - MIPIDisplayOn
>+ * - set pipe to dsr mode
>+ * - wait t5
>+ * - backlight on
>+ * ... issue write_mem_start/write_mem_continue commands ...
>+ * - backlight off
>+ * - wait t6
>+ * - disable pipe dsr mode
>+ * - MIPITearOff
>+ * - MIPIDisplayOff
>+ * - clk/data lines to lp-00
>+ * - MIPIAssertResetPin
>+ * - wait t3
>+ * - power off
>+ * - wait t4
>+ */
> 
> static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> 				 struct intel_crtc_state *pipe_config,
>@@ -557,14 +603,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> 	intel_disable_dsi_pll(encoder);
> 	intel_enable_dsi_pll(encoder, pipe_config);
> 
>-	intel_dsi_prepare(encoder, pipe_config);
>-
>-	/* Panel Enable over CRC PMIC */
>-	if (intel_dsi->gpio_panel)
>-		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
>-
>-	msleep(intel_dsi->panel_on_delay);
>-
> 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> 		u32 val;
> 
>@@ -574,17 +612,44 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> 		I915_WRITE(DSPCLK_GATE_D, val);
> 	}
> 
>-	/* put device in ready state */
>-	intel_dsi_device_ready(encoder);
>+	intel_dsi_prepare(encoder, pipe_config);
> 
>-	drm_panel_prepare(intel_dsi->panel);
>+	/* Power on, try both CRC pmic gpio and VBT */
>+	if (intel_dsi->gpio_panel)
>+		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
>+	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
> 
>-	for_each_dsi_port(port, intel_dsi->ports)
>-		wait_for_dsi_fifo_empty(intel_dsi, port);
>+	/* Deassert reset */
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
>+
>+	/* Put device in ready state (LP-11) */
>+	intel_dsi_device_ready(encoder);
>+
>+	/* Send initialization commands in LP mode */
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> 
> 	/* Enable port in pre-enable phase itself because as per hw team
> 	 * recommendation, port should be enabled befor plane & pipe */
>-	intel_dsi_enable(encoder);
>+	if (is_cmd_mode(intel_dsi)) {
>+		for_each_dsi_port(port, intel_dsi->ports)
>+			I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
>+		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
>+		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
>+	} else {
>+		msleep(20); /* XXX */
>+		for_each_dsi_port(port, intel_dsi->ports)
>+			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
>+		intel_dsi_msleep(intel_dsi, 100);
>+
>+		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
>+
>+		intel_dsi_port_enable(encoder);
>+	}
>+
>+	/* Enable backlight, both pwm and VBT */
>+	intel_panel_enable_backlight(intel_dsi->attached_connector);
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
> }
> 
> static void intel_dsi_enable_nop(struct intel_encoder *encoder,
>@@ -608,8 +673,15 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
> 
> 	DRM_DEBUG_KMS("\n");
> 
>+	/* Disable backlight, both VBT and pwm */
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> 	intel_panel_disable_backlight(intel_dsi->attached_connector);
> 
>+	/*
>+	 * XXX: According to the spec we should send SHUTDOWN before
>+	 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but testing in the field
>+	 * has shown that we should do this for v2 VBTs too?
>+	 */
> 	if (is_vid_mode(intel_dsi)) {
> 		/* Send Shutdown command to the panel in LP mode */
> 		for_each_dsi_port(port, intel_dsi->ports)
>@@ -618,45 +690,6 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
> 	}
> }
> 
>-static void intel_dsi_disable(struct intel_encoder *encoder)
>-{
>-	struct drm_device *dev = encoder->base.dev;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>-	enum port port;
>-	u32 temp;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	if (is_vid_mode(intel_dsi)) {
>-		for_each_dsi_port(port, intel_dsi->ports)
>-			wait_for_dsi_fifo_empty(intel_dsi, port);
>-
>-		intel_dsi_port_disable(encoder);
>-		msleep(2);
>-	}
>-
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		/* Panel commands can be sent when clock is in LP11 */
>-		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>-
>-		intel_dsi_reset_clocks(encoder, port);
>-		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>-
>-		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
>-		temp &= ~VID_MODE_FORMAT_MASK;
>-		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
>-
>-		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
>-	}
>-	/* if disable packets are sent before sending shutdown packet then in
>-	 * some next enable sequence send turn on packet error is observed */
>-	drm_panel_disable(intel_dsi->panel);
>-
>-	for_each_dsi_port(port, intel_dsi->ports)
>-		wait_for_dsi_fifo_empty(intel_dsi, port);
>-}
>-
> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>@@ -698,8 +731,6 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> 		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
> 		usleep_range(2000, 2500);
> 	}
>-
>-	intel_disable_dsi_pll(encoder);
> }
> 
> static void intel_dsi_post_disable(struct intel_encoder *encoder,
>@@ -708,13 +739,47 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>+	enum port port;
>+	u32 temp;
> 
> 	DRM_DEBUG_KMS("\n");
> 
>-	intel_dsi_disable(encoder);
>+	if (is_vid_mode(intel_dsi)) {
>+		for_each_dsi_port(port, intel_dsi->ports)
>+			wait_for_dsi_fifo_empty(intel_dsi, port);
>+
>+		intel_dsi_port_disable(encoder);
>+		usleep_range(2000, 5000);
>+	}
>+
>+	for_each_dsi_port(port, intel_dsi->ports) {
>+		/* Panel commands can be sent when clock is in LP11 */
>+		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>+
>+		intel_dsi_reset_clocks(encoder, port);
>+		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>+
>+		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
>+		temp &= ~VID_MODE_FORMAT_MASK;
>+		I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> 
>+		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
>+	}
>+
>+	/*
>+	 * if disable packets are sent before sending shutdown packet then in
>+	 * some next enable sequence send turn on packet error is observed
>+	 * XXX spec specifies SHUTDOWN before MIPI_SEQ_DISPLAY_OFF for
>+	 * v3 VBTs, but not for v2 VBTs?
>+	 */
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
>+
>+	/* Transition to LP-00 */
> 	intel_dsi_clear_device_ready(encoder);
> 
>+	intel_disable_dsi_pll(encoder);
>+
> 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> 		u32 val;
> 
>@@ -723,11 +788,12 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
> 		I915_WRITE(DSPCLK_GATE_D, val);
> 	}
> 
>-	drm_panel_unprepare(intel_dsi->panel);
>-
>-	msleep(intel_dsi->panel_off_delay);
>+	/* Assert reset */
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
> 
>-	/* Panel Disable over CRC PMIC */
>+	/* Power off, try both CRC pmic gpio and VBT */
>+	intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
>+	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
> 	if (intel_dsi->gpio_panel)
> 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
> 
>@@ -735,7 +801,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
> 	 * FIXME As we do with eDP, just make a note of the time here
> 	 * and perform the wait before the next panel power on.
> 	 */
>-	msleep(intel_dsi->panel_pwr_cycle_delay);
>+	intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
> }
> 
> static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>index 5967ea6..5486491 100644
>--- a/drivers/gpu/drm/i915/intel_dsi.h
>+++ b/drivers/gpu/drm/i915/intel_dsi.h
>@@ -130,6 +130,11 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> 	return container_of(encoder, struct intel_dsi, base.base);
> }
> 
>+void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>+
>+void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,
>+				 enum mipi_seq seq_id);
>+
> bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
> int intel_compute_dsi_pll(struct intel_encoder *encoder,
> 			  struct intel_crtc_state *config);
>diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>index 47cd1b2..f71f913 100644
>--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>@@ -191,6 +191,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
> 		break;
> 	}
> 
>+	wait_for_dsi_fifo_empty(intel_dsi, port);
>+
> out:
> 	data += len;
> 
>@@ -398,10 +400,9 @@ static const char *sequence_name(enum mipi_seq seq_id)
> 		return "(unknown)";
> }
> 
>-static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
>+void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,
>+				 enum mipi_seq seq_id)
> {
>-	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
>-	struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
> 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> 	const u8 *data;
> 	fn_mipi_elem_exec mipi_elem_exec;
>@@ -465,40 +466,6 @@ static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
> 	}
> }
> 
>-static int vbt_panel_prepare(struct drm_panel *panel)
>-{
>-	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
>-	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
>-	generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
>-	generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
>-
>-	return 0;
>-}
>-
>-static int vbt_panel_unprepare(struct drm_panel *panel)
>-{
>-	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
>-	generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
>-
>-	return 0;
>-}
>-
>-static int vbt_panel_enable(struct drm_panel *panel)
>-{
>-	generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON);
>-	generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_ON);
>-
>-	return 0;
>-}
>-
>-static int vbt_panel_disable(struct drm_panel *panel)
>-{
>-	generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_OFF);
>-	generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF);
>-
>-	return 0;
>-}
>-
> static int vbt_panel_get_modes(struct drm_panel *panel)
> {
> 	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
>@@ -522,10 +489,6 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
> }
> 
> static const struct drm_panel_funcs vbt_panel_funcs = {
>-	.disable = vbt_panel_disable,
>-	.unprepare = vbt_panel_unprepare,
>-	.prepare = vbt_panel_prepare,
>-	.enable = vbt_panel_enable,
> 	.get_modes = vbt_panel_get_modes,
> };
>

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Attachments on bug 97529: 126095 | 126099 | 126596 | 127444 | 127445 | 127640 | 128177 | 128410 | 128453

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