Attachment 129533 Details for Bug 99780 – IR Generated by LLVM 3.9.1

IR Generated by LLVM 3.9.1

IR_LLVM3.9.1.txt (text/plain), 7.40 KB, created by Matias N. Goldberg on 2017-02-12 16:19:47 UTC

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Creator: Matias N. Goldberg

Created: 2017-02-12 16:19:47 UTC

Size: 7.40 KB

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obsolete

>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([13 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %23 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 3, !amdgpu.uniform !0
>  %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !invariant.load !0
>  %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 368)
>  %26 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8)
>  %27 = fcmp ult float %25, %26
>  br i1 %27, label %else11, label %if3
>
>if3:                                              ; preds = %main_body
>  %28 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8)
>  %29 = fdiv float 1.000000e+00, %28, !fpmath !1
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8)
>  %31 = fmul float %30, %29
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8)
>  %33 = fmul float %32, %29
>  %34 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8)
>  %35 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 0, !amdgpu.uniform !0
>  %36 = load <8 x i32>, <8 x i32> addrspace(2)* %35, align 32, !invariant.load !0
>  %37 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %38 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %37, i64 0, i64 3, !amdgpu.uniform !0
>  %39 = load <4 x i32>, <4 x i32> addrspace(2)* %38, align 16, !invariant.load !0
>  %40 = extractelement <8 x i32> %36, i32 7
>  %41 = extractelement <4 x i32> %39, i32 0
>  %42 = and i32 %41, %40
>  %43 = insertelement <4 x i32> %39, i32 %42, i32 0
>  %44 = bitcast float %34 to i32
>  %45 = bitcast float %31 to i32
>  %46 = bitcast float %33 to i32
>  %47 = insertelement <4 x i32> undef, i32 %44, i32 0
>  %48 = insertelement <4 x i32> %47, i32 %45, i32 1
>  %49 = insertelement <4 x i32> %48, i32 %46, i32 2
>  %50 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %49, <8 x i32> %36, <4 x i32> %43, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %51 = extractelement <4 x float> %50, i32 0
>  br label %endif22
>
>else11:                                           ; preds = %main_body
>  %52 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 3, !amdgpu.uniform !0
>  %53 = load <16 x i8>, <16 x i8> addrspace(2)* %52, align 16, !invariant.load !0
>  %54 = call float @llvm.SI.load.const(<16 x i8> %53, i32 372)
>  %55 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8)
>  %56 = fcmp ult float %54, %55
>  br i1 %56, label %endif22, label %if13
>
>if13:                                             ; preds = %else11
>  %57 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8)
>  %58 = fdiv float 1.000000e+00, %57, !fpmath !1
>  %59 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8)
>  %60 = fmul float %59, %58
>  %61 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8)
>  %62 = fmul float %61, %58
>  %63 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8)
>  %64 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 2, !amdgpu.uniform !0
>  %65 = load <8 x i32>, <8 x i32> addrspace(2)* %64, align 32, !invariant.load !0
>  %66 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %67 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %66, i64 0, i64 7, !amdgpu.uniform !0
>  %68 = load <4 x i32>, <4 x i32> addrspace(2)* %67, align 16, !invariant.load !0
>  %69 = extractelement <8 x i32> %65, i32 7
>  %70 = extractelement <4 x i32> %68, i32 0
>  %71 = and i32 %70, %69
>  %72 = insertelement <4 x i32> %68, i32 %71, i32 0
>  %73 = bitcast float %63 to i32
>  %74 = bitcast float %60 to i32
>  %75 = bitcast float %62 to i32
>  %76 = insertelement <4 x i32> undef, i32 %73, i32 0
>  %77 = insertelement <4 x i32> %76, i32 %74, i32 1
>  %78 = insertelement <4 x i32> %77, i32 %75, i32 2
>  %79 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %78, <8 x i32> %65, <4 x i32> %72, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %80 = extractelement <4 x float> %79, i32 0
>  br label %endif22
>
>endif22:                                          ; preds = %else11, %if13, %if3
>  %TEMP1.x.1 = phi float [ 0.000000e+00, %if3 ], [ 0.000000e+00, %if13 ], [ 5.000000e-01, %else11 ]
>  %TEMP1.y.1 = phi float [ 0.000000e+00, %if3 ], [ 5.000000e-01, %if13 ], [ 5.000000e-01, %else11 ]
>  %TEMP1.z.1 = phi float [ 5.000000e-01, %if3 ], [ 0.000000e+00, %if13 ], [ 5.000000e-01, %else11 ]
>  %TEMP0.x.1 = phi float [ %51, %if3 ], [ %80, %if13 ], [ 1.000000e+00, %else11 ]
>  %81 = fmul float %TEMP0.x.1, 5.000000e-01
>  %82 = fadd float %TEMP1.x.1, %81
>  %83 = fmul float %TEMP0.x.1, 5.000000e-01
>  %84 = fadd float %TEMP1.y.1, %83
>  %85 = fmul float %TEMP0.x.1, 5.000000e-01
>  %86 = fadd float %TEMP1.z.1, %85
>  %87 = bitcast float %5 to i32
>  %88 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %87, 10
>  %89 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %88, float %82, 11
>  %90 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %89, float %84, 12
>  %91 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %90, float %86, 13
>  %92 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %91, float 1.000000e+00, 14
>  %93 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %92, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %93
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>attributes #1 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}

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Attachments on bug 99780: 129530 | 129531 | 129532 | 129533 | 129534 | 129535 | 129536 | 129675

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