Attachment 130040 Details for Bug 100044 – dmesg log with failed suspend

dmesg log with failed suspend

dmesg.log (text/x-log), 3.07 MB, created by Imre Deak on 2017-03-03 10:14:38 UTC

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Description:

Filename:

MIME Type:

Creator: Imre Deak

Created: 2017-03-03 10:14:38 UTC

Size: 3.07 MB

patch

obsolete

>[    0.000000] Linux version 4.10.0-CI-CI_DRM_2273+ (cidrm@ci-worker1) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4) ) #1 SMP PREEMPT Thu Mar 2 22:32:09 EET 2017
>[    0.000000] Command line: BOOT_IMAGE=/boot/drm_intel root=UUID=0f5434dc-8d7e-4fac-867e-cd350585ceb3 intel_iommu=igfx_off drm.debug=0xe ro 3
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>[    0.000000] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
>[    0.000000] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
>[    0.000000] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
>[    0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format.
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x0000000084cd8fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000084cd9000-0x0000000084cd9fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x0000000084cda000-0x0000000084cdafff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000084cdb000-0x000000008a037fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008a038000-0x000000008a361fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000008a362000-0x000000008a7f9fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008a7fa000-0x000000008ab67fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000008ab68000-0x000000008b289fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000008b28a000-0x000000008b2fdfff] type 20
>[    0.000000] BIOS-e820: [mem 0x000000008b2fe000-0x000000008b2fefff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008b2ff000-0x000000008fffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000026dffffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] efi: EFI v2.50 by American Megatrends
>[    0.000000] efi:  ESRT=0x8b1fecd8  ACPI=0x8aafa000  ACPI 2.0=0x8aafa000  SMBIOS=0x8b1fc000  SMBIOS 3.0=0x8b1fb000 
>[    0.000000] SMBIOS 3.0.0 present.
>[    0.000000] DMI: GIGABYTE GB-BKi7A-7500/MFLP7AP-00, BIOS F1 07/27/2016
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] e820: last_pfn = 0x26e000 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: write-back
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 00C0000000 mask 7FC0000000 uncachable
>[    0.000000]   1 base 00A0000000 mask 7FE0000000 uncachable
>[    0.000000]   2 base 0090000000 mask 7FF0000000 uncachable
>[    0.000000]   3 base 008C000000 mask 7FFC000000 uncachable
>[    0.000000]   4 base 008B800000 mask 7FFF800000 uncachable
>[    0.000000]   5 disabled
>[    0.000000]   6 disabled
>[    0.000000]   7 disabled
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- WT  
>[    0.000000] e820: last_pfn = 0x8b2ff max_arch_pfn = 0x400000000
>[    0.000000] esrt: Reserving ESRT space from 0x000000008b1fecd8 to 0x000000008b1fed10.
>[    0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] BRK [0x056b4000, 0x056b4fff] PGTABLE
>[    0.000000] BRK [0x056b5000, 0x056b5fff] PGTABLE
>[    0.000000] BRK [0x056b6000, 0x056b6fff] PGTABLE
>[    0.000000] BRK [0x056b7000, 0x056b7fff] PGTABLE
>[    0.000000] BRK [0x056b8000, 0x056b8fff] PGTABLE
>[    0.000000] BRK [0x056b9000, 0x056b9fff] PGTABLE
>[    0.000000] Secure boot could not be determined
>[    0.000000] RAMDISK: [mem 0x337fc000-0x35bf5fff]
>[    0.000000] ACPI: Early table checksum verification disabled
>[    0.000000] ACPI: RSDP 0x000000008AAFA000 000024 (v02 GBT   )
>[    0.000000] ACPI: XSDT 0x000000008AAFA0A0 0000BC (v01 GBT    GBTUACPI 01072009 AMI  00010013)
>[    0.000000] ACPI: FACP 0x000000008AB1F200 000114 (v06 GBT    GBTUACPI 01072009 AMI  00010013)
>[    0.000000] ACPI: DSDT 0x000000008AAFA1F0 02500C (v02 GBT    GBTUACPI 01072009 INTL 20160422)
>[    0.000000] ACPI: FACS 0x000000008AB67C40 000040
>[    0.000000] ACPI: APIC 0x000000008AB1F318 000084 (v03 GBT    GBTUACPI 01072009 AMI  00010013)
>[    0.000000] ACPI: FPDT 0x000000008AB1F3A0 000044 (v01 GBT    GBTUACPI 01072009 AMI  00010013)
>[    0.000000] ACPI: MCFG 0x000000008AB1F3E8 00003C (v01 GBT    GBTUACPI 01072009 MSFT 00000097)
>[    0.000000] ACPI: FIDT 0x000000008AB1F428 00009C (v01 GBT    GBTUACPI 01072009 AMI  00010013)
>[    0.000000] ACPI: SSDT 0x000000008AB1F4C8 003154 (v02 SaSsdt SaSsdt   00003000 INTL 20160422)
>[    0.000000] ACPI: HPET 0x000000008AB22620 000038 (v01 INTEL  KBL-ULT  00000001 MSFT 0000005F)
>[    0.000000] ACPI: SSDT 0x000000008AB22658 000E3B (v02 INTEL  Ther_Rvp 00001000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008AB23498 00090B (v02 INTEL  xh_rvp07 00000000 INTL 20160422)
>[    0.000000] ACPI: UEFI 0x000000008AB23DA8 000042 (v01 INTEL  EDK2     00000002      01000013)
>[    0.000000] ACPI: SSDT 0x000000008AB23DF0 000EE0 (v02 CpuRef CpuSsdt  00003000 INTL 20160422)
>[    0.000000] ACPI: LPIT 0x000000008AB24CD0 000094 (v01 INTEL  KBL-ULT  00000000 MSFT 0000005F)
>[    0.000000] ACPI: SSDT 0x000000008AB24D68 00029F (v02 INTEL  sensrhub 00000000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008AB25008 00357E (v02 INTEL  PtidDevc 00001000 INTL 20160422)
>[    0.000000] ACPI: DBGP 0x000000008AB28588 000034 (v01 INTEL           00000002 MSFT 0000005F)
>[    0.000000] ACPI: DBG2 0x000000008AB285C0 000054 (v00 INTEL           00000002 MSFT 0000005F)
>[    0.000000] ACPI: BGRT 0x000000008AB28618 000038 (v01 GBT    GBTUACPI 01072009 AMI  00010013)
>[    0.000000] ACPI: SSDT 0x000000008AB28650 000183 (v01 Intel  IntelRMT 00001000 INTL 20160422)
>[    0.000000] ACPI: ASF! 0x000000008AB287D8 0000A0 (v32 INTEL   HCG     00000001 TFSM 000F4240)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000026dffffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>[    0.000000]   node   0: [mem 0x0000000000059000-0x000000000009dfff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x0000000084cd8fff]
>[    0.000000]   node   0: [mem 0x0000000084cdb000-0x000000008a037fff]
>[    0.000000]   node   0: [mem 0x000000008a362000-0x000000008a7f9fff]
>[    0.000000]   node   0: [mem 0x000000008b2fe000-0x000000008b2fefff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000026dffffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000026dffffff]
>[    0.000000] On node 0 totalpages: 2065515
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 23 pages reserved
>[    0.000000]   DMA zone: 3996 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 8788 pages used for memmap
>[    0.000000]   DMA32 zone: 562383 pages, LIFO batch:31
>[    0.000000]   Normal zone: 23424 pages used for memmap
>[    0.000000]   Normal zone: 1499136 pages, LIFO batch:31
>[    0.000000] Reserving Intel graphics memory at 0x000000008c000000-0x000000008fffffff
>[    0.000000] ACPI: PM-Timer IO Port: 0x1808
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
>[    0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x84cd9000-0x84cd9fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x84cda000-0x84cdafff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8a038000-0x8a361fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8a7fa000-0x8ab67fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8ab68000-0x8b289fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8b28a000-0x8b2fdfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8b2ff000-0x8fffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x90000000-0xdfffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfdffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe000000-0xfe010fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe011000-0xfebfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfedfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff]
>[    0.000000] e820: [mem 0x90000000-0xdfffffff] available for PCI devices
>[    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275 ns
>[    0.000000] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
>[    0.000000] percpu: Embedded 37 pages/cpu @ffff88026dc00000 s111816 r8192 d31544 u524288
>[    0.000000] pcpu-alloc: s111816 r8192 d31544 u524288 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 1 2 3 
>[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 2033216
>[    0.000000] Kernel command line: BOOT_IMAGE=/boot/drm_intel root=UUID=0f5434dc-8d7e-4fac-867e-cd350585ceb3 intel_iommu=igfx_off drm.debug=0xe ro 3
>[    0.000000] DMAR: Disable GFX device mapping
>[    0.000000] log_buf_len individual max cpu contribution: 262144 bytes
>[    0.000000] log_buf_len total cpu_extra contributions: 786432 bytes
>[    0.000000] log_buf_len min size: 262144 bytes
>[    0.000000] log_buf_len: 1048576 bytes
>[    0.000000] early log buf free: 250172(95%)
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
>[    0.000000] Memory: 7873484K/8262060K available (8706K kernel code, 1434K rwdata, 3340K rodata, 1192K init, 22624K bss, 388576K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
>[    0.000000] Running RCU self tests
>[    0.000000] Preemptible hierarchical RCU implementation.
>[    0.000000] 	RCU lockdep checking is enabled.
>[    0.000000] 	Build-time adjustment of leaf fanout to 64.
>[    0.000000] 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4.
>[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
>[    0.000000] kmemleak: Kernel memory leak detector disabled
>[    0.000000] NR_IRQS:4352 nr_irqs:1024 16
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
>[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
>[    0.000000] ... MAX_LOCK_DEPTH:          48
>[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
>[    0.000000] ... CLASSHASH_SIZE:          4096
>[    0.000000] ... MAX_LOCKDEP_ENTRIES:     32768
>[    0.000000] ... MAX_LOCKDEP_CHAINS:      65536
>[    0.000000] ... CHAINHASH_SIZE:          32768
>[    0.000000]  memory used by lock dependency info: 8159 kB
>[    0.000000]  per task-struct memory footprint: 1920 bytes
>[    0.000000] kmemleak: Early log buffer exceeded (2852), please increase DEBUG_KMEMLEAK_EARLY_LOG_SIZE
>[    0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns
>[    0.000000] hpet clockevent registered
>[    0.001000] tsc: Detected 2900.000 MHz processor
>[    0.001000] Calibrating delay loop (skipped), value calculated using timer frequency.. 5808.00 BogoMIPS (lpj=2904000)
>[    0.001000] pid_max: default: 32768 minimum: 301
>[    0.001000] ACPI: Core revision 20170119
>[    0.192214] ACPI: 8 ACPI AML tables successfully acquired and loaded
>[    0.192795] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
>[    0.192807] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
>[    0.193491] CPU: Physical Processor ID: 0
>[    0.193499] CPU: Processor Core ID: 0
>[    0.193508] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>[    0.193517] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>[    0.193530] mce: CPU supports 8 MCE banks
>[    0.193549] CPU0: Thermal monitoring enabled (TM1)
>[    0.193569] process: using mwait in idle threads
>[    0.193578] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
>[    0.193586] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
>[    0.193741] Freeing SMP alternatives memory: 32K
>[    0.201552] smpboot: Max logical packages: 2
>[    0.202789] x2apic: IRQ remapping doesn't support X2APIC mode
>[    0.207000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.216209] TSC deadline timer enabled
>[    0.216216] smpboot: CPU0: Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz (family: 0x6, model: 0x8e, stepping: 0x9)
>[    0.219045] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver.
>[    0.219090] ... version:                4
>[    0.219098] ... bit width:              48
>[    0.219105] ... generic registers:      4
>[    0.219113] ... value mask:             0000ffffffffffff
>[    0.219123] ... max period:             00007fffffffffff
>[    0.219132] ... fixed-purpose events:   3
>[    0.219140] ... event mask:             000000070000000f
>[    0.226042] smp: Bringing up secondary CPUs ...
>[    0.233086] x86: Booting SMP configuration:
>[    0.233099] .... node  #0, CPUs:      #1 #2 #3
>[    0.427061] smp: Brought up 1 node, 4 CPUs
>[    0.427061] smpboot: Total of 4 processors activated (23292.33 BogoMIPS)
>[    0.428198] sched_clock: Marking stable (428000000, 0)->(431709026, -3709026)
>[    0.428636] devtmpfs: initialized
>[    0.429674] PM: Registering ACPI NVS region [mem 0x84cd9000-0x84cd9fff] (4096 bytes)
>[    0.429692] PM: Registering ACPI NVS region [mem 0x8a7fa000-0x8ab67fff] (3596288 bytes)
>[    0.431408] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
>[    0.431429] futex hash table entries: 1024 (order: 5, 131072 bytes)
>[    0.431566] xor: automatically using best checksumming function   avx       
>[    0.431581] pinctrl core: initialized pinctrl subsystem
>[    0.432031] NET: Registered protocol family 16
>[    0.433197] cpuidle: using governor menu
>[    0.433208] PCCT header not found.
>[    0.433295] ACPI: bus type PCI registered
>[    0.433547] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>[    0.433564] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
>[    0.433589] PCI: Using configuration type 1 for base access
>[    0.442875] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[    0.460111] raid6: sse2x1   gen() 11941 MB/s
>[    0.477172] raid6: sse2x1   xor()  9197 MB/s
>[    0.494231] raid6: sse2x2   gen() 14414 MB/s
>[    0.511288] raid6: sse2x2   xor()  9378 MB/s
>[    0.528348] raid6: sse2x4   gen() 16277 MB/s
>[    0.545408] raid6: sse2x4   xor() 11673 MB/s
>[    0.562470] raid6: avx2x1   gen() 23371 MB/s
>[    0.579535] raid6: avx2x1   xor() 16517 MB/s
>[    0.596596] raid6: avx2x2   gen() 27363 MB/s
>[    0.613659] raid6: avx2x2   xor() 18582 MB/s
>[    0.630719] raid6: avx2x4   gen() 29687 MB/s
>[    0.647783] raid6: avx2x4   xor() 19699 MB/s
>[    0.647792] raid6: using algorithm avx2x4 gen() 29687 MB/s
>[    0.647801] raid6: .... xor() 19699 MB/s, rmw enabled
>[    0.647811] raid6: using avx2x2 recovery algorithm
>[    0.647922] ACPI: Added _OSI(Module Device)
>[    0.647931] ACPI: Added _OSI(Processor Device)
>[    0.647940] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.647949] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.657599] ACPI: Executed 30 blocks of module-level executable AML code
>[    0.742481] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
>[    0.758037] ACPI: Dynamic OEM Table Load:
>[    0.758059] ACPI: SSDT 0xFFFF880263D892A8 0006F6 (v02 PmRef  Cpu0Ist  00003000 INTL 20160422)
>[    0.758746] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.759282] ACPI: \_PR_.CPU0: _OSC native thermal LVT Acked
>[    0.769619] ACPI: Dynamic OEM Table Load:
>[    0.769640] ACPI: SSDT 0xFFFF880263CF3FC8 000400 (v02 PmRef  Cpu0Cst  00003001 INTL 20160422)
>[    0.770192] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.770930] ACPI: Dynamic OEM Table Load:
>[    0.770949] ACPI: SSDT 0xFFFF880263F8C6A8 000115 (v02 PmRef  Cpu0Hwp  00003000 INTL 20160422)
>[    0.771195] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.771496] ACPI: Dynamic OEM Table Load:
>[    0.771515] ACPI: SSDT 0xFFFF880263F8F508 0001A4 (v02 PmRef  HwpLvt   00003000 INTL 20160422)
>[    0.771707] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.774466] ACPI: Dynamic OEM Table Load:
>[    0.774489] ACPI: SSDT 0xFFFF880263D8DD28 00065C (v02 PmRef  ApIst    00003000 INTL 20160422)
>[    0.777746] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.778399] ACPI: Dynamic OEM Table Load:
>[    0.778421] ACPI: SSDT 0xFFFF880263F8C9F8 000197 (v02 PmRef  ApHwp    00003000 INTL 20160422)
>[    0.779022] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.779659] ACPI: Dynamic OEM Table Load:
>[    0.779678] ACPI: SSDT 0xFFFF880263F8F1B8 00018A (v02 PmRef  ApCst    00003000 INTL 20160422)
>[    0.780287] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.800151] ACPI: Interpreter enabled
>[    0.800285] ACPI: (supports S0 S3 S4 S5)
>[    0.800294] ACPI: Using IOAPIC for interrupt routing
>[    0.800480] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.827124] ACPI: Power Resource [WRST] (on)
>[    0.829788] ACPI: Power Resource [WRST] (on)
>[    0.832810] ACPI: Power Resource [WRST] (on)
>[    0.835471] ACPI: Power Resource [WRST] (on)
>[    0.838116] ACPI: Power Resource [WRST] (on)
>[    0.840819] ACPI: Power Resource [WRST] (on)
>[    0.843630] ACPI: Power Resource [WRST] (on)
>[    0.846394] ACPI: Power Resource [WRST] (on)
>[    0.849429] ACPI: Power Resource [WRST] (on)
>[    0.852167] ACPI: Power Resource [WRST] (on)
>[    0.854942] ACPI: Power Resource [WRST] (on)
>[    0.857670] ACPI: Power Resource [WRST] (on)
>[    0.860395] ACPI: Power Resource [WRST] (on)
>[    0.863126] ACPI: Power Resource [WRST] (on)
>[    0.865896] ACPI: Power Resource [WRST] (on)
>[    0.868636] ACPI: Power Resource [WRST] (on)
>[    0.871354] ACPI: Power Resource [WRST] (on)
>[    0.882297] ACPI: Power Resource [WRST] (on)
>[    0.884994] ACPI: Power Resource [WRST] (on)
>[    0.887677] ACPI: Power Resource [WRST] (on)
>[    0.951457] ACPI: Power Resource [FN00] (off)
>[    0.952420] ACPI: Power Resource [FN01] (off)
>[    0.953364] ACPI: Power Resource [FN02] (off)
>[    0.954319] ACPI: Power Resource [FN03] (off)
>[    0.955295] ACPI: Power Resource [FN04] (off)
>[    0.963002] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
>[    0.963024] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>[    0.971531] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
>[    0.973559] PCI host bridge to bus 0000:00
>[    0.973571] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
>[    0.973585] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>[    0.973599] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>[    0.973617] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window]
>[    0.973634] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window]
>[    0.973650] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window]
>[    0.973666] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window]
>[    0.973682] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window]
>[    0.973698] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window]
>[    0.973714] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window]
>[    0.973730] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window]
>[    0.973746] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window]
>[    0.973762] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window]
>[    0.973778] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window]
>[    0.973794] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window]
>[    0.973810] pci_bus 0000:00: root bus resource [mem 0x90000000-0xdfffffff window]
>[    0.973826] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window]
>[    0.973842] pci_bus 0000:00: root bus resource [bus 00-fe]
>[    0.973872] pci 0000:00:00.0: [8086:5904] type 00 class 0x060000
>[    0.976014] pci 0000:00:02.0: [8086:5916] type 00 class 0x030000
>[    0.976026] pci 0000:00:02.0: reg 0x10: [mem 0xde000000-0xdeffffff 64bit]
>[    0.976034] pci 0000:00:02.0: reg 0x18: [mem 0xc0000000-0xcfffffff 64bit pref]
>[    0.976039] pci 0000:00:02.0: reg 0x20: [io  0xf000-0xf03f]
>[    0.977164] pci 0000:00:14.0: [8086:9d2f] type 00 class 0x0c0330
>[    0.977186] pci 0000:00:14.0: reg 0x10: [mem 0xdf330000-0xdf33ffff 64bit]
>[    0.977282] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    0.978636] pci 0000:00:14.0: System wakeup disabled by ACPI
>[    0.978880] pci 0000:00:14.2: [8086:9d31] type 00 class 0x118000
>[    0.978901] pci 0000:00:14.2: reg 0x10: [mem 0xdf34e000-0xdf34efff 64bit]
>[    0.979815] pci 0000:00:16.0: [8086:9d3a] type 00 class 0x078000
>[    0.979840] pci 0000:00:16.0: reg 0x10: [mem 0xdf34d000-0xdf34dfff 64bit]
>[    0.979938] pci 0000:00:16.0: PME# supported from D3hot
>[    0.981051] pci 0000:00:17.0: [8086:9d03] type 00 class 0x010601
>[    0.981070] pci 0000:00:17.0: reg 0x10: [mem 0xdf348000-0xdf349fff]
>[    0.981080] pci 0000:00:17.0: reg 0x14: [mem 0xdf34c000-0xdf34c0ff]
>[    0.981090] pci 0000:00:17.0: reg 0x18: [io  0xf090-0xf097]
>[    0.981100] pci 0000:00:17.0: reg 0x1c: [io  0xf080-0xf083]
>[    0.981109] pci 0000:00:17.0: reg 0x20: [io  0xf060-0xf07f]
>[    0.981119] pci 0000:00:17.0: reg 0x24: [mem 0xdf34b000-0xdf34b7ff]
>[    0.981187] pci 0000:00:17.0: PME# supported from D3hot
>[    0.982321] pci 0000:00:1c.0: [8086:9d10] type 01 class 0x060400
>[    0.982415] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    0.983599] pci 0000:00:1c.0: System wakeup disabled by ACPI
>[    0.983850] pci 0000:00:1c.5: [8086:9d15] type 01 class 0x060400
>[    0.983941] pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold
>[    0.985122] pci 0000:00:1c.5: System wakeup disabled by ACPI
>[    0.985365] pci 0000:00:1d.0: [8086:9d18] type 01 class 0x060400
>[    0.985457] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
>[    0.986664] pci 0000:00:1d.0: System wakeup disabled by ACPI
>[    0.986928] pci 0000:00:1f.0: [8086:9d58] type 00 class 0x060100
>[    0.988139] pci 0000:00:1f.2: [8086:9d21] type 00 class 0x058000
>[    0.988151] pci 0000:00:1f.2: reg 0x10: [mem 0xdf344000-0xdf347fff]
>[    0.989303] pci 0000:00:1f.3: [8086:9d71] type 00 class 0x040300
>[    0.989327] pci 0000:00:1f.3: reg 0x10: [mem 0xdf340000-0xdf343fff 64bit]
>[    0.989356] pci 0000:00:1f.3: reg 0x20: [mem 0xdf320000-0xdf32ffff 64bit]
>[    0.989429] pci 0000:00:1f.3: PME# supported from D3hot D3cold
>[    0.990717] pci 0000:00:1f.3: System wakeup disabled by ACPI
>[    0.990958] pci 0000:00:1f.4: [8086:9d23] type 00 class 0x0c0500
>[    0.991005] pci 0000:00:1f.4: reg 0x10: [mem 0xdf34a000-0xdf34a0ff 64bit]
>[    0.991075] pci 0000:00:1f.4: reg 0x20: [io  0xf040-0xf05f]
>[    0.992239] pci 0000:00:1f.6: [8086:156f] type 00 class 0x020000
>[    0.992262] pci 0000:00:1f.6: reg 0x10: [mem 0xdf300000-0xdf31ffff]
>[    0.992389] pci 0000:00:1f.6: PME# supported from D0 D3hot D3cold
>[    0.993345] pci 0000:00:1f.6: System wakeup disabled by ACPI
>[    0.993738] pci 0000:01:00.0: [1b21:1242] type 00 class 0x0c0330
>[    0.993765] pci 0000:01:00.0: reg 0x10: [mem 0xdf200000-0xdf207fff 64bit]
>[    0.993933] pci 0000:01:00.0: PME# supported from D3hot D3cold
>[    0.994404] pci 0000:01:00.0: System wakeup disabled by ACPI
>[    0.994667] pci 0000:00:1c.0: PCI bridge to [bus 01]
>[    0.994682] pci 0000:00:1c.0:   bridge window [mem 0xdf200000-0xdf2fffff]
>[    0.994854] pci 0000:02:00.0: [8086:24fb] type 00 class 0x028000
>[    0.994889] pci 0000:02:00.0: reg 0x10: [mem 0xdf100000-0xdf101fff 64bit]
>[    0.995092] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
>[    0.995573] pci 0000:02:00.0: System wakeup disabled by ACPI
>[    0.995840] pci 0000:00:1c.5: PCI bridge to [bus 02]
>[    0.995854] pci 0000:00:1c.5:   bridge window [mem 0xdf100000-0xdf1fffff]
>[    0.996014] pci 0000:03:00.0: [8086:f1a5] type 00 class 0x010802
>[    0.996040] pci 0000:03:00.0: reg 0x10: [mem 0xdf000000-0xdf003fff 64bit]
>[    0.996669] pci 0000:03:00.0: System wakeup disabled by ACPI
>[    0.996919] pci 0000:00:1d.0: PCI bridge to [bus 03]
>[    0.996933] pci 0000:00:1d.0:   bridge window [mem 0xdf000000-0xdf0fffff]
>[    0.996953] pci_bus 0000:00: on NUMA node 0
>[    1.008296] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.008790] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15)
>[    1.009267] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.009747] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.010216] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.010696] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.011175] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.011655] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.015442] ACPI: Enabled 4 GPEs in block 00 to 7F
>[    1.015970] pci 0000:00:02.0: vgaarb: setting as boot VGA device
>[    1.015984] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
>[    1.016005] pci 0000:00:02.0: vgaarb: bridge control possible
>[    1.016016] vgaarb: loaded
>[    1.016375] SCSI subsystem initialized
>[    1.016511] libata version 3.00 loaded.
>[    1.016634] ACPI: bus type USB registered
>[    1.016762] usbcore: registered new interface driver usbfs
>[    1.016824] usbcore: registered new interface driver hub
>[    1.016894] usbcore: registered new device driver usb
>[    1.017193] Registered efivars operations
>[    1.031835] Advanced Linux Sound Architecture Driver Initialized.
>[    1.031898] PCI: Using ACPI for IRQ routing
>[    1.059967] PCI: pci_cache_line_size set to 64 bytes
>[    1.060033] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    1.060040] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>[    1.060044] e820: reserve RAM buffer [mem 0x84cd9000-0x87ffffff]
>[    1.060048] e820: reserve RAM buffer [mem 0x8a038000-0x8bffffff]
>[    1.060052] e820: reserve RAM buffer [mem 0x8a7fa000-0x8bffffff]
>[    1.060056] e820: reserve RAM buffer [mem 0x8b2ff000-0x8bffffff]
>[    1.060060] e820: reserve RAM buffer [mem 0x26e000000-0x26fffffff]
>[    1.060850] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    1.060871] hpet0: 8 comparators, 64-bit 24.000000 MHz counter
>[    1.062951] clocksource: Switched to clocksource hpet
>[    1.113533] pnp: PnP ACPI init
>[    1.115416] system 00:00: [io  0x0a00-0x0a0f] has been reserved
>[    1.115432] system 00:00: [io  0x0a10-0x0a1f] has been reserved
>[    1.115447] system 00:00: [io  0x0a20-0x0a2f] has been reserved
>[    1.115461] system 00:00: [io  0x0a30-0x0a3f] has been reserved
>[    1.115487] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.116262] system 00:01: [io  0x0680-0x069f] has been reserved
>[    1.116278] system 00:01: [io  0xffff] has been reserved
>[    1.116291] system 00:01: [io  0xffff] has been reserved
>[    1.116304] system 00:01: [io  0xffff] has been reserved
>[    1.116317] system 00:01: [io  0x1800-0x18fe] has been reserved
>[    1.116331] system 00:01: [io  0x164e-0x164f] has been reserved
>[    1.116345] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.116826] pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    1.117119] system 00:03: [io  0x1854-0x1857] has been reserved
>[    1.117134] system 00:03: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
>[    1.118797] system 00:04: [mem 0xfed10000-0xfed17fff] has been reserved
>[    1.118814] system 00:04: [mem 0xfed18000-0xfed18fff] has been reserved
>[    1.118829] system 00:04: [mem 0xfed19000-0xfed19fff] has been reserved
>[    1.118846] system 00:04: [mem 0xe0000000-0xefffffff] has been reserved
>[    1.118862] system 00:04: [mem 0xfed20000-0xfed3ffff] has been reserved
>[    1.118877] system 00:04: [mem 0xfed90000-0xfed93fff] has been reserved
>[    1.118892] system 00:04: [mem 0xfed45000-0xfed8ffff] has been reserved
>[    1.118908] system 00:04: [mem 0xff000000-0xffffffff] has been reserved
>[    1.118927] system 00:04: [mem 0xfee00000-0xfeefffff] could not be reserved
>[    1.118943] system 00:04: [mem 0xdffe0000-0xdfffffff] has been reserved
>[    1.118983] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.119262] system 00:05: [mem 0xfd000000-0xfdabffff] has been reserved
>[    1.119277] system 00:05: [mem 0xfdad0000-0xfdadffff] has been reserved
>[    1.119292] system 00:05: [mem 0xfdb00000-0xfdffffff] has been reserved
>[    1.119310] system 00:05: [mem 0xfe000000-0xfe01ffff] could not be reserved
>[    1.119326] system 00:05: [mem 0xfe036000-0xfe03bfff] has been reserved
>[    1.119341] system 00:05: [mem 0xfe03d000-0xfe3fffff] has been reserved
>[    1.119355] system 00:05: [mem 0xfe410000-0xfe7fffff] has been reserved
>[    1.119370] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.120897] system 00:06: [io  0xff00-0xfffe] has been reserved
>[    1.120912] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.128833] system 00:07: [mem 0xfe029000-0xfe029fff] has been reserved
>[    1.128849] system 00:07: [mem 0xfe028000-0xfe028fff] has been reserved
>[    1.128864] system 00:07: [mem 0xfdaf0000-0xfdafffff] has been reserved
>[    1.128879] system 00:07: [mem 0xfdae0000-0xfdaeffff] has been reserved
>[    1.128897] system 00:07: [mem 0xfdac0000-0xfdacffff] has been reserved
>[    1.128912] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.134873] pnp: PnP ACPI: found 8 devices
>[    1.150734] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>[    1.150774] pci 0000:00:1c.0: PCI bridge to [bus 01]
>[    1.150788] pci 0000:00:1c.0:   bridge window [mem 0xdf200000-0xdf2fffff]
>[    1.150805] pci 0000:00:1c.5: PCI bridge to [bus 02]
>[    1.150817] pci 0000:00:1c.5:   bridge window [mem 0xdf100000-0xdf1fffff]
>[    1.150834] pci 0000:00:1d.0: PCI bridge to [bus 03]
>[    1.150846] pci 0000:00:1d.0:   bridge window [mem 0xdf000000-0xdf0fffff]
>[    1.150864] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
>[    1.150866] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
>[    1.150867] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
>[    1.150869] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window]
>[    1.150870] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window]
>[    1.150871] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window]
>[    1.150873] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window]
>[    1.150874] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window]
>[    1.150876] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window]
>[    1.150877] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window]
>[    1.150878] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window]
>[    1.150880] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window]
>[    1.150881] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window]
>[    1.150882] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window]
>[    1.150884] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window]
>[    1.150885] pci_bus 0000:00: resource 19 [mem 0x90000000-0xdfffffff window]
>[    1.150887] pci_bus 0000:00: resource 20 [mem 0xfd000000-0xfe7fffff window]
>[    1.150888] pci_bus 0000:01: resource 1 [mem 0xdf200000-0xdf2fffff]
>[    1.150890] pci_bus 0000:02: resource 1 [mem 0xdf100000-0xdf1fffff]
>[    1.150891] pci_bus 0000:03: resource 1 [mem 0xdf000000-0xdf0fffff]
>[    1.151701] NET: Registered protocol family 2
>[    1.152146] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
>[    1.152214] TCP bind hash table entries: 65536 (order: 10, 4194304 bytes)
>[    1.154773] TCP: Hash tables configured (established 65536 bind 65536)
>[    1.154893] UDP hash table entries: 4096 (order: 7, 655360 bytes)
>[    1.155293] UDP-Lite hash table entries: 4096 (order: 7, 655360 bytes)
>[    1.155778] NET: Registered protocol family 1
>[    1.155808] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>[    1.158650] PCI: CLS 0 bytes, default 64
>[    1.158846] Unpacking initramfs...
>[    1.599097] Freeing initrd memory: 36840K
>[    1.599110] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    1.599122] software IO TLB [mem 0x7fb4e000-0x83b4e000] (64MB) mapped at [ffff88007fb4e000-ffff880083b4dfff]
>[    1.599280] RAPL PMU: API unit is 2^-32 Joules, 5 fixed counters, 655360 ms ovfl timer
>[    1.599295] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules
>[    1.599305] RAPL PMU: hw unit of domain package 2^-14 Joules
>[    1.599315] RAPL PMU: hw unit of domain dram 2^-14 Joules
>[    1.599324] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules
>[    1.599334] RAPL PMU: hw unit of domain psys 2^-14 Joules
>[    1.599643] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x29dc05e54fc, max_idle_ns: 440795291716 ns
>[    1.605668] workingset: timestamp_bits=46 max_order=21 bucket_order=0
>[    1.628343] ntfs: driver 2.1.32 [Flags: R/O].
>[    1.642848] NET: Registered protocol family 38
>[    1.643243] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
>[    1.643263] io scheduler noop registered
>[    1.643620] io scheduler cfq registered (default)
>[    1.643629] io scheduler mq-deadline registered
>[    1.643638] start plist test
>[    1.644835] end plist test
>[    1.649298] pcieport 0000:00:1c.0: AER enabled with IRQ 120
>[    1.649391] pcieport 0000:00:1c.5: AER enabled with IRQ 121
>[    1.649482] pcieport 0000:00:1d.0: AER enabled with IRQ 122
>[    1.649560] pcieport 0000:00:1c.0: Signaling PME with IRQ 120
>[    1.649610] pcieport 0000:00:1c.5: Signaling PME with IRQ 121
>[    1.649660] pcieport 0000:00:1d.0: Signaling PME with IRQ 122
>[    1.650056] uvesafb: failed to execute /sbin/v86d
>[    1.650067] uvesafb: make sure that the v86d helper is installed and executable
>[    1.650082] uvesafb: Getting VBE info block failed (eax=0x4f00, err=-2)
>[    1.650097] uvesafb: vbe_init() failed with -22
>[    1.650120] uvesafb: probe of uvesafb.0 failed with error -22
>[    1.650200] intel_idle: MWAIT substates: 0x11142120
>[    1.650202] intel_idle: v0.4.1 model 0x8E
>[    1.652063] intel_idle: lapic_timer_reliable_states 0xffffffff
>[    1.652465] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0
>[    1.652496] ACPI: Sleep Button [SLPB]
>[    1.652734] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>[    1.652754] ACPI: Power Button [PWRB]
>[    1.653045] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
>[    1.653064] ACPI: Power Button [PWRF]
>[    1.699516] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>[    1.736157] thermal LNXTHERM:00: registered as thermal_zone0
>[    1.736171] ACPI: Thermal Zone [TZ00] (28 C)
>[    1.737703] thermal LNXTHERM:01: registered as thermal_zone1
>[    1.737716] ACPI: Thermal Zone [TZ01] (30 C)
>[    1.738033] GHES: HEST is not enabled!
>[    1.738313] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>[    1.741114] Non-volatile memory driver v1.3
>[    1.741351] Linux agpgart interface v0.103
>[    1.743995] loop: module loaded
>[    1.744943] nvme nvme0: pci function 0000:03:00.0
>[    1.745084] ahci 0000:00:17.0: version 3.0
>[    1.746423] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
>[    1.746442] ahci 0000:00:17.0: flags: 64bit ncq pm led clo only pio slum part deso sadm sds apst 
>[    1.748532] scsi host0: ahci
>[    1.749402] scsi host1: ahci
>[    1.749741] ata1: SATA max UDMA/133 abar m2048@0xdf34b000 port 0xdf34b100 irq 124
>[    1.749758] ata2: SATA max UDMA/133 abar m2048@0xdf34b000 port 0xdf34b180 irq 124
>[    1.749977] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    1.750009] ehci-pci: EHCI PCI platform driver
>[    1.750081] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    1.750101] ohci-pci: OHCI PCI platform driver
>[    1.750154] uhci_hcd: USB Universal Host Controller Interface driver
>[    1.751322] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.751377] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>[    1.752574] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00109810
>[    1.752597] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
>[    1.752999] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.753017] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.753033] usb usb1: Product: xHCI Host Controller
>[    1.753045] usb usb1: Manufacturer: Linux 4.10.0-CI-CI_DRM_2273+ xhci-hcd
>[    1.753059] usb usb1: SerialNumber: 0000:00:14.0
>[    1.753912] hub 1-0:1.0: USB hub found
>[    1.754021] hub 1-0:1.0: 12 ports detected
>[    1.810469] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.810491] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    1.810707] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.810723] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.810738] usb usb2: Product: xHCI Host Controller
>[    1.810749] usb usb2: Manufacturer: Linux 4.10.0-CI-CI_DRM_2273+ xhci-hcd
>[    1.810763] usb usb2: SerialNumber: 0000:00:14.0
>[    1.811601] hub 2-0:1.0: USB hub found
>[    1.811671] hub 2-0:1.0: 6 ports detected
>[    1.840374] xhci_hcd 0000:01:00.0: xHCI Host Controller
>[    1.840402] xhci_hcd 0000:01:00.0: new USB bus registered, assigned bus number 3
>[    1.899372] xhci_hcd 0000:01:00.0: hcc params 0x0200eec1 hci version 0x110 quirks 0x00000010
>[    1.900167] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.900183] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.900200] usb usb3: Product: xHCI Host Controller
>[    1.900211] usb usb3: Manufacturer: Linux 4.10.0-CI-CI_DRM_2273+ xhci-hcd
>[    1.900225] usb usb3: SerialNumber: 0000:01:00.0
>[    1.900910] hub 3-0:1.0: USB hub found
>[    1.900995] hub 3-0:1.0: 2 ports detected
>[    1.901602] xhci_hcd 0000:01:00.0: xHCI Host Controller
>[    1.901624] xhci_hcd 0000:01:00.0: new USB bus registered, assigned bus number 4
>[    1.901718] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
>[    1.901853] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.901867] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.901882] usb usb4: Product: xHCI Host Controller
>[    1.901893] usb usb4: Manufacturer: Linux 4.10.0-CI-CI_DRM_2273+ xhci-hcd
>[    1.901907] usb usb4: SerialNumber: 0000:01:00.0
>[    1.902603] hub 4-0:1.0: USB hub found
>[    1.902653] hub 4-0:1.0: 2 ports detected
>[    1.903395] usbcore: registered new interface driver usb-storage
>[    1.903580] i8042: PNP: No PS/2 controller found.
>[    1.903589] i8042: Probing ports directly.
>[    2.105390]  nvme0n1: p1 p2 p3
>[    2.203357] ata2: SATA link down (SStatus 4 SControl 300)
>[    2.207622] ata1: SATA link down (SStatus 4 SControl 300)
>[    2.997802] i8042: No controller found
>[    2.997803] clocksource: Switched to clocksource tsc
>[    2.998107] mousedev: PS/2 mouse device common for all mice
>[    2.999066] rtc_cmos 00:02: RTC can wake from S4
>[    2.999753] rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0
>[    2.999859] rtc_cmos 00:02: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    3.000414] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
>[    3.001132] device-mapper: uevent: version 1.0.3
>[    3.001696] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
>[    3.001712] intel_pstate: Intel P-state driver initializing
>[    3.002491] intel_pstate: HWP enabled
>[    3.005461] EFI Variables Facility v0.08 2004-May-17
>[    3.024210] hidraw: raw HID events driver (C) Jiri Kosina
>[    3.024670] usbcore: registered new interface driver usbhid
>[    3.024680] usbhid: USB HID core driver
>[    3.024914] intel_rapl: Found RAPL domain package
>[    3.024924] intel_rapl: Found RAPL domain core
>[    3.024933] intel_rapl: Found RAPL domain uncore
>[    3.024942] intel_rapl: Found RAPL domain dram
>[    3.026435] Initializing XFRM netlink socket
>[    3.027735] NET: Registered protocol family 10
>[    3.028944] Segment Routing with IPv6
>[    3.028984] mip6: Mobile IPv6
>[    3.028998] NET: Registered protocol family 17
>[    3.029049] NET: Registered protocol family 15
>[    3.030186] AVX2 version of gcm_enc/dec engaged.
>[    3.030195] AES CTR mode by8 optimization enabled
>[    3.053830] alg: No test for pcbc(aes) (pcbc-aes-aesni)
>[    3.054450] registered taskstats version 1
>[    3.058138] Btrfs loaded, crc32c=crc32c-generic
>[    3.064492] rtc_cmos 00:02: setting system clock to 2017-03-02 20:34:18 UTC (1488486858)
>[    3.064967] PM: Hibernation image not present or could not be loaded.
>[    3.064974] ALSA device list:
>[    3.064981]   No soundcards found.
>[    3.066140] Freeing unused kernel memory: 1192K
>[    3.066150] Write protecting the kernel read-only data: 14336k
>[    3.066904] Freeing unused kernel memory: 1512K
>[    3.067989] Freeing unused kernel memory: 756K
>[    3.090205] random: systemd-udevd: uninitialized urandom read (16 bytes read)
>[    3.090464] random: systemd-udevd: uninitialized urandom read (16 bytes read)
>[    3.090492] random: systemd-udevd: uninitialized urandom read (16 bytes read)
>[    3.091591] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.091699] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.098527] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.098712] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.098885] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.099172] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.099357] random: udevadm: uninitialized urandom read (16 bytes read)
>[    3.156001] usb 1-7: new full-speed USB device number 2 using xhci_hcd
>[    3.246302] pps_core: LinuxPPS API ver. 1 registered
>[    3.246323] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    3.247617] PTP clock support registered
>[    3.251456] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
>[    3.251479] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
>[    3.253549] e1000e 0000:00:1f.6: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
>[    3.325726] usb 1-7: New USB device found, idVendor=8087, idProduct=0aa7
>[    3.325747] usb 1-7: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    3.347623] e1000e 0000:00:1f.6 0000:00:1f.6 (uninitialized): registered PHC clock
>[    3.430120] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 1c:1b:0d:84:93:99
>[    3.430191] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection
>[    3.430300] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: FFFFFF-0FF
>[    3.433463] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[    3.433525] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[    3.434372] e1000e 0000:00:1f.6 enp0s31f6: renamed from eth0
>[    3.436100] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[    3.436148] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[    3.436181] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[    3.436211] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[    3.436239] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[    3.436268] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[    3.436295] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[    3.436323] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[    3.436351] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[    3.436378] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[    3.436405] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[    3.436432] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[    3.436458] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[    3.436485] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[    3.436511] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[    3.436538] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[    3.436564] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[    3.436590] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[    3.436615] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[    3.436641] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[    3.436667] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[    3.436693] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[    3.436718] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[    3.436744] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[    3.436769] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[    3.436794] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[    3.436820] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[    3.436846] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[    3.436872] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[    3.436897] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[    3.436923] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[    3.436949] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[    3.436999] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[    3.437024] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[    3.437050] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[    3.439118] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[    3.439170] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[    3.439216] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[    3.439262] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[    3.439307] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[    3.439345] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[    3.439374] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[    3.439402] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[    3.439430] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[    3.439458] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[    3.439488] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[    3.439518] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[    3.439554] [drm] Memory usable by graphics device = 4096M
>[    3.439611] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[    3.439647] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[    3.439676] [drm] Replacing VGA console driver
>[    3.439778] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[    3.439876] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ab63018
>[    3.439941] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[    3.439992] [drm:intel_opregion_setup [i915]] SWSCI supported
>[    3.446109] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[    3.446153] [drm:intel_opregion_setup [i915]] ASLE supported
>[    3.446193] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[    3.446232] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[    3.446514] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[    3.446523] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    3.446548] [drm] Driver supports precise vblank timestamp query.
>[    3.446610] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[    3.446650] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[    3.446688] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[    3.446723] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[    3.448829] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[    3.448876] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[    3.448918] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[    3.448966] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[    3.448998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    3.449046] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[    3.449083] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[    3.449118] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[    3.449153] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[    3.449192] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[    3.449226] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[    3.449260] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[    3.449293] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    3.449325] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 10
>[    3.449358] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    3.449389] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 10
>[    3.449762] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[    3.449816] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[    3.449854] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[    3.449916] [drm:intel_power_well_enable [i915]] enabling power well 1
>[    3.449961] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[    3.450022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 675000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    3.450063] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[    3.450101] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[    3.450150] [drm:intel_power_well_enable [i915]] enabling always-on
>[    3.450183] [drm:intel_power_well_enable [i915]] enabling DC off
>[    3.450215] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[    3.450252] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    3.450285] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[    3.450316] [drm:skl_set_power_well [i915]] Enabling DDI A/E IO power well
>[    3.450345] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[    3.450375] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[    3.450403] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[    3.450433] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[    3.450463] [drm:skl_set_power_well [i915]] Enabling DDI D IO power well
>[    3.450511] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[    3.451891] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[    3.454151] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[    3.454195] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[    3.454229] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[    3.454261] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[    3.454291] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[    3.454321] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[    3.454350] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[    3.454379] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[    3.454407] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[    3.454452] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[    3.454801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 675000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    3.454819] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[    3.455233] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[    3.455391] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[    3.455501] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0
>[    3.455544] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[    3.455581] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[    3.455617] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[    3.455697] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af05
>[    3.455739] [drm:intel_edp_panel_vdd_sanitize [i915]] VDD left on by BIOS, adjusting state tracking
>[    3.464426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.472950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.481454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.489923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.498400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.506865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.515340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.523805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.532269] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.540733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.549197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.557661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.566125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.574590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.583053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.591518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.599983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.608448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.616912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.625386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.633851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.642315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.650779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.659243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.667707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.676172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.684636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.689726] random: fast init done
>[    3.693100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.701564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.710026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.718487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.726948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    3.726970] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[    3.726975] [drm] failed to retrieve link info, disabling eDP
>[    3.727025] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[    3.727083] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[    3.727178] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[    3.727237] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[    3.727303] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[    3.727362] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[    3.727396] [drm:intel_ddi_init [i915]] VBT says port C has lspcon
>[    3.727426] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[    3.727461] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[    3.728193] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    3.728970] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[    3.729625] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[    3.729651] [drm:lspcon_init [i915]] LSPCON detected
>[    3.730329] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    3.731145] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[    3.731937] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[    3.731960] [drm:lspcon_init [i915]] Success: LSPCON init
>[    3.731993] [drm:intel_ddi_init [i915]] LSPCON init success on port C
>[    3.732076] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: enabled
>[    3.732104] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[    3.732129] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[    3.732152] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[    3.732175] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1
>[    3.732196] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[    3.732218] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[    3.732240] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[    3.732260] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:49:DP-MST A] hw state readout: disabled, pipe A
>[    3.732279] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DP-MST B] hw state readout: disabled, pipe B
>[    3.732298] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DP-MST C] hw state readout: disabled, pipe C
>[    3.732324] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI C] hw state readout: enabled, pipe A
>[    3.732343] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[    3.732361] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[    3.732380] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST C] hw state readout: disabled, pipe C
>[    3.732401] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:DP-1] hw state readout: disabled
>[    3.732422] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:54:HDMI-A-1] hw state readout: disabled
>[    3.732443] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-2] hw state readout: enabled
>[    3.732532] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[    3.732553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[    3.732574] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    3.732595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    3.732599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 331 540000 1600 1648 1680 1760 900 903 908 926 0x40 0x5
>[    3.732618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    3.732621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 331 540000 1600 1648 1680 1760 900 903 908 926 0x40 0x5
>[    3.732641] [drm:intel_dump_pipe_config [i915]] crtc timings: 540000 1600 1648 1680 1760 900 903 908 926, type: 0x40 flags: 0x5
>[    3.732661] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 800x600, pixel rate 540000
>[    3.732681] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>[    3.732700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x06400384, enabled
>[    3.732719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    3.732741] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[    3.732760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    3.732780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[    3.732799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[    3.732817] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[    3.732837] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[    3.732856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[    3.732874] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    3.732893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    3.732896] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    3.732914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    3.732917] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    3.732935] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    3.732954] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[    3.732980] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[    3.732999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    3.733016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    3.733038] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    3.733057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    3.733076] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[    3.733095] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[    3.733114] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[    3.733134] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[    3.733152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[    3.733170] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    3.733188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    3.733191] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    3.733209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    3.733212] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    3.733230] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    3.733248] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[    3.733266] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[    3.733284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    3.733303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    3.733324] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    3.733343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    3.733361] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[    3.733380] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[    3.733398] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[    3.733419] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[    3.733484] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[    3.733509] [drm:skl_set_power_well [i915]] Disabling DDI D IO power well
>[    3.733530] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[    3.733551] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[    3.733570] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[    3.733590] [drm:skl_set_power_well [i915]] Disabling DDI A/E IO power well
>[    3.733629] [drm:skylake_get_initial_plane_config [i915]] pipe A with fb: size=800x600@32, offset=0, pitch 3200, size 0x1d4c00
>[    3.733654] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=1d5000
>[    3.733691] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space
>[    3.733721] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/kbl_huc_ver02_00_1810.bin
>[    3.733743] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[    3.733957] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/kbl_huc_ver02_00_1810.bin succeeded, fw ffff880256fac008
>[    3.733987] [drm:intel_uc_fw_fetch [i915]] firmware version 2.0 OK (minimum 2.0)
>[    3.734182] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880256ed8040
>[    3.734503] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[    3.734592] [drm:i915_gem_context_init [i915]] LR context support initialized
>[    3.734643] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[    3.735483] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[    3.735524] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[    3.735598] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[    3.735673] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[    3.735744] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[    3.735807] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[    3.735816] [drm] GuC firmware load skipped
>[    3.737085] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[    3.737111] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[    3.737135] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[    3.737158] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[    3.738526] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[    3.739505] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[    3.739920] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[    3.740552] [drm:intel_opregion_register [i915]] 3 outputs detected
>[    3.749045] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[    3.750451] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3
>[    3.751172] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[    3.751186] [drm:drm_setup_crtcs] 
>[    3.751192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[    3.751230] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[    3.751231] [drm] DRM_I915_DEBUG enabled
>[    3.751241] [drm] DRM_I915_DEBUG_GEM enabled
>[    3.751249] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to disconnected
>[    3.751303] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[    3.751308] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[    3.751344] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[    3.753579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    3.753607] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    3.755807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    3.755811] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    3.758043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    3.758068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    3.760130] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    3.760135] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[    3.760139] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] status updated from unknown to disconnected
>[    3.760141] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[    3.760144] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[    3.760169] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[    3.760902] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    3.760933] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    3.761612] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    3.762436] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[    3.763934] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[    3.763961] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    3.763992] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    3.764014] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    3.764802] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[    3.765505] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    3.767780] [drm:drm_dp_i2c_do_msg] native defer
>[    3.768907] [drm:drm_dp_i2c_do_msg] native defer
>[    3.770308] [drm:drm_dp_i2c_do_msg] native defer
>[    3.771451] [drm:drm_dp_i2c_do_msg] native defer
>[    3.772814] [drm:drm_dp_i2c_do_msg] native defer
>[    3.773965] [drm:drm_dp_i2c_do_msg] native defer
>[    3.775367] [drm:drm_dp_i2c_do_msg] native defer
>[    3.776491] [drm:drm_dp_i2c_do_msg] native defer
>[    3.777874] [drm:drm_dp_i2c_do_msg] native defer
>[    3.779013] [drm:drm_dp_i2c_do_msg] native defer
>[    3.780423] [drm:drm_dp_i2c_do_msg] native defer
>[    3.781510] [drm:drm_dp_i2c_do_msg] native defer
>[    3.782914] [drm:drm_dp_i2c_do_msg] native defer
>[    3.784054] [drm:drm_dp_i2c_do_msg] native defer
>[    3.785454] [drm:drm_dp_i2c_do_msg] native defer
>[    3.786592] [drm:drm_dp_i2c_do_msg] native defer
>[    3.788865] [drm:drm_dp_i2c_do_msg] native defer
>[    3.790006] [drm:drm_dp_i2c_do_msg] native defer
>[    3.791406] [drm:drm_dp_i2c_do_msg] native defer
>[    3.792545] [drm:drm_dp_i2c_do_msg] native defer
>[    3.793945] [drm:drm_dp_i2c_do_msg] native defer
>[    3.795098] [drm:drm_dp_i2c_do_msg] native defer
>[    3.796500] [drm:drm_dp_i2c_do_msg] native defer
>[    3.797636] [drm:drm_dp_i2c_do_msg] native defer
>[    3.799035] [drm:drm_dp_i2c_do_msg] native defer
>[    3.800175] [drm:drm_dp_i2c_do_msg] native defer
>[    3.801577] [drm:drm_dp_i2c_do_msg] native defer
>[    3.802719] [drm:drm_dp_i2c_do_msg] native defer
>[    3.804119] [drm:drm_dp_i2c_do_msg] native defer
>[    3.805259] [drm:drm_dp_i2c_do_msg] native defer
>[    3.806661] [drm:drm_dp_i2c_do_msg] native defer
>[    3.807802] [drm:drm_dp_i2c_do_msg] native defer
>[    3.808919] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    3.809608] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] status updated from unknown to connected
>[    3.809746] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[    3.809748] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[    3.809751] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[    3.809753] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    3.809794] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[    3.809796] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    3.809800] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[    3.809802] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[    3.809806] [drm:drm_mode_debug_printmodeline] Modeline 103:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[    3.809808] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    3.809814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[    3.809816] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[    3.809819] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    3.809821] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    3.809824] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    3.809826] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    3.809829] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    3.809831] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    3.809833] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    3.809836] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    3.809838] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    3.809841] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    3.809843] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    3.809845] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    3.809848] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    3.809850] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    3.809853] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    3.809855] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    3.809857] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    3.809860] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    3.809862] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    3.809864] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    3.809867] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    3.809869] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    3.809871] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    3.809881] [drm:drm_setup_crtcs] connector 48 enabled? no
>[    3.809883] [drm:drm_setup_crtcs] connector 54 enabled? no
>[    3.809885] [drm:drm_setup_crtcs] connector 57 enabled? yes
>[    3.809913] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    3.809917] [drm:drm_setup_crtcs] looking for cmdline mode on connector 57
>[    3.809919] [drm:drm_setup_crtcs] looking for preferred mode on connector 57 0
>[    3.809921] [drm:drm_setup_crtcs] found mode 1600x900
>[    3.809923] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    3.809929] [drm:drm_setup_crtcs] desired mode 1600x900 set on crtc 32 (0,0)
>[    3.809963] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[    3.810304] [drm:intelfb_create [i915]] allocated 1600x900 fb: 0x00040000
>[    3.810742] fbcon: inteldrmfb (fb0) is primary device
>[    3.811275] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[    3.811300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[    3.811326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[    3.811351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[    3.811372] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[    3.811396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    3.811419] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[    3.811440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[    3.811461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[    3.811481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[    3.811500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    3.811503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[    3.811522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    3.811524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[    3.811543] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[    3.811562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[    3.811580] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>[    3.811598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    3.811616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    3.811639] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[    3.811658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    3.811677] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[    3.811696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[    3.811714] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[    3.811736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[    3.811760] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[    3.811780] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[    3.811800] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[    3.812060] [drm:intel_disable_pipe [i915]] disabling pipe A
>[    3.825055] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[    3.825080] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[    3.825137] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[    3.825171] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[    3.825200] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[    3.825233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    3.825256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[    3.825280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[    3.825301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[    3.825322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[    3.825342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[    3.825362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[    3.825381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[    3.825400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[    3.825421] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[    3.825443] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[    3.825464] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[    3.825486] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[    3.825510] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[    3.825531] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[    3.827725] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[    3.827749] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[    3.837341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.845834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.854317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.862800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.871282] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.879763] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.888243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.896744] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.905225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.913706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.922183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.930665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.939138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.947611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.956082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.964553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.973025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.981496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[    3.989114] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[    4.050338] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[    4.050372] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[    4.050433] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[    4.051079] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    4.051968] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[    4.053106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[    4.053135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[    4.053161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    4.053188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[    4.058934] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[    4.058959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[    4.064105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[    4.066597] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880256ec2548
>[    4.067187] [drm:intel_enable_pipe [i915]] enabling pipe A
>[    4.067231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[    4.067256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[    4.067306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[    4.067349] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[    4.067376] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[    4.100723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[    4.100777] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[    4.100847] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[    4.100888] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[    4.101031] Console: switching to colour frame buffer device 200x56
>[    4.122100] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    4.341535] EXT4-fs (nvme0n1p2): mounted filesystem with ordered data mode. Opts: (null)
>[    4.480616] systemd[1]: systemd 229 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN)
>[    4.481059] systemd[1]: Detected architecture x86-64.
>[    4.481759] systemd[1]: Set hostname to <kbl-7500u>.
>[    4.563972] systemd[1]: Listening on fsck to fsckd communication Socket.
>[    4.564544] systemd[1]: Created slice System Slice.
>[    4.564839] systemd[1]: Reached target Encrypted Volumes.
>[    4.565230] systemd[1]: Listening on Journal Socket (/dev/log).
>[    4.565636] systemd[1]: Listening on udev Control Socket.
>[    4.569337] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>[    4.573709] systemd[1]: Listening on udev Kernel Socket.
>[    4.808698] EXT4-fs (nvme0n1p2): re-mounted. Opts: errors=remount-ro
>[    4.834803] systemd-journald[271]: Received request to flush runtime journal from PID 1
>[    5.186112] mei_me 0000:00:16.0: enabling device (0000 -> 0002)
>[    5.269230] snd_hda_intel 0000:00:1f.3: enabling device (0000 -> 0002)
>[    5.274054] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[    5.281366] Adding 8261628k swap on /dev/nvme0n1p3.  Priority:-1 extents:1 across:8261628k SSFS
>[    5.320843] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[    5.320845] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[    5.320847] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[    5.320849] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[    5.320850] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[    5.341746] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    5.341780] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    5.341805] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    5.341842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    5.341865] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    5.341887] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    5.341910] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    5.341933] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    5.351540] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input4
>[    5.352511] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input5
>[    5.353184] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input6
>[    5.353807] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input7
>[    5.354569] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input8
>[    5.355113] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input9
>[    5.732672] [drm] RC6 on
>[    6.052700] IPv6: ADDRCONF(NETDEV_UP): enp0s31f6: link is not ready
>[    6.260484] IPv6: ADDRCONF(NETDEV_UP): enp0s31f6: link is not ready
>[    7.008116] random: crng init done
>[    9.096236] e1000e: enp0s31f6 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[    9.096458] IPv6: ADDRCONF(NETDEV_CHANGE): enp0s31f6: link becomes ready
>[   13.797331] [drm:drm_fb_helper_hotplug_event] 
>[   13.797367] [drm:drm_setup_crtcs] 
>[   13.797385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[   13.797502] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[   13.797565] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[   13.797581] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[   13.797684] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[   13.802302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   13.802329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   13.804142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   13.804149] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   13.806146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   13.806172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   13.808129] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   13.808137] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   13.808142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[   13.808146] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[   13.808173] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[   13.808947] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[   13.809013] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[   13.809741] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[   13.810575] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[   13.812128] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[   13.812154] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   13.812178] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[   13.812200] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[   13.813212] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[   13.813948] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[   13.815029] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[   13.815034] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[   13.815038] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[   13.815041] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[   13.815167] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   13.815171] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: VIRTUAL_X
>[   13.815178] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   13.815181] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: VIRTUAL_X
>[   13.815188] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   13.815191] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: VIRTUAL_X
>[   13.815198] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   13.815201] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: VIRTUAL_X
>[   13.815207] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 0 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   13.815210] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: VIRTUAL_X
>[   13.815216] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 0 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   13.815219] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: VIRTUAL_X
>[   13.815225] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   13.815228] [drm:drm_mode_prune_invalid] Not using 1280x1024 mode: VIRTUAL_Y
>[   13.815235] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   13.815238] [drm:drm_mode_prune_invalid] Not using 1280x1024 mode: VIRTUAL_Y
>[   13.815244] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   13.815247] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[   13.815253] [drm:drm_mode_debug_printmodeline] Modeline 110:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   13.815256] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[   13.815263] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   13.815266] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[   13.815370] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[   13.815375] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[   13.815379] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   13.815382] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   13.815386] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   13.815390] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   13.815394] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   13.815397] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   13.815401] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   13.815405] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   13.815409] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   13.815412] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   13.815416] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   13.815420] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   13.815423] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   13.815427] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   13.815431] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   13.815445] [drm:drm_setup_crtcs] connector 48 enabled? no
>[   13.815448] [drm:drm_setup_crtcs] connector 54 enabled? no
>[   13.815451] [drm:drm_setup_crtcs] connector 57 enabled? yes
>[   13.815481] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[   13.815488] [drm:drm_setup_crtcs] looking for cmdline mode on connector 57
>[   13.815491] [drm:drm_setup_crtcs] looking for preferred mode on connector 57 0
>[   13.815494] [drm:drm_setup_crtcs] found mode 1600x900
>[   13.815497] [drm:drm_setup_crtcs] picking CRTCs for 1600x900 config
>[   13.815510] [drm:drm_setup_crtcs] desired mode 1600x900 set on crtc 32 (0,0)
>[   65.686032] Console: switching to colour dummy device 80x25
>[   65.686139] [IGT] core_auth: executing
>[   65.700434] [IGT] core_auth: starting subtest basic-auth
>[   65.700770] [IGT] core_auth: exiting, ret=0
>[   65.723416] Console: switching to colour frame buffer device 200x56
>[   65.809635] Console: switching to colour dummy device 80x25
>[   65.809729] [IGT] core_prop_blob: executing
>[   65.820372] [IGT] core_prop_blob: starting subtest basic
>[   65.820458] [IGT] core_prop_blob: exiting, ret=0
>[   65.873556] Console: switching to colour frame buffer device 200x56
>[   65.961467] Console: switching to colour dummy device 80x25
>[   65.961559] [IGT] drv_getparams_basic: executing
>[   65.982277] [IGT] drv_getparams_basic: starting subtest basic-eu-total
>[   65.982350] [IGT] drv_getparams_basic: exiting, ret=0
>[   66.023592] Console: switching to colour frame buffer device 200x56
>[   66.128440] Console: switching to colour dummy device 80x25
>[   66.128587] [IGT] drv_getparams_basic: executing
>[   66.141315] [IGT] drv_getparams_basic: starting subtest basic-subslice-total
>[   66.141392] [IGT] drv_getparams_basic: exiting, ret=0
>[   66.190659] Console: switching to colour frame buffer device 200x56
>[   66.302323] Console: switching to colour dummy device 80x25
>[   66.302464] [IGT] drv_hangman: executing
>[   66.315657] [IGT] drv_hangman: starting subtest error-state-basic
>[   66.315834] [drm:error_state_write [i915]] Resetting error state
>[   66.319110] [drm] GPU HANG: ecode 9:-1:0x00000000, reason: Manually setting wedged to 1, action: reset
>[   66.319119] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
>[   66.319121] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
>[   66.319123] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
>[   66.319125] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
>[   66.319127] [drm] GPU crash dump saved to /sys/class/drm/card0/error
>[   66.319595] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   66.319677] drm/i915: Resetting chip after gpu hang
>[   66.323298] [drm] RC6 on
>[   66.340076] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   66.340116] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[   66.340194] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   66.340271] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   66.340345] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   66.340399] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[   66.340408] [drm] GuC firmware load skipped
>[   66.360567] [drm:error_state_write [i915]] Resetting error state
>[   66.360801] [IGT] drv_hangman: exiting, ret=0
>[   66.390861] Console: switching to colour frame buffer device 200x56
>[   66.500199] Console: switching to colour dummy device 80x25
>[   66.500342] [IGT] gem_basic: executing
>[   66.514349] [IGT] gem_basic: starting subtest bad-close
>[   66.514425] [IGT] gem_basic: exiting, ret=0
>[   66.540410] Console: switching to colour frame buffer device 200x56
>[   66.604604] Console: switching to colour dummy device 80x25
>[   66.604757] [IGT] gem_basic: executing
>[   66.626195] [IGT] gem_basic: starting subtest create-close
>[   66.626311] [IGT] gem_basic: exiting, ret=0
>[   66.640365] Console: switching to colour frame buffer device 200x56
>[   66.714906] Console: switching to colour dummy device 80x25
>[   66.715065] [IGT] gem_basic: executing
>[   66.729441] [IGT] gem_basic: starting subtest create-fd-close
>[   66.729785] [IGT] gem_basic: exiting, ret=0
>[   66.773891] Console: switching to colour frame buffer device 200x56
>[   66.902033] Console: switching to colour dummy device 80x25
>[   66.902154] [IGT] gem_busy: executing
>[   66.925102] [IGT] gem_busy: starting subtest basic-busy-default
>[   66.950273] [IGT] gem_busy: exiting, ret=0
>[   67.007763] Console: switching to colour frame buffer device 200x56
>[   67.113785] Console: switching to colour dummy device 80x25
>[   67.114142] [IGT] gem_busy: executing
>[   67.129798] [IGT] gem_busy: starting subtest basic-hang-default
>[   78.759283] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_busy [6183], reason: Hang on render ring, action: reset
>[   78.759467] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   78.759549] drm/i915: Resetting chip after gpu hang
>[   78.760324] [drm:i915_gem_reset [i915]] context gem_busy[6183]/0 marked guilty (score 10) banned? no
>[   78.760340] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x168
>[   78.760421] [drm] RC6 on
>[   78.776900] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   78.776918] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x168, 0x0]
>[   78.776943] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[   78.777050] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   78.777111] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   78.777156] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   78.777187] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[   78.777192] [drm] GuC firmware load skipped
>[   78.777554] [IGT] gem_busy: exiting, ret=0
>[   78.828121] Console: switching to colour frame buffer device 200x56
>[   78.880213] Console: switching to colour dummy device 80x25
>[   78.880309] [IGT] gem_close_race: executing
>[   78.910211] [IGT] gem_close_race: starting subtest basic-process
>[   78.935529] [IGT] gem_close_race: exiting, ret=0
>[   78.978678] Console: switching to colour frame buffer device 200x56
>[   79.070611] Console: switching to colour dummy device 80x25
>[   79.070706] [IGT] gem_close_race: executing
>[   79.083095] [IGT] gem_close_race: starting subtest basic-threads
>[   80.159762] [IGT] gem_close_race: exiting, ret=0
>[   80.211940] Console: switching to colour frame buffer device 200x56
>[   80.265585] Console: switching to colour dummy device 80x25
>[   80.266167] [IGT] gem_cpu_reloc: executing
>[   80.294408] [IGT] gem_cpu_reloc: starting subtest basic
>[   80.304506] [IGT] gem_cpu_reloc: exiting, ret=0
>[   80.362558] Console: switching to colour frame buffer device 200x56
>[   80.461085] Console: switching to colour dummy device 80x25
>[   80.461191] [IGT] gem_cs_tlb: executing
>[   80.475401] [IGT] gem_cs_tlb: starting subtest basic-default
>[   81.603989] [IGT] gem_cs_tlb: exiting, ret=0
>[   81.645829] Console: switching to colour frame buffer device 200x56
>[   81.693796] Console: switching to colour dummy device 80x25
>[   81.693887] [IGT] gem_ctx_basic: executing
>[   84.737268] [IGT] gem_ctx_basic: exiting, ret=0
>[   84.763641] Console: switching to colour frame buffer device 200x56
>[   84.847027] Console: switching to colour dummy device 80x25
>[   84.847152] [IGT] gem_ctx_create: executing
>[   84.868836] [IGT] gem_ctx_create: starting subtest basic
>[   84.870130] [IGT] gem_ctx_create: exiting, ret=0
>[   84.913703] Console: switching to colour frame buffer device 200x56
>[   84.968341] Console: switching to colour dummy device 80x25
>[   84.968467] [IGT] gem_ctx_create: executing
>[   84.992312] [IGT] gem_ctx_create: starting subtest basic-files
>[   90.905105] [IGT] gem_ctx_create: exiting, ret=0
>[   90.965946] Console: switching to colour frame buffer device 200x56
>[   91.057420] Console: switching to colour dummy device 80x25
>[   91.057543] [IGT] gem_ctx_exec: executing
>[   91.071494] [IGT] gem_ctx_exec: starting subtest basic
>[   91.072281] [IGT] gem_ctx_exec: exiting, ret=0
>[   91.099427] Console: switching to colour frame buffer device 200x56
>[   91.234269] Console: switching to colour dummy device 80x25
>[   91.234418] [IGT] gem_ctx_param: executing
>[   91.245338] [IGT] gem_ctx_param: starting subtest basic
>[   91.245475] [IGT] gem_ctx_param: exiting, ret=0
>[   91.282773] Console: switching to colour frame buffer device 200x56
>[   91.390098] Console: switching to colour dummy device 80x25
>[   91.390208] [IGT] gem_ctx_param: executing
>[   91.403248] [IGT] gem_ctx_param: starting subtest basic-default
>[   91.403355] [IGT] gem_ctx_param: exiting, ret=0
>[   91.449553] Console: switching to colour frame buffer device 200x56
>[   91.557718] Console: switching to colour dummy device 80x25
>[   91.557863] [IGT] gem_ctx_switch: executing
>[   91.571675] [IGT] gem_ctx_switch: starting subtest basic-default
>[   96.998732] [IGT] gem_ctx_switch: exiting, ret=0
>[   97.085439] Console: switching to colour frame buffer device 200x56
>[   97.199289] Console: switching to colour dummy device 80x25
>[   97.199405] [IGT] gem_ctx_switch: executing
>[   97.222751] [IGT] gem_ctx_switch: starting subtest basic-default-heavy
>[  113.663343] [IGT] gem_ctx_switch: exiting, ret=0
>[  113.724299] Console: switching to colour frame buffer device 200x56
>[  113.849009] Console: switching to colour dummy device 80x25
>[  113.849159] [IGT] gem_exec_basic: executing
>[  113.862125] [IGT] gem_exec_basic: starting subtest basic-blt
>[  113.863183] [IGT] gem_exec_basic: exiting, ret=0
>[  113.907856] Console: switching to colour frame buffer device 200x56
>[  114.023333] Console: switching to colour dummy device 80x25
>[  114.023520] [IGT] gem_exec_basic: executing
>[  114.034302] [IGT] gem_exec_basic: starting subtest basic-bsd
>[  114.035600] [IGT] gem_exec_basic: exiting, ret=0
>[  114.091538] Console: switching to colour frame buffer device 200x56
>[  114.200352] Console: switching to colour dummy device 80x25
>[  114.200518] [IGT] gem_exec_basic: executing
>[  114.213720] [IGT] gem_exec_basic: starting subtest basic-bsd1
>[  114.215557] [IGT] gem_exec_basic: exiting, ret=77
>[  114.274937] Console: switching to colour frame buffer device 200x56
>[  114.389750] Console: switching to colour dummy device 80x25
>[  114.389939] [IGT] gem_exec_basic: executing
>[  114.412069] [IGT] gem_exec_basic: starting subtest basic-bsd2
>[  114.413265] [IGT] gem_exec_basic: exiting, ret=77
>[  114.458324] Console: switching to colour frame buffer device 200x56
>[  114.571355] Console: switching to colour dummy device 80x25
>[  114.571462] [IGT] gem_exec_basic: executing
>[  114.592999] [IGT] gem_exec_basic: starting subtest basic-default
>[  114.594291] [IGT] gem_exec_basic: exiting, ret=0
>[  114.641367] Console: switching to colour frame buffer device 200x56
>[  114.718762] Console: switching to colour dummy device 80x25
>[  114.718857] [IGT] gem_exec_basic: executing
>[  114.727946] [IGT] gem_exec_basic: starting subtest basic-render
>[  114.729118] [IGT] gem_exec_basic: exiting, ret=0
>[  114.774840] Console: switching to colour frame buffer device 200x56
>[  114.879824] Console: switching to colour dummy device 80x25
>[  114.880102] [IGT] gem_exec_basic: executing
>[  114.898077] [IGT] gem_exec_basic: starting subtest basic-vebox
>[  114.900115] [IGT] gem_exec_basic: exiting, ret=0
>[  114.942162] Console: switching to colour frame buffer device 200x56
>[  115.043371] Console: switching to colour dummy device 80x25
>[  115.043499] [IGT] gem_exec_basic: executing
>[  115.065326] [IGT] gem_exec_basic: starting subtest gtt-blt
>[  115.067157] [IGT] gem_exec_basic: exiting, ret=0
>[  115.125475] Console: switching to colour frame buffer device 200x56
>[  115.233496] Console: switching to colour dummy device 80x25
>[  115.233603] [IGT] gem_exec_basic: executing
>[  115.256072] [IGT] gem_exec_basic: starting subtest gtt-bsd
>[  115.257371] [IGT] gem_exec_basic: exiting, ret=0
>[  115.308590] Console: switching to colour frame buffer device 200x56
>[  115.408760] Console: switching to colour dummy device 80x25
>[  115.408854] [IGT] gem_exec_basic: executing
>[  115.419978] [IGT] gem_exec_basic: starting subtest gtt-bsd1
>[  115.420834] [IGT] gem_exec_basic: exiting, ret=77
>[  115.458384] Console: switching to colour frame buffer device 200x56
>[  115.563439] Console: switching to colour dummy device 80x25
>[  115.563616] [IGT] gem_exec_basic: executing
>[  115.587399] [IGT] gem_exec_basic: starting subtest gtt-bsd2
>[  115.588686] [IGT] gem_exec_basic: exiting, ret=77
>[  115.642387] Console: switching to colour frame buffer device 200x56
>[  115.736844] Console: switching to colour dummy device 80x25
>[  115.737060] [IGT] gem_exec_basic: executing
>[  115.763315] [IGT] gem_exec_basic: starting subtest gtt-default
>[  115.765199] [IGT] gem_exec_basic: exiting, ret=0
>[  115.809185] Console: switching to colour frame buffer device 200x56
>[  115.905445] Console: switching to colour dummy device 80x25
>[  115.905543] [IGT] gem_exec_basic: executing
>[  115.928066] [IGT] gem_exec_basic: starting subtest gtt-render
>[  115.929341] [IGT] gem_exec_basic: exiting, ret=0
>[  115.975245] Console: switching to colour frame buffer device 200x56
>[  116.106361] Console: switching to colour dummy device 80x25
>[  116.106509] [IGT] gem_exec_basic: executing
>[  116.118571] [IGT] gem_exec_basic: starting subtest gtt-vebox
>[  116.120225] [IGT] gem_exec_basic: exiting, ret=0
>[  116.158805] Console: switching to colour frame buffer device 200x56
>[  116.258541] Console: switching to colour dummy device 80x25
>[  116.258644] [IGT] gem_exec_basic: executing
>[  116.271134] [IGT] gem_exec_basic: starting subtest readonly-blt
>[  116.272303] [IGT] gem_exec_basic: exiting, ret=0
>[  116.326071] Console: switching to colour frame buffer device 200x56
>[  116.434186] Console: switching to colour dummy device 80x25
>[  116.434314] [IGT] gem_exec_basic: executing
>[  116.446934] [IGT] gem_exec_basic: starting subtest readonly-bsd
>[  116.448063] [IGT] gem_exec_basic: exiting, ret=0
>[  116.492166] Console: switching to colour frame buffer device 200x56
>[  116.604830] Console: switching to colour dummy device 80x25
>[  116.605015] [IGT] gem_exec_basic: executing
>[  116.627005] [IGT] gem_exec_basic: starting subtest readonly-bsd1
>[  116.628429] [IGT] gem_exec_basic: exiting, ret=77
>[  116.676110] Console: switching to colour frame buffer device 200x56
>[  116.786628] Console: switching to colour dummy device 80x25
>[  116.786775] [IGT] gem_exec_basic: executing
>[  116.801622] [IGT] gem_exec_basic: starting subtest readonly-bsd2
>[  116.803148] [IGT] gem_exec_basic: exiting, ret=77
>[  116.842665] Console: switching to colour frame buffer device 200x56
>[  116.949994] Console: switching to colour dummy device 80x25
>[  116.950099] [IGT] gem_exec_basic: executing
>[  116.970806] [IGT] gem_exec_basic: starting subtest readonly-default
>[  116.972001] [IGT] gem_exec_basic: exiting, ret=0
>[  117.026189] Console: switching to colour frame buffer device 200x56
>[  117.144632] Console: switching to colour dummy device 80x25
>[  117.144820] [IGT] gem_exec_basic: executing
>[  117.157345] [IGT] gem_exec_basic: starting subtest readonly-render
>[  117.158834] [IGT] gem_exec_basic: exiting, ret=0
>[  117.209523] Console: switching to colour frame buffer device 200x56
>[  117.303353] Console: switching to colour dummy device 80x25
>[  117.303447] [IGT] gem_exec_basic: executing
>[  117.313991] [IGT] gem_exec_basic: starting subtest readonly-vebox
>[  117.315214] [IGT] gem_exec_basic: exiting, ret=0
>[  117.359084] Console: switching to colour frame buffer device 200x56
>[  117.446721] Console: switching to colour dummy device 80x25
>[  117.446816] [IGT] gem_exec_create: executing
>[  117.457942] [IGT] gem_exec_create: starting subtest basic
>[  122.653878] [IGT] gem_exec_create: exiting, ret=0
>[  122.694627] Console: switching to colour frame buffer device 200x56
>[  122.798761] Console: switching to colour dummy device 80x25
>[  122.798862] [IGT] gem_exec_fence: executing
>[  122.811374] [IGT] gem_exec_fence: starting subtest basic-busy-default
>[  122.835228] [IGT] gem_exec_fence: exiting, ret=0
>[  122.878178] Console: switching to colour frame buffer device 200x56
>[  122.975099] Console: switching to colour dummy device 80x25
>[  122.975194] [IGT] gem_exec_fence: executing
>[  122.986412] [IGT] gem_exec_fence: starting subtest basic-wait-default
>[  123.022327] [IGT] gem_exec_fence: exiting, ret=0
>[  123.078279] Console: switching to colour frame buffer device 200x56
>[  123.183868] Console: switching to colour dummy device 80x25
>[  123.184047] [IGT] gem_exec_fence: executing
>[  123.194485] [IGT] gem_exec_fence: starting subtest basic-await-default
>[  124.203094] [IGT] gem_exec_fence: exiting, ret=0
>[  124.244879] Console: switching to colour frame buffer device 200x56
>[  124.321726] Console: switching to colour dummy device 80x25
>[  124.321821] [IGT] gem_exec_fence: executing
>[  124.333392] [IGT] gem_exec_fence: starting subtest await-hang-default
>[  128.741981] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  132.715748] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_exec_fence [6348], reason: Hang on render ring, action: reset
>[  132.715831] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  132.715866] drm/i915: Resetting chip after gpu hang
>[  132.716327] [drm:i915_gem_reset [i915]] context gem_exec_fence[6348]/0 marked guilty (score 10) banned? no
>[  132.716342] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x2533c
>[  132.716408] [drm] RC6 on
>[  132.733145] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  132.733169] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x2533e, 0x0]
>[  132.733201] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  132.733263] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  132.733324] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  132.733383] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  132.733424] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  132.733431] [drm] GuC firmware load skipped
>[  132.743863] [IGT] gem_exec_fence: exiting, ret=0
>[  132.798454] Console: switching to colour frame buffer device 200x56
>[  132.902949] Console: switching to colour dummy device 80x25
>[  132.903081] [IGT] gem_exec_fence: executing
>[  132.915457] [IGT] gem_exec_fence: starting subtest nb-await-default
>[  133.917451] [IGT] gem_exec_fence: exiting, ret=0
>[  133.965645] Console: switching to colour frame buffer device 200x56
>[  134.029778] Console: switching to colour dummy device 80x25
>[  134.029873] [IGT] gem_exec_flush: executing
>[  134.041090] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-cmd
>[  134.042451] [IGT] gem_exec_flush: exiting, ret=77
>[  134.082287] Console: switching to colour frame buffer device 200x56
>[  134.189401] Console: switching to colour dummy device 80x25
>[  134.189510] [IGT] gem_exec_flush: executing
>[  134.204114] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-uc
>[  139.689968] [IGT] gem_exec_flush: exiting, ret=0
>[  139.734175] Console: switching to colour frame buffer device 200x56
>[  139.869406] Console: switching to colour dummy device 80x25
>[  139.869527] [IGT] gem_exec_flush: executing
>[  139.880133] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-wb
>[  145.343937] [IGT] gem_exec_flush: exiting, ret=0
>[  145.386185] Console: switching to colour frame buffer device 200x56
>[  145.554852] Console: switching to colour dummy device 80x25
>[  145.555602] [IGT] gem_exec_flush: executing
>[  145.585116] [IGT] gem_exec_flush: starting subtest basic-uc-pro-default
>[  150.967758] [IGT] gem_exec_flush: exiting, ret=0
>[  151.004481] Console: switching to colour frame buffer device 200x56
>[  151.163522] Console: switching to colour dummy device 80x25
>[  151.163714] [IGT] gem_exec_flush: executing
>[  151.188179] [IGT] gem_exec_flush: starting subtest basic-uc-prw-default
>[  156.569177] [IGT] gem_exec_flush: exiting, ret=0
>[  156.606950] Console: switching to colour frame buffer device 200x56
>[  156.752745] Console: switching to colour dummy device 80x25
>[  156.753309] [IGT] gem_exec_flush: executing
>[  156.783386] [IGT] gem_exec_flush: starting subtest basic-uc-ro-default
>[  162.181369] [IGT] gem_exec_flush: exiting, ret=0
>[  162.225296] Console: switching to colour frame buffer device 200x56
>[  162.386857] Console: switching to colour dummy device 80x25
>[  162.387147] [IGT] gem_exec_flush: executing
>[  162.403162] [IGT] gem_exec_flush: starting subtest basic-uc-rw-default
>[  167.783038] [IGT] gem_exec_flush: exiting, ret=0
>[  167.827816] Console: switching to colour frame buffer device 200x56
>[  167.991461] Console: switching to colour dummy device 80x25
>[  167.991890] [IGT] gem_exec_flush: executing
>[  168.025293] [IGT] gem_exec_flush: starting subtest basic-uc-set-default
>[  173.420041] [IGT] gem_exec_flush: exiting, ret=0
>[  173.462781] Console: switching to colour frame buffer device 200x56
>[  173.526085] Console: switching to colour dummy device 80x25
>[  173.526273] [IGT] gem_exec_flush: executing
>[  173.544010] [IGT] gem_exec_flush: starting subtest basic-wb-pro-default
>[  178.938610] [IGT] gem_exec_flush: exiting, ret=0
>[  178.981840] Console: switching to colour frame buffer device 200x56
>[  179.129276] Console: switching to colour dummy device 80x25
>[  179.129432] [IGT] gem_exec_flush: executing
>[  179.141353] [IGT] gem_exec_flush: starting subtest basic-wb-prw-default
>[  184.518848] [IGT] gem_exec_flush: exiting, ret=0
>[  184.567309] Console: switching to colour frame buffer device 200x56
>[  184.719263] Console: switching to colour dummy device 80x25
>[  184.719455] [IGT] gem_exec_flush: executing
>[  184.744453] [IGT] gem_exec_flush: starting subtest basic-wb-ro-before-default
>[  190.122559] [IGT] gem_exec_flush: exiting, ret=0
>[  190.169310] Console: switching to colour frame buffer device 200x56
>[  190.312173] Console: switching to colour dummy device 80x25
>[  190.312416] [IGT] gem_exec_flush: executing
>[  190.336859] [IGT] gem_exec_flush: starting subtest basic-wb-ro-default
>[  195.716391] [IGT] gem_exec_flush: exiting, ret=0
>[  195.771458] Console: switching to colour frame buffer device 200x56
>[  195.926582] Console: switching to colour dummy device 80x25
>[  195.927460] [IGT] gem_exec_flush: executing
>[  195.959414] [IGT] gem_exec_flush: starting subtest basic-wb-rw-before-default
>[  201.352039] [IGT] gem_exec_flush: exiting, ret=0
>[  201.390163] Console: switching to colour frame buffer device 200x56
>[  201.536955] Console: switching to colour dummy device 80x25
>[  201.537389] [IGT] gem_exec_flush: executing
>[  201.556910] [IGT] gem_exec_flush: starting subtest basic-wb-rw-default
>[  206.958830] [IGT] gem_exec_flush: exiting, ret=0
>[  207.008419] Console: switching to colour frame buffer device 200x56
>[  207.163375] Console: switching to colour dummy device 80x25
>[  207.163835] [IGT] gem_exec_flush: executing
>[  207.195699] [IGT] gem_exec_flush: starting subtest basic-wb-set-default
>[  212.591380] [IGT] gem_exec_flush: exiting, ret=0
>[  212.644279] Console: switching to colour frame buffer device 200x56
>[  212.802462] Console: switching to colour dummy device 80x25
>[  212.802890] [IGT] gem_exec_gttfill: executing
>[  212.834089] [IGT] gem_exec_gttfill: starting subtest basic
>[  212.834664] gem_exec_gttfil (6476): drop_caches: 4
>[  216.099506] [IGT] gem_exec_gttfill: exiting, ret=0
>[  216.145070] Console: switching to colour frame buffer device 200x56
>[  216.216749] Console: switching to colour dummy device 80x25
>[  216.216847] [IGT] gem_exec_nop: executing
>[  216.239778] [IGT] gem_exec_nop: starting subtest basic-parallel
>[  225.487719] [IGT] gem_exec_nop: exiting, ret=0
>[  225.531856] Console: switching to colour frame buffer device 200x56
>[  225.587741] Console: switching to colour dummy device 80x25
>[  225.587881] [IGT] gem_exec_nop: executing
>[  225.600041] [IGT] gem_exec_nop: starting subtest basic-series
>[  234.861809] [IGT] gem_exec_nop: exiting, ret=0
>[  234.901989] Console: switching to colour frame buffer device 200x56
>[  235.012471] Console: switching to colour dummy device 80x25
>[  235.012588] [IGT] gem_exec_parallel: executing
>[  235.025125] [IGT] gem_exec_parallel: starting subtest basic
>[  235.722114] [IGT] gem_exec_parallel: exiting, ret=0
>[  235.768996] Console: switching to colour frame buffer device 200x56
>[  235.863034] Console: switching to colour dummy device 80x25
>[  235.863330] [IGT] gem_exec_parse: executing
>[  235.882559] [IGT] gem_exec_parse: exiting, ret=77
>[  235.919557] Console: switching to colour frame buffer device 200x56
>[  236.053713] Console: switching to colour dummy device 80x25
>[  236.053834] [IGT] gem_exec_parse: executing
>[  236.064422] [IGT] gem_exec_parse: exiting, ret=77
>[  236.085792] Console: switching to colour frame buffer device 200x56
>[  236.174636] Console: switching to colour dummy device 80x25
>[  236.174813] [IGT] gem_exec_reloc: executing
>[  236.186201] [IGT] gem_exec_reloc: starting subtest basic-cpu
>[  236.190617] [IGT] gem_exec_reloc: exiting, ret=0
>[  236.236395] Console: switching to colour frame buffer device 200x56
>[  236.328285] Console: switching to colour dummy device 80x25
>[  236.328402] [IGT] gem_exec_reloc: executing
>[  236.349218] [IGT] gem_exec_reloc: starting subtest basic-gtt
>[  236.350718] [IGT] gem_exec_reloc: exiting, ret=0
>[  236.403122] Console: switching to colour frame buffer device 200x56
>[  236.536447] Console: switching to colour dummy device 80x25
>[  236.536594] [IGT] gem_exec_reloc: executing
>[  236.549515] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt
>[  236.551420] [IGT] gem_exec_reloc: exiting, ret=0
>[  236.586206] Console: switching to colour frame buffer device 200x56
>[  236.677156] Console: switching to colour dummy device 80x25
>[  236.677250] [IGT] gem_exec_reloc: executing
>[  236.698279] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu
>[  236.699681] [IGT] gem_exec_reloc: exiting, ret=0
>[  236.752953] Console: switching to colour frame buffer device 200x56
>[  236.849188] Console: switching to colour dummy device 80x25
>[  236.849282] [IGT] gem_exec_reloc: executing
>[  236.874257] [IGT] gem_exec_reloc: starting subtest basic-cpu-read
>[  236.875545] [IGT] gem_exec_reloc: exiting, ret=0
>[  236.919650] Console: switching to colour frame buffer device 200x56
>[  237.025703] Console: switching to colour dummy device 80x25
>[  237.025804] [IGT] gem_exec_reloc: executing
>[  237.036305] [IGT] gem_exec_reloc: starting subtest basic-gtt-read
>[  237.037523] [IGT] gem_exec_reloc: exiting, ret=0
>[  237.086252] Console: switching to colour frame buffer device 200x56
>[  237.175439] Console: switching to colour dummy device 80x25
>[  237.175532] [IGT] gem_exec_reloc: executing
>[  237.195305] [IGT] gem_exec_reloc: starting subtest basic-write-cpu
>[  237.196566] [IGT] gem_exec_reloc: exiting, ret=0
>[  237.253351] Console: switching to colour frame buffer device 200x56
>[  237.371860] Console: switching to colour dummy device 80x25
>[  237.372138] [IGT] gem_exec_reloc: executing
>[  237.385440] [IGT] gem_exec_reloc: starting subtest basic-write-gtt
>[  237.387280] [IGT] gem_exec_reloc: exiting, ret=0
>[  237.436764] Console: switching to colour frame buffer device 200x56
>[  237.535487] Console: switching to colour dummy device 80x25
>[  237.535585] [IGT] gem_exec_reloc: executing
>[  237.548315] [IGT] gem_exec_reloc: starting subtest basic-write-read
>[  237.549389] [IGT] gem_exec_reloc: exiting, ret=0
>[  237.586288] Console: switching to colour frame buffer device 200x56
>[  237.674306] Console: switching to colour dummy device 80x25
>[  237.674400] [IGT] gem_exec_reloc: executing
>[  237.688307] [IGT] gem_exec_reloc: starting subtest basic-cpu-noreloc
>[  237.689444] [IGT] gem_exec_reloc: exiting, ret=0
>[  237.736562] Console: switching to colour frame buffer device 200x56
>[  237.829806] Console: switching to colour dummy device 80x25
>[  237.829901] [IGT] gem_exec_reloc: executing
>[  237.843407] [IGT] gem_exec_reloc: starting subtest basic-gtt-noreloc
>[  237.844564] [IGT] gem_exec_reloc: exiting, ret=0
>[  237.886581] Console: switching to colour frame buffer device 200x56
>[  237.974807] Console: switching to colour dummy device 80x25
>[  237.974916] [IGT] gem_exec_reloc: executing
>[  237.996136] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt-noreloc
>[  237.997289] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.036613] Console: switching to colour frame buffer device 200x56
>[  238.125974] Console: switching to colour dummy device 80x25
>[  238.126071] [IGT] gem_exec_reloc: executing
>[  238.134312] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu-noreloc
>[  238.135443] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.186735] Console: switching to colour frame buffer device 200x56
>[  238.276279] Console: switching to colour dummy device 80x25
>[  238.276375] [IGT] gem_exec_reloc: executing
>[  238.289343] [IGT] gem_exec_reloc: starting subtest basic-cpu-read-noreloc
>[  238.290408] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.336780] Console: switching to colour frame buffer device 200x56
>[  238.430155] Console: switching to colour dummy device 80x25
>[  238.430251] [IGT] gem_exec_reloc: executing
>[  238.441289] [IGT] gem_exec_reloc: starting subtest basic-gtt-read-noreloc
>[  238.442387] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.503691] Console: switching to colour frame buffer device 200x56
>[  238.603151] Console: switching to colour dummy device 80x25
>[  238.603253] [IGT] gem_exec_reloc: executing
>[  238.615366] [IGT] gem_exec_reloc: starting subtest basic-write-cpu-noreloc
>[  238.616412] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.653474] Console: switching to colour frame buffer device 200x56
>[  238.732637] Console: switching to colour dummy device 80x25
>[  238.732790] [IGT] gem_exec_reloc: executing
>[  238.741412] [IGT] gem_exec_reloc: starting subtest basic-write-gtt-noreloc
>[  238.742841] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.787242] Console: switching to colour frame buffer device 200x56
>[  238.888652] Console: switching to colour dummy device 80x25
>[  238.888840] [IGT] gem_exec_reloc: executing
>[  238.912371] [IGT] gem_exec_reloc: starting subtest basic-write-read-noreloc
>[  238.913836] [IGT] gem_exec_reloc: exiting, ret=0
>[  238.953818] Console: switching to colour frame buffer device 200x56
>[  239.052664] Console: switching to colour dummy device 80x25
>[  239.052759] [IGT] gem_exec_reloc: executing
>[  239.062413] [IGT] gem_exec_reloc: starting subtest basic-cpu-active
>[  239.171680] [IGT] gem_exec_reloc: exiting, ret=0
>[  239.220834] Console: switching to colour frame buffer device 200x56
>[  239.319132] Console: switching to colour dummy device 80x25
>[  239.319238] [IGT] gem_exec_reloc: executing
>[  239.333403] [IGT] gem_exec_reloc: starting subtest basic-gtt-active
>[  239.445284] [IGT] gem_exec_reloc: exiting, ret=0
>[  239.504487] Console: switching to colour frame buffer device 200x56
>[  239.609517] Console: switching to colour dummy device 80x25
>[  239.609639] [IGT] gem_exec_reloc: executing
>[  239.628158] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt-active
>[  239.737648] [IGT] gem_exec_reloc: exiting, ret=0
>[  239.787646] Console: switching to colour frame buffer device 200x56
>[  239.882438] Console: switching to colour dummy device 80x25
>[  239.882532] [IGT] gem_exec_reloc: executing
>[  239.892319] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu-active
>[  240.006316] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.054479] Console: switching to colour frame buffer device 200x56
>[  240.141529] Console: switching to colour dummy device 80x25
>[  240.141633] [IGT] gem_exec_reloc: executing
>[  240.162242] [IGT] gem_exec_reloc: starting subtest basic-cpu-read-active
>[  240.274740] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.337942] Console: switching to colour frame buffer device 200x56
>[  240.438625] Console: switching to colour dummy device 80x25
>[  240.438729] [IGT] gem_exec_reloc: executing
>[  240.459237] [IGT] gem_exec_reloc: starting subtest basic-gtt-read-active
>[  240.571938] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.621292] Console: switching to colour frame buffer device 200x56
>[  240.721613] Console: switching to colour dummy device 80x25
>[  240.721717] [IGT] gem_exec_reloc: executing
>[  240.743192] [IGT] gem_exec_reloc: starting subtest basic-write-cpu-active
>[  240.857565] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.921425] Console: switching to colour frame buffer device 200x56
>[  241.024007] Console: switching to colour dummy device 80x25
>[  241.024102] [IGT] gem_exec_reloc: executing
>[  241.049112] [IGT] gem_exec_reloc: starting subtest basic-write-gtt-active
>[  241.160121] [IGT] gem_exec_reloc: exiting, ret=0
>[  241.204753] Console: switching to colour frame buffer device 200x56
>[  241.304044] Console: switching to colour dummy device 80x25
>[  241.304165] [IGT] gem_exec_reloc: executing
>[  241.325219] [IGT] gem_exec_reloc: starting subtest basic-write-read-active
>[  241.437266] [IGT] gem_exec_reloc: exiting, ret=0
>[  241.488343] Console: switching to colour frame buffer device 200x56
>[  241.582365] Console: switching to colour dummy device 80x25
>[  241.582459] [IGT] gem_exec_reloc: executing
>[  241.603301] [IGT] gem_exec_reloc: starting subtest basic-softpin
>[  241.603831] [IGT] gem_exec_reloc: exiting, ret=0
>[  241.637917] Console: switching to colour frame buffer device 200x56
>[  241.744515] Console: switching to colour dummy device 80x25
>[  241.744608] [IGT] gem_exec_store: executing
>[  241.770029] [IGT] gem_exec_store: starting subtest basic-all
>[  241.802379] [IGT] gem_exec_store: exiting, ret=0
>[  241.855256] Console: switching to colour frame buffer device 200x56
>[  241.959969] Console: switching to colour dummy device 80x25
>[  241.960065] [IGT] gem_exec_store: executing
>[  241.972200] [IGT] gem_exec_store: starting subtest basic-blt
>[  242.009668] [IGT] gem_exec_store: exiting, ret=0
>[  242.055334] Console: switching to colour frame buffer device 200x56
>[  242.156982] Console: switching to colour dummy device 80x25
>[  242.157173] [IGT] gem_exec_store: executing
>[  242.171526] [IGT] gem_exec_store: starting subtest basic-bsd
>[  242.216605] [IGT] gem_exec_store: exiting, ret=0
>[  242.271895] Console: switching to colour frame buffer device 200x56
>[  242.374403] Console: switching to colour dummy device 80x25
>[  242.374593] [IGT] gem_exec_store: executing
>[  242.399519] [IGT] gem_exec_store: starting subtest basic-bsd1
>[  242.400932] [IGT] gem_exec_store: exiting, ret=77
>[  242.438696] Console: switching to colour frame buffer device 200x56
>[  242.541036] Console: switching to colour dummy device 80x25
>[  242.541228] [IGT] gem_exec_store: executing
>[  242.555553] [IGT] gem_exec_store: starting subtest basic-bsd2
>[  242.557087] [IGT] gem_exec_store: exiting, ret=77
>[  242.605464] Console: switching to colour frame buffer device 200x56
>[  242.708365] Console: switching to colour dummy device 80x25
>[  242.708554] [IGT] gem_exec_store: executing
>[  242.736501] [IGT] gem_exec_store: starting subtest basic-default
>[  242.786710] [IGT] gem_exec_store: exiting, ret=0
>[  242.838812] Console: switching to colour frame buffer device 200x56
>[  242.938929] Console: switching to colour dummy device 80x25
>[  242.939219] [IGT] gem_exec_store: executing
>[  242.954699] [IGT] gem_exec_store: starting subtest basic-render
>[  243.005177] [IGT] gem_exec_store: exiting, ret=0
>[  243.055507] Console: switching to colour frame buffer device 200x56
>[  243.156542] Console: switching to colour dummy device 80x25
>[  243.156637] [IGT] gem_exec_store: executing
>[  243.169004] [IGT] gem_exec_store: starting subtest basic-vebox
>[  243.194021] [IGT] gem_exec_store: exiting, ret=0
>[  243.238851] Console: switching to colour frame buffer device 200x56
>[  243.359184] Console: switching to colour dummy device 80x25
>[  243.359334] [IGT] gem_exec_suspend: executing
>[  243.370102] [IGT] gem_exec_suspend: starting subtest basic
>[  243.485859] [IGT] gem_exec_suspend: exiting, ret=0
>[  243.521781] Console: switching to colour frame buffer device 200x56
>[  243.603493] Console: switching to colour dummy device 80x25
>[  243.603686] [IGT] gem_exec_suspend: executing
>[  243.617937] [IGT] gem_exec_suspend: starting subtest basic-S3
>[  244.186232] PM: Syncing filesystems ... done.
>[  244.186724] PM: Preparing system for sleep (mem)
>[  244.190427] Freezing user space processes ... 
>[  264.199520] Freezing of tasks failed after 20.009 seconds (1 tasks refusing to freeze, wq_busy=0):
>[  264.199722] systemd-udevd   D    0   319    281 0x00000004
>[  264.199785] Call Trace:
>[  264.199819]  __schedule+0x30e/0xbd0
>[  264.199848]  schedule+0x3b/0x90
>[  264.199867]  schedule_timeout+0x23b/0x490
>[  264.199886]  ? _raw_spin_unlock_irq+0x27/0x50
>[  264.199904]  ? __this_cpu_preempt_check+0x13/0x20
>[  264.199923]  ? trace_hardirqs_on_caller+0xe7/0x200
>[  264.199947]  wait_for_common+0x11a/0x1d0
>[  264.200075]  ? wake_up_q+0x70/0x70
>[  264.200100]  wait_for_completion+0x18/0x20
>[  264.200118]  cpuhp_issue_call+0x9b/0xd0
>[  264.200137]  __cpuhp_setup_state+0xe9/0x170
>[  264.200159]  ? coretemp_remove+0x60/0x60 [coretemp]
>[  264.200174]  ? 0xffffffffa0275000
>[  264.200197]  coretemp_init+0x8b/0x1000 [coretemp]
>[  264.200217]  do_one_initcall+0x3f/0x170
>[  264.200236]  ? rcu_read_lock_sched_held+0x75/0x80
>[  264.200255]  ? kmem_cache_alloc_trace+0x274/0x2e0
>[  264.200269]  ? do_init_module+0x22/0x1fb
>[  264.200291]  do_init_module+0x5a/0x1fb
>[  264.200311]  load_module+0x2091/0x2410
>[  264.200326]  ? symbol_put_addr+0x60/0x60
>[  264.200356]  ? kernel_read_file+0x105/0x190
>[  264.200389]  SyS_finit_module+0xbc/0xf0
>[  264.200424]  entry_SYSCALL_64_fastpath+0x1c/0xb1
>[  264.200437] RIP: 0033:0x7f52a15708e9
>[  264.200449] RSP: 002b:00007ffedc0bbc38 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[  264.200472] RAX: ffffffffffffffda RBX: ffffffff81482393 RCX: 00007f52a15708e9
>[  264.200483] RDX: 0000000000000000 RSI: 00007f52a1a66e2a RDI: 0000000000000010
>[  264.200494] RBP: ffffc9000062ff88 R08: 0000000000000000 R09: 000055de625810a0
>[  264.200505] R10: 0000000000000010 R11: 0000000000000246 R12: 0000000000020000
>[  264.200516] R13: 000055de6253ea80 R14: 0000000000000000 R15: 000055de625810a0
>[  264.200535]  ? __this_cpu_preempt_check+0x13/0x20
>[  264.200611] Restarting tasks ... done.
>[  264.212866] [IGT] gem_exec_suspend: exiting, ret=99
>[  264.263560] Console: switching to colour frame buffer device 200x56
>[  264.368311] Console: switching to colour dummy device 80x25
>[  264.368504] [IGT] gem_exec_suspend: executing
>[  264.393349] [IGT] gem_exec_suspend: starting subtest basic-S4-devices
>[  264.896138] PM: Syncing filesystems ... 
>[  264.897674] done.
>[  264.897677] Freezing user space processes ... 
>[  284.903366] Freezing of tasks failed after 20.005 seconds (1 tasks refusing to freeze, wq_busy=0):
>[  284.903547] systemd-udevd   D    0   319    281 0x00000004
>[  284.903576] Call Trace:
>[  284.903609]  __schedule+0x30e/0xbd0
>[  284.903638]  schedule+0x3b/0x90
>[  284.903657]  schedule_timeout+0x23b/0x490
>[  284.903677]  ? _raw_spin_unlock_irq+0x27/0x50
>[  284.903695]  ? __this_cpu_preempt_check+0x13/0x20
>[  284.903714]  ? trace_hardirqs_on_caller+0xe7/0x200
>[  284.903738]  wait_for_common+0x11a/0x1d0
>[  284.903760]  ? wake_up_q+0x70/0x70
>[  284.903784]  wait_for_completion+0x18/0x20
>[  284.903802]  cpuhp_issue_call+0x9b/0xd0
>[  284.903821]  __cpuhp_setup_state+0xe9/0x170
>[  284.903842]  ? coretemp_remove+0x60/0x60 [coretemp]
>[  284.903858]  ? 0xffffffffa0275000
>[  284.903880]  coretemp_init+0x8b/0x1000 [coretemp]
>[  284.903901]  do_one_initcall+0x3f/0x170
>[  284.903920]  ? rcu_read_lock_sched_held+0x75/0x80
>[  284.903939]  ? kmem_cache_alloc_trace+0x274/0x2e0
>[  284.903953]  ? do_init_module+0x22/0x1fb
>[  284.904038]  do_init_module+0x5a/0x1fb
>[  284.904059]  load_module+0x2091/0x2410
>[  284.904075]  ? symbol_put_addr+0x60/0x60
>[  284.904106]  ? kernel_read_file+0x105/0x190
>[  284.904139]  SyS_finit_module+0xbc/0xf0
>[  284.904174]  entry_SYSCALL_64_fastpath+0x1c/0xb1
>[  284.904186] RIP: 0033:0x7f52a15708e9
>[  284.904198] RSP: 002b:00007ffedc0bbc38 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[  284.904221] RAX: ffffffffffffffda RBX: ffffffff81482393 RCX: 00007f52a15708e9
>[  284.904232] RDX: 0000000000000000 RSI: 00007f52a1a66e2a RDI: 0000000000000010
>[  284.904243] RBP: ffffc9000062ff88 R08: 0000000000000000 R09: 000055de625810a0
>[  284.904254] R10: 0000000000000010 R11: 0000000000000246 R12: 0000000000020000
>[  284.904265] R13: 000055de6253ea80 R14: 0000000000000000 R15: 000055de625810a0
>[  284.904284]  ? __this_cpu_preempt_check+0x13/0x20
>[  284.904355] Restarting tasks ... done.
>[  284.915982] [IGT] gem_exec_suspend: exiting, ret=99
>[  284.971321] Console: switching to colour frame buffer device 200x56
>[  285.044893] Console: switching to colour dummy device 80x25
>[  285.045021] [IGT] gem_flink_basic: executing
>[  285.057251] [IGT] gem_flink_basic: starting subtest bad-flink
>[  285.057311] [IGT] gem_flink_basic: exiting, ret=0
>[  285.087138] Console: switching to colour frame buffer device 200x56
>[  285.192903] Console: switching to colour dummy device 80x25
>[  285.193076] [IGT] gem_flink_basic: executing
>[  285.215321] [IGT] gem_flink_basic: starting subtest bad-open
>[  285.215385] [IGT] gem_flink_basic: exiting, ret=0
>[  285.237191] Console: switching to colour frame buffer device 200x56
>[  285.335882] Console: switching to colour dummy device 80x25
>[  285.336115] [IGT] gem_flink_basic: executing
>[  285.347461] [IGT] gem_flink_basic: starting subtest basic
>[  285.347573] [IGT] gem_flink_basic: exiting, ret=0
>[  285.370539] Console: switching to colour frame buffer device 200x56
>[  285.442192] Console: switching to colour dummy device 80x25
>[  285.442371] [IGT] gem_flink_basic: executing
>[  285.456726] [IGT] gem_flink_basic: starting subtest double-flink
>[  285.456885] [IGT] gem_flink_basic: exiting, ret=0
>[  285.487834] Console: switching to colour frame buffer device 200x56
>[  285.603703] Console: switching to colour dummy device 80x25
>[  285.603854] [IGT] gem_flink_basic: executing
>[  285.617433] [IGT] gem_flink_basic: starting subtest flink-lifetime
>[  285.617695] [IGT] gem_flink_basic: exiting, ret=0
>[  285.654127] Console: switching to colour frame buffer device 200x56
>[  285.729327] Console: switching to colour dummy device 80x25
>[  285.729424] [IGT] gem_linear_blits: executing
>[  285.750295] [IGT] gem_linear_blits: starting subtest basic
>[  285.758831] [IGT] gem_linear_blits: exiting, ret=0
>[  285.787357] Console: switching to colour frame buffer device 200x56
>[  285.866665] Console: switching to colour dummy device 80x25
>[  285.866857] [IGT] gem_mmap: executing
>[  285.878500] [IGT] gem_mmap: starting subtest basic
>[  285.878822] [IGT] gem_mmap: exiting, ret=0
>[  285.921063] Console: switching to colour frame buffer device 200x56
>[  285.991545] Console: switching to colour dummy device 80x25
>[  285.991635] [IGT] gem_mmap: executing
>[  286.001359] [IGT] gem_mmap: starting subtest basic-small-bo
>[  286.159287] [IGT] gem_mmap: exiting, ret=0
>[  286.187475] Console: switching to colour frame buffer device 200x56
>[  286.267397] Console: switching to colour dummy device 80x25
>[  286.267517] [IGT] gem_mmap_gtt: executing
>[  286.279484] [IGT] gem_mmap_gtt: starting subtest basic
>[  286.279715] [IGT] gem_mmap_gtt: exiting, ret=0
>[  286.304355] Console: switching to colour frame buffer device 200x56
>[  286.399776] Console: switching to colour dummy device 80x25
>[  286.399951] [IGT] gem_mmap_gtt: executing
>[  286.411555] [IGT] gem_mmap_gtt: starting subtest basic-copy
>[  286.582028] [IGT] gem_mmap_gtt: exiting, ret=0
>[  286.620911] Console: switching to colour frame buffer device 200x56
>[  286.675915] Console: switching to colour dummy device 80x25
>[  286.676090] [IGT] gem_mmap_gtt: executing
>[  286.690509] [IGT] gem_mmap_gtt: starting subtest basic-read
>[  286.711114] [IGT] gem_mmap_gtt: exiting, ret=0
>[  286.754392] Console: switching to colour frame buffer device 200x56
>[  286.822247] Console: switching to colour dummy device 80x25
>[  286.822344] [IGT] gem_mmap_gtt: executing
>[  286.833461] [IGT] gem_mmap_gtt: starting subtest basic-read-no-prefault
>[  286.833557] Setting dangerous option prefault_disable - tainting kernel
>[  286.852096] Setting dangerous option prefault_disable - tainting kernel
>[  286.852199] [IGT] gem_mmap_gtt: exiting, ret=0
>[  286.852270] Setting dangerous option prefault_disable - tainting kernel
>[  286.904484] Console: switching to colour frame buffer device 200x56
>[  286.984609] Console: switching to colour dummy device 80x25
>[  286.984714] [IGT] gem_mmap_gtt: executing
>[  286.996475] [IGT] gem_mmap_gtt: starting subtest basic-read-write
>[  287.004137] [IGT] gem_mmap_gtt: exiting, ret=0
>[  287.054594] Console: switching to colour frame buffer device 200x56
>[  287.172894] Console: switching to colour dummy device 80x25
>[  287.173109] [IGT] gem_mmap_gtt: executing
>[  287.185385] [IGT] gem_mmap_gtt: starting subtest basic-read-write-distinct
>[  287.194715] [IGT] gem_mmap_gtt: exiting, ret=0
>[  287.237927] Console: switching to colour frame buffer device 200x56
>[  287.306352] Console: switching to colour dummy device 80x25
>[  287.306495] [IGT] gem_mmap_gtt: executing
>[  287.320584] [IGT] gem_mmap_gtt: starting subtest basic-short
>[  287.340852] [IGT] gem_mmap_gtt: exiting, ret=0
>[  287.404631] Console: switching to colour frame buffer device 200x56
>[  287.458581] Console: switching to colour dummy device 80x25
>[  287.458676] [IGT] gem_mmap_gtt: executing
>[  287.480312] [IGT] gem_mmap_gtt: starting subtest basic-small-bo
>[  287.550460] [IGT] gem_mmap_gtt: exiting, ret=0
>[  287.621368] Console: switching to colour frame buffer device 200x56
>[  287.714787] Console: switching to colour dummy device 80x25
>[  287.714946] [IGT] gem_mmap_gtt: executing
>[  287.729495] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledX
>[  287.802214] [IGT] gem_mmap_gtt: exiting, ret=0
>[  287.871449] Console: switching to colour frame buffer device 200x56
>[  287.950477] Console: switching to colour dummy device 80x25
>[  287.950574] [IGT] gem_mmap_gtt: executing
>[  287.961375] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledY
>[  288.025648] [IGT] gem_mmap_gtt: exiting, ret=0
>[  288.104892] Console: switching to colour frame buffer device 200x56
>[  288.220882] Console: switching to colour dummy device 80x25
>[  288.221095] [IGT] gem_mmap_gtt: executing
>[  288.231388] [IGT] gem_mmap_gtt: starting subtest basic-small-copy
>[  288.460226] [IGT] gem_mmap_gtt: exiting, ret=0
>[  288.488190] Console: switching to colour frame buffer device 200x56
>[  288.554441] Console: switching to colour dummy device 80x25
>[  288.554538] [IGT] gem_mmap_gtt: executing
>[  288.565309] [IGT] gem_mmap_gtt: starting subtest basic-small-copy-XY
>[  288.814309] [IGT] gem_mmap_gtt: exiting, ret=0
>[  288.855023] Console: switching to colour frame buffer device 200x56
>[  288.921427] Console: switching to colour dummy device 80x25
>[  288.921526] [IGT] gem_mmap_gtt: executing
>[  288.932476] [IGT] gem_mmap_gtt: starting subtest basic-wc
>[  289.562013] [IGT] gem_mmap_gtt: exiting, ret=0
>[  289.622211] Console: switching to colour frame buffer device 200x56
>[  289.703396] Console: switching to colour dummy device 80x25
>[  289.703503] [IGT] gem_mmap_gtt: executing
>[  289.717517] [IGT] gem_mmap_gtt: starting subtest basic-write
>[  289.799275] [IGT] gem_mmap_gtt: exiting, ret=0
>[  289.855520] Console: switching to colour frame buffer device 200x56
>[  289.926467] Console: switching to colour dummy device 80x25
>[  289.926596] [IGT] gem_mmap_gtt: executing
>[  289.938419] [IGT] gem_mmap_gtt: starting subtest basic-write-cpu-read-gtt
>[  290.081600] [IGT] gem_mmap_gtt: exiting, ret=0
>[  290.139010] Console: switching to colour frame buffer device 200x56
>[  290.211396] Console: switching to colour dummy device 80x25
>[  290.211506] [IGT] gem_mmap_gtt: executing
>[  290.232293] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt
>[  290.315585] [IGT] gem_mmap_gtt: exiting, ret=0
>[  290.355704] Console: switching to colour frame buffer device 200x56
>[  290.424435] Console: switching to colour dummy device 80x25
>[  290.424586] [IGT] gem_mmap_gtt: executing
>[  290.438632] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt-no-prefault
>[  290.438769] Setting dangerous option prefault_disable - tainting kernel
>[  290.531772] Setting dangerous option prefault_disable - tainting kernel
>[  290.531862] [IGT] gem_mmap_gtt: exiting, ret=0
>[  290.531922] Setting dangerous option prefault_disable - tainting kernel
>[  290.572414] Console: switching to colour frame buffer device 200x56
>[  290.633459] Console: switching to colour dummy device 80x25
>[  290.633575] [IGT] gem_mmap_gtt: executing
>[  290.653155] [IGT] gem_mmap_gtt: starting subtest basic-write-no-prefault
>[  290.653201] Setting dangerous option prefault_disable - tainting kernel
>[  290.734885] Setting dangerous option prefault_disable - tainting kernel
>[  290.735005] [IGT] gem_mmap_gtt: exiting, ret=0
>[  290.735086] Setting dangerous option prefault_disable - tainting kernel
>[  290.772494] Console: switching to colour frame buffer device 200x56
>[  290.830059] Console: switching to colour dummy device 80x25
>[  290.830161] [IGT] gem_mmap_gtt: executing
>[  290.851212] [IGT] gem_mmap_gtt: starting subtest basic-write-read
>[  290.858856] [IGT] gem_mmap_gtt: exiting, ret=0
>[  290.905948] Console: switching to colour frame buffer device 200x56
>[  291.008498] Console: switching to colour dummy device 80x25
>[  291.008614] [IGT] gem_mmap_gtt: executing
>[  291.020436] [IGT] gem_mmap_gtt: starting subtest basic-write-read-distinct
>[  291.028235] [IGT] gem_mmap_gtt: exiting, ret=0
>[  291.072699] Console: switching to colour frame buffer device 200x56
>[  291.152325] Console: switching to colour dummy device 80x25
>[  291.152474] [IGT] gem_pread: executing
>[  291.174274] [IGT] gem_pread: starting subtest basic
>[  291.946318] [IGT] gem_pread: exiting, ret=0
>[  291.989628] Console: switching to colour frame buffer device 200x56
>[  292.046666] Console: switching to colour dummy device 80x25
>[  292.046760] [IGT] gem_pwrite: executing
>[  292.068342] [IGT] gem_pwrite: starting subtest basic
>[  292.996279] [IGT] gem_pwrite: exiting, ret=0
>[  293.040051] Console: switching to colour frame buffer device 200x56
>[  293.098551] Console: switching to colour dummy device 80x25
>[  293.098676] [IGT] gem_render_linear_blits: executing
>[  293.120298] [IGT] gem_render_linear_blits: starting subtest basic
>[  293.132764] [IGT] gem_render_linear_blits: exiting, ret=0
>[  293.173777] Console: switching to colour frame buffer device 200x56
>[  293.245728] Console: switching to colour dummy device 80x25
>[  293.245822] [IGT] gem_render_tiled_blits: executing
>[  293.257366] [IGT] gem_render_tiled_blits: starting subtest basic
>[  293.266059] [IGT] gem_render_tiled_blits: exiting, ret=0
>[  293.290100] Console: switching to colour frame buffer device 200x56
>[  293.341488] Console: switching to colour dummy device 80x25
>[  293.341591] [IGT] gem_ringfill: executing
>[  293.362238] [IGT] gem_ringfill: starting subtest basic-default
>[  293.713178] [IGT] gem_ringfill: exiting, ret=0
>[  293.757036] Console: switching to colour frame buffer device 200x56
>[  293.828201] Console: switching to colour dummy device 80x25
>[  293.828311] [IGT] gem_ringfill: executing
>[  293.846192] [IGT] gem_ringfill: starting subtest basic-default-interruptible
>[  297.077183] [IGT] gem_ringfill: exiting, ret=0
>[  297.125223] Console: switching to colour frame buffer device 200x56
>[  297.200792] Console: switching to colour dummy device 80x25
>[  297.200888] [IGT] gem_ringfill: executing
>[  297.219095] [IGT] gem_ringfill: starting subtest basic-default-forked
>[  298.537166] [IGT] gem_ringfill: exiting, ret=0
>[  298.575784] Console: switching to colour frame buffer device 200x56
>[  298.680946] Console: switching to colour dummy device 80x25
>[  298.681278] [IGT] gem_ringfill: executing
>[  298.703445] [IGT] gem_ringfill: starting subtest basic-default-fd
>[  301.059553] [IGT] gem_ringfill: exiting, ret=0
>[  301.110100] Console: switching to colour frame buffer device 200x56
>[  301.211512] Console: switching to colour dummy device 80x25
>[  301.211606] [IGT] gem_ringfill: executing
>[  301.225376] [IGT] gem_ringfill: starting subtest basic-default-hang
>[  305.764754] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  310.763451] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_ringfill [7780], reason: Hang on render ring, action: reset
>[  310.763699] drm/i915: Resetting chip after gpu hang
>[  310.763741] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  310.764594] [drm:i915_gem_reset [i915]] context gem_ringfill[7780]/0 marked guilty (score 10) banned? no
>[  310.764609] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x2d0746
>[  310.764678] [drm] RC6 on
>[  310.780176] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  310.780196] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x2d07c2, 0x0]
>[  310.780223] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  310.780270] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  310.780316] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  310.780362] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  310.780395] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  310.780400] [drm] GuC firmware load skipped
>[  311.125120] [IGT] gem_ringfill: exiting, ret=0
>[  311.163721] Console: switching to colour frame buffer device 200x56
>[  311.236310] Console: switching to colour dummy device 80x25
>[  311.236406] [IGT] gem_sync: executing
>[  311.248162] [IGT] gem_sync: starting subtest basic-all
>[  316.340801] [IGT] gem_sync: exiting, ret=0
>[  316.381801] Console: switching to colour frame buffer device 200x56
>[  316.451040] Console: switching to colour dummy device 80x25
>[  316.451184] [IGT] gem_sync: executing
>[  316.464727] [IGT] gem_sync: starting subtest basic-each
>[  321.540826] [IGT] gem_sync: exiting, ret=0
>[  321.583717] Console: switching to colour frame buffer device 200x56
>[  321.669460] Console: switching to colour dummy device 80x25
>[  321.669700] [IGT] gem_sync: executing
>[  321.684866] [IGT] gem_sync: starting subtest basic-many-each
>[  327.216151] [IGT] gem_sync: exiting, ret=0
>[  327.252550] Console: switching to colour frame buffer device 200x56
>[  327.335281] Console: switching to colour dummy device 80x25
>[  327.335506] [IGT] gem_sync: executing
>[  327.363286] [IGT] gem_sync: starting subtest basic-store-all
>[  332.655878] [IGT] gem_sync: exiting, ret=0
>[  332.704832] Console: switching to colour frame buffer device 200x56
>[  332.774613] Console: switching to colour dummy device 80x25
>[  332.774708] [IGT] gem_sync: executing
>[  332.785202] [IGT] gem_sync: starting subtest basic-store-each
>[  338.013931] [IGT] gem_sync: exiting, ret=0
>[  338.056572] Console: switching to colour frame buffer device 200x56
>[  338.161271] Console: switching to colour dummy device 80x25
>[  338.161372] [IGT] gem_tiled_blits: executing
>[  338.175530] [IGT] gem_tiled_blits: starting subtest basic
>[  338.186532] [IGT] gem_tiled_blits: exiting, ret=0
>[  338.240078] Console: switching to colour frame buffer device 200x56
>[  338.351680] Console: switching to colour dummy device 80x25
>[  338.351774] [IGT] gem_tiled_fence_blits: executing
>[  338.361362] [IGT] gem_tiled_fence_blits: starting subtest basic
>[  338.367209] [IGT] gem_tiled_fence_blits: exiting, ret=0
>[  338.406594] Console: switching to colour frame buffer device 200x56
>[  338.494679] Console: switching to colour dummy device 80x25
>[  338.494772] [IGT] gem_tiled_pread_basic: executing
>[  338.606691] [IGT] gem_tiled_pread_basic: exiting, ret=0
>[  338.656699] Console: switching to colour frame buffer device 200x56
>[  338.732616] Console: switching to colour dummy device 80x25
>[  338.732772] [IGT] gem_wait: executing
>[  338.746792] [IGT] gem_wait: starting subtest basic-busy-all
>[  339.270130] [IGT] gem_wait: exiting, ret=0
>[  339.323561] Console: switching to colour frame buffer device 200x56
>[  339.385625] Console: switching to colour dummy device 80x25
>[  339.385718] [IGT] gem_wait: executing
>[  339.399607] [IGT] gem_wait: starting subtest basic-wait-all
>[  340.440398] [IGT] gem_wait: exiting, ret=0
>[  340.491226] Console: switching to colour frame buffer device 200x56
>[  340.595621] Console: switching to colour dummy device 80x25
>[  340.595715] [IGT] gem_wait: executing
>[  340.607653] [IGT] gem_wait: starting subtest basic-await-all
>[  340.639149] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  340.640074] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  341.670863] [IGT] gem_wait: exiting, ret=0
>[  341.725055] Console: switching to colour frame buffer device 200x56
>[  341.833363] Console: switching to colour dummy device 80x25
>[  341.833510] [IGT] gem_workarounds: executing
>[  341.857947] [IGT] gem_workarounds: starting subtest basic-read
>[  341.871262] [IGT] gem_workarounds: exiting, ret=0
>[  341.908404] Console: switching to colour frame buffer device 200x56
>[  342.038203] Console: switching to colour dummy device 80x25
>[  342.038297] [IGT] kms_addfb_basic: executing
>[  342.059234] [drm:drm_mode_addfb2] [FB:61]
>[  342.059463] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
>[  342.059492] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  342.065211] [drm:drm_mode_addfb2] [FB:61]
>[  342.065305] [IGT] kms_addfb_basic: exiting, ret=0
>[  342.125167] Console: switching to colour frame buffer device 200x56
>[  342.233794] Console: switching to colour dummy device 80x25
>[  342.233889] [IGT] kms_addfb_basic: executing
>[  342.243341] [drm:drm_mode_addfb2] [FB:64]
>[  342.243480] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling
>[  342.243500] [drm:drm_mode_addfb2] [FB:64]
>[  342.247583] [drm:drm_mode_addfb2] [FB:64]
>[  342.247659] [IGT] kms_addfb_basic: exiting, ret=0
>[  342.291446] Console: switching to colour frame buffer device 200x56
>[  342.398415] Console: switching to colour dummy device 80x25
>[  342.398509] [IGT] kms_addfb_basic: executing
>[  342.406356] [drm:drm_mode_addfb2] [FB:61]
>[  342.406481] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
>[  342.406501] [drm:drm_internal_framebuffer_create] bad fb modifier 72057594037927937 for plane 0
>[  342.410748] [drm:drm_mode_addfb2] [FB:61]
>[  342.410818] [IGT] kms_addfb_basic: exiting, ret=0
>[  342.458165] Console: switching to colour frame buffer device 200x56
>[  342.563755] Console: switching to colour dummy device 80x25
>[  342.563855] [IGT] kms_addfb_basic: executing
>[  342.573393] [drm:drm_mode_addfb2] [FB:64]
>[  342.573533] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled
>[  342.573553] [drm:drm_mode_addfb2] [FB:64]
>[  342.577618] [drm:drm_mode_addfb2] [FB:64]
>[  342.577687] [IGT] kms_addfb_basic: exiting, ret=0
>[  342.641933] Console: switching to colour frame buffer device 200x56
>[  342.748872] Console: switching to colour dummy device 80x25
>[  342.749119] [IGT] kms_addfb_basic: executing
>[  342.761376] [drm:drm_mode_addfb2] [FB:61]
>[  342.761517] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled-mismatch
>[  342.761536] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  342.765771] [drm:drm_mode_addfb2] [FB:61]
>[  342.765840] [IGT] kms_addfb_basic: exiting, ret=0
>[  342.808297] Console: switching to colour frame buffer device 200x56
>[  342.897291] Console: switching to colour dummy device 80x25
>[  342.897385] [IGT] kms_addfb_basic: executing
>[  342.917266] [drm:drm_mode_addfb2] [FB:64]
>[  342.917474] [IGT] kms_addfb_basic: starting subtest addfb25-Yf-tiled
>[  342.917499] [drm:drm_mode_addfb2] [FB:64]
>[  342.921706] [drm:drm_mode_addfb2] [FB:64]
>[  342.921777] [IGT] kms_addfb_basic: exiting, ret=0
>[  342.975232] Console: switching to colour frame buffer device 200x56
>[  343.081632] Console: switching to colour dummy device 80x25
>[  343.081727] [IGT] kms_addfb_basic: executing
>[  343.092400] [drm:drm_mode_addfb2] [FB:61]
>[  343.092579] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled
>[  343.092599] [drm:drm_mode_addfb2] [FB:61]
>[  343.096617] [drm:drm_mode_addfb2] [FB:61]
>[  343.096704] [IGT] kms_addfb_basic: exiting, ret=0
>[  343.141839] Console: switching to colour frame buffer device 200x56
>[  343.247150] Console: switching to colour dummy device 80x25
>[  343.247247] [IGT] kms_addfb_basic: executing
>[  343.259412] [drm:drm_mode_addfb2] [FB:64]
>[  343.259587] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled-small
>[  343.259611] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  343.263775] [drm:drm_mode_addfb2] [FB:64]
>[  343.263846] [IGT] kms_addfb_basic: exiting, ret=0
>[  343.308500] Console: switching to colour frame buffer device 200x56
>[  343.398550] Console: switching to colour dummy device 80x25
>[  343.398646] [IGT] kms_addfb_basic: executing
>[  343.407353] [drm:drm_mode_addfb2] [FB:61]
>[  343.407417] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
>[  343.407432] [drm:drm_internal_framebuffer_create] bad pitch 0 for plane 0
>[  343.411572] [drm:drm_mode_addfb2] [FB:61]
>[  343.411640] [IGT] kms_addfb_basic: exiting, ret=0
>[  343.458648] Console: switching to colour frame buffer device 200x56
>[  343.578552] Console: switching to colour dummy device 80x25
>[  343.578649] [IGT] kms_addfb_basic: executing
>[  343.596254] [drm:drm_mode_addfb2] [FB:64]
>[  343.596340] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
>[  343.596368] [drm:drm_internal_framebuffer_create] bad pitch 1024 for plane 0
>[  343.600608] [drm:drm_mode_addfb2] [FB:64]
>[  343.600679] [IGT] kms_addfb_basic: exiting, ret=0
>[  343.642093] Console: switching to colour frame buffer device 200x56
>[  343.738215] Console: switching to colour dummy device 80x25
>[  343.738309] [IGT] kms_addfb_basic: executing
>[  343.750419] [drm:drm_mode_addfb2] [FB:61]
>[  343.750501] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
>[  343.750521] [drm:drm_internal_framebuffer_create] bad pitch 128 for plane 0
>[  343.754957] [drm:drm_mode_addfb2] [FB:61]
>[  343.755039] [IGT] kms_addfb_basic: exiting, ret=0
>[  343.808721] Console: switching to colour frame buffer device 200x56
>[  343.905670] Console: switching to colour dummy device 80x25
>[  343.905775] [IGT] kms_addfb_basic: executing
>[  343.916427] [drm:drm_mode_addfb2] [FB:64]
>[  343.916498] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
>[  343.916514] [drm:drm_internal_framebuffer_create] bad pitch 256 for plane 0
>[  343.920908] [drm:drm_mode_addfb2] [FB:64]
>[  343.921029] [IGT] kms_addfb_basic: exiting, ret=0
>[  343.975538] Console: switching to colour frame buffer device 200x56
>[  344.085221] Console: switching to colour dummy device 80x25
>[  344.085347] [IGT] kms_addfb_basic: executing
>[  344.097489] [drm:drm_mode_addfb2] [FB:61]
>[  344.097577] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
>[  344.097597] [drm:drm_internal_framebuffer_create] bad pitch 32 for plane 0
>[  344.103051] [drm:drm_mode_addfb2] [FB:61]
>[  344.103138] [IGT] kms_addfb_basic: exiting, ret=0
>[  344.159253] Console: switching to colour frame buffer device 200x56
>[  344.272485] Console: switching to colour dummy device 80x25
>[  344.272613] [IGT] kms_addfb_basic: executing
>[  344.285471] [drm:drm_mode_addfb2] [FB:64]
>[  344.285561] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
>[  344.285582] [drm:drm_internal_framebuffer_create] bad pitch 63 for plane 0
>[  344.290348] [drm:drm_mode_addfb2] [FB:64]
>[  344.290424] [IGT] kms_addfb_basic: exiting, ret=0
>[  344.342343] Console: switching to colour frame buffer device 200x56
>[  344.453542] Console: switching to colour dummy device 80x25
>[  344.453666] [IGT] kms_addfb_basic: executing
>[  344.464440] [drm:drm_mode_addfb2] [FB:61]
>[  344.464515] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
>[  344.464538] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  344.469155] [drm:drm_mode_addfb2] [FB:61]
>[  344.469247] [IGT] kms_addfb_basic: exiting, ret=0
>[  344.508957] Console: switching to colour frame buffer device 200x56
>[  344.612830] Console: switching to colour dummy device 80x25
>[  344.612929] [IGT] kms_addfb_basic: executing
>[  344.624447] [drm:drm_mode_addfb2] [FB:64]
>[  344.624514] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
>[  344.624529] [drm:drm_internal_framebuffer_create] bad pitch 999 for plane 0
>[  344.628654] [drm:drm_mode_addfb2] [FB:64]
>[  344.628722] [IGT] kms_addfb_basic: exiting, ret=0
>[  344.675722] Console: switching to colour frame buffer device 200x56
>[  344.770945] Console: switching to colour dummy device 80x25
>[  344.771109] [IGT] kms_addfb_basic: executing
>[  344.796293] [drm:drm_mode_addfb2] [FB:61]
>[  344.796373] [IGT] kms_addfb_basic: starting subtest basic
>[  344.796397] [drm:drm_mode_addfb2] [FB:61]
>[  344.800673] [drm:drm_mode_addfb2] [FB:61]
>[  344.800743] [IGT] kms_addfb_basic: exiting, ret=0
>[  344.842364] Console: switching to colour frame buffer device 200x56
>[  344.944569] Console: switching to colour dummy device 80x25
>[  344.944667] [IGT] kms_addfb_basic: executing
>[  344.954597] [drm:drm_mode_addfb2] [FB:64]
>[  344.958763] [IGT] kms_addfb_basic: starting subtest basic-X-tiled
>[  344.958811] [drm:drm_mode_addfb2] [FB:64]
>[  344.958889] [drm:drm_mode_addfb2] [FB:64]
>[  344.958986] [IGT] kms_addfb_basic: exiting, ret=0
>[  345.009240] Console: switching to colour frame buffer device 200x56
>[  345.113258] Console: switching to colour dummy device 80x25
>[  345.113352] [IGT] kms_addfb_basic: executing
>[  345.122345] [drm:drm_mode_addfb2] [FB:61]
>[  345.126479] [IGT] kms_addfb_basic: starting subtest basic-Y-tiled
>[  345.126511] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  345.126578] [drm:drm_mode_addfb2] [FB:61]
>[  345.126634] [IGT] kms_addfb_basic: exiting, ret=0
>[  345.175867] Console: switching to colour frame buffer device 200x56
>[  345.269094] Console: switching to colour dummy device 80x25
>[  345.269210] [IGT] kms_addfb_basic: executing
>[  345.280543] [drm:drm_mode_addfb2] [FB:64]
>[  345.280683] [IGT] kms_addfb_basic: starting subtest bo-too-small
>[  345.280713] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  345.285759] [drm:drm_mode_addfb2] [FB:64]
>[  345.285854] [IGT] kms_addfb_basic: exiting, ret=0
>[  345.325955] Console: switching to colour frame buffer device 200x56
>[  345.428325] Console: switching to colour dummy device 80x25
>[  345.428421] [IGT] kms_addfb_basic: executing
>[  345.439335] [drm:drm_mode_addfb2] [FB:61]
>[  345.439439] [IGT] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
>[  345.439468] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  345.443593] [drm:drm_mode_addfb2] [FB:61]
>[  345.443661] [IGT] kms_addfb_basic: exiting, ret=0
>[  345.492729] Console: switching to colour frame buffer device 200x56
>[  345.598621] Console: switching to colour dummy device 80x25
>[  345.598728] [IGT] kms_addfb_basic: executing
>[  345.609351] [drm:drm_mode_addfb2] [FB:64]
>[  345.609394] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
>[  345.609425] [drm:drm_mode_addfb2] [FB:64]
>[  345.614035] [drm:drm_mode_addfb2] [FB:64]
>[  345.614109] [IGT] kms_addfb_basic: exiting, ret=0
>[  345.659432] Console: switching to colour frame buffer device 200x56
>[  345.768840] Console: switching to colour dummy device 80x25
>[  345.768995] [IGT] kms_addfb_basic: executing
>[  345.782414] [drm:drm_mode_addfb2] [FB:61]
>[  345.786513] [IGT] kms_addfb_basic: starting subtest framebuffer-vs-set-tiling
>[  345.786554] [drm:drm_mode_addfb2] [FB:61]
>[  345.786623] [drm:drm_mode_addfb2] [FB:61]
>[  345.786678] [IGT] kms_addfb_basic: exiting, ret=0
>[  345.842915] Console: switching to colour frame buffer device 200x56
>[  345.933701] Console: switching to colour dummy device 80x25
>[  345.933799] [IGT] kms_addfb_basic: executing
>[  345.954283] [drm:drm_mode_addfb2] [FB:64]
>[  345.958575] [drm:drm_mode_addfb2] [FB:64]
>[  345.958619] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
>[  345.958790] [IGT] kms_addfb_basic: exiting, ret=0
>[  346.009467] Console: switching to colour frame buffer device 200x56
>[  346.109764] Console: switching to colour dummy device 80x25
>[  346.109858] [IGT] kms_addfb_basic: executing
>[  346.119407] [drm:drm_mode_addfb2] [FB:61]
>[  346.123503] [drm:drm_mode_addfb2] [FB:61]
>[  346.123545] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
>[  346.123656] [IGT] kms_addfb_basic: exiting, ret=0
>[  346.176332] Console: switching to colour frame buffer device 200x56
>[  346.289323] Console: switching to colour dummy device 80x25
>[  346.289450] [IGT] kms_addfb_basic: executing
>[  346.303483] [drm:drm_mode_addfb2] [FB:64]
>[  346.308240] [drm:drm_mode_addfb2] [FB:64]
>[  346.308286] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
>[  346.308394] [IGT] kms_addfb_basic: exiting, ret=0
>[  346.359753] Console: switching to colour frame buffer device 200x56
>[  346.465249] Console: switching to colour dummy device 80x25
>[  346.465344] [IGT] kms_addfb_basic: executing
>[  346.475343] [drm:drm_mode_addfb2] [FB:61]
>[  346.479482] [drm:drm_mode_addfb2] [FB:61]
>[  346.479525] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
>[  346.479635] [IGT] kms_addfb_basic: exiting, ret=0
>[  346.526383] Console: switching to colour frame buffer device 200x56
>[  346.619227] Console: switching to colour dummy device 80x25
>[  346.619322] [IGT] kms_addfb_basic: executing
>[  346.631287] [drm:drm_mode_addfb2] [FB:64]
>[  346.631356] [IGT] kms_addfb_basic: starting subtest no-handle
>[  346.631372] [drm:drm_internal_framebuffer_create] no buffer object handle for plane 0
>[  346.635465] [drm:drm_mode_addfb2] [FB:64]
>[  346.635533] [IGT] kms_addfb_basic: exiting, ret=0
>[  346.676470] Console: switching to colour frame buffer device 200x56
>[  346.799591] Console: switching to colour dummy device 80x25
>[  346.800604] [IGT] kms_addfb_basic: executing
>[  346.828949] [drm:drm_mode_addfb2] [FB:61]
>[  346.830063] [IGT] kms_addfb_basic: starting subtest size-max
>[  346.830169] [drm:drm_mode_addfb2] [FB:61]
>[  346.830221] [drm:drm_mode_addfb2] [FB:61]
>[  346.830268] [drm:drm_mode_addfb2] [FB:61]
>[  346.850146] [drm:drm_mode_addfb2] [FB:61]
>[  346.850315] [IGT] kms_addfb_basic: exiting, ret=0
>[  346.909823] Console: switching to colour frame buffer device 200x56
>[  347.007186] Console: switching to colour dummy device 80x25
>[  347.007283] [IGT] kms_addfb_basic: executing
>[  347.028290] [drm:drm_mode_addfb2] [FB:64]
>[  347.028407] [IGT] kms_addfb_basic: starting subtest small-bo
>[  347.028431] [drm:drm_mode_addfb2] [FB:64]
>[  347.032658] [drm:drm_mode_addfb2] [FB:64]
>[  347.032727] [IGT] kms_addfb_basic: exiting, ret=0
>[  347.076551] Console: switching to colour frame buffer device 200x56
>[  347.182566] Console: switching to colour dummy device 80x25
>[  347.182677] [IGT] kms_addfb_basic: executing
>[  347.194455] [drm:drm_mode_addfb2] [FB:61]
>[  347.198616] [IGT] kms_addfb_basic: starting subtest tile-pitch-mismatch
>[  347.198647] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  347.198706] [drm:drm_mode_addfb2] [FB:61]
>[  347.198760] [IGT] kms_addfb_basic: exiting, ret=0
>[  347.243427] Console: switching to colour frame buffer device 200x56
>[  347.349779] Console: switching to colour dummy device 80x25
>[  347.349878] [IGT] kms_addfb_basic: executing
>[  347.363285] [drm:drm_mode_addfb2] [FB:64]
>[  347.363387] [IGT] kms_addfb_basic: starting subtest too-high
>[  347.363408] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  347.363416] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  347.363423] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  347.367564] [drm:drm_mode_addfb2] [FB:64]
>[  347.367633] [IGT] kms_addfb_basic: exiting, ret=0
>[  347.410040] Console: switching to colour frame buffer device 200x56
>[  347.508417] Console: switching to colour dummy device 80x25
>[  347.508520] [IGT] kms_addfb_basic: executing
>[  347.520473] [drm:drm_mode_addfb2] [FB:61]
>[  347.520600] [IGT] kms_addfb_basic: starting subtest too-wide
>[  347.520619] [drm:drm_internal_framebuffer_create] bad pitch 4096 for plane 0
>[  347.520623] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  347.520627] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  347.525148] [drm:drm_mode_addfb2] [FB:61]
>[  347.525221] [IGT] kms_addfb_basic: exiting, ret=0
>[  347.576770] Console: switching to colour frame buffer device 200x56
>[  347.695226] Console: switching to colour dummy device 80x25
>[  347.695332] [IGT] kms_addfb_basic: executing
>[  347.717322] [drm:drm_mode_addfb2] [FB:64]
>[  347.717369] [IGT] kms_addfb_basic: starting subtest unused-handle
>[  347.717392] [drm:drm_internal_framebuffer_create] buffer object handle for unused plane 1
>[  347.721662] [drm:drm_mode_addfb2] [FB:64]
>[  347.721733] [IGT] kms_addfb_basic: exiting, ret=0
>[  347.777425] Console: switching to colour frame buffer device 200x56
>[  347.890008] Console: switching to colour dummy device 80x25
>[  347.890138] [IGT] kms_addfb_basic: executing
>[  347.901420] [drm:drm_mode_addfb2] [FB:61]
>[  347.901459] [IGT] kms_addfb_basic: starting subtest unused-modifier
>[  347.901480] [drm:drm_internal_framebuffer_create] non-zero modifier for unused plane 1
>[  347.906216] [drm:drm_mode_addfb2] [FB:61]
>[  347.906291] [IGT] kms_addfb_basic: exiting, ret=0
>[  347.960284] Console: switching to colour frame buffer device 200x56
>[  348.073580] Console: switching to colour dummy device 80x25
>[  348.073703] [IGT] kms_addfb_basic: executing
>[  348.086451] [drm:drm_mode_addfb2] [FB:64]
>[  348.086489] [IGT] kms_addfb_basic: starting subtest unused-offsets
>[  348.086510] [drm:drm_internal_framebuffer_create] non-zero offset for unused plane 1
>[  348.091156] [drm:drm_mode_addfb2] [FB:64]
>[  348.091243] [IGT] kms_addfb_basic: exiting, ret=0
>[  348.143741] Console: switching to colour frame buffer device 200x56
>[  348.250436] Console: switching to colour dummy device 80x25
>[  348.250532] [IGT] kms_addfb_basic: executing
>[  348.270163] [drm:drm_mode_addfb2] [FB:61]
>[  348.270198] [IGT] kms_addfb_basic: starting subtest unused-pitches
>[  348.270216] [drm:drm_internal_framebuffer_create] non-zero pitch for unused plane 1
>[  348.274307] [drm:drm_mode_addfb2] [FB:61]
>[  348.274377] [IGT] kms_addfb_basic: exiting, ret=0
>[  348.310290] Console: switching to colour frame buffer device 200x56
>[  348.412926] Console: switching to colour dummy device 80x25
>[  348.413099] [IGT] kms_busy: executing
>[  348.457858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  348.457896] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  348.457920] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  348.458347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  348.458376] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  348.460626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  348.460662] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  348.462904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  348.462911] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  348.465159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  348.465189] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  348.467435] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  348.467443] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  348.467449] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  348.467736] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  348.467761] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  348.468627] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  348.468654] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  348.469381] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  348.470202] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  348.471717] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  348.471736] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  348.471754] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  348.471771] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  348.472570] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  348.473276] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  348.474196] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  348.474200] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  348.474202] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  348.474204] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  348.474269] [drm:drm_mode_debug_printmodeline] Modeline 101:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  348.474271] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  348.474275] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  348.474277] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  348.474281] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  348.474283] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  348.474289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  348.474292] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  348.474295] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  348.474297] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  348.474300] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  348.474302] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  348.474304] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  348.474307] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  348.474309] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  348.474312] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  348.474314] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  348.474317] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  348.474319] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  348.474321] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  348.474324] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  348.474326] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  348.474329] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  348.474331] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  348.474333] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  348.474336] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  348.474338] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  348.474341] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  348.474343] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  348.474346] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  348.474348] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  348.474641] [IGT] kms_busy: starting subtest basic-flip-default-A
>[  348.477547] [drm:drm_mode_addfb2] [FB:65]
>[  348.585957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  348.586002] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  348.610360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  348.610482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.613467] [drm:drm_mode_addfb2] [FB:61]
>[  349.299546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.299618] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  349.299652] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.299899] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  349.312608] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  349.312637] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  349.312675] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  349.345267] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  349.345365] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  349.345485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.345542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  349.345588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  349.345632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  349.345675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  349.345722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  349.345764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  349.345805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  349.345851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  349.345902] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  349.345951] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  349.345997] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  349.346332] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  349.346458] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.346635] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.346743] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  349.346830] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.346896] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.346945] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.347470] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.349229] [IGT] kms_busy: exiting, ret=0
>[  349.379565] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  349.379654] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.379731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  349.379811] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  349.379876] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  349.379945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.380014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  349.380121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  349.380184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  349.380244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.380301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.380315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  349.380371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.380381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  349.380438] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  349.380493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  349.380547] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  349.380600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.380653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.380720] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.380776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.380830] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  349.380882] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  349.380933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  349.381000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.381137] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  349.381202] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  349.381422] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.381486] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.381811] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.381894] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.381960] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.382937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.383016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  349.383127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  349.383189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  349.383247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  349.383303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  349.383359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  349.383415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  349.383477] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  349.383546] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  349.383609] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  349.383669] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  349.383769] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  349.383841] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  349.385161] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  349.385216] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  349.395886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.404444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.412942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.421442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.429911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.438373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.446835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.455295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.463758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.472222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.480684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.489146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.497607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.506068] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.514530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.522992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.531453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.539914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.547715] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  349.607842] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  349.607859] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  349.607892] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  349.609472] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  349.612065] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  349.613406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.613422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.613438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.613454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.618588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.618604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  349.623749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.626229] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  349.626767] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  349.626807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  349.626823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  349.626853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.627024] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  349.627047] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  349.643601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  349.643624] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  349.643664] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  349.643879] Console: switching to colour frame buffer device 200x56
>[  349.719325] Console: switching to colour dummy device 80x25
>[  349.719480] [IGT] kms_busy: executing
>[  349.762051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  349.762096] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  349.762112] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  349.762521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  349.762557] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  349.764792] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  349.764829] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  349.767083] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  349.767093] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  349.769328] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  349.769365] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  349.771597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  349.771606] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  349.771613] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  349.772182] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  349.772235] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  349.773059] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  349.773114] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  349.773901] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  349.774775] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  349.776385] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  349.776419] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  349.776450] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  349.776480] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  349.777327] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  349.778142] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  349.779249] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  349.779254] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  349.779259] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  349.779263] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  349.779405] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  349.779409] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  349.779417] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  349.779420] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  349.779428] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  349.779431] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  349.779742] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  349.779748] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  349.779752] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  349.779757] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  349.779762] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  349.779767] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  349.779771] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  349.779776] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  349.779780] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  349.779785] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  349.779789] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  349.779794] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  349.779799] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  349.779803] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  349.779808] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  349.779812] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  349.779817] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  349.779821] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  349.779826] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  349.779830] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  349.779835] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  349.779839] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  349.779844] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  349.779848] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  349.779853] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  349.780749] [IGT] kms_busy: starting subtest basic-flip-default-B
>[  349.786021] [drm:drm_mode_addfb2] [FB:64]
>[  349.826153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  349.826199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.826275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  349.826310] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.826543] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  349.828470] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  349.828492] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  349.828520] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  349.828562] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  349.828590] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  349.828627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.828644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  349.828659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  349.828674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  349.828687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  349.828702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  349.828715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  349.828728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  349.828743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  349.828759] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  349.828774] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  349.828788] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  349.828802] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  349.828827] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.828860] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.828881] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  349.828898] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.828912] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.828924] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.829357] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.829449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  349.829459] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  349.829498] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  349.829514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.829532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  349.829550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  349.829565] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  349.829581] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.829597] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  349.829612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  349.829627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  349.829641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.829654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.829658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  349.829671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.829674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  349.829688] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  349.829701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  349.829714] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  349.829726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.829739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.829755] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.829768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.829781] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  349.829793] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  349.829806] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  349.829821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.829839] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  349.829854] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  349.829868] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  349.830123] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.830136] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.830241] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.830259] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.830272] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.830317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.830335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  349.830349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  349.830364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  349.830378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  349.830392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  349.830405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  349.830419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  349.830434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  349.830450] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  349.830466] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  349.830481] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  349.830499] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  349.830514] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  349.832101] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  349.832130] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  349.841571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.850053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.858515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.866974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.875446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.883905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.892363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.900822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.909280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.917740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.926200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.934659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.943118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.951576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.960047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.968508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.976968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.985439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.993898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.994937] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  350.055710] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  350.055729] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  350.055797] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  350.056561] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  350.057372] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  350.058096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.058116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.058134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.058152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.063900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.063918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.069043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.071494] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  350.071965] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  350.072103] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  350.072120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  350.072147] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.088899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  350.088926] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  350.088967] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  350.105618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  350.109099] [drm:drm_mode_addfb2] [FB:65]
>[  350.778305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.778427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.778481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  350.778500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  350.778533] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  350.791346] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  350.791364] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  350.791391] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  350.791413] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.791451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  350.791471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  350.791489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  350.791506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  350.791522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  350.791539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  350.791555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  350.791570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  350.791588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  350.791607] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  350.791625] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  350.791642] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  350.791658] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  350.791683] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.791706] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.791729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  350.791747] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.791764] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.791778] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.792793] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.793257] [IGT] kms_busy: exiting, ret=0
>[  350.814629] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  350.814660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.814690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  350.814722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  350.814748] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  350.814776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.814804] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  350.814829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.814854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  350.814878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.814901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.814907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  350.814929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.814933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  350.814956] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  350.814978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  350.815020] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.815042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.815064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.815090] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.815112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.815134] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  350.815156] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  350.815177] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  350.815203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.815232] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  350.815258] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.815344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.815366] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.815648] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.815681] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.815708] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.815772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  350.815800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  350.815823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  350.815845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  350.815866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  350.815887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  350.815908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  350.815928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  350.815952] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  350.815978] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  350.816019] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  350.816044] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  350.816073] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  350.816098] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.818087] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  350.818113] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  350.827691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.836289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.844937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.853661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.862327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.870995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.879713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.888377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.897041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.905707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.914369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.923043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.931662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.940225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.948753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.957253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.965769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.974239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.980355] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  351.040228] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  351.040311] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  351.040461] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  351.041564] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  351.042845] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  351.045179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.045263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.045340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.045422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.051631] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.051707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.057204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.059933] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  351.062091] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.062214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  351.062287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.062386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.062562] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.062637] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.079249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  351.079357] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  351.079526] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  351.080139] Console: switching to colour frame buffer device 200x56
>[  351.247682] Console: switching to colour dummy device 80x25
>[  351.247805] [IGT] kms_busy: executing
>[  351.294502] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  351.294549] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  351.294566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  351.295200] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  351.295231] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  351.297474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  351.297506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  351.299746] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  351.299753] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  351.301985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  351.302029] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  351.304262] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  351.304269] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  351.304274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  351.304613] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  351.304641] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  351.305549] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  351.305579] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  351.306394] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  351.307232] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  351.308774] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  351.308798] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  351.308820] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  351.308841] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  351.309645] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  351.310412] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  351.311300] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  351.311304] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  351.311306] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  351.311309] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  351.311394] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  351.311397] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  351.311402] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  351.311404] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  351.311409] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  351.311411] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  351.311419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  351.311422] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  351.311425] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  351.311428] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  351.311431] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  351.311434] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  351.311436] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  351.311439] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  351.311442] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  351.311445] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  351.311448] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  351.311450] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  351.311453] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  351.311456] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  351.311459] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  351.311461] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  351.311464] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  351.311467] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  351.311470] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  351.311472] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  351.311475] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  351.311478] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  351.311481] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  351.311483] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  351.311486] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  351.311957] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  351.315713] [drm:drm_mode_addfb2] [FB:61]
>[  351.343674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  351.343718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.343783] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.343804] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  351.343856] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.347436] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  351.347451] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  351.347472] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.347492] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  351.347509] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.347543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  351.347560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  351.347574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  351.347588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  351.347601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  351.347615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  351.347627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  351.347639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  351.347654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  351.347670] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  351.347685] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  351.347699] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  351.347713] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  351.347734] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.347754] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.347774] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  351.347791] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.347805] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.347817] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.348262] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.348375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  351.348802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  351.348816] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  351.348869] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  351.348891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.348913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  351.348937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  351.348958] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  351.348999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.349017] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  351.349040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  351.349061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  351.349082] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.349101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.349107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  351.349127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.349132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  351.349150] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  351.349170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  351.349190] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  351.349210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.349230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.349252] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.349272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.349291] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  351.349311] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  351.349330] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  351.349348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.349371] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  351.349392] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  351.349413] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  351.349686] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.349705] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.350001] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.350028] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.350050] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.350090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  351.350108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  351.350124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  351.350139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  351.350153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  351.350168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  351.350181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  351.350195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  351.350210] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  351.350233] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  351.350257] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  351.350279] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  351.350305] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  351.350328] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.352092] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  351.352108] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  351.361564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.370030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.378491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.386951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.395471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.403930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.412388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.420847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.429302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.437762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.446220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.454678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.463136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.471591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.480048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.488505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.496962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.505432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  351.513211] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  351.572891] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  351.572908] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  351.572941] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  351.573770] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  351.574457] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  351.576213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.576233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.576250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.576269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.582185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.582203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.587328] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.589812] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  351.590333] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  351.590387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  351.590403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  351.590425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.607180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  351.607206] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  351.607247] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  351.627063] [drm:drm_mode_addfb2] [FB:65]
>[  352.297662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.298587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.298880] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  352.298984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  352.299309] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  352.308360] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  352.308443] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  352.308565] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  352.308669] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.308828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.308924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  352.309032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  352.309301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  352.309406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  352.309530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.309625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.309735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  352.309838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  352.309967] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  352.310157] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  352.310278] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  352.310396] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  352.310558] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.310697] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.310842] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  352.310972] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.311159] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.311271] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.311792] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.313619] [IGT] kms_busy: exiting, ret=0
>[  352.339972] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  352.340166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.340273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  352.340382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  352.340468] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  352.340561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.340653] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  352.340737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.340819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  352.340899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.340974] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.341035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  352.341113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.341127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  352.341204] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  352.341279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  352.341352] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.341424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.341493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.341583] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.341657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.341729] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  352.341800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  352.341869] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  352.341959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.342111] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  352.342197] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.342493] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.342565] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.342899] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.343009] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.343161] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.343354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.343448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  352.343526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  352.343600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  352.343673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  352.343745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.343814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.343884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  352.343963] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  352.344101] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  352.344184] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  352.344264] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  352.344362] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  352.344444] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.346361] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  352.346446] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  352.356699] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.365599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.374452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.383300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.392138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.400979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.409883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.418719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.427497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.436153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.444809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.453333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.461836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.470317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.478785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.487247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.495709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.504169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.508596] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  352.569660] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  352.569676] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  352.569700] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  352.570519] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  352.571252] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  352.573839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.573857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.573874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.573892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.579290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.579306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.584437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.586922] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  352.587472] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.587547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  352.587563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.587586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.587627] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.587643] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.604340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  352.604366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.604409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  352.604567] Console: switching to colour frame buffer device 200x56
>[  352.725119] Console: switching to colour dummy device 80x25
>[  352.725456] [IGT] kms_cursor_legacy: executing
>[  352.789220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  352.789284] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  352.789301] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  352.789745] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  352.789784] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  352.792056] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  352.792096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  352.794335] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  352.794344] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  352.796581] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  352.796613] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  352.798872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  352.798884] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  352.798891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  352.799557] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  352.799597] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  352.800542] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  352.800577] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  352.801426] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  352.802280] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  352.803930] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  352.803954] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  352.803976] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  352.804153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  352.804963] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  352.805771] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  352.806694] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  352.806698] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  352.806701] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  352.806704] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  352.806804] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  352.806807] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  352.806813] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  352.806815] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  352.806821] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  352.806823] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  352.806833] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  352.806837] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  352.806840] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  352.806844] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  352.806847] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  352.806850] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  352.806853] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  352.806857] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  352.806860] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  352.806863] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  352.806867] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  352.806870] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  352.806873] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  352.806876] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  352.806879] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  352.806883] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  352.806886] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  352.806889] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  352.806892] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  352.806896] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  352.806899] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  352.806902] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  352.806905] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  352.806908] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  352.806912] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  352.808091] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-atomic
>[  352.808455] [drm:drm_mode_addfb2] [FB:64]
>[  352.839173] [drm:drm_mode_addfb2] [FB:78]
>[  352.907739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.908453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.908635] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.908696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  352.908791] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.922161] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  352.922248] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  352.922370] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.922480] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  352.922578] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.922748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.922846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  352.922930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  352.923007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  352.923987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  352.924227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.924359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.924482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  352.924606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  352.924746] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  352.924877] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  352.925005] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  352.925264] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  352.925425] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.925580] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.925739] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.925883] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.926008] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.926214] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.926751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.928165] [IGT] kms_cursor_legacy: exiting, ret=0
>[  352.957155] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  352.957213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.957272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  352.957333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  352.957383] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  352.957436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.957489] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  352.957538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.957586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  352.957631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.957675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.957685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  352.957728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.957736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  352.957779] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  352.957820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  352.957862] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.957903] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.957943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.957994] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.958069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.958111] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  352.958152] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  352.958193] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  352.958244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.958301] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  352.958349] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.958489] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.958528] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.958830] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.958893] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.958954] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.959112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.959168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  352.959216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  352.959260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  352.959303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  352.959345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.959387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.959428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  352.959476] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  352.959529] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  352.959580] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  352.959629] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  352.959688] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  352.959737] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.961166] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  352.961218] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  352.971086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.979689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.988208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  352.996687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.005150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.013612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.022074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.030537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.039000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.047480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.055942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.064405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.072865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.081327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.089789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.098251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.106713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.115174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.122774] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  353.183285] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  353.183305] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  353.183334] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  353.184316] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  353.186895] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  353.188237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.188254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.188269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.188285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.193418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.193433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.198564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.201048] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  353.201581] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.201622] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  353.201637] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.201661] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.201702] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.201718] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.218416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  353.218439] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  353.218495] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  353.218648] Console: switching to colour frame buffer device 200x56
>[  353.293631] Console: switching to colour dummy device 80x25
>[  353.293764] [IGT] kms_cursor_legacy: executing
>[  353.320716] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  353.320755] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  353.320769] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  353.321296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  353.321328] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  353.323183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.323215] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  353.325451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.325460] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  353.327749] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  353.327780] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  353.330028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  353.330036] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  353.330042] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  353.330440] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  353.330474] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  353.331254] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  353.331290] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  353.332143] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  353.333120] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  353.334691] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  353.334721] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  353.334747] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  353.334773] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  353.335659] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  353.336469] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  353.337428] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  353.337433] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  353.337437] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  353.337441] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  353.337560] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  353.337564] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  353.337570] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  353.337573] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  353.337580] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  353.337583] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  353.337594] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  353.337598] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  353.337603] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.337607] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.337611] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  353.337615] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  353.337618] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  353.337622] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  353.337626] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.337630] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.337634] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  353.337638] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.337642] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.337646] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  353.337650] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  353.337653] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  353.337657] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  353.337661] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  353.337665] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  353.337669] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.337673] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.337677] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  353.337680] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.337684] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.337688] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  353.339135] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-legacy
>[  353.339652] [drm:drm_mode_addfb2] [FB:61]
>[  353.379042] [drm:drm_mode_addfb2] [FB:78]
>[  353.436964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.437086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.437120] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  353.437176] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.452482] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  353.452531] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  353.452598] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.452659] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  353.452714] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.452810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  353.452865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  353.452911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  353.452954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  353.452997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  353.453135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  353.453200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  353.453268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  353.453338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  353.453417] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  353.453488] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  353.453557] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  353.453624] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  353.453715] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.453800] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.453885] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  353.453964] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.454102] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.454155] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.454623] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.455314] [IGT] kms_cursor_legacy: exiting, ret=0
>[  353.481351] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  353.481427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.481505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  353.481586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  353.481651] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  353.481720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.481788] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  353.481851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.481913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  353.481971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.482065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.482079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  353.482135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.482146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  353.482205] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  353.482262] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  353.482318] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.482373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.482426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.482493] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.482549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.482604] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  353.482658] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  353.482712] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  353.482779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.482854] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  353.482918] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.483165] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.483218] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.483531] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.483613] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.483687] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.483834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  353.483906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  353.483963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  353.484081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  353.484136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  353.484189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  353.484241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  353.484292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  353.484351] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  353.484416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  353.484477] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  353.484538] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  353.484611] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  353.484671] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.486209] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  353.486272] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  353.496172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.505109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.513908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.522791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.531458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.540009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.548529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.557024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.565504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.573971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.582450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.590912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.599374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.607837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.616298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.624759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.633220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.641680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  353.647796] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  353.707938] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  353.707956] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  353.707982] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  353.708807] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  353.709545] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  353.712135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.712153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.712171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.712189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.717582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.717599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.722743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.725228] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  353.725762] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.725801] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  353.725816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.725839] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.725880] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.725896] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.742596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  353.742621] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  353.742665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  353.742823] Console: switching to colour frame buffer device 200x56
>[  353.830910] Console: switching to colour dummy device 80x25
>[  353.831320] [IGT] kms_cursor_legacy: executing
>[  353.868147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  353.868202] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  353.868220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  353.868708] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  353.868752] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  353.871012] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.871089] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  353.873336] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.873348] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  353.875598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  353.875643] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  353.877891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  353.877904] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  353.877912] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  353.878742] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  353.878789] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  353.879612] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  353.879659] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  353.880677] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  353.881656] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  353.883406] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  353.883447] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  353.883484] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  353.883520] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  353.884393] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  353.885179] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  353.886388] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  353.886395] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  353.886401] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  353.886406] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  353.886574] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  353.886579] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  353.886589] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  353.886593] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  353.886602] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  353.886607] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  353.886623] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  353.886629] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  353.886635] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.886641] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.886646] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  353.886652] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  353.886658] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  353.886663] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  353.886669] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.886674] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.886680] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  353.886685] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.886691] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.886697] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  353.886702] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  353.886707] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  353.886713] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  353.886719] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  353.886724] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  353.886730] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.886735] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.886741] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  353.886746] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.886752] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.886757] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  353.888444] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-atomic
>[  353.889160] [drm:drm_mode_addfb2] [FB:64]
>[  353.939073] [drm:drm_mode_addfb2] [FB:78]
>[  354.001291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.002016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.002596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  354.002758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  354.002995] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  354.010160] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  354.010248] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  354.010367] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  354.010478] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  354.010579] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.010747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  354.010845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  354.010928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  354.011008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  354.011811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  354.011924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  354.012013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  354.012291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  354.012423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  354.012573] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  354.012711] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  354.012821] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  354.012911] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  354.013123] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.013303] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.013477] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  354.013636] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.013747] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.013821] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.014829] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.016241] [IGT] kms_cursor_legacy: exiting, ret=0
>[  354.044838] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  354.044881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.044926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  354.044973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  354.045055] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  354.045094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.045134] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  354.045171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  354.045206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  354.045241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.045273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.045281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  354.045314] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.045319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  354.045353] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  354.045384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  354.045416] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.045447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.045477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.045515] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.045547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.045579] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  354.045609] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  354.045640] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  354.045678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.045720] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  354.045757] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  354.045883] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.045913] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.046231] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.046279] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.046317] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.046407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  354.046447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  354.046481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  354.046513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  354.046544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  354.046575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  354.046605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  354.046634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  354.046668] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  354.046705] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  354.046740] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  354.046775] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  354.046817] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  354.046852] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.048135] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  354.048171] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  354.057833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.066419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.074933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.083420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.091889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.100367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.108829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.117290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.125752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.134215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.142677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.151141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.159604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.168065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.176527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.184989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.193451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.201913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.209714] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  354.270779] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  354.270795] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  354.270819] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  354.271644] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  354.272383] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  354.274970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.275005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.275022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.275040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.280420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.280436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.285567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.288049] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  354.288581] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  354.288624] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  354.288640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  354.288663] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.288711] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  354.288735] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  354.305422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  354.305448] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  354.305491] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  354.305644] Console: switching to colour frame buffer device 200x56
>[  354.423264] Console: switching to colour dummy device 80x25
>[  354.423432] [IGT] kms_cursor_legacy: executing
>[  354.448388] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  354.448417] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  354.448431] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  354.448734] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  354.448759] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  354.451002] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.451046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.453193] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.453200] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.455429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.455455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.457681] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.457688] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.457693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  354.458189] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  354.458216] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  354.458956] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  354.459128] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 1 ms
>[  354.459848] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  354.460684] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  354.462266] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  354.462291] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  354.462313] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  354.462334] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  354.463172] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  354.463893] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.464812] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  354.464816] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  354.464819] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  354.464822] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.464921] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.464924] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.464929] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.464932] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.464938] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.464940] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.464950] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  354.464953] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  354.464957] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.464961] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.465399] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.465402] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.465406] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.465409] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.465412] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.465416] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.465419] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.465422] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.465426] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.465429] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.465432] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.465435] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.465438] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.465442] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.465445] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.465448] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.465451] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.465454] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.465458] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.465461] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.465464] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.465824] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-legacy
>[  354.466854] [drm:drm_mode_addfb2] [FB:61]
>[  354.500446] [drm:drm_mode_addfb2] [FB:78]
>[  354.557560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.557777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.557882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  354.557918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  354.557986] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  354.573598] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  354.573646] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  354.573711] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  354.573770] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  354.573825] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.573921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  354.573975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  354.574576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  354.574624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  354.574669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  354.574718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  354.574760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  354.574802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  354.574849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  354.574899] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  354.574946] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  354.574991] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  354.575685] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  354.575807] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.575923] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.576166] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  354.576285] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.576376] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.576458] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.576950] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.577937] [IGT] kms_cursor_legacy: exiting, ret=0
>[  354.602499] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  354.602569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.602642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  354.602719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  354.602780] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  354.602847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.602912] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  354.602973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  354.603095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  354.603153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.603207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.603221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  354.603273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.603283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  354.603337] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  354.603389] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  354.603441] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.603494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.603544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.603608] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.603659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.603711] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  354.603762] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  354.603812] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  354.603876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.603947] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  354.604008] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  354.604270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.604319] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.604631] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.604709] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.604777] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.604927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  354.604997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  354.605096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  354.605152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  354.605207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  354.605260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  354.605313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  354.605365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  354.605424] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  354.605491] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  354.605552] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  354.605613] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  354.605687] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  354.605749] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.607207] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  354.607270] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  354.617284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.625963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.634565] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.643059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.651547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.660009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.668471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.676934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.685396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.693859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.702322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.710784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.719245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.727709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.736170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.744631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.753093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.761555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  354.767468] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  354.828603] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  354.828619] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  354.828643] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  354.829462] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  354.830200] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  354.832788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.832806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.832823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.832841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.838239] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.838255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.843385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.845788] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  354.846339] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  354.846394] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  354.846409] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  354.846432] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.846481] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  354.846504] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  354.863192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  354.863218] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  354.863262] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  354.863417] Console: switching to colour frame buffer device 200x56
>[  354.966017] Console: switching to colour dummy device 80x25
>[  354.966196] [IGT] kms_cursor_legacy: executing
>[  354.997932] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  354.997972] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  354.998142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  354.998505] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  354.998539] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  355.000781] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  355.000815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  355.003070] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  355.003079] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  355.005312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  355.005346] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  355.007581] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  355.007590] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  355.007597] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  355.008206] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  355.008240] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  355.009139] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  355.009176] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  355.009934] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  355.010794] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  355.012376] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  355.012406] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  355.012433] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  355.012459] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  355.013295] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  355.014107] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  355.015193] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  355.015198] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  355.015202] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  355.015206] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  355.015332] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  355.015336] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  355.015343] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  355.015347] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  355.015354] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  355.015357] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  355.015369] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  355.015374] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  355.015378] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  355.015382] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  355.015386] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  355.015391] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  355.015395] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  355.015399] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  355.015403] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  355.015407] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  355.015411] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  355.015415] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  355.015419] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  355.015424] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  355.015428] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  355.015432] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  355.015436] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  355.015440] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  355.015444] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  355.015448] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  355.015452] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  355.015456] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  355.015460] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  355.015464] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  355.015468] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  355.015926] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-varying-size
>[  355.017138] [drm:drm_mode_addfb2] [FB:64]
>[  355.058026] [drm:drm_mode_addfb2] [FB:78]
>[  355.058115] [drm:drm_mode_addfb2] [FB:80]
>[  355.115016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.115203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.115297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  355.115328] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  355.115387] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.130625] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  355.130664] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  355.130717] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  355.130765] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  355.130807] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.130882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.130925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  355.130962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  355.131428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  355.131465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  355.131504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  355.131538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  355.131570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  355.131607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  355.131647] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  355.131685] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  355.131721] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  355.131756] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  355.131807] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.131854] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.131904] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.131947] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.131981] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.132556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.133496] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.133943] [IGT] kms_cursor_legacy: exiting, ret=0
>[  355.161536] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  355.161611] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.161689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  355.161769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  355.161833] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  355.161901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.161969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  355.162076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  355.162140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  355.162200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.162257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.162271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  355.162328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.162338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  355.162396] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  355.162451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  355.162505] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.162558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.162611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.162678] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.162733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.162788] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  355.162841] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  355.162893] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  355.162960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.163070] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  355.163132] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  355.163355] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.163410] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.163727] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.163810] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.163877] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.164042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.164172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  355.164230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  355.164285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  355.164339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  355.164391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  355.164443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  355.164494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  355.164552] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  355.164618] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  355.164680] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  355.164741] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  355.164816] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  355.164877] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.166207] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  355.166270] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  355.176716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.185517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.194133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.202652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.211140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.219610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.228071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.236532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.244993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.253458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.261919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.270381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.278841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.287303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.295764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.304225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.312687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.321147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.327275] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  355.389063] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  355.389081] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  355.389143] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  355.389809] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  355.390620] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  355.391364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.391382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.391400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.391418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.397202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.397219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.402350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.404829] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  355.405375] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  355.405408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  355.405423] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  355.405446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.405497] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  355.405521] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  355.422208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  355.422234] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.422277] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  355.422430] Console: switching to colour frame buffer device 200x56
>[  355.537368] Console: switching to colour dummy device 80x25
>[  355.537504] [IGT] kms_cursor_legacy: executing
>[  355.562273] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  355.562305] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  355.562319] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  355.562605] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  355.562631] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  355.564861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  355.564887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  355.567131] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  355.567139] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  355.569370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  355.569396] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  355.571621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  355.571628] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  355.571633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  355.572110] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  355.572137] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  355.573847] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  355.573878] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  355.574646] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  355.575521] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  355.577073] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  355.577097] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  355.577119] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  355.577140] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  355.577950] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  355.578679] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  355.579637] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  355.579641] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  355.579644] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  355.579647] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  355.579747] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  355.579750] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  355.579756] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  355.579758] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  355.579764] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  355.579766] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  355.579775] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  355.579779] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  355.579782] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  355.579786] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  355.579789] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  355.579792] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  355.579796] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  355.579799] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  355.579802] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  355.579805] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  355.579809] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  355.579812] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  355.579815] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  355.579818] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  355.579821] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  355.579825] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  355.579828] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  355.579831] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  355.579834] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  355.579837] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  355.579841] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  355.579844] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  355.579847] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  355.579850] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  355.579853] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  355.580404] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-atomic
>[  355.580780] [drm:drm_mode_addfb2] [FB:61]
>[  355.616610] [drm:drm_mode_addfb2] [FB:78]
>[  355.673850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.673948] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  355.673979] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  355.674085] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.691365] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  355.691405] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  355.691457] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  355.691505] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  355.691548] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.691625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.691668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  355.691704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  355.691738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  355.691771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  355.691806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  355.691838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  355.691869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  355.691905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  355.691945] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  355.691982] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  355.692104] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  355.692158] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  355.692232] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.692300] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.692371] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.692433] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.692485] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.692533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.692991] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.694056] [IGT] kms_cursor_legacy: exiting, ret=0
>[  355.716111] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  355.716165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.716222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  355.716281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  355.716328] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  355.716378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.716428] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  355.716475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  355.716520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  355.716563] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.716605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.716615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  355.716656] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.716663] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  355.716705] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  355.716747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  355.716787] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.716827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.716866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.716914] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.716955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.716994] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  355.717064] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  355.717103] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  355.717152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.717206] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  355.717252] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  355.717385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.717423] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.717724] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.717783] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.717836] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.717945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.717997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  355.718066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  355.718108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  355.718147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  355.718185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  355.718223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  355.718260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  355.718303] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  355.718350] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  355.718395] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  355.718438] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  355.718492] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  355.718537] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.720222] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  355.720271] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  355.730105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.738786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.747439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.755979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.764533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.773124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.781591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.790054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.798516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.806992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.815455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.823917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.832378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.840839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.849302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.857764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.866226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.874688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  355.882487] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  355.942976] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  355.942993] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  355.943025] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  355.943844] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  355.944568] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  355.947141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.947158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.947173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.947190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.952583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.952597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.957731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.960218] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  355.960717] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  355.960788] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  355.960803] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  355.960824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.960869] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  355.960889] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  355.977585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  355.977609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.977649] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  355.977802] Console: switching to colour frame buffer device 200x56
>[  356.067113] Console: switching to colour dummy device 80x25
>[  356.067308] [IGT] kms_cursor_legacy: executing
>[  356.107531] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  356.107580] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  356.107599] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  356.108165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  356.108210] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  356.110450] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  356.110493] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  356.112743] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  356.112755] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  356.115013] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  356.115088] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  356.117338] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  356.117350] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  356.117359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  356.117925] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  356.117972] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  356.118847] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  356.118894] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  356.119791] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  356.120701] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  356.122368] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  356.122410] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  356.122446] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  356.122483] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  356.123358] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  356.124162] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  356.125373] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  356.125380] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  356.125386] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  356.125391] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  356.125560] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  356.125565] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  356.125575] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  356.125579] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  356.125588] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  356.125593] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  356.125609] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  356.125615] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  356.125621] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  356.125627] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  356.125633] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  356.125638] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  356.125644] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  356.125649] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  356.125655] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  356.125660] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  356.125666] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  356.125671] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  356.125677] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  356.125682] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  356.125688] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  356.125693] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  356.125699] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  356.125704] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  356.125710] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  356.125715] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  356.125721] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  356.125726] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  356.125732] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  356.125737] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  356.125742] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  356.126653] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-legacy
>[  356.127369] [drm:drm_mode_addfb2] [FB:64]
>[  356.174104] [drm:drm_mode_addfb2] [FB:78]
>[  356.229352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.229591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.229776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.229862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  356.229894] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  356.229955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  356.246740] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  356.246781] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  356.246838] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  356.246889] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  356.246936] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.247095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  356.247147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  356.247198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  356.247249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  356.247299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  356.247349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  356.247389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  356.247427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  356.247468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  356.247511] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  356.247552] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  356.247591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  356.247631] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  356.247689] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.247740] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.247794] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  356.247840] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.247877] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.247910] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.248424] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.249437] [IGT] kms_cursor_legacy: exiting, ret=0
>[  356.280215] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  356.280275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.280337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  356.280401] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  356.280453] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  356.280508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.280563] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  356.280614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  356.280663] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  356.280711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.280757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.280768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  356.280813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.280821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  356.280868] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  356.280913] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  356.280957] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.281000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.281100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.281155] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.281199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.281243] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  356.281286] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  356.281328] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  356.281382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.281442] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  356.281494] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  356.281675] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.281717] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.282086] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.282560] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.282609] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.282726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  356.282785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  356.282832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  356.282876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  356.282920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  356.282964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  356.283045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  356.283087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  356.283135] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  356.283189] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  356.283240] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  356.283288] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  356.283348] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  356.283397] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.285168] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  356.285219] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  356.295057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.303765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.312343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.320858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.329343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.337823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.346285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.354749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.363211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.371672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.380134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.388596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.397059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.405520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.413983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.422445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.430905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.439382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.445295] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  356.505986] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  356.506006] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  356.506054] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  356.507174] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  356.509752] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  356.511094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.511110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.511124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.511140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.516272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.516287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.521419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.523903] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  356.524454] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  356.524527] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  356.524543] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  356.524566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.524614] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  356.524638] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  356.541322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  356.541346] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  356.541386] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  356.541525] Console: switching to colour frame buffer device 200x56
>[  356.646025] Console: switching to colour dummy device 80x25
>[  356.646167] [IGT] kms_cursor_legacy: executing
>[  356.671011] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  356.671041] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  356.671054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  356.671320] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  356.671343] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  356.673160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  356.673180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  356.675412] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  356.675418] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  356.677642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  356.677662] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  356.679911] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  356.679920] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  356.679925] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  356.680413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  356.680438] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  356.681174] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  356.681199] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  356.681882] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  356.682701] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  356.684228] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  356.684247] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  356.684264] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  356.684281] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  356.685093] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  356.685800] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  356.686674] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  356.686677] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  356.686679] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  356.686682] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  356.686759] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  356.686761] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  356.686765] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  356.686767] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  356.686772] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  356.686774] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  356.686781] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  356.686784] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  356.686787] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  356.686790] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  356.686792] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  356.686795] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  356.686797] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  356.686800] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  356.686802] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  356.686805] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  356.686807] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  356.686810] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  356.686812] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  356.686815] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  356.686817] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  356.686820] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  356.686822] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  356.686825] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  356.686827] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  356.686830] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  356.686832] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  356.686834] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  356.686837] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  356.686839] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  356.686842] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  356.687772] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size
>[  356.688118] [drm:drm_mode_addfb2] [FB:61]
>[  356.717862] [drm:drm_mode_addfb2] [FB:78]
>[  356.717952] [drm:drm_mode_addfb2] [FB:80]
>[  356.776648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.776851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.776951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  356.777198] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  356.777283] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  356.792303] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  356.792362] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  356.792443] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  356.792517] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  356.792583] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.792699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  356.792765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  356.792821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  356.792874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  356.792925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  356.792980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  356.793710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  356.793775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  356.793837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  356.793908] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  356.793969] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  356.794182] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  356.794244] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  356.794327] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.794399] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.794483] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  356.794550] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.794605] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.794652] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.795620] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.796343] [IGT] kms_cursor_legacy: exiting, ret=0
>[  356.829873] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  356.829974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.830133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  356.830241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  356.830329] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  356.830422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.830515] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  356.830600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  356.830683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  356.830765] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.830843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.830861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  356.830937] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.830951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  356.831029] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  356.831180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  356.831255] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.831329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.831400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.831491] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.831565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.831638] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  356.831711] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  356.831782] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  356.831873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.831975] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  356.832119] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  356.832411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.832483] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.832818] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.832926] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.833001] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.833333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  356.833432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  356.833515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  356.833594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  356.833669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  356.833743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  356.833819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  356.833893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  356.833976] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  356.834121] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  356.834209] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  356.834295] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  356.834399] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  356.834486] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.836834] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  356.836919] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  356.847199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.855918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.864471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.872979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.881483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.889959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.898447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.906911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.915374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.923841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.932306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.940769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.949232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.957697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.966158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.974809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.983271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.991734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  356.999548] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  357.059619] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  357.059636] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  357.059668] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  357.060357] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  357.061157] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  357.062951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.062968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.062994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.063010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.068873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.068888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.074013] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.076493] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  357.077007] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  357.077070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  357.077084] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  357.077106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.077151] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  357.077172] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  357.093867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  357.093890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  357.093930] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.094086] Console: switching to colour frame buffer device 200x56
>[  357.178644] Console: switching to colour dummy device 80x25
>[  357.178818] [IGT] kms_flip: executing
>[  357.191632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  357.191672] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  357.191689] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  357.191709] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  357.191743] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  357.193168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  357.193204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  357.195169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  357.195179] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  357.197163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  357.197200] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  357.199170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  357.199180] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  357.199187] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  357.199210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  357.199249] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  357.200061] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  357.200111] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  357.200903] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  357.201772] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  357.203365] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  357.203399] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  357.203429] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  357.203458] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  357.204309] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  357.205082] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  357.206152] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  357.206158] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  357.206162] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  357.206167] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  357.206307] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  357.206311] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  357.206319] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  357.206323] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  357.206330] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  357.206334] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  357.206348] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  357.206353] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.206358] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  357.206362] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  357.206367] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  357.206372] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  357.206376] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  357.206381] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  357.206386] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  357.206390] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  357.206395] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  357.206399] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  357.206404] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  357.206408] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  357.206413] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  357.206418] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  357.206422] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  357.206427] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  357.206431] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  357.206436] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  357.206440] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  357.206444] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  357.206449] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  357.206453] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  357.206458] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  357.206811] [IGT] kms_flip: starting subtest basic-flip-vs-dpms
>[  357.207784] [drm:drm_mode_addfb2] [FB:64]
>[  357.207825] [drm:drm_mode_addfb2] [FB:78]
>[  357.271194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  357.271242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.271309] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  357.271329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  357.271366] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  357.278053] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  357.278069] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  357.278090] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  357.278110] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  357.278128] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.278161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.278179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  357.278193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  357.278207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  357.278220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  357.278234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.278247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.278260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  357.278274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  357.278290] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  357.278305] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.278320] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  357.278334] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  357.278356] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.278376] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.278398] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  357.278415] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.278429] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.278441] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.278858] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.278904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  357.278998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  357.279382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  357.279392] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  357.279429] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  357.279445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.279462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  357.279480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  357.279495] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  357.279511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.279526] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  357.279541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  357.279555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  357.279569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.279582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.279585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.279598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.279601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.279614] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  357.279627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  357.279640] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.279653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.279665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.279681] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.279693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.279706] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  357.279719] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  357.279731] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  357.279746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.279763] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  357.279777] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  357.280016] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.280033] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.280310] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.280340] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.280358] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.280396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.280414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  357.280429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  357.280443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  357.280457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  357.280470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.280483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.280496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  357.280511] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  357.280526] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.280541] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  357.280556] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  357.280573] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  357.280588] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.282732] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  357.282747] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  357.292291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.300755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.309216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.317676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.326136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.334596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.343057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.351516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.359991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.368451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.376913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.385372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.393833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.402292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.410752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.419212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.427670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.436129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.443912] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  357.504784] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  357.504809] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  357.504866] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  357.505594] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  357.506403] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  357.507124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.507143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.507161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.507180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.512929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.512947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.518073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.520755] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  357.523219] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  357.523400] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  357.523490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  357.523603] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.523916] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  357.524014] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  357.540399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  357.540527] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  357.540712] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.574570] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  357.574673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.574777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  357.574882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  357.574969] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  357.575201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.575352] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  357.575459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  357.575584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  357.575687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.575803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.575832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.575938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.575972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.576155] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  357.576248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  357.576354] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.576444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.576547] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.576653] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.576758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.576851] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  357.576959] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  357.577156] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  357.577254] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  357.577382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.577517] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  357.577623] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  357.591334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  357.591454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  357.591635] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  357.609349] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  357.609456] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  357.609601] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  357.609733] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  357.609853] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.610060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.610423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  357.610558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  357.610709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  357.610857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  357.611005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.611240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.611384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  357.611537] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  357.611695] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.611850] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  357.612007] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  357.612378] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.612565] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.612727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  357.612881] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  357.613055] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.613331] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.613478] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.613613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.614677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.616454] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  357.616564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.616683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  357.616808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  357.616909] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  357.617018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.617317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  357.617480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  357.617639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  357.617788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.617937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.617977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.618206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.618240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.618388] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  357.618525] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  357.618666] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.618804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.618913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.619071] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.619314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.619462] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  357.619604] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  357.619739] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  357.619876] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  357.620041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.620316] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  357.620470] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  357.621022] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.621272] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.621661] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.622320] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.622442] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.622636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.622774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  357.622895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  357.623018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  357.623230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  357.623351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.623471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.623586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  357.623713] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  357.623848] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.623975] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  357.624349] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  357.624492] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  357.624615] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.626974] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  357.627149] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  357.637250] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.646175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.655160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.664135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.673133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.682124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.691039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.700032] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.708994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.717853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.726490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.735067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.743605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.752112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.760599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.769070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.777532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.785991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.788530] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  357.849435] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  357.849457] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  357.849499] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  357.850344] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  357.851056] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  357.853663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.853683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.853701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.853720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.859153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.859171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.864294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.866767] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  357.867309] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  357.867353] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  357.867370] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  357.867392] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.867435] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  357.867452] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  357.884148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  357.884174] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  357.884216] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.885193] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  357.885215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.885238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  357.885262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  357.885282] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  357.885302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.885323] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  357.885343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  357.885362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  357.885380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.885397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.885403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.885420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.885423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.885441] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  357.885458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  357.885475] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.885491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.885507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.885527] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.885544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.885562] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  357.885578] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  357.885594] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  357.885610] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  357.885630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.885652] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  357.885672] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  357.900965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  357.901018] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  357.901066] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  357.918357] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  357.918390] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  357.918434] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  357.918474] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  357.918510] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.918576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.918612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  357.918642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  357.918669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  357.918697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  357.918724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.918751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.918777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  357.918806] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  357.918839] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.918869] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  357.918898] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  357.918944] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.919195] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.919290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  357.919338] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  357.919388] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.919437] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.919480] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.919520] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.919965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.920932] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  357.920965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.921106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  357.921159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  357.921203] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  357.921249] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.921295] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  357.921339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  357.921382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  357.921425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.921466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.921477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.921513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.921523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  357.921562] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  357.921602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  357.921643] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.921684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.921724] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.921769] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.921809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.921849] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  357.921890] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  357.921929] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  357.921969] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  357.922185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.922222] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  357.922251] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  357.922359] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.922384] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.922669] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.922705] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.922739] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.922807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.922842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  357.922870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  357.922898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  357.922925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  357.922951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.922977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.923159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  357.923202] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  357.923248] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  357.923292] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  357.923336] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  357.923384] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  357.923427] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.925596] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  357.925628] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  357.935448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.944099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.952840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.961605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.970359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.980106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.988857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  357.997610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.006370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.015128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.023879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.032636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.041305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.049885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.058422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.066931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.075418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.083888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.086625] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  358.147374] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  358.147392] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  358.147457] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  358.148302] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  358.148997] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  358.150767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.150787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.150804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.150824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.156698] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.156715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.161838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.164319] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  358.164786] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  358.164846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  358.164862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  358.164885] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.164926] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  358.164943] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  358.181662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  358.181692] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  358.181735] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.182705] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  358.182726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.182747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  358.182768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  358.182785] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  358.182804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.182823] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  358.182840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  358.182857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  358.182873] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.182889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.182894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.182909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.182913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.182928] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  358.182944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  358.182959] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.183303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.183328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.183357] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.183383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.183402] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  358.183418] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  358.183434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  358.183449] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  358.183468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.183488] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  358.183506] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  358.198461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  358.198497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  358.198551] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  358.215879] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  358.215911] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  358.215955] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  358.216260] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  358.216319] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.216411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  358.216450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  358.216480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  358.216509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  358.216537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  358.216564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  358.216591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  358.216617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  358.216647] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  358.216679] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.216708] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  358.216738] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  358.216781] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.216820] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.216853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  358.216883] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  358.216915] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.216948] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.216977] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.217555] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.218509] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.218872] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  358.218905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.218940] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  358.218977] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  358.219189] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  358.219299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.219348] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  358.219393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  358.219431] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  358.219459] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.219486] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.219494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.219521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.219527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.219554] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  358.219579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  358.219605] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.219630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.219655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.219686] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.219712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.219739] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  358.219765] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  358.219790] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  358.219815] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  358.219846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.219880] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  358.219909] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  358.220638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.220678] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.220978] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.221499] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.221541] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.221629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  358.221665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  358.221695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  358.221724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  358.221751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  358.221778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  358.221804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  358.221830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  358.221859] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  358.221890] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.221920] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  358.221949] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  358.221984] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  358.222430] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.224654] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  358.224694] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  358.234630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.243334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.252100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.260881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.269649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.278415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.287173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.295996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.304818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.313581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.322347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.331111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.339754] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.348321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.356859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.365386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.374820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.383292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.387703] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  358.448530] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  358.448548] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  358.448583] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  358.449409] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  358.450097] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  358.451857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.451876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.451894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.451913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.457776] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.457794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.462918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.465400] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  358.465868] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  358.465927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  358.465943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  358.465966] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.466175] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  358.466193] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  358.482717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  358.482742] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  358.482783] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.483681] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  358.483701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.483722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  358.483744] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  358.483762] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  358.483780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.483799] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  358.483817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  358.483833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  358.483849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.483864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.483869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.483884] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.483888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.483903] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  358.483918] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  358.483933] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.483948] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.483962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.484019] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.484042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.484066] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  358.484087] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  358.484109] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  358.484133] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  358.484160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.484188] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  358.484210] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  358.499508] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  358.499536] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  358.499577] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  358.516853] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  358.516881] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  358.516918] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  358.516953] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  358.516983] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.517134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  358.517184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  358.517216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  358.517252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  358.517282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  358.517324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  358.517357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  358.517391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  358.517423] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  358.517462] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.517501] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  358.517534] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  358.517589] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.517636] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.517675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  358.517712] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  358.517751] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.517791] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.517827] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.517855] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.518326] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.518722] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  358.518749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.518779] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  358.518810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  358.518835] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  358.518862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.518888] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  358.518912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  358.518937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  358.518960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.519019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.519034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.519064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.519073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.519107] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  358.519142] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  358.519171] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.519203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.519230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.519269] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.519297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.519330] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  358.519365] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  358.519393] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  358.519440] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  358.519483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.519529] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  358.519565] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  358.519723] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.519754] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.520089] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.520142] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.520182] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.520250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  358.520299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  358.520334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  358.520372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  358.520406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  358.520443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  358.520475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  358.520511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  358.520546] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  358.520589] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.520632] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  358.520674] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  358.520722] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  358.520758] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.522953] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  358.523063] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  358.532692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.541336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.550004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.558717] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.567383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.576047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.584708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.593366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.602071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.610772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.619433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.628071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.636636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.645169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.653697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.662187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.670660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.679122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.685218] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  358.746044] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  358.746064] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  358.746121] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  358.746796] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  358.747603] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  358.748325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.748345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.748363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.748382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.754212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.754232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.759386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.761856] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  358.762456] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  358.762498] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  358.762516] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  358.762541] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.762586] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  358.762604] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  358.779303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  358.779337] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  358.779388] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.780355] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  358.780381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.780407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  358.780435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  358.780457] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  358.780481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.780505] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  358.780527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  358.780548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  358.780569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.780588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.780594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.780613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.780617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.780637] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  358.780656] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  358.780674] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.780693] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.780711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.780734] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.780753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.780773] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  358.780792] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  358.780811] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  358.780829] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  358.780852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.780877] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  358.780899] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  358.796147] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  358.796188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  358.796249] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  358.813538] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  358.813577] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  358.813629] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  358.813679] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  358.813722] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.813800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  358.813843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  358.813879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  358.813914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  358.813947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  358.813979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  358.814508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  358.814550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  358.814601] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  358.814657] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.814710] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  358.814761] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  358.814830] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.814897] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.814953] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  358.815160] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  358.815226] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.815289] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.815329] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.815360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.815798] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.816461] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  358.816501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.816544] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  358.816589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  358.816624] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  358.816662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.816701] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  358.816737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  358.816772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  358.816805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.816837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.816846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.816877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.816884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  358.816916] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  358.816948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  358.816978] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.817195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.817244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.817301] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.817351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.817404] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  358.817453] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  358.817501] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  358.817545] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  358.817590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.817649] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  358.817692] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  358.817881] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.817920] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.818262] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.818328] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.818379] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.818475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  358.818538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  358.818590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  358.818642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  358.818693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  358.818733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  358.818780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  358.818819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  358.818868] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  358.818924] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  358.818980] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  358.819065] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  358.819126] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  358.819172] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.821386] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  358.821435] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  358.831234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.840064] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.849192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.858158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.867141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.876122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.885007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.893870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.902694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.911592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.920418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.929249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.937878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.946444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.954989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.963514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.972001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.980473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  358.983200] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  359.042481] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  359.042499] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  359.042548] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  359.043371] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  359.044452] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  359.047014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.047032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.047048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.047065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.052189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.052206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.057331] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.059802] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  359.060346] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  359.060390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  359.060407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  359.060429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.060471] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  359.060488] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  359.077180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.077207] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.077248] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.078177] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.078201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.078229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.078258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.078279] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.078304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.078327] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.078350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.078371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.078393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.078412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.078417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.078437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.078442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.078464] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.078482] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.078503] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.078521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.078542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.078564] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.078585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.078608] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.078627] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.078648] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.078666] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.078690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.078718] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.078739] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.094020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  359.094054] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  359.094103] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  359.111401] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  359.111429] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  359.111466] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  359.111500] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  359.111530] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.111587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  359.111617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  359.111642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  359.111666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  359.111690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  359.111713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  359.111735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  359.111758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  359.111784] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  359.111811] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.111837] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  359.111862] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  359.111901] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.111935] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.111963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.112157] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.112202] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.112248] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.112287] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.112322] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.112765] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.113251] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.113284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.113322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.113363] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.113394] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.113430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.113462] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.113495] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.113525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.113559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.113586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.113595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.113624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.113631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.113663] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.113690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.113720] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.113746] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.113776] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.113808] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.113838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.113872] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.113899] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.113929] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.113955] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.114018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.114059] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.114091] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.114227] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.114260] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.114553] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.114597] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.114630] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.114694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  359.114733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  359.114762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  359.114795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  359.114823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  359.114854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  359.114881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  359.114912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  359.114941] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  359.114981] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.115040] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  359.115077] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  359.115119] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  359.115150] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.117313] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  359.117340] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  359.126905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.135489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.144127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.152778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.161468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.170121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.178772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.187427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.196080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.204759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.213412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.222062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.230679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.239240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.247777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.256274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.264756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.273222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.277431] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  359.340021] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  359.340040] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  359.340104] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  359.340785] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  359.341595] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  359.342317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.342336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.342355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.342374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.348235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.348254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.353388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.355859] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  359.356419] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  359.356448] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  359.356466] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  359.356491] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.356535] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  359.356554] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  359.373186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.373216] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.373260] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.374202] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.374226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.374249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.374273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.374293] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.374314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.374335] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.374354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.374373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.374391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.374408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.374412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.374429] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.374433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.374450] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.374467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.374483] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.374499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.374515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.374536] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.374553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.374570] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.374587] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.374603] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.374619] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.374639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.374661] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.374681] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.390084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  359.390125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  359.390198] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  359.407457] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  359.407496] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  359.407550] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  359.407599] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  359.407643] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.407720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  359.407764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  359.407800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  359.407835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  359.407869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  359.407902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  359.407934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  359.407966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  359.408100] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  359.408154] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.408207] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  359.408256] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  359.408330] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.408379] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.408420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.408458] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.408499] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.408540] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.408575] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.408606] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.409097] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.409941] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.409979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.410086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.410135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.410172] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.410213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.410251] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.410288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.410324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.410357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.410389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.410400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.410432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.410440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.410473] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.410506] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.410538] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.410569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.410601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.410639] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.410671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.410704] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.410737] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.410768] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.410799] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.410836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.410879] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.410916] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.411111] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.411151] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.411460] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.411522] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.411574] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.411679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  359.411721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  359.411756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  359.411792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  359.411827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  359.411861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  359.411893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  359.411926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  359.411961] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  359.412043] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.412091] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  359.412138] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  359.412192] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  359.412246] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.414433] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  359.414472] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  359.424207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.433013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.441967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.450959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.459951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.468951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.477940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.487283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.496144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.504978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.513870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.522706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.531392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.539985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.548564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.557081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.565572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.574061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.576809] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  359.637711] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  359.637733] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  359.637786] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  359.638469] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  359.639278] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  359.640007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.640028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.640053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.640072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.645808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.645826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.650952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.652449] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  359.652916] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  359.652947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  359.652964] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  359.653020] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.653080] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  359.653100] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  359.669740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.669765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.669805] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.670700] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.670721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.670741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.670763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.670780] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.670799] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.670817] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.670835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.670852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.670868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.670883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.670888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.670903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.670906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.670936] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.670953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.670969] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.671024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.671046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.671072] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.671094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.671118] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.671140] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.671162] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.671184] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.671210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.671236] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.671266] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.686556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  359.686589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  359.686642] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  359.703830] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  359.703858] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  359.703895] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  359.703929] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  359.703959] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.704119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  359.704170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  359.704212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  359.704249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  359.704276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  359.704303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  359.704330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  359.704355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  359.704382] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  359.704414] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.704458] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  359.704491] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  359.704536] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.704575] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.704609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.704642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.704676] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.704709] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.704738] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.704763] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.705254] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.706136] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.706170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.706205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.706241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.706271] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.706303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.706334] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.706363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.706391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.706419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.706445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.706452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.706478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.706484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.706511] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.706537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.706562] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.706588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.706613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.706644] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.706670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.706697] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.706723] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.706748] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.706773] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.706804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.706839] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.706869] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.706975] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.707046] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.707341] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.707393] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.707429] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.707507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  359.707551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  359.707586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  359.707630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  359.707672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  359.707712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  359.707752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  359.707792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  359.707836] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  359.707886] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.707931] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  359.707971] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  359.708049] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  359.708088] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.710259] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  359.710291] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  359.719911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.728560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.737301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.746074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.754835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.763605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.773220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.781997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.790814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.799578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.808336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.817094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.825777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.834368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.842907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.851420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.859911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.868386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  359.872813] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  359.933694] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  359.933714] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  359.933754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  359.934595] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  359.935391] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  359.938309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.938326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.938342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.938359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.943484] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.943501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.948625] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.951109] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  359.951576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  359.951634] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  359.951650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  359.951673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.951715] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  359.951732] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  359.968416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  359.968443] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.968484] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  359.969365] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  359.969385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.969406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  359.969428] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  359.969445] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  359.969464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.969483] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  359.969501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  359.969518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  359.969534] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.969550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.969555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.969570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.969574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  359.969589] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  359.969604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  359.969619] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  359.969634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.969649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.969667] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.969682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.969698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  359.969712] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  359.969727] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  359.969741] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  359.969759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.969778] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  359.969796] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  359.985243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  359.985279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  359.985333] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  360.002539] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  360.002567] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  360.002605] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  360.002639] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  360.002670] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.002726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.002757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.002783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.002807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.002830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.002853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.002876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.002897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.002922] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.002949] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.002975] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.003275] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.003320] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.003360] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.003395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.003429] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.003464] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.003497] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.003526] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.003551] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.004486] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.004836] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.004867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.004901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.004937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.004967] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.005164] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.005197] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.005228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.005257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.005285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.005312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.005322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.005347] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.005354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.005382] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.005409] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.005436] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.005461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.005487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.005518] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.005545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.005571] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.005598] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.005623] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.005650] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.005680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.005715] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.005745] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.005853] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.005878] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.006448] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.006745] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.006779] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.006847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.006882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.006912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.006939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.006966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.007164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.007193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.007221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.007251] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.007285] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.007316] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.007347] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.007383] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  360.007413] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.009571] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  360.009602] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  360.019446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.028116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.036846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.045604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.054364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.063134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.071887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.080648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.089404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.098155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.106916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.115802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.124487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.133077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.141613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.150123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.158609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.167080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.169616] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  360.231074] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  360.231094] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  360.231131] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  360.231958] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  360.232640] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  360.234422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.234443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.234463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.234484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.240385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.240405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.245538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.248026] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  360.248527] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  360.248598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  360.248616] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  360.248641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.248685] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  360.248704] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  360.265400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.265429] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.265474] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.266380] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.266402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.266425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.266450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.266469] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.266490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.266510] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.266530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.266549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.266567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.266584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.266589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.266605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.266609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.266627] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.266643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.266660] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.266677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.266693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.266713] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.266730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.266747] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.266764] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.266780] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.266796] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.266816] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.266838] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.266857] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.282209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  360.282245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  360.282299] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  360.301146] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  360.301178] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  360.301222] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  360.301262] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  360.301298] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.301363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.301399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.301429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.301457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.301484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.301511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.301537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.301563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.301593] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.301625] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.301655] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.301684] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.301730] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.301769] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.301802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.301832] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.301864] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.301896] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.301925] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.301950] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.302931] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.303422] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.303456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.303491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.303528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.303558] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.303590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.303622] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.303652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.303681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.303708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.303734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.303741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.303767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.303773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.303799] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.303825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.303851] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.303876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.303901] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.303933] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.303958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.304131] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.304173] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.304215] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.304255] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.304302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.304351] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.304383] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.304490] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.304515] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.304799] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.304835] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.304861] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.304912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.304945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.304973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.305137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.305180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.305222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.305262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.305302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.305344] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.305377] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.305409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.305439] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.305475] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  360.305505] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.307695] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  360.307728] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  360.317457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.326113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.334844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.343606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.352376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.361146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.369903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.378855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.387619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.396375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.405138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.413896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.422585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.431181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.439720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.448233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.456720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.465194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.469621] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  360.530013] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  360.530032] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  360.530066] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  360.530885] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  360.531609] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  360.534187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.534207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.534225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.534244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.539623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.539640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.544780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.547277] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  360.547743] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  360.547788] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  360.547805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  360.547827] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.547869] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  360.547885] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  360.564583] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.564610] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.564651] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.565544] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.565564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.565585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.565607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.565624] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.565643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.565662] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.565680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.565697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.565713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.565729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.565734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.565750] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.565753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.565769] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.565785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.565800] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.565814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.565829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.565847] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.565862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.565878] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.565893] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.565908] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.565922] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.565940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.565960] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.566092] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.581389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  360.581425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  360.581480] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  360.598816] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  360.598848] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  360.598892] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  360.598932] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  360.598967] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.599246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.599302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.599345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.599388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.599424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.599462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.599495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.599532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.599568] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.599612] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.599656] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.599698] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.599757] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.599811] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.599855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.599899] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.599947] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.600148] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.600191] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.600230] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.600672] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.601143] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.601176] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.601213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.601250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.601280] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.601312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.601344] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.601373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.601402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.601429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.601455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.601463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.601489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.601495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.601522] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.601548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.601574] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.601599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.601624] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.601655] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.601681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.601708] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.601734] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.601759] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.601784] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.601814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.601849] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.601878] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.602179] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.602218] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.602516] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.602567] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.602606] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.602719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.602765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.602800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.602841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.602873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.602911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.602943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.602983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.603150] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.603195] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.603240] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.603282] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.603330] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  360.603366] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.605535] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  360.605567] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  360.615353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.624004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.632796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.641556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.650324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.659080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.667841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.676603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.685361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.694114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.702865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.711620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.720305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.728895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.737435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.745941] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.754517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.762992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.767415] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  360.827863] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  360.827882] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  360.827923] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  360.828756] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  360.829481] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  360.832062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.832081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.832099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.832118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.837499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.837516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.842639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.845121] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  360.845588] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  360.845647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  360.845663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  360.845685] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.845727] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  360.845743] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  360.862483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.862516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.862566] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.863603] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.863625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.863649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.863673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.863693] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.863714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.863736] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.863755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.863774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.863792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.863809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.863815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.863832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.863835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.863853] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.863870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.863887] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.863904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.863921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.863941] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.863958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.864106] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.864160] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.864182] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.864206] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.864232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.864262] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.864286] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.879261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  360.879297] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  360.879352] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  360.896695] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  360.896728] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  360.896772] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  360.896813] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  360.896849] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.896914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.896949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.896979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.897215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.897257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.897301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.897335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.897373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.897409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.897454] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.897497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.897539] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.897598] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.897652] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.897754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  360.897798] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  360.897845] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.897895] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.897937] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.897977] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.898571] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.898947] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  360.898979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.899113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  360.899164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  360.899200] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  360.899242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.899280] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  360.899320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.899355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  360.899394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.899426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.899437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.899471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.899480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  360.899517] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  360.899549] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  360.899586] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.899617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.899653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.899691] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.899727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.899761] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  360.899798] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  360.899830] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  360.899865] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  360.899902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.899947] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  360.899984] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.900321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.900360] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.900659] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.900709] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.900749] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.900864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  360.900910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  360.900945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  360.900987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  360.901143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  360.901172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  360.901199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  360.901226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  360.901255] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  360.901287] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  360.901318] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  360.901348] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  360.901384] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  360.901414] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.903604] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  360.903637] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  360.913469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.922122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.930868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.939625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.948387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.957141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.965900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.974977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.983837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.992599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.001369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.010136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.018803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.027390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.035933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.044443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.052933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.061408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.065836] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  361.125736] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  361.125754] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  361.125787] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  361.126612] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  361.127337] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  361.129944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.129963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.130056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.130078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.135384] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.135402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  361.140526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.143006] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  361.143473] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.143535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  361.143552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  361.143574] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  361.143616] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.143632] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.160350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  361.160381] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.160423] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.161353] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  361.161374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.161395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  361.161417] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  361.161435] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  361.161454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.161472] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.161490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.161507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  361.161523] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.161538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.161543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.161558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.161561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.161577] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  361.161592] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  361.161607] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.161622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.161636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.161654] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.161669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.161685] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  361.161699] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  361.161714] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  361.161727] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  361.161745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.161765] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  361.161782] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.177138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  361.177174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  361.177229] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  361.194484] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  361.194516] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  361.194561] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  361.194600] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  361.194636] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  361.194702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.194738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  361.194768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  361.194797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  361.194824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  361.194852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  361.194878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  361.194905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  361.194935] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  361.194966] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.195524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  361.195558] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  361.195602] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  361.195641] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  361.195677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  361.195710] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.195744] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.195777] [drm:intel_power_well_disable [i915]] disabling DC off
>[  361.195806] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  361.195831] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  361.196834] [drm:intel_power_well_disable [i915]] disabling always-on
>[  361.197324] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  361.197357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.197393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  361.197430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  361.197460] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  361.197492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.197524] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.197553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.197582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  361.197609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.197636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.197643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.197669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.197675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.197701] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  361.197727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  361.197754] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.197780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.197804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.197836] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.197861] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.197888] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  361.197913] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  361.197938] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  361.197962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  361.198551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.198599] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  361.198636] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.198794] [drm:intel_power_well_enable [i915]] enabling always-on
>[  361.198826] [drm:intel_power_well_enable [i915]] enabling DC off
>[  361.199165] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  361.199216] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  361.199255] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  361.199325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.199372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  361.199427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  361.199474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  361.199514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  361.199560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  361.199600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  361.199645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  361.199688] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  361.199740] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.199792] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  361.199842] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  361.199900] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  361.199943] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  361.202173] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  361.202211] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  361.212005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.220872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.229682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.238485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.247305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.256113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.264984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.273840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.282617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.291391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.300165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.308976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.317632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.326189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.334719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.343226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.351713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.360182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.364593] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  361.424746] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  361.424766] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  361.424808] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  361.425643] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  361.426351] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  361.428158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.428177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.428195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.428214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.434067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.434084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  361.439202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.441590] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  361.442114] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.442159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  361.442176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  361.442198] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  361.442241] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.442258] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.458975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  361.459017] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.459058] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.459967] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  361.460118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.460138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  361.460160] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  361.460178] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  361.460198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.460216] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.460234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.460251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  361.460268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.460283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.460288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.460303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.460307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.460322] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  361.460337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  361.460352] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.460367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.460382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.460400] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.460415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.460431] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  361.460446] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  361.460460] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  361.460475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  361.460495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.460515] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  361.460532] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.475769] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  361.475802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  361.475852] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  361.493047] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  361.493072] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  361.493105] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  361.493135] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  361.493162] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  361.493212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.493239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  361.493262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  361.493282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  361.493303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  361.493323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  361.493343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  361.493362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  361.493384] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  361.493407] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.493430] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  361.493451] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  361.493486] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  361.493516] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  361.493541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  361.493564] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.493588] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.493612] [drm:intel_power_well_disable [i915]] disabling DC off
>[  361.493634] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  361.493653] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  361.494156] [drm:intel_power_well_disable [i915]] disabling always-on
>[  361.495034] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  361.495074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.495115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  361.495157] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  361.495193] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  361.495231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.495269] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.495306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.495342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  361.495376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.495410] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.495419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.495450] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.495458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.495491] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  361.495527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  361.495562] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.495596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.495630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.495669] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.495702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.495738] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  361.495774] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  361.495808] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  361.495841] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  361.495880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.495920] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  361.495958] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.496124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  361.496157] [drm:intel_power_well_enable [i915]] enabling DC off
>[  361.496451] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  361.496496] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  361.496530] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  361.496591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.496633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  361.496669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  361.496705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  361.496740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  361.496774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  361.496808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  361.496842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  361.496877] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  361.496916] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.496953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  361.497025] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  361.497069] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  361.497107] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  361.499277] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  361.499304] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  361.508938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.517589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.526234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.534898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.543559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.552220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.560922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.569673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.578335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.586995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.595699] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.604358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.612983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.621574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.630099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.638597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.647077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.655547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.661659] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  361.722542] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  361.722564] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  361.722608] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  361.723232] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  361.724052] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  361.724769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.724789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.724807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.724826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.730575] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.730594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  361.735751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.738234] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  361.738735] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.738812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  361.738829] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  361.738854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  361.738898] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.738917] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.755608] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  361.755637] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.755682] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.755893] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  361.755916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.755940] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  361.755965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  361.756028] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  361.756061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.756087] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.756115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.756139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  361.756166] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.756189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.756197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.756219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.756225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.756250] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  361.756273] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  361.756298] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.756318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.756342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.756366] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.756390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.756416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  361.756437] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  361.756461] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  361.756481] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  361.756508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.756538] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  361.756561] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.772423] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  361.772458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  361.772527] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  361.791170] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  361.791210] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  361.791263] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  361.791311] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  361.791355] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  361.791434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.791477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  361.791513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  361.791548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  361.791581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  361.791614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  361.791647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  361.791679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  361.791714] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  361.791754] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.791792] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  361.791828] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  361.791886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  361.791926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.791969] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.802288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.810959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.819783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.828631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.837426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.846185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.854988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.863810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.872574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.881329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.890086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.898833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.907571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.916168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.924730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.933221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.941681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.950126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.954245] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  361.954290] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  361.954306] [drm:intel_power_well_disable [i915]] disabling DC off
>[  361.954321] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  361.954335] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  361.954751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  361.954837] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  361.954855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.954874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  361.954894] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  361.954910] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  361.954928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.954945] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.954961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.955064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  361.955108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.955127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.955134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.955153] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.955158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  361.955178] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  361.955196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  361.955217] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.955234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.955255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.955276] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.955295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.955313] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  361.955333] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  361.955351] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  361.955370] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  361.955390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.955415] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  361.955435] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.955522] [drm:intel_power_well_enable [i915]] enabling always-on
>[  361.955543] [drm:intel_power_well_enable [i915]] enabling DC off
>[  361.955820] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  361.955848] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  361.955870] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  361.955935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.955961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  361.956086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  361.956105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  361.956127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  361.956145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  361.956165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  361.956183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  361.956204] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  361.956231] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  361.956254] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  361.956277] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  361.956304] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  361.956323] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  361.958466] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  361.958483] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  361.959601] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  362.014525] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  362.014545] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  362.014577] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  362.015991] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  362.018541] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  362.019872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  362.019888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  362.019903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  362.019918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  362.025036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  362.025051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  362.030167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  362.032647] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  362.033136] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  362.033174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  362.033189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  362.033210] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  362.033254] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  362.033276] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  362.049968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.050008] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.050045] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.050931] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.050948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.050966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.051055] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.051077] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.051098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.051121] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.051140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.051162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.051179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.051199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.051204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.051223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.051228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.051248] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.051264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.051284] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.051301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.051320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.051339] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.051359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.051376] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.051396] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.051412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.051431] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.051451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.051475] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.051494] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.066750] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  362.066779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  362.066830] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  362.084139] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  362.084163] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  362.084196] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  362.084227] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  362.084254] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  362.084304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.084331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.084353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.084373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.084393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.084413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.084432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.084451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.084473] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.084496] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.084518] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.084540] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.084574] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  362.084605] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  362.084629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.084652] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.084677] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.084701] [drm:intel_power_well_disable [i915]] disabling DC off
>[  362.084722] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  362.084741] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  362.085703] [drm:intel_power_well_disable [i915]] disabling always-on
>[  362.086158] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.086187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.086220] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.086256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.086282] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.086314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.086342] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.086372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.086398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.086426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.086450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.086458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.086483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.086489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.086519] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.086542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.086569] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.086593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.086619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.086647] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.086673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.086703] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.086726] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.086753] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.086775] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.086806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.086839] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.086865] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.086983] [drm:intel_power_well_enable [i915]] enabling always-on
>[  362.087142] [drm:intel_power_well_enable [i915]] enabling DC off
>[  362.087472] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  362.087510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  362.087539] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  362.087595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.087630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.087656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.087685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.087710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.087737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.087760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.087787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.087814] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.087846] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.087877] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.087908] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.087943] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  362.087970] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  362.090237] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  362.090264] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  362.099812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.108387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.116981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.125606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.134196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.142785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.151378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.159963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.168590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.177182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.185773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.194363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.202924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.211446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.219942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.228508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.236975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.245448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.251544] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  362.311228] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  362.311248] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  362.311291] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  362.312127] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  362.312822] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  362.315406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  362.315426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  362.315444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  362.315462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  362.320860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  362.320877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  362.326005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  362.328487] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  362.328954] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  362.329112] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  362.329129] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  362.329153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  362.329200] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  362.329224] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  362.345806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.345832] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.345873] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.346757] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.346778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.346798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.346820] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.346838] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.346856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.346875] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.346892] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.346909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.346924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.346940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.346944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.346959] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.347319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.347348] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.347367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.347385] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.347403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.347420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.347441] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.347458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.347476] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.347494] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.347510] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.347526] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.347547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.347569] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.347588] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.362611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  362.362648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  362.362713] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  362.379883] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  362.379915] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  362.379959] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  362.380353] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  362.380395] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  362.380463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.380500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.380531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.380560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.380587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.380614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.380640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.380666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.380695] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.380727] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.380757] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.380786] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.380829] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  362.380867] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  362.380900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.380930] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.380963] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.381752] [drm:intel_power_well_disable [i915]] disabling DC off
>[  362.381795] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  362.381834] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  362.382772] [drm:intel_power_well_disable [i915]] disabling always-on
>[  362.383215] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.383249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.383284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.383320] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.383350] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.383382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.383413] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.383443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.383472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.383499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.383525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.383533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.383558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.383564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.383590] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.383615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.383641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.383665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.383690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.383720] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.383746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.383772] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.383797] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.383821] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.383846] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.383876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.383911] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.383940] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.385157] [drm:intel_power_well_enable [i915]] enabling always-on
>[  362.385197] [drm:intel_power_well_enable [i915]] enabling DC off
>[  362.385495] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  362.385548] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  362.385588] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  362.385663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.385712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.385754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.385796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.385836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.385876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.385916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.385956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.386047] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.386097] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.386142] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.386187] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.386238] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  362.386281] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  362.388469] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  362.388508] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  362.398248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.406921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.415795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.424496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.433192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.441844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.450501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.459193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.467850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.476509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.485166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.493768] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.502317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.510833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.519326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.527801] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.536265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.544736] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.549146] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  362.609263] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  362.609283] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  362.609317] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  362.610621] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  362.613177] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  362.614508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  362.614524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  362.614539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  362.614554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  362.619669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  362.619684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  362.624801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  362.627283] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  362.627721] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  362.627755] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  362.627770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  362.627791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  362.627835] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  362.627856] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  362.644533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.644555] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.644591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.645492] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.645509] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.645528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.645548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.645563] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.645580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.645597] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.645613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.645629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.645644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.645658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.645662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.645675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.645679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.645693] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.645706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.645720] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.645733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.645746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.645763] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.645776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.645790] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.645804] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.645817] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.645830] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.645846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.645863] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.645879] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.661357] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  362.661390] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  362.661446] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  362.679872] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  362.679900] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  362.679938] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  362.679972] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  362.680247] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  362.680310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.680344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.680370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.680395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.680419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.680442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.680466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.680489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.680514] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.680542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.680568] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.680593] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.680630] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  362.680664] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  362.680692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.680719] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.680746] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.680774] [drm:intel_power_well_disable [i915]] disabling DC off
>[  362.680799] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  362.680820] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  362.682025] [drm:intel_power_well_disable [i915]] disabling always-on
>[  362.682326] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.682353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.682382] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.682412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.682437] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.682464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.682491] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.682516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.682541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.682564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.682587] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.682593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.682615] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.682620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.682642] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.682664] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.682686] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.682707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.682728] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.682755] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.682776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.682799] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.682820] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.682842] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.682863] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.682888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.682918] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.682943] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.683702] [drm:intel_power_well_enable [i915]] enabling always-on
>[  362.683725] [drm:intel_power_well_enable [i915]] enabling DC off
>[  362.684063] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  362.684109] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  362.684144] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  362.684211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.684254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.684286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.684320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.684348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.684380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.684408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.684440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.684470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.684508] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.684545] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.684581] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.684622] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  362.684653] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  362.686820] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  362.686847] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  362.696487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.705084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.713782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.722488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.731147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.739805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.748489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.757186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.765849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.774512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.783173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.791826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.800439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.809016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.817539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.826035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.834512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.842989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.849084] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  362.909661] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  362.909681] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  362.909718] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  362.910548] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  362.911244] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  362.913831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  362.913852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  362.913872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  362.913893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  362.919279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  362.919298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  362.924431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  362.926904] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  362.927476] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  362.927542] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  362.927560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  362.927586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  362.927638] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  362.927664] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  362.944322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.944349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.944392] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.945300] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.945321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.945344] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.945368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.945387] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.945408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.945428] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.945447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.945466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.945484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.945501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.945505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.945522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.945526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.945543] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.945560] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.945576] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.945592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.945609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.945629] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.945645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.945662] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.945679] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.945696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.945712] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.945732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.945753] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.945772] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.961154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  362.961190] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  362.961258] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  362.979913] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  362.979953] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  362.980615] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  362.980666] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  362.980711] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  362.980789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.980832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.980868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.980903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.980937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.980970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.981147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.981197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.981253] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.981303] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.981342] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.981380] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.981431] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  362.981479] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  362.981520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  362.981560] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  362.981600] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.981641] [drm:intel_power_well_disable [i915]] disabling DC off
>[  362.981677] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  362.981710] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  362.982668] [drm:intel_power_well_disable [i915]] disabling always-on
>[  362.983187] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  362.983226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.983269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  362.983313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  362.983349] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  362.983387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.983425] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  362.983462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  362.983497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  362.983530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  362.983563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.983572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.983604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.983611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  362.983645] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  362.983676] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  362.983708] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.983739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.983770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.983808] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.983839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.983871] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  362.983903] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  362.983934] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  362.983964] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  362.984038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.984081] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  362.984123] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  362.984253] [drm:intel_power_well_enable [i915]] enabling always-on
>[  362.984299] [drm:intel_power_well_enable [i915]] enabling DC off
>[  362.984607] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  362.984679] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  362.984731] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  362.984826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  362.984888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  362.984942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  362.984997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  362.985081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  362.985124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.985163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.985213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  362.985268] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  362.985328] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  362.985384] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  362.985438] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  362.985483] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  362.985520] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  362.987700] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  362.987738] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  362.997584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.006383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.015213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.024037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.032936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.042092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.050911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.059955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.068841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.077664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.086489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.095308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.103987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.112617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.121156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.129669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.138159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.146634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.149395] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  363.208497] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  363.208520] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  363.208556] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  363.209827] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  363.212382] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  363.213732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  363.213750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  363.213766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  363.213783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  363.218907] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  363.218925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  363.224051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  363.226534] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  363.227067] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  363.227110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  363.227126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  363.227149] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  363.227197] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  363.227220] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  363.243900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  363.243924] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  363.243962] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.244929] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  363.244949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  363.244969] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  363.245051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  363.245078] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  363.245105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  363.245125] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  363.245143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  363.245160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  363.245177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  363.245193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  363.245198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.245213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  363.245217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.245232] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  363.245248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  363.245264] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  363.245279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  363.245294] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  363.245313] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  363.245328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  363.245344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  363.245360] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  363.245375] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  363.245389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  363.245408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.245427] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  363.245446] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  363.260700] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  363.260731] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  363.260787] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  363.279081] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  363.279109] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  363.279146] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  363.279181] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  363.279211] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  363.279268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  363.279299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  363.279324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  363.279349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  363.279373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  363.279396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  363.279420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  363.279442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  363.279467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  363.279494] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.279520] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  363.279545] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  363.279584] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  363.279617] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  363.279646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  363.279673] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  363.279701] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.279729] [drm:intel_power_well_disable [i915]] disabling DC off
>[  363.279753] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  363.279774] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  363.280744] [drm:intel_power_well_disable [i915]] disabling always-on
>[  363.281233] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  363.281261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  363.281291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  363.281323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  363.281348] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  363.281375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  363.281402] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  363.281427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  363.281452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  363.281475] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  363.281498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  363.281505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.281527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  363.281532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.281555] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  363.281576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  363.281611] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  363.281636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  363.281660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  363.281691] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  363.281716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  363.281743] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  363.281768] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  363.281793] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  363.281817] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  363.281848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.281882] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  363.281911] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  363.282192] [drm:intel_power_well_enable [i915]] enabling always-on
>[  363.282234] [drm:intel_power_well_enable [i915]] enabling DC off
>[  363.282536] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  363.282595] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  363.282637] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  363.282701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  363.282737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  363.282768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  363.282798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  363.282826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  363.282854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  363.282881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  363.282907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  363.282936] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  363.282969] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.283147] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  363.283193] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  363.283246] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  363.283292] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  363.285451] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  363.285483] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  363.295156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.303792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.312494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.321192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.329846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.338500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.347192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.355845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.364504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.373207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.381917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.390682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.399247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.407793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.416299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.424786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.433257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.441716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.447811] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  363.507995] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  363.508015] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  363.508053] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  363.508879] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  363.509608] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  363.512197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  363.512218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  363.512238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  363.512258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  363.517642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  363.517661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  363.522800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  363.525283] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  363.525783] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  363.525862] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  363.525880] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  363.525905] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  363.525957] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  363.526062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  363.542655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  363.542684] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  363.542729] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.543620] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  363.543643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  363.543665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  363.543690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  363.543709] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  363.543730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  363.543751] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  363.543771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  363.543790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  363.543808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  363.543825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  363.543830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.543847] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  363.543851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.543868] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  363.543885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  363.543901] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  363.543918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  363.543934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  363.543954] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  363.543970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  363.544101] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  363.544130] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  363.544157] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  363.544184] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  363.544214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.544245] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  363.544265] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  363.559490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  363.559526] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  363.559591] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  363.577785] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  363.577818] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  363.577861] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  363.577902] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  363.577938] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  363.578190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  363.578249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  363.578296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  363.578345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  363.578386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  363.578417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  363.578445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  363.578473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  363.578504] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  363.578538] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.578570] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  363.578602] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  363.578645] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  363.578686] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  363.578720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  363.578751] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  363.578785] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.578819] [drm:intel_power_well_disable [i915]] disabling DC off
>[  363.578848] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  363.578873] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  363.579822] [drm:intel_power_well_disable [i915]] disabling always-on
>[  363.580269] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  363.580301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  363.580335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  363.580372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  363.580401] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  363.580433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  363.580465] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  363.580494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  363.580523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  363.580551] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  363.580578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  363.580586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.580611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  363.580617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.580644] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  363.580670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  363.580695] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  363.580720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  363.580745] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  363.580776] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  363.580802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  363.580829] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  363.580854] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  363.580879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  363.580905] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  363.580935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.580970] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  363.581032] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  363.581139] [drm:intel_power_well_enable [i915]] enabling always-on
>[  363.581165] [drm:intel_power_well_enable [i915]] enabling DC off
>[  363.581463] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  363.581547] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  363.581599] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  363.581693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  363.581755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  363.581805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  363.581840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  363.581873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  363.581907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  363.581940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  363.581973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  363.582054] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  363.582096] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.582133] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  363.582172] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  363.582218] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  363.582257] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  363.584439] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  363.584476] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  363.594227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.602968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.611800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.620567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.629328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.638090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.646847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.655606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.664362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.673133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.681894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.690627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.699237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.707816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.716341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.724856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.733339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.741807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.746218] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  363.806238] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  363.806256] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  363.806314] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  363.807004] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  363.807805] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  363.808521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  363.808539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  363.808556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  363.808573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  363.814314] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  363.814329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  363.819445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  363.821910] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  363.822403] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  363.822451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  363.822465] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  363.822486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  363.822530] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  363.822551] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  363.839240] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  363.839264] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  363.839302] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.840210] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  363.840228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  363.840246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  363.840266] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  363.840282] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  363.840299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  363.840316] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  363.840332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  363.840348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  363.840362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  363.840376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  363.840380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.840394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  363.840397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.840411] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  363.840425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  363.840438] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  363.840452] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  363.840465] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  363.840481] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  363.840495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  363.840509] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  363.840523] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  363.840536] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  363.840549] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  363.840565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.840582] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  363.840598] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  363.856033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  363.856064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  363.856116] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  363.874268] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  363.874292] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  363.874325] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  363.874355] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  363.874381] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  363.874431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  363.874458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  363.874480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  363.874500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  363.874521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  363.874541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  363.874561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  363.874580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  363.874602] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  363.874626] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.874649] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  363.874670] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  363.874705] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  363.874734] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  363.874759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  363.874782] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  363.874806] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.874831] [drm:intel_power_well_disable [i915]] disabling DC off
>[  363.874852] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  363.874871] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  363.875831] [drm:intel_power_well_disable [i915]] disabling always-on
>[  363.876232] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  363.876257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  363.876282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  363.876309] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  363.876331] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  363.876355] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  363.876378] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  363.876400] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  363.876422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  363.876442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  363.876462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  363.876468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.876487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  363.876491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  363.876511] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  363.876530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  363.876549] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  363.876568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  363.876586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  363.876609] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  363.876628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  363.876648] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  363.876667] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  363.876685] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  363.876703] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  363.876725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.876751] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  363.876772] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  363.876851] [drm:intel_power_well_enable [i915]] enabling always-on
>[  363.876869] [drm:intel_power_well_enable [i915]] enabling DC off
>[  363.877257] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  363.877674] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  363.877707] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  363.877767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  363.877805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  363.877829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  363.877852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  363.877873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  363.877894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  363.877914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  363.877934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  363.877956] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  363.878065] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  363.878100] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  363.878135] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  363.878173] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  363.878195] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  363.880346] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  363.880369] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  363.889974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.898554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.907140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.915731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.924324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.932914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.941507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.950099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.958691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.967284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.976581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.985176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  363.993745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.002275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.010783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.019267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.027735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.036195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.040406] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  364.101119] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  364.101140] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  364.101171] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  364.102553] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  364.104312] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  364.106171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.106188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.106204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.106221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.111345] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.111362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  364.116486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.118966] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  364.119446] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  364.119494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  364.119510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  364.119532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  364.119580] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  364.119604] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  364.136287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.136313] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.136354] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.137215] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  364.137235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.137269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  364.137293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  364.137312] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  364.137333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.137354] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  364.137373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  364.137391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  364.137409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.137427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.137431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.137448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.137452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.137469] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  364.137486] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  364.137502] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.137519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.137535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.137555] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.137572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.137589] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  364.137605] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  364.137622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  364.137638] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  364.137658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.137679] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  364.137699] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  364.153134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  364.153170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  364.153233] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  364.170210] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  364.170239] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  364.170276] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  364.170311] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  364.170341] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  364.170398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.170428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.170454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.170478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.170501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.170525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.170547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.170569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.170594] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.170621] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.170647] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.170672] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.170711] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  364.170745] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  364.170774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.170800] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.170828] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.170857] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.170881] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  364.170902] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  364.171881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.173341] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  364.173374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.173409] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  364.173447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  364.173477] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  364.173508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.173540] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  364.173570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  364.173599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  364.173625] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.173651] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.173659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.173684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.173690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.173717] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  364.173742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  364.173767] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.173792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.173817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.173847] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.173873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.173899] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  364.173925] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  364.173950] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  364.173975] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  364.174179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.174230] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  364.174275] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  364.174434] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.174459] [drm:intel_power_well_enable [i915]] enabling DC off
>[  364.174745] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  364.174782] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  364.174815] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  364.174884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.174920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.174949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.174978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.175113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.175155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.175197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.175231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.175261] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.175295] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.175327] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.175359] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.175395] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  364.175425] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  364.177617] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  364.177650] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  364.187460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.196117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.204851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.213616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.222391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.231154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.239913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.248862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.257622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.266387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.275157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.283844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.292437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.300979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.309512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.318002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.326475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.334939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.339151] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  364.400720] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  364.400751] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  364.400789] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  364.401617] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  364.402344] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  364.404935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.404954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.404972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.405044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.410386] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.410403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  364.415526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.418010] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  364.418477] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  364.418536] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  364.418552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  364.418574] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  364.418623] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  364.418647] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  364.435330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.435357] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.435398] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.436294] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  364.436314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.436334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  364.436356] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  364.436374] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  364.436393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.436412] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  364.436430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  364.436447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  364.436463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.436478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.436483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.436499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.436502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.436518] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  364.436532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  364.436547] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.436562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.436576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.436595] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.436610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.436625] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  364.436640] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  364.436654] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  364.436669] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  364.436687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.436706] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  364.436724] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  364.452154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  364.452189] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  364.452252] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  364.470911] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  364.470943] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  364.470987] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  364.471188] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  364.471250] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  364.471347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.471388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.471421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.471453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.471483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.471514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.471542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.471570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.471600] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.471634] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.471666] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.471697] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.471741] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  364.471781] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  364.471815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.471848] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.471881] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.471915] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.471944] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  364.471969] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  364.472585] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.473086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.473505] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.473540] [drm:intel_power_well_enable [i915]] enabling DC off
>[  364.473828] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  364.473876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.473910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.473941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.473970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.474031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.474061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.474094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.474121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.474153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.474186] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.474226] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.474259] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.474306] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.474385] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.474443] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.474490] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  364.474531] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  364.474963] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.475270] [drm:drm_mode_addfb2] [FB:64]
>[  364.475310] [drm:drm_mode_addfb2] [FB:65]
>[  364.547852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  364.548705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  364.549452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  364.550173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  364.550242] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  364.550571] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  364.550668] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.550770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  364.550875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  364.550961] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  364.551203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.551347] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  364.551485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  364.551615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  364.551741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.551862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.551897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.552012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.552107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.552234] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  364.552363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  364.552480] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.552596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.552710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.552817] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.552930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.553051] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  364.553263] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  364.553387] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  364.553529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.553664] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  364.553788] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  364.555736] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.555812] [drm:intel_power_well_enable [i915]] enabling DC off
>[  364.556263] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  364.556717] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  364.556836] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  364.557204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.557349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.557451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.557572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.557671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.557783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.557877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.557984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.558186] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.558325] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.558458] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.558587] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.558732] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  364.558838] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  364.561198] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  364.561288] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  364.571394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.580308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.589149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.597987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.606834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.615472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.624060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.632595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.641104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.649592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.658063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.666520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.674991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.683451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.691910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.700369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.708828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.717287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.721499] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  364.782086] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  364.782105] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  364.782132] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  364.782941] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  364.785492] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  364.787143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.787159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.787173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.787189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.792303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.792319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  364.797433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.799905] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  364.800404] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  364.800439] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  364.800454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  364.800475] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  364.817233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.817257] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  364.817295] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.850863] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  364.850889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.850914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  364.850941] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  364.850962] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  364.851233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.851257] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  364.851277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  364.851297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  364.851315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.851333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.851338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.851356] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.851360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.851377] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  364.851395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  364.851412] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.851429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.851445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.851466] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.851483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.851501] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  364.851517] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  364.851534] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  364.851550] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  364.851571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.851595] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  364.851615] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  364.867396] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  364.867432] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  364.867496] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  364.884870] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  364.884902] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  364.884949] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  364.884988] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  364.885364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.885404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.885435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.885465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.885492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.885520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.885547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.885573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.885603] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.885636] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.885667] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.885697] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.885742] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  364.885782] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  364.885815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  364.885846] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  364.885876] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.885908] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.885936] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  364.885961] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  364.887144] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.887895] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  364.887928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.887964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  364.888209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  364.888240] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  364.888273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.888306] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  364.888336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  364.888364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  364.888391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.888417] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.888425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.888451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.888457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  364.888483] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  364.888509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  364.888534] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.888559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.888584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.888615] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.888641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.888668] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  364.888693] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  364.888718] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  364.888742] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  364.888772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.888807] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  364.888837] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  364.888944] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.888968] [drm:intel_power_well_enable [i915]] enabling DC off
>[  364.890177] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  364.890230] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  364.890272] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  364.890391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.890439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  364.890482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  364.890524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  364.890563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  364.890603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.890641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.890680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  364.890722] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  364.890767] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  364.890810] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  364.890853] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  364.890902] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  364.890945] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  364.891431] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  364.891459] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  364.901148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.909802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.918555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.927323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.936086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.944846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.953605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.962367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.971139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.980134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.988896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.997658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.006342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.014936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.023598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.032109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.040599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.049073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.051611] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  365.112299] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  365.112319] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  365.112365] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  365.113190] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  365.115423] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  365.116825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.116843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.116861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.116879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.122014] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.122033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  365.127166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.129644] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  365.130215] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.130278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  365.130296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.130321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.147074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  365.147104] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.147149] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.148158] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  365.148180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.148204] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  365.148228] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  365.148248] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  365.148268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.148289] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.148309] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.148328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  365.148345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.148363] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.148367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.148384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.148388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.148405] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  365.148422] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  365.148439] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  365.148455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.148472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.148492] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  365.148508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.148526] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  365.148542] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  365.148558] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  365.148574] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  365.148595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.148617] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  365.148636] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  365.163875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.163911] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.163976] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.181786] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  365.181819] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  365.181866] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  365.181904] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  365.181971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.182378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  365.182412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  365.182442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  365.182471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  365.182499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  365.182527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  365.182554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  365.182584] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  365.182616] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.182646] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  365.182676] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  365.182722] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  365.182762] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  365.182795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  365.182826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.182857] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.182889] [drm:intel_power_well_disable [i915]] disabling DC off
>[  365.182917] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  365.182942] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  365.184420] [drm:intel_power_well_disable [i915]] disabling always-on
>[  365.184900] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  365.184940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.184982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  365.185269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  365.185307] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  365.185347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.185386] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.185423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.185457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  365.185489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.185521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.185531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.185562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.185570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.185602] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  365.185634] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  365.185664] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  365.185695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.185725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.185763] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  365.185795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.185828] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  365.185859] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  365.185890] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  365.185920] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  365.185957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.186914] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  365.186967] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  365.187301] [drm:intel_power_well_enable [i915]] enabling always-on
>[  365.187349] [drm:intel_power_well_enable [i915]] enabling DC off
>[  365.187653] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  365.187715] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  365.187763] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  365.187906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.187964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  365.188261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  365.188298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  365.188333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  365.188368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  365.188401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  365.188433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  365.188469] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  365.188509] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.188547] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  365.188583] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  365.188627] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  365.188664] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  365.190842] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  365.190880] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  365.200651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.209411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.218182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.227012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.235837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.244601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.253364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.262127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.270886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.279653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.288426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.297099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.305689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.314232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.322742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.331231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.339704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.348167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.352389] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  365.413523] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  365.413542] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  365.413586] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  365.414416] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  365.415109] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  365.417670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.417688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.417705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.417722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.423188] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.423204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  365.428321] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.430785] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  365.431280] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.431327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  365.431341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.431362] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.448123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  365.448147] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.448185] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.449156] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  365.449174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.449193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  365.449213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  365.449229] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  365.449246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.449263] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.449279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.449294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  365.449309] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.449323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.449326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.449340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.449343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.449358] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  365.449371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  365.449385] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  365.449398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.449411] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.449428] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  365.449441] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.449455] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  365.449468] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  365.449482] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  365.449495] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  365.449511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.449529] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  365.449545] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  365.464910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.464939] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.465044] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.482257] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  365.482282] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  365.482317] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  365.482345] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  365.482397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.482423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  365.482445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  365.482467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  365.482487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  365.482508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  365.482527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  365.482547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  365.482569] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  365.482593] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.482615] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  365.482636] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  365.482672] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  365.482702] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  365.482726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  365.482749] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.482772] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.482796] [drm:intel_power_well_disable [i915]] disabling DC off
>[  365.482817] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  365.482836] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  365.483327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  365.484029] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  365.484052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.484078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  365.484105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  365.484126] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  365.484150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.484173] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.484195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.484216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  365.484236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.484255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.484261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.484280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.484284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.484303] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  365.484322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  365.484341] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  365.484360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.484378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.484400] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  365.484419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.484439] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  365.484458] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  365.484477] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  365.484496] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  365.484518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.484544] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  365.484566] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  365.484646] [drm:intel_power_well_enable [i915]] enabling always-on
>[  365.484665] [drm:intel_power_well_enable [i915]] enabling DC off
>[  365.484943] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  365.484969] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  365.485046] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  365.485109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.485146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  365.485175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  365.485205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  365.485234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  365.485262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  365.485289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  365.485317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  365.485347] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  365.485382] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.485416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  365.485449] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  365.485486] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  365.485517] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  365.487712] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  365.487740] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  365.497427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.506046] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.514676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.523341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.532003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.540711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.549373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.558046] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.566712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.575376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.584038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.592691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.601344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.609935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.618631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.627140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.635642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.644116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.650212] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  365.709957] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  365.709975] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  365.710014] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  365.710840] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  365.711547] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  365.713298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.713316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.713332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.713349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.719222] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.719238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  365.724378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.726830] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  365.727328] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.727385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  365.727400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.727421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.744204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  365.744229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.744267] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.745182] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  365.745200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.745219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  365.745239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  365.745254] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  365.745271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.745287] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.745303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.745319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  365.745333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.745348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.745352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.745366] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.745369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.745383] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  365.745398] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  365.745411] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  365.745425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.745438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.745455] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  365.745469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.745483] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  365.745497] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  365.745510] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  365.745523] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  365.745539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.745557] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  365.745573] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  365.760971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.761028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.761075] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.778217] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  365.778239] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  365.778271] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  365.778296] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  365.778343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.778367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  365.778387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  365.778406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  365.778424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  365.778442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  365.778460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  365.778476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  365.778495] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  365.778517] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.778536] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  365.778555] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  365.778586] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  365.778614] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  365.778636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  365.778657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.778677] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.778698] [drm:intel_power_well_disable [i915]] disabling DC off
>[  365.778717] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  365.778734] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  365.779232] [drm:intel_power_well_disable [i915]] disabling always-on
>[  365.780048] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  365.780081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.780111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  365.780146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  365.780173] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  365.780205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.780232] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.780262] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.780288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  365.780316] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.780340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.780348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.780374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.780380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  365.780407] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  365.780431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  365.780458] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  365.780481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.780507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.780535] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  365.780562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.780587] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  365.780614] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  365.780638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  365.780664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  365.780696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.780731] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  365.780757] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  365.780873] [drm:intel_power_well_enable [i915]] enabling always-on
>[  365.780896] [drm:intel_power_well_enable [i915]] enabling DC off
>[  365.781203] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  365.781241] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  365.781271] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  365.781358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.781392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  365.781426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  365.781452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  365.781481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  365.781505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  365.781532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  365.781556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  365.781585] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  365.781618] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  365.781650] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  365.781680] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  365.781716] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  365.781742] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  365.783928] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  365.783953] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  365.793646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.802194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.810770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.819368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.827959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.836585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.845177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.853764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.862357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.870944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.879698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.888291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.896865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.905395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.913909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.922398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.930875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.939337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  365.945432] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  366.006261] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  366.006280] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  366.006322] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  366.007156] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  366.007844] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  366.010427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  366.010446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  366.010464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  366.010483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  366.015864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  366.015881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  366.021006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  366.023488] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  366.023960] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  366.024117] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  366.024134] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  366.024158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  366.040910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.040937] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.041073] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.041954] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.041974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.042098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.042120] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.042137] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.042157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.042175] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.042193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.042211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.042227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.042243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.042248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.042263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.042267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.042282] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.042297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.042312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.042327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.042342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.042360] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.042375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.042391] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.042405] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.042420] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.042435] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.042455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.042474] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.042492] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.057655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  366.057683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  366.057735] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  366.074628] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  366.074652] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  366.074688] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  366.074717] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  366.074768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.074795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.074817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.074839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.074860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.074881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.074901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.074920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.074942] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.074966] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.075379] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.075403] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.075437] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  366.075468] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  366.075494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.075518] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.075542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.075566] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.075588] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  366.075607] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  366.076533] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.076826] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.076853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.076882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.076913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.076938] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.076964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.077221] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.077247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.077273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.077297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.077321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.077328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.077350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.077355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.077378] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.077401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.077423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.077444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.077466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.077492] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.077514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.077537] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.077559] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.077580] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.077601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.077627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.077657] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.077683] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.077774] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.077796] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.078660] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  366.078950] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  366.078976] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  366.079163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.079193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.079218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.079242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.079265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.079288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.079310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.079332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.079358] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.079385] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.079411] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.079436] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.079466] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  366.079491] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  366.081649] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  366.081676] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  366.091362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.099949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.108699] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.117292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.125885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.134476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.143070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.151659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.160248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.168837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.178353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.186924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.195452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.203955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.212522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.220992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.229451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.237909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.242319] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  366.303032] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  366.303052] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  366.303093] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  366.303922] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  366.304625] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  366.307210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  366.307230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  366.307248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  366.307266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  366.312649] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  366.312667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  366.317808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  366.320296] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  366.320768] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  366.320817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  366.320833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  366.320855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  366.337608] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.337649] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.337694] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.338609] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.338631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.338654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.338678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.338698] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.338718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.338739] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.338759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.338778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.338796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.338813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.338817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.338834] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.338838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.338855] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.338872] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.338889] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.338905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.338921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.338941] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.338958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.338975] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.339465] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.339485] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.339504] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.339525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.339548] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.339568] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.354361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  366.354392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  366.354451] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  366.373560] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  366.373591] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  366.373638] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  366.373676] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  366.373742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.373778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.373807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.373836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.373863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.373891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.373918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.373944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.373973] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.374483] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.374517] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.374548] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.374592] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  366.374631] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  366.374665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.374698] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.374729] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.374761] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.374789] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  366.374814] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  366.375945] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.376879] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.376919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.376961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.377210] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.377264] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.377308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.377348] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.377385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.377421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.377455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.377488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.377498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.377529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.377536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.377569] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.377601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.377632] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.377662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.377693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.377731] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.377762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.377795] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.377826] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.377855] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.377887] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.377924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.377967] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.378576] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.378742] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.378789] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.379154] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  366.379613] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  366.379664] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  366.379755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.379814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.379867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.379918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.379968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.380060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.380114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.380166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.380219] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.380277] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.380332] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.380385] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.380446] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  366.380499] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  366.382721] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  366.382761] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  366.392570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.401343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.410145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.418927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.427810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.436585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.445353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.454118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.462881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.471641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.480420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.489095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.497678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.506220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.514730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.523220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.531705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.540168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.544578] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  366.604893] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  366.604986] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  366.605237] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  366.606360] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  366.607726] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  366.611220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  366.611310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  366.611393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  366.611478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  366.617312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  366.617392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  366.622840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  366.625555] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  366.627564] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  366.627700] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  366.627776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  366.627872] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  366.644641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.644753] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.644915] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.646829] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.646913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.646999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.647389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.647502] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.647620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.647735] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.647842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.647947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.648051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.648395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.648421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.648514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.648536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.648636] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.648734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.648833] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.648933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.649029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.649431] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.649533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.649639] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.649738] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.649838] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.649939] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.650053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.650419] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.650496] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.661489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  366.661610] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  366.661834] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  366.678807] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  366.678900] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  366.679032] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  366.679340] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  366.679587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.679694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.679779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.679864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.679942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.680032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.680220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.680327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.680435] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.680577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.680680] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.680770] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.680897] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  366.681007] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  366.681220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.681335] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.681466] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.681572] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.681654] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  366.681728] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  366.682751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.684300] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.684391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.684491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.684596] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.684680] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.684769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.684858] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.684941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.685023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.685223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.685322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.685356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.685451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.685479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.685576] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.685670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.685765] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.685856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.685967] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.686155] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.686253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.686377] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.686455] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.686527] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.686597] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.686687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.686790] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.686875] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.687331] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.687405] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.687740] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  366.687843] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  366.687940] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  366.688237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.688380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.688468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.688553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.688632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.688714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.688789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.688864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.688948] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.689134] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.689249] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.689359] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.689507] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  366.689639] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  366.691997] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  366.692151] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  366.702254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.711126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.719965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.728853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.737689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.746597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.755433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.764380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.773221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.781973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.790631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.799187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.807705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.816201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.824679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.833145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.841603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.850060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.854467] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  366.915201] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  366.915221] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  366.915262] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  366.916094] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  366.916808] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  366.919390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  366.919409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  366.919427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  366.919446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  366.924829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  366.924846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  366.929970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  366.932463] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  366.932935] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  366.933050] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  366.933070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  366.933101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  366.949784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.949811] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.949852] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.950734] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.950754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.950775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.950796] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.950814] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.950832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.950851] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.950869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.950886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.950902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.950918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.950922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.950937] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.950940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.950956] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.950971] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.951081] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.951127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.951146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.951171] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.951190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.951213] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.951237] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.951255] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.951277] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.951298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.951324] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.951345] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.966523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  366.966551] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  366.966602] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  366.983918] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  366.983947] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  366.983987] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  366.984186] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  366.984276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.984312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.984340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.984365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.984391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.984415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.984439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.984462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.984488] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.984516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.984542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.984567] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.984605] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  366.984639] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  366.984667] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  366.984693] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  366.984719] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.984746] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.984770] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  366.984791] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  366.985774] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.986344] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  366.986377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.986413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  366.986450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  366.986479] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  366.986511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.986542] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  366.986572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  366.986600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  366.986628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  366.986654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.986662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.986688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.986694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  366.986720] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  366.986746] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  366.986771] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.986796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.986821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.986852] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.986878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.986905] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  366.986931] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  366.986956] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  366.986980] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  366.987193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.987286] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  366.987322] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  366.987474] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.987511] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.987809] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  366.987859] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  366.987899] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  366.987969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  366.988123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  366.988164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  366.988198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  366.988236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  366.988269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.988307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.988339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  366.988380] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  366.988427] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  366.988471] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  366.988514] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  366.988562] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  366.988598] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  366.990762] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  366.990793] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  367.000478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.009119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.017775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.026432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.035083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.043782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.052475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.061121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.069767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.078559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.087213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.095874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.104432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.112954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.121526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.130007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.138475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.146935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.153028] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  367.214876] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  367.214973] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  367.215177] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  367.216401] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  367.218060] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  367.221061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  367.221219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  367.221304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  367.221391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  367.227026] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  367.227171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  367.232628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  367.235349] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  367.237353] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  367.237488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  367.237563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  367.237660] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  367.254426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  367.254536] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  367.254694] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.256263] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  367.256346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.256431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  367.256520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  367.256593] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  367.256670] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.256747] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  367.256818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  367.256888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  367.256955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  367.257118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.257152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.257255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.257280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.257388] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  367.257474] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  367.257571] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.257652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.257745] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.257839] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  367.257932] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.258037] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  367.258186] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  367.258267] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  367.258361] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  367.258467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  367.258578] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  367.258663] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  367.271510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  367.271639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  367.271870] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  367.289492] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  367.289599] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  367.289754] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  367.289882] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  367.290250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  367.290374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  367.290477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  367.290575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  367.290672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  367.290765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  367.290857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  367.290962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  367.291131] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  367.291226] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.291319] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  367.291408] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  367.291534] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  367.291643] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  367.291739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  367.291832] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  367.291921] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.292020] [drm:intel_power_well_disable [i915]] disabling DC off
>[  367.292188] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  367.292262] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  367.292745] [drm:intel_power_well_disable [i915]] disabling always-on
>[  367.294295] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  367.294385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.294481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  367.294584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  367.294667] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  367.294757] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.294846] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  367.294930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  367.295046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  367.295247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  367.295344] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.295373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.295461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.295481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.295577] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  367.295670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  367.295760] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.295849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.295935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.296099] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  367.296174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.296251] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  367.296326] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  367.296403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  367.296474] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  367.296564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  367.296664] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  367.296750] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  367.297129] [drm:intel_power_well_enable [i915]] enabling always-on
>[  367.297202] [drm:intel_power_well_enable [i915]] enabling DC off
>[  367.297533] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  367.297634] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  367.297745] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  367.297929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  367.298029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  367.298191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  367.298270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  367.298351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  367.298426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  367.298503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  367.298577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  367.298663] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  367.298754] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.298841] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  367.298928] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  367.299028] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  367.299196] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  367.301455] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  367.301545] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  367.311890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.321189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.330150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.339113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.347958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.356823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.365641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.375226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.384044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.392834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.401446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.410018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.418531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.427025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.435500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.443962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.452432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.460888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.463611] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  367.524372] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  367.524391] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  367.524427] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  367.525256] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  367.525935] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  367.527689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  367.527708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  367.527725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  367.527744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  367.533619] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  367.533639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  367.538822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  367.541306] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  367.541811] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  367.541883] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  367.541901] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  367.541925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  367.558666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  367.558693] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  367.558737] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.559654] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  367.559676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.559699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  367.559723] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  367.559742] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  367.559763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.559784] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  367.559803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  367.559822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  367.559840] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  367.559857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.559862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.559879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.559882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.559900] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  367.559917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  367.559933] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.559950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.559966] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.560022] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  367.560052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.560082] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  367.560110] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  367.560137] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  367.560164] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  367.560194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  367.560226] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  367.560256] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  367.575388] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  367.575418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  367.575464] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  367.592793] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  367.592825] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  367.592872] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  367.592910] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  367.592976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  367.593109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  367.593159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  367.593211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  367.593256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  367.593301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  367.593347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  367.593393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  367.593438] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  367.593486] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.593530] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  367.593574] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  367.593634] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  367.593690] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  367.593738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  367.593783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  367.593827] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.593874] [drm:intel_power_well_disable [i915]] disabling DC off
>[  367.593917] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  367.593957] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  367.594439] [drm:intel_power_well_disable [i915]] disabling always-on
>[  367.594821] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  367.594853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.594887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  367.594924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  367.594953] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  367.594985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.595071] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  367.595110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  367.595156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  367.595200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  367.595242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.595255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.595292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.595303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.595342] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  367.595383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  367.595423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.595463] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.595503] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.595549] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  367.595588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.595630] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  367.595669] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  367.595709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  367.595748] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  367.595794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  367.595841] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  367.595885] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  367.596082] [drm:intel_power_well_enable [i915]] enabling always-on
>[  367.596123] [drm:intel_power_well_enable [i915]] enabling DC off
>[  367.596417] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  367.596468] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  367.596509] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  367.596581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  367.596629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  367.596672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  367.596712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  367.596752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  367.596791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  367.596830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  367.596869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  367.596911] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  367.596972] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.597071] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  367.597128] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  367.597190] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  367.597242] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  367.599468] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  367.599507] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  367.609277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.617999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.626837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.635609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.644378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.653138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.661895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.670654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.679427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.688195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.697011] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.705781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.714392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.722958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.731557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.740078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.748560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.757027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.761438] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  367.823021] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  367.823040] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  367.823082] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  367.823912] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  367.824616] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  367.827198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  367.827217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  367.827235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  367.827255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  367.832636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  367.832653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  367.837808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  367.840291] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  367.840762] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  367.840816] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  367.840833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  367.840855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  367.857595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  367.857619] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  367.857660] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.858559] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  367.858579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.858600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  367.858621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  367.858639] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  367.858658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.858676] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  367.858693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  367.858710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  367.858725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  367.858741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.858746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.858760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.858764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.858779] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  367.858794] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  367.858809] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.858824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.858838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.858856] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  367.858871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.858887] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  367.858902] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  367.858917] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  367.858931] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  367.858949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  367.858968] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  367.859453] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  367.874351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  367.874379] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  367.874420] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  367.891627] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  367.891656] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  367.891697] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  367.891730] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  367.891789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  367.891820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  367.891846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  367.891870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  367.891894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  367.891916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  367.891939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  367.891960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  367.892386] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  367.892416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.892443] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  367.892468] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  367.892506] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  367.892541] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  367.892570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  367.892598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  367.892624] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.892651] [drm:intel_power_well_disable [i915]] disabling DC off
>[  367.892675] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  367.892697] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  367.893695] [drm:intel_power_well_disable [i915]] disabling always-on
>[  367.894103] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  367.894131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.894160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  367.894191] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  367.894216] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  367.894243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.894270] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  367.894295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  367.894320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  367.894343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  367.894366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.894373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.894395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.894399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  367.894422] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  367.894444] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  367.894466] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.894488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.894509] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.894535] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  367.894557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.894580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  367.894602] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  367.894623] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  367.894644] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  367.894670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  367.894700] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  367.894725] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  367.894816] [drm:intel_power_well_enable [i915]] enabling always-on
>[  367.894837] [drm:intel_power_well_enable [i915]] enabling DC off
>[  367.895821] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  367.896186] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  367.896227] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  367.896323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  367.896362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  367.896393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  367.896423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  367.896451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  367.896480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  367.896508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  367.896535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  367.896565] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  367.896598] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  367.896630] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  367.896660] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  367.896696] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  367.896726] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  367.898868] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  367.898896] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  367.908580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.917211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.925914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.934574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.943235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.951891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.960546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.969201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.978689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.987346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  367.996001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.004674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.013238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.021794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.030304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.038791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.047264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.055740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.061834] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  368.122573] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  368.122593] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  368.122631] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  368.123481] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  368.124212] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  368.126793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  368.126812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  368.126831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.126849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  368.132233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  368.132250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  368.137386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  368.139860] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  368.140429] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  368.140496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  368.140512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  368.140535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  368.157287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  368.157314] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.157355] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.158243] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  368.158263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.158284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  368.158306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  368.158323] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  368.158342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.158361] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  368.158378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  368.158396] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  368.158412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.158428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.158432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.158447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.158450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.158465] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  368.158481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  368.158496] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.158511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.158526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.158544] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.158559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.158574] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  368.158590] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  368.158604] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  368.158618] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  368.158636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.158655] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  368.158673] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  368.174005] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  368.174033] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  368.174075] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  368.192534] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  368.192562] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  368.192602] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  368.192634] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  368.192693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.192724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  368.192750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  368.192774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  368.192798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  368.192821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  368.192843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  368.192866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  368.192890] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  368.192917] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.192943] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  368.192968] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  368.193185] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  368.193238] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  368.193281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  368.193312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.193339] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.193368] [drm:intel_power_well_disable [i915]] disabling DC off
>[  368.193394] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  368.193415] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  368.193842] [drm:intel_power_well_disable [i915]] disabling always-on
>[  368.194260] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  368.194288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.194318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  368.194349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  368.194373] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  368.194400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.194427] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  368.194453] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  368.194478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  368.194501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.194524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.194530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.194552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.194557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.194580] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  368.194601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  368.194623] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.194644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.194665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.194692] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.194713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.194736] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  368.194758] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  368.194779] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  368.194800] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  368.194825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.194855] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  368.194880] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  368.194971] [drm:intel_power_well_enable [i915]] enabling always-on
>[  368.195137] [drm:intel_power_well_enable [i915]] enabling DC off
>[  368.195429] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  368.195478] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  368.195514] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  368.195587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.195626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  368.195652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  368.195677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  368.195700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  368.195724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  368.195746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  368.195768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  368.195793] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  368.195821] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.195847] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  368.195872] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  368.195902] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  368.195927] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  368.198114] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  368.198143] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  368.207738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.216327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.224965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.233663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.242318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.250972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.259666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.268327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.276977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.285671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.294324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.302977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.311636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.320204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.328727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.337225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.345704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.354173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.358397] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  368.419158] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  368.419178] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  368.419216] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  368.420048] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  368.420736] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  368.423321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  368.423341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  368.423360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.423378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  368.428778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  368.428795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  368.433922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  368.436404] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  368.436876] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  368.436930] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  368.436947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  368.436969] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  368.453722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  368.453749] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.453791] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.454678] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  368.454698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.454719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  368.454741] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  368.454759] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  368.454777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.454796] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  368.454813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  368.454831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  368.454847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.454862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.454867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.454882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.454886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.454901] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  368.454916] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  368.454931] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.454946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.454961] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.455075] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.455101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.455127] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  368.455152] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  368.455175] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  368.455198] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  368.455225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.455247] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  368.455265] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  368.470465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  368.470493] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  368.470534] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  368.489034] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  368.489062] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  368.489103] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  368.489135] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  368.489193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.489224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  368.489250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  368.489274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  368.489298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  368.489321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  368.489344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  368.489366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  368.489391] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  368.489418] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.489443] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  368.489468] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  368.489508] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  368.489542] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  368.489570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  368.489597] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.489622] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.489649] [drm:intel_power_well_disable [i915]] disabling DC off
>[  368.489673] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  368.489694] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  368.490664] [drm:intel_power_well_disable [i915]] disabling always-on
>[  368.491150] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  368.491178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.491208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  368.491239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  368.491265] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  368.491293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.491319] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  368.491345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  368.491370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  368.491393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.491415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.491422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.491444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.491449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.491472] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  368.491511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  368.491536] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.491561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.491586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.491617] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.491642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.491669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  368.491694] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  368.491719] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  368.491744] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  368.491774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.491808] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  368.491838] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  368.491942] [drm:intel_power_well_enable [i915]] enabling always-on
>[  368.491967] [drm:intel_power_well_enable [i915]] enabling DC off
>[  368.492439] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  368.492497] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  368.492541] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  368.492622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.492674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  368.492711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  368.492740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  368.492768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  368.492796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  368.492822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  368.492849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  368.492878] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  368.492912] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.492943] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  368.492973] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  368.493154] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  368.493201] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  368.495369] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  368.495400] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  368.505070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.513705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.522364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.531065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.539721] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.548380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.557034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.565684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.575155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.583812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.592475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.601107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.609668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.618194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.626691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.635175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.643646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.652106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.658200] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  368.717508] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  368.717596] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  368.717755] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  368.718880] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  368.721257] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  368.724335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  368.724432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  368.724518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.724606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  368.730351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  368.730462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  368.735964] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  368.738808] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  368.741356] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  368.741519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  368.741608] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  368.741723] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  368.758500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  368.758628] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.758814] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.760948] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  368.761046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.761435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  368.761589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  368.761718] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  368.761849] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.761945] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  368.762035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  368.762386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  368.762509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.762626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.762656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.762737] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.762755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.762835] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  368.762912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  368.762989] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.763338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.763451] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.763583] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.763697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.763811] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  368.763890] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  368.763966] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  368.764307] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  368.764438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.764577] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  368.764678] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  368.775376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  368.775498] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  368.775678] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  368.793706] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  368.793795] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  368.793927] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  368.794037] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  368.794663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.794812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  368.794937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  368.795061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  368.795428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  368.795545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  368.795663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  368.795757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  368.795847] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  368.795944] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.796319] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  368.796457] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  368.796640] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  368.796783] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  368.796886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  368.796982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.797457] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.797605] [drm:intel_power_well_disable [i915]] disabling DC off
>[  368.797719] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  368.797792] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  368.798819] [drm:intel_power_well_disable [i915]] disabling always-on
>[  368.800523] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  368.800618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.800718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  368.800824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  368.800908] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  368.801000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.801372] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  368.801501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  368.801625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  368.801721] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.801802] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.801824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.801903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.801921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  368.801998] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  368.802380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  368.802495] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.802611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.802724] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.802845] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.802922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.803006] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  368.803374] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  368.803488] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  368.803601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  368.803735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.803860] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  368.803949] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  368.804619] [drm:intel_power_well_enable [i915]] enabling always-on
>[  368.804692] [drm:intel_power_well_enable [i915]] enabling DC off
>[  368.805022] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  368.805660] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  368.805782] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  368.806028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.806376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  368.806507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  368.806628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  368.806711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  368.806794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  368.806871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  368.806951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  368.807035] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  368.807425] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  368.807559] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  368.807691] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  368.807801] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  368.807889] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  368.810202] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  368.810293] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  368.820376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.829275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.838191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.847139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.856142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.865115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.873931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.883109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.891932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.900891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.909511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.918077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.926600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.935101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.943594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.952063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.960521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.968992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  368.971713] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  369.031528] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  369.031559] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  369.031595] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  369.032427] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  369.033111] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  369.034870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  369.034889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  369.034907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  369.034926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  369.040787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  369.040804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  369.045929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  369.048398] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  369.048869] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  369.048938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  369.048954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  369.049009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  369.065960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.066194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.066379] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.068432] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.068530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.068630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.068735] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.068821] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.068913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.069004] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.069216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.069353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.069456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.069568] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.069600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.069718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.069748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.069857] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.069952] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.070128] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.070226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.070329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.070435] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.070537] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.070649] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.070741] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.070843] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.070931] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.071057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.071275] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.071383] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.082932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  369.083265] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  369.084303] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  369.100366] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  369.100472] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  369.100630] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  369.100758] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  369.100968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  369.101264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  369.101377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  369.101484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  369.101587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  369.101689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  369.101784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  369.101904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  369.102061] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  369.102317] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.102480] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  369.102636] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  369.102857] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  369.103058] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  369.103296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.103408] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.103516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.103626] [drm:intel_power_well_disable [i915]] disabling DC off
>[  369.103723] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  369.103807] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  369.104402] [drm:intel_power_well_disable [i915]] disabling always-on
>[  369.106254] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.106368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.106485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.106608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.106709] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.106816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.106925] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.107026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.107229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.107327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.107422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.107447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.107537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.107559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.107651] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.107740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.107830] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.107916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.108001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.108166] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.108257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.108350] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.108440] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.108531] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.108616] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.108724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.108843] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.108945] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.109385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  369.109471] [drm:intel_power_well_enable [i915]] enabling DC off
>[  369.109821] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  369.109936] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  369.110065] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  369.110366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  369.110511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  369.110639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  369.110738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  369.110833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  369.110931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  369.111031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  369.111191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  369.111293] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  369.111411] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.111522] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  369.111632] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  369.111758] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  369.111861] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  369.113249] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  369.113330] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  369.123379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.132360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.141263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.150160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.159135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.168080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.176969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.185926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.195210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.203976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.212647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.221223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.229760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.238267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.246753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.255225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.263684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.272143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.274665] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  369.335427] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  369.335448] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  369.335478] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  369.336601] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  369.338384] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  369.340248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  369.340266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  369.340282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  369.340299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  369.345423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  369.345440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  369.350564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  369.353049] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  369.353520] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  369.353572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  369.353589] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  369.353612] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  369.370367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.370394] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.370434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.371296] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.371315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.371336] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.371358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.371375] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.371394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.371413] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.371430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.371447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.371463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.371478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.371482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.371497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.371501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.371516] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.371532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.371560] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.371576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.371592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.371612] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.371629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.371646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.371663] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.371679] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.371695] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.371714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.371736] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.371755] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.387200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  369.387236] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  369.387300] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  369.404557] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  369.404590] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  369.404638] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  369.404676] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  369.404743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  369.404780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  369.404811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  369.404840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  369.404868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  369.404895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  369.404921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  369.404947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  369.404976] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  369.405292] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.405326] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  369.405357] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  369.405402] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  369.405443] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  369.405477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.405511] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.405543] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.405575] [drm:intel_power_well_disable [i915]] disabling DC off
>[  369.405604] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  369.405630] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  369.406562] [drm:intel_power_well_disable [i915]] disabling always-on
>[  369.406908] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.406938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.406972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.407082] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.407115] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.407146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.407178] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.407209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.407254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.407288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.407319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.407331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.407362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.407370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.407403] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.407435] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.407466] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.407497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.407528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.407565] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.407599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.407632] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.407665] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.407695] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.407726] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.407765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.407807] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.407843] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.407971] [drm:intel_power_well_enable [i915]] enabling always-on
>[  369.408164] [drm:intel_power_well_enable [i915]] enabling DC off
>[  369.408466] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  369.408534] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  369.408579] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  369.408661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  369.408704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  369.408741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  369.408777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  369.408811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  369.408845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  369.408877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  369.408910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  369.408946] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  369.408990] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.409074] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  369.409122] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  369.409177] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  369.409221] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  369.411409] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  369.411447] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  369.421193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.429916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.438882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.447640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.456397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.465151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.473901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.482669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.491428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.500186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.508992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.517741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.526338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.534886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.543400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.551889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.560363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.568827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.573929] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  369.634616] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  369.634635] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  369.634702] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  369.635382] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  369.636190] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  369.638008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  369.638027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  369.638045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  369.638064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  369.643927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  369.643944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  369.649069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  369.651551] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  369.652068] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  369.652128] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  369.652144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  369.652167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  369.668921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.668948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.669046] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.669922] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.669942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.669962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.670033] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.670051] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.670070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.670090] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.670107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.670125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.670142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.670158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.670162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.670178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.670181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.670197] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.670212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.670227] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.670242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.670257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.670275] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.670291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.670307] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.670322] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.670338] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.670352] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.670370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.670391] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.670408] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.685729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  369.685765] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  369.685828] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  369.702912] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  369.702944] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  369.702990] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  369.703278] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  369.703352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  369.703391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  369.703421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  369.703451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  369.703479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  369.703507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  369.703534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  369.703560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  369.703591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  369.703623] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.703654] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  369.703683] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  369.703727] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  369.703766] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  369.703798] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.703829] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.703859] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.703891] [drm:intel_power_well_disable [i915]] disabling DC off
>[  369.703919] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  369.703944] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  369.704915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  369.705392] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.705425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.705459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.705496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.705525] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.705557] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.705588] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.705617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.705646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.705673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.705699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.705706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.705732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.705738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.705765] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.705791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.705817] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.705842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.705867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.705899] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.705925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.705952] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.705978] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.706288] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.706315] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.706348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.706384] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.706415] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.706522] [drm:intel_power_well_enable [i915]] enabling always-on
>[  369.706547] [drm:intel_power_well_enable [i915]] enabling DC off
>[  369.706829] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  369.706864] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  369.706896] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  369.706970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  369.707220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  369.707251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  369.707281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  369.707309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  369.707337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  369.707363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  369.707390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  369.707420] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  369.707452] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.707483] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  369.707514] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  369.707550] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  369.707581] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  369.709757] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  369.709796] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  369.719537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.728250] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.737018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.745840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.754602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.763362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.772123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.780884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.789652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.798415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.807182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.815957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.824621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.833195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.841723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.850226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.858707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.867177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  369.871390] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  369.932094] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  369.932115] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  369.932151] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  369.932980] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  369.933681] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  369.935439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  369.935459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  369.935477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  369.935495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  369.941384] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  369.941404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  369.946539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  369.949004] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  369.949507] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  369.949549] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  369.949567] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  369.949591] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  369.966337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  369.966365] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.966409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  369.967304] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  369.967326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.967349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  369.967373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  369.967393] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  369.967413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.967434] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  369.967454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  369.967473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  369.967491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  369.967508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.967513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.967530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.967533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  369.967551] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  369.967569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  369.967585] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.967602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.967618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.967638] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  369.967655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.967672] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  369.967689] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  369.967705] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  369.967721] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  369.967741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  369.967762] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  369.967782] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  369.983133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  369.983175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  369.983245] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  370.000457] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  370.000490] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  370.000537] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  370.000576] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  370.000643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.000679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.000709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.000758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.000792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.000825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.000858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.000889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.000925] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.000965] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.001369] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.001407] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.001462] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  370.001510] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  370.001552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.001591] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.001630] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.001669] [drm:intel_power_well_disable [i915]] disabling DC off
>[  370.001704] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  370.001735] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  370.002685] [drm:intel_power_well_disable [i915]] disabling always-on
>[  370.003272] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.003311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.003353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.003397] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.003433] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.003471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.003509] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.003545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.003580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.003613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.003645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.003654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.003685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.003692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.003724] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.003755] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.003786] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.003816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.003847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.003884] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.003916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.003948] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.003979] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.004337] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.004370] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.004409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.004453] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.004491] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.004619] [drm:intel_power_well_enable [i915]] enabling always-on
>[  370.004649] [drm:intel_power_well_enable [i915]] enabling DC off
>[  370.004939] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  370.004984] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  370.005276] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  370.005363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.005407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.005443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.005479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.005512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.005546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.005579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.005612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.005648] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.005687] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.005725] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.005762] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.005806] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  370.005843] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  370.008070] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  370.008111] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  370.017968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.026803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.035678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.044572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.053400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.062228] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.071125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.079947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.089318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.098154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.107042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.115785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.124392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.132943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.141619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.150111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.158588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.167051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.169775] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  370.228964] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  370.229068] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  370.229308] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  370.230814] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  370.232190] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  370.234709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  370.234817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  370.234916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  370.235019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  370.241726] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  370.241820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  370.247621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  370.250335] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  370.252538] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  370.252704] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  370.252792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  370.252904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  370.269742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.269876] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.270322] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.272190] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.272285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.272387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.272493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.272579] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.272669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.272759] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.272842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.272925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.273001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.273220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.273262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.273371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.273403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.273520] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.273640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.273760] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.273876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.273996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.274179] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.274302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.274408] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.274521] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.274642] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.274758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.274887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.275029] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.275390] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.286523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  370.286646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  370.286839] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  370.304979] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  370.305213] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  370.305370] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  370.305498] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  370.305708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.305827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.305929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.306026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.307212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.307363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.307467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.307567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.307672] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.307790] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.307879] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.307967] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.308807] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  370.308917] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  370.309021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.309292] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.309435] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.309567] [drm:intel_power_well_disable [i915]] disabling DC off
>[  370.309687] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  370.309834] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  370.310869] [drm:intel_power_well_disable [i915]] disabling always-on
>[  370.312528] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.312641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.312757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.312879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.312980] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.313235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.313397] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.313525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.313668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.313789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.313924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.313961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.314175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.314204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.314340] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.314456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.314595] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.314703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.314823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.314949] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.315171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.315312] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.315426] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.315553] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.315663] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.315800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.315954] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.316192] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.316722] [drm:intel_power_well_enable [i915]] enabling always-on
>[  370.316828] [drm:intel_power_well_enable [i915]] enabling DC off
>[  370.317319] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  370.317761] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  370.317872] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  370.318193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.318324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.318423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.318534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.318631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.318737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.318829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.318931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.319037] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.319252] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.319371] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.319489] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.319626] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  370.319728] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  370.322166] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  370.322256] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  370.332396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.341399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.350377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.359278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.368154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.377087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.385972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.394931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.404124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.412941] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.421841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.430443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.438990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.447525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.456015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.464490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.472952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.481451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.482299] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  370.543107] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  370.543127] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  370.543163] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  370.544024] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  370.544704] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  370.546498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  370.546518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  370.546535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  370.546554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  370.552434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  370.552453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  370.557586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  370.560033] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  370.560536] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  370.560595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  370.560613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  370.560637] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  370.577392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.577422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.577467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.578378] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.578400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.578422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.578447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.578467] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.578488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.578509] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.578528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.578548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.578567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.578584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.578588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.578606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.578610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.578627] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.578644] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.578661] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.578678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.578694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.578714] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.578731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.578749] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.578766] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.578782] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.578798] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.578818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.578840] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.578859] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.594227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  370.594266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  370.594339] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  370.612988] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  370.613073] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  370.613131] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  370.613178] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  370.613258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.613301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.613337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.613372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.613404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.613436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.613467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.613498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.613534] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.613572] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.613608] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.613644] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.613698] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  370.613745] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  370.613785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.613823] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.613859] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.613897] [drm:intel_power_well_disable [i915]] disabling DC off
>[  370.613931] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  370.613961] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  370.614602] [drm:intel_power_well_disable [i915]] disabling always-on
>[  370.615251] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.615291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.615334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.615379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.615416] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.615454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.615493] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.615529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.615565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.615598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.615631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.615641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.615672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.615679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.615711] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.615743] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.615774] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.615805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.615835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.615873] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.615904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.615936] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.615967] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.616177] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.616228] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.616286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.616347] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.616402] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.616558] [drm:intel_power_well_enable [i915]] enabling always-on
>[  370.616589] [drm:intel_power_well_enable [i915]] enabling DC off
>[  370.616876] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  370.616918] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  370.616949] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  370.617152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.617214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.617267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.617310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.617344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.617377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.617408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.617441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.617477] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.617517] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.617555] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.617592] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.617636] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  370.617673] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  370.619859] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  370.619898] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  370.629688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.638449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.647340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.656232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.665132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.674114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.683006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.691979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.700950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.709886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.718706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.727615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.736293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.744893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.753437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.761948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.770475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.778951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.781781] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  370.842049] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  370.842153] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  370.842365] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  370.844217] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  370.845311] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  370.846919] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  370.847028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  370.847341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  370.847476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  370.853790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  370.853887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  370.859450] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  370.862235] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  370.864583] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  370.864731] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  370.864819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  370.864932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  370.881715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.881845] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.882031] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.884328] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.884426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.884526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.884629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.884713] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.884804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.884893] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.884977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.885211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.885321] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.885444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.885480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.885597] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.885624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.885745] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.885863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.885957] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.886161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.886267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.886399] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.886514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.886632] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.886748] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.886841] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.886950] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.887168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.887309] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.887435] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.898631] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  370.898753] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  370.898989] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  370.917292] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  370.917382] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  370.917513] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  370.917619] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  370.917799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.917900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.917984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.918826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.918912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.919001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.919458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.919539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.919627] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.919723] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.919813] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.919900] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.920021] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  370.920870] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  370.920990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  370.921276] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  370.921429] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.921578] [drm:intel_power_well_disable [i915]] disabling DC off
>[  370.921698] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  370.921774] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  370.922793] [drm:intel_power_well_disable [i915]] disabling always-on
>[  370.924285] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  370.924382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.924481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  370.924587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  370.924671] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  370.924764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.924854] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  370.924939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.925022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  370.925223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.925323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.925357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.925449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.925477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  370.925574] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  370.925668] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  370.925762] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.925856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.925968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.926164] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.926262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.926381] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  370.926463] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  370.926536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  370.926610] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  370.926699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.926802] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  370.926890] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.927353] [drm:intel_power_well_enable [i915]] enabling always-on
>[  370.927426] [drm:intel_power_well_enable [i915]] enabling DC off
>[  370.927756] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  370.927856] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  370.927963] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  370.928287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  370.928391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  370.928474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  370.928556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  370.928633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  370.928714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  370.928790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  370.928867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  370.928951] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  370.929142] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  370.929258] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  370.929368] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  370.929495] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  370.929620] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  370.931969] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  370.932122] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  370.942392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.951394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.960382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.969353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.978760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.987705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  370.996604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.005492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.014386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.023101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.031737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.040287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.048807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.057302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.065778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.074243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.082701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.091159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.093886] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  371.154692] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  371.154710] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  371.154742] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  371.155569] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  371.156275] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  371.158037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  371.158056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  371.158075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  371.158093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  371.163962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  371.163991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  371.169124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  371.171603] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  371.172137] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  371.172182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  371.172199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  371.172221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  371.188979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.189024] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  371.189065] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.189950] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  371.189969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.190014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  371.190037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  371.190054] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  371.190074] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.190093] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  371.190111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  371.190128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  371.190144] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.190160] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.190164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.190180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.190184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.190200] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  371.190215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  371.190230] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  371.190246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.190261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.190280] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  371.190295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.190311] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  371.190326] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  371.190342] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  371.190356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  371.190375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.190395] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  371.190413] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  371.205810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  371.205842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  371.205901] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  371.222964] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  371.223028] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  371.223069] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  371.223102] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  371.223159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.223190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.223215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.223240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.223263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.223286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.223308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.223329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.223355] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.223382] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.223407] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.223432] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.223472] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  371.223506] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  371.223534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.223561] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  371.223586] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.223613] [drm:intel_power_well_disable [i915]] disabling DC off
>[  371.223637] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  371.223658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  371.225017] [drm:intel_power_well_disable [i915]] disabling always-on
>[  371.225322] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  371.225350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.225380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  371.225411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  371.225437] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  371.225465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.225492] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  371.225517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  371.225542] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  371.225565] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.225587] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.225594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.225616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.225621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.225644] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  371.225665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  371.225687] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  371.225708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.225729] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.225755] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  371.225777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.225800] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  371.225821] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  371.225842] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  371.225864] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  371.225890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.225919] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  371.225944] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  371.226617] [drm:intel_power_well_enable [i915]] enabling always-on
>[  371.226640] [drm:intel_power_well_enable [i915]] enabling DC off
>[  371.226921] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  371.226965] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  371.227065] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  371.227140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.227193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.227226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.227256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.227287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.227316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.227344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.227372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.227402] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.227436] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.227467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.227497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.227534] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  371.227566] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  371.229754] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  371.229786] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  371.239491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.248118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.256822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.265586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.274355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.283118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.291880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.300641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.309412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.318176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.326995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.335769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.344379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.352930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.361454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.369956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.378531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.387002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.391416] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  371.452237] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  371.452257] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  371.452314] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  371.453150] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  371.453844] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  371.456428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  371.456447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  371.456465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  371.456484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  371.461865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  371.461883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  371.467009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  371.469490] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  371.469963] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  371.470120] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  371.470137] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  371.470160] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  371.486945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.486974] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  371.487201] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.488164] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  371.488185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.488207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  371.488229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  371.488246] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  371.488265] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.488284] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  371.488301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  371.488319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  371.488334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.488350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.488355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.488370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.488373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.488389] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  371.488404] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  371.488419] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  371.488434] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.488448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.488466] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  371.488481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.488497] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  371.488512] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  371.488526] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  371.488540] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  371.488558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.488578] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  371.488595] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  371.503677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  371.503708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  371.503754] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  371.521050] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  371.521078] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  371.521118] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  371.521150] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  371.521207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.521238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.521263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.521287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.521311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.521334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.521356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.521378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.521402] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.521429] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.521454] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.521479] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.521519] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  371.521552] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  371.521580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.521606] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  371.521632] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.521660] [drm:intel_power_well_disable [i915]] disabling DC off
>[  371.521684] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  371.521705] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  371.523134] [drm:intel_power_well_disable [i915]] disabling always-on
>[  371.523435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.523484] [drm:intel_power_well_enable [i915]] enabling always-on
>[  371.523505] [drm:intel_power_well_enable [i915]] enabling DC off
>[  371.523781] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  371.523821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.523848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.523873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.523897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.523921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.523944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.523967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.524051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.524092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.524133] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.524174] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.524213] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.524250] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.524297] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  371.524334] [drm:intel_power_well_disable [i915]] disabling DC off
>[  371.524371] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  371.524405] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  371.524836] [drm:intel_power_well_disable [i915]] disabling always-on
>[  371.525137] [drm:drm_mode_addfb2] [FB:64]
>[  371.525172] [drm:drm_mode_addfb2] [FB:65]
>[  371.565104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  371.565578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  371.566173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  371.566659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  371.566684] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  371.566810] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  371.566861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.566915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  371.566972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  371.567088] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  371.567163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.567224] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  371.567289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  371.567346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  371.567409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.567461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.567480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.567533] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.567546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.567605] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  371.567658] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  371.567718] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  371.567770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.567824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.567881] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  371.567936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.567988] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  371.568094] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  371.568144] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  371.568216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.568291] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  371.568347] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  371.569297] [drm:intel_power_well_enable [i915]] enabling always-on
>[  371.569346] [drm:intel_power_well_enable [i915]] enabling DC off
>[  371.569643] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  371.569698] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  371.569752] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  371.569860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.569917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.569965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.570115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.570181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.570249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.570313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.570375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.570442] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.570515] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.570584] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.570653] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.570730] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  371.570798] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  371.573468] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  371.573517] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  371.583645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.592312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.600974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.609673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.618329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.626985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.635680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.644339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.652940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.661708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.670223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.678722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.687204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.695681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.704140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.712598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.721056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.729514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.735610] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  371.796377] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  371.796407] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  371.796443] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  371.797281] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  371.797965] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  371.799735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  371.799755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  371.799773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  371.799792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  371.805648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  371.805665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  371.810795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  371.813274] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  371.813753] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  371.813803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  371.813819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  371.813842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  371.830596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.830623] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  371.830665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.864252] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  371.864282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.864311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  371.864341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  371.864365] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  371.864390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.864416] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  371.864439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  371.864462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  371.864484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.864505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.864511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.864531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.864536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.864557] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  371.864577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  371.864598] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  371.864619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.864638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.864663] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  371.864684] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.864705] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  371.864724] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  371.864744] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  371.864764] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  371.864788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.864814] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  371.864837] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  371.880769] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  371.880810] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  371.880883] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  371.898080] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  371.898119] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  371.898176] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  371.898222] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  371.898302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.898346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.898383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.898417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.898450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.898483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.898514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.898545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.898581] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.898619] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.898656] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.898691] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.898746] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  371.898793] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  371.898832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  371.898870] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  371.898907] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.898944] [drm:intel_power_well_disable [i915]] disabling DC off
>[  371.898978] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  371.899243] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  371.899697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  371.900376] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  371.900432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.900489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  371.900548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  371.900600] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  371.900677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.900746] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  371.900812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  371.900878] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  371.900942] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.901005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.901083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.901148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.901165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  371.901227] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  371.901292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  371.901356] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  371.901419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.901484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.901557] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  371.901618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.901688] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  371.901752] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  371.901814] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  371.901877] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  371.901936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.902013] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  371.902132] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  371.902380] [drm:intel_power_well_enable [i915]] enabling always-on
>[  371.902441] [drm:intel_power_well_enable [i915]] enabling DC off
>[  371.902757] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  371.902838] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  371.902902] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  371.903017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.903140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  371.903209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  371.903275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  371.903341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  371.903404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  371.903467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  371.903528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  371.903594] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  371.903663] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  371.903731] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  371.903797] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  371.903873] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  371.903940] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  371.906208] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  371.906256] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  371.916099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.924968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.933968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.942927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.951961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.960921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.970193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.979015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.987933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  371.996910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.006116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.014936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.024007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.032652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.041201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.049720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.058213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.066689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.069435] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  372.130260] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  372.130291] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  372.130338] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  372.131168] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  372.131881] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  372.134464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  372.134484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  372.134501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.134520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  372.139900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  372.139918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  372.145044] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  372.147525] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  372.148066] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  372.148101] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  372.148118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  372.148140] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  372.164899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  372.164926] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  372.164967] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.165933] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  372.165953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.165974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  372.166066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  372.166093] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  372.166121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.166149] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  372.166175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.166200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  372.166224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.166249] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.166255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.166276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.166282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.166304] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  372.166328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  372.166351] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.166374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.166398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.166425] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.166448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.166472] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  372.166496] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  372.166519] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  372.166543] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  372.166568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.166596] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  372.166622] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.181651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  372.181681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  372.181739] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  372.198636] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  372.198664] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  372.198704] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  372.198737] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  372.198793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.198824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  372.198850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  372.198874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  372.198898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  372.198921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  372.198943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  372.198965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  372.199172] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  372.199219] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.199262] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  372.199300] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  372.199352] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  372.199400] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  372.199442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  372.199481] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  372.199520] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.199560] [drm:intel_power_well_disable [i915]] disabling DC off
>[  372.199596] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  372.199630] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  372.200571] [drm:intel_power_well_disable [i915]] disabling always-on
>[  372.200937] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  372.200965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.201089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  372.201134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  372.201171] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  372.201211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.201250] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  372.201287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.201324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  372.201361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.201396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.201405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.201437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.201445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.201481] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  372.201514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  372.201548] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.201583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.201617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.201671] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.201712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.201754] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  372.201794] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  372.201834] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  372.201872] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  372.201919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.201968] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  372.202198] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.202329] [drm:intel_power_well_enable [i915]] enabling always-on
>[  372.202355] [drm:intel_power_well_enable [i915]] enabling DC off
>[  372.202638] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  372.202673] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  372.202701] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  372.202771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.202806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  372.202836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  372.202864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  372.202892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  372.202920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  372.202946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  372.202973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  372.203155] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  372.203201] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.203245] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  372.203289] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  372.203338] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  372.203381] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  372.205549] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  372.205581] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  372.215362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.224013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.232725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.241381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.250035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.258691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.267342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.275994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.284689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.293348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.301999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.310673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.319234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.327757] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.336261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.344748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.353219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.361678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.367771] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  372.428564] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  372.428582] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  372.428616] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  372.429467] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  372.430197] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  372.432778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  372.432798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  372.432816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.432834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  372.438222] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  372.438239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  372.443380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  372.445848] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  372.446391] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  372.446438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  372.446454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  372.446477] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  372.463234] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  372.463261] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  372.463302] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.464171] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  372.464190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.464211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  372.464233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  372.464250] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  372.464269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.464288] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  372.464305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.464322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  372.464338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.464354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.464358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.464373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.464376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.464392] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  372.464407] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  372.464422] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.464437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.464451] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.464469] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.464484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.464499] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  372.464514] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  372.464528] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  372.464543] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  372.464560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.464579] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  372.464597] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.479986] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  372.480039] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  372.480097] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  372.498965] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  372.499039] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  372.499088] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  372.499126] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  372.499193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.499229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  372.499259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  372.499287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  372.499315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  372.499342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  372.499368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  372.499394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  372.499424] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  372.499456] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.499487] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  372.499516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  372.499563] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  372.499602] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  372.499636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  372.499667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  372.499697] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.499728] [drm:intel_power_well_disable [i915]] disabling DC off
>[  372.499757] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  372.499781] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  372.501194] [drm:intel_power_well_disable [i915]] disabling always-on
>[  372.501625] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  372.501666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.501710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  372.501755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  372.501791] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  372.501831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.501870] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  372.501907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.501943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  372.501976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.502066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.502088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.502131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.502143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.502192] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  372.502234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  372.502280] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.502320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.502366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.502420] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.502460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.502507] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  372.502556] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  372.502604] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  372.502651] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  372.502707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.502768] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  372.502823] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.502991] [drm:intel_power_well_enable [i915]] enabling always-on
>[  372.503074] [drm:intel_power_well_enable [i915]] enabling DC off
>[  372.503385] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  372.503453] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  372.503504] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  372.503594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.503650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  372.503693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  372.503740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  372.503780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  372.503825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  372.503864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  372.503908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  372.503950] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  372.504040] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.504096] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  372.504151] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  372.504212] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  372.504257] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  372.506451] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  372.506490] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  372.516251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.524988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.533882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.542751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.551586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.560405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.569223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.578704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.587575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.596406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.605233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.614118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.622840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.631452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.640006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.648521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.657016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.665493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.668040] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  372.728820] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  372.728851] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  372.728887] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  372.729718] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  372.730476] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  372.733056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  372.733075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  372.733092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.733111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  372.738492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  372.738510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  372.743633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  372.746115] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  372.746594] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  372.746641] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  372.746657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  372.746680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  372.763433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  372.763460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  372.763501] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.764385] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  372.764405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.764425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  372.764447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  372.764465] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  372.764484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.764502] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  372.764520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.764536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  372.764552] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.764567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.764571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.764587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.764590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.764606] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  372.764621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  372.764636] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.764651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.764666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.764684] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.764700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.764716] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  372.764731] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  372.764746] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  372.764761] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  372.764778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.764798] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  372.764815] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.780183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  372.780215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  372.780273] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  372.797567] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  372.797600] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  372.797647] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  372.797685] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  372.797752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.797788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  372.797818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  372.797847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  372.797875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  372.797902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  372.797929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  372.797955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  372.797984] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  372.798513] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.798546] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  372.798577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  372.798622] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  372.798662] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  372.798697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  372.798730] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  372.798761] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.798792] [drm:intel_power_well_disable [i915]] disabling DC off
>[  372.798821] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  372.798846] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  372.799908] [drm:intel_power_well_disable [i915]] disabling always-on
>[  372.800346] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  372.800379] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.800415] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  372.800452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  372.800482] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  372.800513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.800545] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  372.800574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.800602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  372.800629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.800655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.800662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.800688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.800694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  372.800721] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  372.800747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  372.800772] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.800797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.800822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.800852] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.800878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.800905] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  372.800931] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  372.800956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  372.800980] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  372.801660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.801702] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  372.801734] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.801831] [drm:intel_power_well_enable [i915]] enabling always-on
>[  372.801856] [drm:intel_power_well_enable [i915]] enabling DC off
>[  372.802225] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  372.802658] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  372.802690] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  372.802777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.802819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  372.802857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  372.802891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  372.802925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  372.802959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  372.803043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  372.803086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  372.803132] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  372.803182] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  372.803239] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  372.803288] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  372.803333] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  372.803370] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  372.805529] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  372.805565] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  372.815342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.824071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.832832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.841600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.850364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.859123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.867877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.876636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.885391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.894158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.902912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.911825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.920436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.928986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.937523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.946020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.954501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.962969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  372.967392] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  373.028549] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  373.028569] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  373.028612] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  373.029476] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  373.030179] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  373.031938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  373.031958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  373.031976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.032025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  373.037848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  373.037866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  373.042998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  373.045479] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  373.045957] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  373.046057] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  373.046074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  373.046097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  373.062864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.062893] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.062937] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.063979] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.064018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.064041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.064065] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.064085] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.064106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.064127] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.064146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.064165] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.064183] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.064200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.064205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.064222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.064226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.064243] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.064260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.064276] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.064293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.064309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.064329] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.064346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.064363] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.064380] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.064398] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.064414] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.064434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.064455] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.064474] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.079664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  373.079699] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  373.079752] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  373.096992] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  373.097064] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  373.097112] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  373.097150] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  373.097216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.097252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.097282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.097310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.097338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.097365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.097391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.097417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.097446] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.097479] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.097509] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.097538] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.097585] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  373.097625] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  373.097658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.097689] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.097718] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.097750] [drm:intel_power_well_disable [i915]] disabling DC off
>[  373.097778] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  373.097803] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  373.098294] [drm:intel_power_well_disable [i915]] disabling always-on
>[  373.099266] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.099311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.099358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.099406] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.099449] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.099493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.099537] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.099579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.099621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.099660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.099699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.099710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.099747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.099756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.099794] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.099834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.099874] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.099914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.099953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.099999] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.100075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.100124] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.100164] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.100207] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.100249] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.100295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.100345] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.100388] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.100551] [drm:intel_power_well_enable [i915]] enabling always-on
>[  373.100591] [drm:intel_power_well_enable [i915]] enabling DC off
>[  373.100886] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  373.100939] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  373.100981] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  373.101090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.101139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.101182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.101224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.101265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.101306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.101346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.101385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.101427] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.101472] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.101516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.101560] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.101608] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  373.101651] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  373.103873] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  373.103913] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  373.113679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.122378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.131162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.140001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.148825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.157589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.166354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.175213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.183980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.192821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.201589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.210350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.219003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.227630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.236169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.244690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.253175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.261647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.266081] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  373.325980] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  373.326000] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  373.326037] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  373.327303] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  373.329887] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  373.331223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  373.331240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  373.331256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.331273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  373.336397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  373.336414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  373.341537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  373.344023] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  373.344502] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  373.344545] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  373.344561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  373.344583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  373.361341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.361368] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.361410] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.362305] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.362325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.362346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.362368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.362385] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.362404] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.362423] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.362440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.362457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.362473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.362488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.362493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.362508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.362511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.362527] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.362541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.362556] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.362571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.362585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.362604] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.362619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.362634] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.362649] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.362664] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.362678] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.362696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.362716] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.362734] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.378119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  373.378155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  373.378345] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  373.395035] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  373.395068] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  373.395115] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  373.395154] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  373.395220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.395257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.395287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.395315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.395343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.395371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.395397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.395423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.395453] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.395484] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.395514] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.395542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.395590] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  373.395629] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  373.395662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.395693] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.395722] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.395753] [drm:intel_power_well_disable [i915]] disabling DC off
>[  373.395781] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  373.395806] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  373.396790] [drm:intel_power_well_disable [i915]] disabling always-on
>[  373.397364] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.397403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.397447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.397494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.397530] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.397572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.397609] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.397649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.397685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.397722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.397755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.397766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.397800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.397808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.397847] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.397879] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.397914] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.397945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.397984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.398177] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.398260] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.398301] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.398334] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.398371] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.398403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.398447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.398493] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.398530] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.398684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  373.398716] [drm:intel_power_well_enable [i915]] enabling DC off
>[  373.399120] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  373.399522] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  373.399562] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  373.399632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.399696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.399739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.399786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.399826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.399872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.399911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.399954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.400002] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.400211] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.400250] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.400288] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.400332] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  373.400369] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  373.402547] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  373.402586] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  373.412495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.421261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.430031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.438852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.447613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.456378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.465135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.473889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.482651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.491419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.500181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.508954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.517723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.526272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.534786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.543283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.551764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.560231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.562755] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  373.623345] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  373.623367] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  373.623401] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  373.624526] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  373.626288] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  373.628149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  373.628166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  373.628182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.628198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  373.633322] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  373.633340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  373.638462] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  373.640927] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  373.641454] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  373.641521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  373.641537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  373.641559] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  373.658315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.658343] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.658384] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.659263] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.659283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.659303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.659325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.659343] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.659362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.659381] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.659398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.659415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.659431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.659447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.659451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.659466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.659470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.659485] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.659501] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.659515] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.659530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.659545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.659562] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.659577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.659593] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.659608] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.659622] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.659636] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.659654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.659674] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.659691] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.675119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  373.675152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  373.675326] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  373.691979] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  373.692034] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  373.692071] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  373.692100] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  373.692151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.692178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.692200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.692221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.692241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.692260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.692280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.692298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.692320] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.692344] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.692366] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.692388] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.692424] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  373.692454] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  373.692478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.692501] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.692524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.692547] [drm:intel_power_well_disable [i915]] disabling DC off
>[  373.692568] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  373.692587] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  373.693552] [drm:intel_power_well_disable [i915]] disabling always-on
>[  373.694079] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.694108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.694138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.694170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.694195] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.694223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.694250] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.694275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.694300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.694323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.694345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.694352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.694374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.694379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.694401] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.694424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.694445] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.694467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.694488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.694514] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.694535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.694558] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.694580] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.694600] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.694621] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.694647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.694677] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.694702] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.694792] [drm:intel_power_well_enable [i915]] enabling always-on
>[  373.694814] [drm:intel_power_well_enable [i915]] enabling DC off
>[  373.695250] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  373.695606] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  373.695639] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  373.695704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.695743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.695773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.695806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.695835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.695868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.695895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.695927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.695957] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.696093] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.696129] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.696165] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.696206] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  373.696237] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  373.698399] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  373.698426] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  373.708067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.716652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.725245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.733841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.742435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.751027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.759616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.768202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.776838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.785432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.794029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.802601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.811132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.819632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.828115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.836585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.845046] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.853502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  373.859596] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  373.920291] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  373.920310] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  373.920351] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  373.921185] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  373.921883] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  373.924474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  373.924495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  373.924515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.924535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  373.929919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  373.929938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  373.935073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  373.937560] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  373.938134] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  373.938184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  373.938202] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  373.938227] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  373.954982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.955031] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.955077] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.955959] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.956060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.956090] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.956123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.956146] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.956174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.956199] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.956228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.956251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.956277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.956298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.956305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.956327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.956333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.956357] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.956378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.956402] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.956422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.956445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.956469] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.956493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.956519] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.956540] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.956563] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.956583] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.956610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.956640] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.956664] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.971726] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  373.971758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  373.971910] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  373.990145] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  373.990179] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  373.990227] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  373.990265] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  373.990332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.990368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.990399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.990428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.990455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.990482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.990507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.990533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.990563] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.990595] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.990624] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.990653] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.990700] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  373.990740] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  373.990774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  373.990805] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  373.990835] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.990865] [drm:intel_power_well_disable [i915]] disabling DC off
>[  373.990894] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  373.990919] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  373.991906] [drm:intel_power_well_disable [i915]] disabling always-on
>[  373.992489] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  373.992522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.992557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  373.992594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  373.992623] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  373.992675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.992715] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  373.992752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  373.992788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  373.992821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.992854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.992863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.992895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.992902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  373.992936] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  373.992968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  373.993189] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  373.993287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.993326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.993377] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  373.993417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.993467] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  373.993507] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  373.993552] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  373.993591] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  373.993641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.993696] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  373.993740] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  373.993928] [drm:intel_power_well_enable [i915]] enabling always-on
>[  373.993966] [drm:intel_power_well_enable [i915]] enabling DC off
>[  373.994427] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  373.994489] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  373.994537] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  373.994628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.994683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  373.994727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  373.994777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  373.994818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  373.994863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  373.994904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  373.994949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  373.994994] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  373.995188] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  373.995239] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  373.995290] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  373.995348] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  373.995392] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  373.997579] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  373.997617] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  374.007507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.016249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.025017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.033839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.042599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.051357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.060112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.068862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.077618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.086374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.095139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.103845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.112443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.120988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.129522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.138013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.146486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.154949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.159207] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  374.220280] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  374.220299] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  374.220340] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  374.221175] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  374.221868] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  374.223633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  374.223653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.223671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.223690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.229556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.229573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  374.234687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.237155] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  374.237632] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  374.237694] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  374.237710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  374.237732] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  374.254515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  374.254542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  374.254583] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.255556] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  374.255578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.255601] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  374.255625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  374.255644] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  374.255665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.255686] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  374.255705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  374.255724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  374.255742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.255760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.255764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.255781] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.255785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.255802] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  374.255819] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  374.255836] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  374.255852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.255869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.255889] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  374.255905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.255923] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  374.255940] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  374.255956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  374.255972] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  374.256037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.256071] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  374.256101] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  374.271316] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  374.271351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  374.271404] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  374.288781] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  374.288814] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  374.288862] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  374.288900] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  374.288967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.289099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  374.289151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  374.289198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  374.289243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  374.289288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  374.289332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  374.289373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  374.289419] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  374.289465] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.289510] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  374.289554] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  374.289616] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  374.289672] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  374.289719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  374.289764] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  374.289808] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.289855] [drm:intel_power_well_disable [i915]] disabling DC off
>[  374.289899] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  374.289938] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  374.290420] [drm:intel_power_well_disable [i915]] disabling always-on
>[  374.290854] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  374.290886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.290920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  374.290957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  374.290986] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  374.291071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.291113] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  374.291159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  374.291205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  374.291249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.291292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.291305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.291342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.291356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.291393] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  374.291432] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  374.291472] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  374.291512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.291543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.291587] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  374.291626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.291668] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  374.291707] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  374.291747] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  374.291788] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  374.291834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.291882] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  374.291926] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  374.292123] [drm:intel_power_well_enable [i915]] enabling always-on
>[  374.292162] [drm:intel_power_well_enable [i915]] enabling DC off
>[  374.292458] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  374.292510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  374.292551] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  374.292623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.292670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  374.292713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  374.292753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  374.292793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  374.292833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  374.292872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  374.292910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  374.292953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  374.293039] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.293087] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  374.293133] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  374.293183] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  374.293226] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  374.295394] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  374.295425] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  374.305170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.313835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.322591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.331363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.340131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.348895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.357659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.366416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.375212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.383973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.392801] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.401563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.410248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.418837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.427400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.435910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.444398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.452871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.455411] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  374.516201] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  374.516222] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  374.516286] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  374.517127] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  374.517806] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  374.519559] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  374.519579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.519597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.519616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.525503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.525521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  374.530645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.533130] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  374.533610] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  374.533653] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  374.533669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  374.533692] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  374.550431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  374.550456] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  374.550496] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.551361] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  374.551381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.551401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  374.551423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  374.551441] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  374.551460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.551478] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  374.551495] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  374.551512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  374.551528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.551544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.551548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.551563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.551566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.551582] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  374.551597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  374.551612] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  374.551627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.551641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.551660] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  374.551675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.551691] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  374.551706] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  374.551720] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  374.551734] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  374.551752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.551771] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  374.551788] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  374.567156] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  374.567183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  374.567235] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  374.584407] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  374.584435] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  374.584476] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  374.584509] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  374.584567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.584598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  374.584623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  374.584648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  374.584671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  374.584694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  374.584716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  374.584738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  374.584763] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  374.584791] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.584817] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  374.584841] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  374.584882] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  374.584916] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  374.584944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  374.584971] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  374.585075] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.585112] [drm:intel_power_well_disable [i915]] disabling DC off
>[  374.585149] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  374.585183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  374.585623] [drm:intel_power_well_disable [i915]] disabling always-on
>[  374.585926] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  374.585953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.585986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  374.586072] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  374.586104] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  374.586145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.586184] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  374.586223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  374.586260] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  374.586295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.586329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.586339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.586370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.586378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.586412] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  374.586446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  374.586481] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  374.586514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.586548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.586586] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  374.586620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.586656] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  374.586691] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  374.586725] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  374.586758] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  374.586795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.586836] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  374.586872] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  374.587042] [drm:intel_power_well_enable [i915]] enabling always-on
>[  374.587078] [drm:intel_power_well_enable [i915]] enabling DC off
>[  374.587371] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  374.587414] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  374.587449] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  374.587512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.587551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  374.587587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  374.587622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  374.587656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  374.587690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  374.587723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  374.587755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  374.587791] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  374.587829] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.587866] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  374.587903] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  374.587944] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  374.587983] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  374.590181] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  374.590208] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  374.599832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.608428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.617075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.625769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.634426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.643086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.651776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.660432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.669083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.677774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.686425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.695083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.703693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.712246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.720783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.729279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.737757] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.746221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.752317] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  374.813060] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  374.813078] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  374.813116] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  374.813948] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  374.814645] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  374.816430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  374.816450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.816468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.816487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.822388] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.822406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  374.827530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.830016] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  374.830495] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  374.830537] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  374.830554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  374.830576] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  374.847333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  374.847360] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  374.847402] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.848286] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  374.848306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.848326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  374.848348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  374.848365] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  374.848384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.848403] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  374.848421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  374.848437] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  374.848453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.848469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.848473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.848488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.848492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.848508] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  374.848523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  374.848538] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  374.848553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.848567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.848585] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  374.848600] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.848616] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  374.848631] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  374.848645] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  374.848659] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  374.848677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.848696] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  374.848713] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  374.864149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  374.864185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  374.864380] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  374.881043] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  374.881071] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  374.881111] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  374.881143] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  374.881200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.881231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  374.881256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  374.881281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  374.881305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  374.881328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  374.881351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  374.881373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  374.881398] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  374.881425] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.881451] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  374.881476] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  374.881516] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  374.881550] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  374.881579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  374.881606] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  374.881631] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.881658] [drm:intel_power_well_disable [i915]] disabling DC off
>[  374.881683] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  374.881704] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  374.883121] [drm:intel_power_well_disable [i915]] disabling always-on
>[  374.883455] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  374.883490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.883525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  374.883563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  374.883593] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  374.883625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.883657] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  374.883687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  374.883716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  374.883743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.883770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.883778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.883805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.883810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  374.883837] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  374.883863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  374.883889] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  374.883914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.883939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.883970] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  374.884048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.884086] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  374.884121] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  374.884156] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  374.884189] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  374.884228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.884271] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  374.884308] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  374.884441] [drm:intel_power_well_enable [i915]] enabling always-on
>[  374.884466] [drm:intel_power_well_enable [i915]] enabling DC off
>[  374.884748] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  374.884785] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  374.884812] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  374.884884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.884918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  374.884948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  374.884976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  374.885038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  374.885073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  374.885107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  374.885141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  374.885177] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  374.885218] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  374.885265] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  374.885303] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  374.885340] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  374.885370] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  374.887529] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  374.887561] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  374.897279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.905930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.914832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.923615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.932397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.941176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.950009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.958838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.967615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.976386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.985163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  374.994028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.002795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.011444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.020018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.028532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.037023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.045498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.049924] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  375.110674] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  375.110694] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  375.110743] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  375.111575] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  375.112344] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  375.114952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.114972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.115053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.115079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.120393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.120411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  375.125536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.128020] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  375.128499] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.128544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  375.128561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.128583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.145340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  375.145367] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.145408] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.146288] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  375.146308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.146329] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  375.146350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  375.146368] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  375.146387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.146406] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.146423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.146440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  375.146456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.146472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.146476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.146491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.146495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.146510] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  375.146525] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  375.146540] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.146555] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.146569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.146587] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.146602] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.146617] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  375.146632] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  375.146646] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  375.146660] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  375.146678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.146697] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  375.146715] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  375.162144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.162176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.162351] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.179019] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  375.179044] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  375.179079] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  375.179107] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  375.179158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.179186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  375.179208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  375.179230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  375.179250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  375.179270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  375.179290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  375.179309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  375.179331] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  375.179354] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.179376] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  375.179398] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  375.179434] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  375.179463] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  375.179488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  375.179511] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.179534] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.179557] [drm:intel_power_well_disable [i915]] disabling DC off
>[  375.179579] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  375.179597] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  375.180531] [drm:intel_power_well_disable [i915]] disabling always-on
>[  375.180992] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  375.181066] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.181112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  375.181159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  375.181197] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  375.181236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.181274] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.181311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.181347] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  375.181382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.181416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.181426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.181456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.181465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.181496] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  375.181530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  375.181562] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.181596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.181629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.181667] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.181701] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.181736] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  375.181772] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  375.181806] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  375.181839] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  375.181878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.181919] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  375.181956] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  375.182124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  375.182158] [drm:intel_power_well_enable [i915]] enabling DC off
>[  375.182451] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  375.182499] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  375.182536] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  375.182634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.182675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  375.182712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  375.182748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  375.182783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  375.182818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  375.182851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  375.182884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  375.182920] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  375.182960] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.183034] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  375.183074] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  375.183118] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  375.183156] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  375.185320] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  375.185346] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  375.194906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.203492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.212086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.220680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.229275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.237867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.246460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.255051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.263641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.272232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.280857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.289435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.297967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.306492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.314981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.323473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.331936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.340394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.346489] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  375.407271] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  375.407291] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  375.407339] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  375.408171] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  375.408885] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  375.411470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.411489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.411507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.411526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.416908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.416925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  375.422051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.424533] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  375.425078] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.425110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  375.425127] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.425150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.441908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  375.441935] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.441977] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.442963] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  375.443052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.443073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  375.443094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  375.443112] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  375.443131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.443150] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.443167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.443185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  375.443200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.443216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.443220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.443235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.443238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.443254] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  375.443269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  375.443284] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.443299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.443314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.443332] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.443347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.443363] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  375.443377] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  375.443392] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  375.443406] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  375.443424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.443445] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  375.443462] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  375.458712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.458745] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.458920] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.477146] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  375.477174] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  375.477214] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  375.477246] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  375.477304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.477335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  375.477361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  375.477385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  375.477409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  375.477432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  375.477454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  375.477476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  375.477501] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  375.477528] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.477553] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  375.477578] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  375.477618] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  375.477653] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  375.477681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  375.477708] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.477733] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.477760] [drm:intel_power_well_disable [i915]] disabling DC off
>[  375.477784] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  375.477806] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  375.479263] [drm:intel_power_well_disable [i915]] disabling always-on
>[  375.479577] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  375.479605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.479634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  375.479665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  375.479691] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  375.479718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.479745] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.479769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.479793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  375.479815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.479837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.479844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.479866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.479871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.479893] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  375.479915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  375.479936] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.479957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.479978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.480576] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.480613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.480651] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  375.480686] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  375.480720] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  375.480754] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  375.480792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.480834] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  375.480871] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  375.481211] [drm:intel_power_well_enable [i915]] enabling always-on
>[  375.481232] [drm:intel_power_well_enable [i915]] enabling DC off
>[  375.481506] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  375.481536] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  375.481563] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  375.481622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.481653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  375.481678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  375.481701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  375.481725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  375.481748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  375.481771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  375.481793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  375.481818] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  375.481845] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.481871] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  375.481896] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  375.481927] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  375.481952] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  375.482550] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  375.482587] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  375.492316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.500903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.509504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.518100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.526695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.535291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.543885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.552479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.561071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.569658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.578554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.587127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.595657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.604163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.612648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.621117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.629577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.638051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.643946] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  375.704731] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  375.704751] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  375.704798] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  375.705634] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  375.706337] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  375.708112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.708131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.708149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.708168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.714049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.714068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  375.719215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.721661] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  375.722208] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.722276] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  375.722294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.722319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.739126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  375.739159] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.739207] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.740274] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  375.740297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.740320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  375.740345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  375.740365] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  375.740386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.740407] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.740427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.740446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  375.740464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.740481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.740486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.740503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.740507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.740525] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  375.740541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  375.740558] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.740575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.740590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.740615] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.740631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.740649] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  375.740665] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  375.740682] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  375.740698] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  375.740718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.740741] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  375.740760] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  375.755845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.755878] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.755930] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.773116] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  375.773149] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  375.773197] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  375.773235] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  375.773302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.773338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  375.773368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  375.773402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  375.773432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  375.773461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  375.773487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  375.773513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  375.773542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  375.773575] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.773604] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  375.773633] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  375.773679] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  375.773718] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  375.773750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  375.773781] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.773811] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.773842] [drm:intel_power_well_disable [i915]] disabling DC off
>[  375.773871] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  375.773896] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  375.774405] [drm:intel_power_well_disable [i915]] disabling always-on
>[  375.775224] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  375.775256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.775291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  375.775328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  375.775358] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  375.775390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.775421] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.775451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.775480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  375.775507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.775534] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.775542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.775567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.775573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  375.775600] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  375.775626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  375.775653] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.775679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.775704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.775736] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.775761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.775788] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  375.775814] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  375.775839] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  375.775863] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  375.775894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.775928] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  375.775958] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  375.776150] [drm:intel_power_well_enable [i915]] enabling always-on
>[  375.776183] [drm:intel_power_well_enable [i915]] enabling DC off
>[  375.776464] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  375.776500] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  375.776528] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  375.776621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.776656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  375.776687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  375.776715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  375.776743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  375.776771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  375.776798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  375.776826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  375.776855] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  375.776888] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  375.776919] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  375.776948] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  375.776988] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  375.777056] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  375.779240] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  375.779279] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  375.788968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.797736] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.806554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.815324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.824089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.832862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.841629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.850395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.859159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.867918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.876989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.885808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.894483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.903059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.911589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.920093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.928580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.937057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.939808] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  376.000047] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  376.000069] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  376.000125] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  376.001612] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  376.003422] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  376.005283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  376.005301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  376.005318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  376.005334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  376.010459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  376.010476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  376.015600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  376.018082] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  376.018561] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  376.018608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  376.018624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  376.018647] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  376.035401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.035428] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.035470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.036351] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.036371] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.036391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.036413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.036430] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.036448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.036467] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.036484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.036501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.036517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.036532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.036536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.036552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.036555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.036571] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.036586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.036601] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.036616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.036631] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.036649] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.036664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.036680] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.036695] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.036710] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.036724] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.036742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.036762] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.036779] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.052212] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  376.052245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  376.052421] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  376.069020] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  376.069044] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  376.069080] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  376.069108] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  376.069159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.069186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.069208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.069229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.069249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.069270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.069289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.069308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.069330] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.069353] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.069375] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.069396] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.069432] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  376.069463] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  376.069488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.069511] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.069533] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.069556] [drm:intel_power_well_disable [i915]] disabling DC off
>[  376.069577] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  376.069596] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  376.071144] [drm:intel_power_well_disable [i915]] disabling always-on
>[  376.071434] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.071463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.071493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.071524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.071550] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.071577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.071604] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.071629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.071654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.071678] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.071700] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.071707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.071729] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.071734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.071756] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.071778] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.071800] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.071821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.071841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.071867] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.071889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.071911] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.071933] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.071955] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.071976] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.072840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.072882] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.072920] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.073162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  376.073183] [drm:intel_power_well_enable [i915]] enabling DC off
>[  376.073461] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  376.073491] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  376.073516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  376.073576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.073607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.073632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.073656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.073679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.073701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.073724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.073746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.073772] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.073799] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.073825] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.073851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.073881] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  376.073906] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  376.076064] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  376.076091] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  376.085733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.094328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.102928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.111701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.120297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.128891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.137496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.146093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.154684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.163278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.171868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.180436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.188965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.197492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.205978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.214463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.222924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.231383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.237479] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  376.297730] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  376.297750] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  376.297797] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  376.298627] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  376.299349] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  376.301951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  376.301973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  376.302056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  376.302083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  376.307400] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  376.307420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  376.312553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  376.315039] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  376.315552] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  376.315614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  376.315632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  376.315657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  376.332412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.332442] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.332488] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.333392] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.333414] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.333437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.333461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.333481] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.333502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.333523] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.333542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.333561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.333579] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.333597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.333601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.333618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.333622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.333640] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.333657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.333674] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.333690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.333706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.333727] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.333743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.333761] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.333778] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.333794] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.333810] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.333830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.333852] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.333871] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.349210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  376.349247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  376.349442] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  376.366051] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  376.366084] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  376.366131] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  376.366170] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  376.366236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.366273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.366303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.366332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.366359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.366385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.366412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.366438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.366467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.366499] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.366529] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.366559] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.366606] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  376.366645] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  376.366678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.366709] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.366739] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.366770] [drm:intel_power_well_disable [i915]] disabling DC off
>[  376.366799] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  376.366824] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  376.367339] [drm:intel_power_well_disable [i915]] disabling always-on
>[  376.368292] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.368338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.368385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.368438] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.368478] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.368522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.368567] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.368609] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.368650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.368690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.368729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.368740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.368777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.368786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.368824] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.368865] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.368905] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.368944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.368984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.369068] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.369111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.369154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.369197] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.369236] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.369276] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.369322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.369370] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.369415] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.369578] [drm:intel_power_well_enable [i915]] enabling always-on
>[  376.369618] [drm:intel_power_well_enable [i915]] enabling DC off
>[  376.369913] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  376.369965] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  376.370043] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  376.370116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.370164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.370206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.370250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.370291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.370331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.370370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.370410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.370452] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.370498] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.370542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.370585] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.370634] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  376.370677] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  376.373470] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  376.373511] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  376.383252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.391947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.400836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.409601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.418364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.427122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.435880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.444641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.453398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.462155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.470907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.479793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.488441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.497017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.505552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.514070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.522554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.531023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.533563] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  376.594687] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  376.594706] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  376.594754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  376.595589] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  376.596298] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  376.598076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  376.598096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  376.598113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  376.598132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  376.604002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  376.604019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  376.609153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  376.611542] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  376.612066] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  376.612111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  376.612127] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  376.612150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  376.628930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.628957] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.629049] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.629974] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.630031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.630062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.630093] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.630113] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.630133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.630152] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.630171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.630188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.630204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.630221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.630227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.630243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.630246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.630263] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.630278] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.630293] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.630308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.630323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.630341] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.630357] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.630373] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.630388] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.630403] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.630418] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.630438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.630458] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.630476] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.645711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  376.645743] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  376.645793] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  376.663037] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  376.663065] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  376.663106] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  376.663138] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  376.663196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.663227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.663252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.663276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.663300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.663323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.663345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.663367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.663392] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.663419] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.663445] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.663469] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.663510] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  376.663544] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  376.663573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.663600] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.663626] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.663652] [drm:intel_power_well_disable [i915]] disabling DC off
>[  376.663677] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  376.663698] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  376.664164] [drm:intel_power_well_disable [i915]] disabling always-on
>[  376.664717] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.664746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.664776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.664808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.664834] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.664861] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.664889] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.664915] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.664940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.664965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.665019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.665031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.665058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.665067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.665096] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.665125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.665153] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.665181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.665208] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.665241] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.665270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.665307] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.665500] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.665524] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.665547] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.665573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.665604] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.665630] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.665721] [drm:intel_power_well_enable [i915]] enabling always-on
>[  376.665743] [drm:intel_power_well_enable [i915]] enabling DC off
>[  376.666070] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  376.666120] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  376.666147] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  376.666223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.666252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.666276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.666300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.666324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.666347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.666369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.666391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.666416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.666442] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.666468] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.666493] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.666523] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  376.666548] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  376.668705] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  376.668736] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  376.678451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.687078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.695778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.704476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.713140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.721799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.730462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.739124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.747784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.756476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.765140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.773799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.782452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.791009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.799529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.808022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.816500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.824964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.831074] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  376.891747] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  376.891765] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  376.891798] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  376.892639] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  376.893339] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  376.895944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  376.895964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  376.896041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  376.896065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  376.901381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  376.901399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  376.906522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  376.909004] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  376.909483] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  376.909530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  376.909546] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  376.909569] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  376.926325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.926352] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.926393] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.927278] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.927299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.927319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.927340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.927358] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.927376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.927395] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.927413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.927430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.927445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.927461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.927465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.927481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.927484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.927500] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.927515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.927530] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.927544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.927559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.927577] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.927593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.927608] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.927623] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.927638] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.927653] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.927670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.927690] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.927707] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.943130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  376.943165] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  376.943361] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  376.960068] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  376.960100] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  376.960148] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  376.960186] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  376.960253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.960289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.960319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.960348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.960376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.960404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.960430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.960456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.960486] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.960518] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.960548] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.960577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.960624] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  376.960664] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  376.960697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  376.960727] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  376.960757] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.960788] [drm:intel_power_well_disable [i915]] disabling DC off
>[  376.960816] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  376.960841] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  376.961356] [drm:intel_power_well_disable [i915]] disabling always-on
>[  376.962289] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  376.962331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.962379] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  376.962427] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  376.962470] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  376.962515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.962559] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  376.962601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  376.962643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  376.962683] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  376.962722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.962733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.962769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.962779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  376.962816] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  376.962856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  376.962896] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.962937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.962976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.963060] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.963102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.963144] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  376.963185] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  376.963226] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  376.963267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  376.963312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.963361] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  376.963404] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  376.963566] [drm:intel_power_well_enable [i915]] enabling always-on
>[  376.963608] [drm:intel_power_well_enable [i915]] enabling DC off
>[  376.963904] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  376.963956] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  376.964033] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  376.964107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  376.964155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  376.964200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  376.964241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  376.964283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  376.964324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  376.964364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  376.964404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  376.964447] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  376.964493] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  376.964537] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  376.964580] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  376.964629] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  376.964672] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  376.966895] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  376.966935] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  376.976877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.985580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.994354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.003123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.011881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.020650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.029414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.038176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.046973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.055802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.064562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.073317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.081963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.090559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.099097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.107601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.116086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.124571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.128998] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  377.189950] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  377.189970] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  377.190014] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  377.190846] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  377.191577] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  377.194163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  377.194183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  377.194201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  377.194219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  377.199600] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  377.199617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  377.204761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  377.207245] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  377.207724] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  377.207768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  377.207785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  377.207807] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  377.224579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  377.224606] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  377.224648] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.225570] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  377.225590] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.225611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  377.225633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  377.225651] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  377.225670] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.225689] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  377.225706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  377.225723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  377.225739] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  377.225754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.225759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.225774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.225778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.225793] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  377.225808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  377.225823] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.225838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.225853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.225872] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  377.225887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.225903] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  377.225918] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  377.225933] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  377.225947] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  377.225965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  377.226012] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  377.226034] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  377.241353] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  377.241385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  377.241560] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  377.260148] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  377.260176] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  377.260217] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  377.260250] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  377.260307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  377.260338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  377.260364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  377.260388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  377.260412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  377.260435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  377.260457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  377.260479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  377.260504] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  377.260531] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.260557] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  377.260582] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  377.260623] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  377.260657] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  377.260685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  377.260712] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  377.260737] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.260764] [drm:intel_power_well_disable [i915]] disabling DC off
>[  377.260788] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  377.260810] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  377.261302] [drm:intel_power_well_disable [i915]] disabling always-on
>[  377.262343] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  377.262376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.262411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  377.262448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  377.262477] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  377.262509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.262540] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  377.262570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  377.262599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  377.262626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  377.262653] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.262661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.262686] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.262692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.262718] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  377.262744] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  377.262769] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.262795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.262819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.262850] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  377.262875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.262902] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  377.262927] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  377.262952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  377.262977] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  377.263053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  377.263097] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  377.263134] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  377.263543] [drm:intel_power_well_enable [i915]] enabling always-on
>[  377.263569] [drm:intel_power_well_enable [i915]] enabling DC off
>[  377.263848] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  377.263884] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  377.263916] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  377.263993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  377.264063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  377.264100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  377.264136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  377.264171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  377.264205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  377.264244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  377.264428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  377.264459] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  377.264494] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.264524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  377.264554] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  377.264591] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  377.264622] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  377.266782] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  377.266814] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  377.276497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.285136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.293896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.302567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.311222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.319905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.328562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.337218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.345902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.354557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.363210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.371862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.380422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.388947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.397563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.406059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.414530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.422989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.427397] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  377.488062] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  377.488096] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  377.488139] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  377.488831] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  377.489636] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  377.491465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  377.491484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  377.491502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  377.491521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  377.497391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  377.497409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  377.502532] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  377.505000] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  377.505478] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  377.505541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  377.505557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  377.505580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  377.522336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  377.522364] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  377.522405] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.523291] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  377.523310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.523331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  377.523353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  377.523371] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  377.523390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.523408] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  377.523425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  377.523443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  377.523459] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  377.523474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.523478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.523493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.523497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.523512] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  377.523527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  377.523542] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.523558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.523572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.523590] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  377.523605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.523621] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  377.523636] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  377.523651] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  377.523666] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  377.523684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  377.523703] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  377.523720] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  377.539138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  377.539174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  377.539370] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  377.556050] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  377.556083] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  377.556131] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  377.556169] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  377.556236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  377.556273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  377.556303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  377.556332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  377.556359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  377.556386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  377.556413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  377.556438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  377.556468] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  377.556500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.556531] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  377.556560] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  377.556607] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  377.556646] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  377.556679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  377.556710] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  377.556740] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.556771] [drm:intel_power_well_disable [i915]] disabling DC off
>[  377.556799] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  377.556824] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  377.557333] [drm:intel_power_well_disable [i915]] disabling always-on
>[  377.558372] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  377.558405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.558441] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  377.558478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  377.558507] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  377.558539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.558571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  377.558601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  377.558630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  377.558658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  377.558685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.558693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.558719] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.558725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.558751] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  377.558777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  377.558802] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.558828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.558853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.558884] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  377.558909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.558936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  377.558961] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  377.559032] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  377.559066] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  377.559106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  377.559150] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  377.559187] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  377.559561] [drm:intel_power_well_enable [i915]] enabling always-on
>[  377.559586] [drm:intel_power_well_enable [i915]] enabling DC off
>[  377.559865] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  377.559901] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  377.559931] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  377.560035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  377.560080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  377.560120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  377.560163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  377.560293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  377.560322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  377.560349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  377.560376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  377.560406] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  377.560439] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.560470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  377.560500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  377.560538] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  377.560568] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  377.562748] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  377.562787] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  377.573465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.582174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.590980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.599805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.608574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.617336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.626099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.634854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.643614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.652373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.661131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.669892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.678540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.687114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.695650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.704157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.712640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.721110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.725532] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  377.784850] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  377.784873] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  377.784916] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  377.786124] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  377.788340] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  377.789775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  377.789793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  377.789809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  377.789825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  377.794950] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  377.794968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  377.800173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  377.802647] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  377.803206] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  377.803232] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  377.803249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  377.803271] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  377.820027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  377.820054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  377.820095] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.820967] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  377.821091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.821112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  377.821135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  377.821152] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  377.821172] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.821191] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  377.821210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  377.821227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  377.821244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  377.821260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.821265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.821280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.821284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.821300] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  377.821316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  377.821332] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.821347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.821362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.821380] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  377.821395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.821412] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  377.821427] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  377.821441] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  377.821456] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  377.821474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  377.821493] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  377.821512] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  377.836797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  377.836833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  377.837256] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  377.853982] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  377.854053] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  377.854100] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  377.854138] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  377.854205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  377.854241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  377.854271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  377.854299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  377.854327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  377.854354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  377.854381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  377.854407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  377.854436] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  377.854468] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.854499] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  377.854527] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  377.854574] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  377.854613] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  377.854646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  377.854677] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  377.854707] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.854737] [drm:intel_power_well_disable [i915]] disabling DC off
>[  377.854766] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  377.854791] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  377.855796] [drm:intel_power_well_disable [i915]] disabling always-on
>[  377.856301] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  377.856333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.856368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  377.856405] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  377.856434] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  377.856466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.856497] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  377.856526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  377.856555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  377.856583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  377.856609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.856617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.856643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.856649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  377.856676] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  377.856701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  377.856726] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.856752] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.856776] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.856808] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  377.856833] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.856860] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  377.856886] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  377.856911] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  377.856936] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  377.856966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  377.857274] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  377.857305] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  377.857411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  377.857436] [drm:intel_power_well_enable [i915]] enabling DC off
>[  377.857717] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  377.857752] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  377.857780] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  377.857857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  377.857893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  377.857922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  377.857952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  377.857979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  377.858220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  377.858248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  377.858276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  377.858305] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  377.858339] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  377.858370] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  377.858400] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  377.858436] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  377.858467] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  377.860628] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  377.860660] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  377.870447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.879101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.887858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.896627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.905393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.914153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.922911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.932029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.940855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.949616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.958376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.967133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.975817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.984413] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  377.992954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.001656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.010147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.018621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.021362] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  378.082152] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  378.082171] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  378.082207] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  378.083037] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  378.083716] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  378.085498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  378.085518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  378.085536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  378.085555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  378.091430] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  378.091450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  378.096586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  378.099075] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  378.099588] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  378.099647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  378.099665] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  378.099689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  378.116444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.116474] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.116520] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.117428] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  378.117450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.117473] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  378.117497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  378.117517] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  378.117538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.117559] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  378.117579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  378.117597] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  378.117615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  378.117633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.117637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.117655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.117659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.117676] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  378.117693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  378.117710] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  378.117727] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.117743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.117763] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.117780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.117798] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  378.117815] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  378.117831] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  378.117847] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  378.117867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.117888] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  378.117908] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  378.133260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  378.133297] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  378.133507] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  378.152202] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  378.152235] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  378.152281] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  378.152319] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  378.152386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.152423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.152453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.152481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.152509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.152537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.152563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.152589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.152619] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.152651] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.152681] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.152711] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.152758] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  378.152797] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  378.152830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.152862] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.152892] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.152923] [drm:intel_power_well_disable [i915]] disabling DC off
>[  378.152951] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  378.152976] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  378.153872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  378.154531] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  378.154565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.154600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  378.154637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  378.154666] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  378.154699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.154730] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  378.154760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  378.154789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  378.154816] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  378.154842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.154850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.154876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.154881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.154908] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  378.154934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  378.154959] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  378.155367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.155409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.155455] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.155498] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.155542] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  378.155585] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  378.155626] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  378.155668] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  378.155714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.155763] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  378.155806] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  378.155966] [drm:intel_power_well_enable [i915]] enabling always-on
>[  378.156141] [drm:intel_power_well_enable [i915]] enabling DC off
>[  378.156435] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  378.156487] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  378.156529] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  378.156648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.156696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.156738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.156779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.156819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.156859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.156899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.156938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.156982] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.157167] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.157199] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.157229] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.157265] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  378.157296] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  378.159455] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  378.159487] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  378.169169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.178598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.187356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.196126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.204887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.213656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.222421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.231185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.239991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.248810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.257571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.266330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.274999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.283620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.292160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.300670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.309159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.317630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.320371] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  378.381683] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  378.381715] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  378.381765] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  378.382598] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  378.383338] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  378.385945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  378.385965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  378.386043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  378.386067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  378.391384] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  378.391402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  378.396527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  378.399010] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  378.399489] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  378.399534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  378.399550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  378.399572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  378.416329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.416356] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.416397] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.417277] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  378.417297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.417318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  378.417339] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  378.417357] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  378.417375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.417394] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  378.417411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  378.417429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  378.417445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  378.417460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.417464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.417480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.417483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.417499] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  378.417515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  378.417530] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  378.417545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.417560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.417578] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.417593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.417609] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  378.417625] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  378.417639] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  378.417654] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  378.417672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.417692] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  378.417710] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  378.433135] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  378.433171] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  378.433365] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  378.450051] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  378.450083] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  378.450130] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  378.450170] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  378.450236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.450273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.450303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.450332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.450359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.450386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.450412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.450438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.450467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.450498] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.450528] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.450557] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.450605] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  378.450644] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  378.450677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.450708] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.450738] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.450769] [drm:intel_power_well_disable [i915]] disabling DC off
>[  378.450798] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  378.450823] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  378.451331] [drm:intel_power_well_disable [i915]] disabling always-on
>[  378.452436] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  378.452470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.452505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  378.452542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  378.452572] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  378.452604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.452635] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  378.452665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  378.452694] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  378.452720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  378.452746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.452754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.452780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.452786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.452812] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  378.452837] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  378.452862] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  378.452887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.452912] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.452942] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.452968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.453044] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:64, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  378.453079] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  378.453112] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  378.453145] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  378.453183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.453227] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  378.453263] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  378.453653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  378.453679] [drm:intel_power_well_enable [i915]] enabling DC off
>[  378.453962] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  378.454047] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  378.454171] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  378.454243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.454280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.454310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.454339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.454367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.454395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.454422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.454449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.454478] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.454512] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.454544] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.454576] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.454611] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  378.454643] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  378.456821] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  378.456860] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  378.466601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.475301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.484072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.492831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.501602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.510365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.519125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.527881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.536642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.545408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.554171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.562927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.571704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.580286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.588824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.597332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.605820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.614291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.618716] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  378.679545] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  378.679565] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  378.679605] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  378.680687] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  378.681144] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  378.682576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  378.682595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  378.682613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  378.682632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  378.688509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  378.688529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  378.693662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  378.696110] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  378.696622] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  378.696672] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  378.696690] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  378.696714] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  378.713468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.713497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.713541] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.714466] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  378.714489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.714512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  378.714537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  378.714556] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  378.714577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.714599] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  378.714619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  378.714638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  378.714656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  378.714673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.714677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.714695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.714699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.714716] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  378.714733] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  378.714750] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  378.714766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.714782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.714803] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.714820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.714837] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] FB:65, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  378.714854] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  378.714871] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  378.714887] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  378.714907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.714929] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  378.714948] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  378.730261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  378.730296] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  378.730359] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  378.747670] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  378.747703] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  378.747750] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  378.747788] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  378.747855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.747891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.747921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.747950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.747977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.748089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.748129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.748172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.748211] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.748262] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.748307] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.748351] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.748414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  378.748468] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  378.748513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.748556] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.748600] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.748648] [drm:intel_power_well_disable [i915]] disabling DC off
>[  378.748690] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  378.748722] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  378.749194] [drm:intel_power_well_disable [i915]] disabling always-on
>[  378.749579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.749667] [drm:intel_power_well_enable [i915]] enabling always-on
>[  378.749707] [drm:intel_power_well_enable [i915]] enabling DC off
>[  378.750050] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  378.750116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.750161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.750197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.750237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.750271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.750310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.750343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.750382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.750418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  378.750459] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.750503] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.750546] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.750588] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.750642] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  378.750684] [drm:intel_power_well_disable [i915]] disabling DC off
>[  378.750728] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  378.750767] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  378.751250] [drm:intel_power_well_disable [i915]] disabling always-on
>[  378.756127] [IGT] kms_flip: exiting, ret=0
>[  378.780947] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  378.781048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.781213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  378.781321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  378.781410] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  378.781505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.781598] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  378.781683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  378.781767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  378.781846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  378.781923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.781941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.782017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.782075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  378.782157] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  378.782233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  378.782308] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  378.782382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.782454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.782544] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.782620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.782694] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  378.782768] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  378.782841] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  378.782932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.783032] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  378.783175] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  378.783427] [drm:intel_power_well_enable [i915]] enabling always-on
>[  378.783498] [drm:intel_power_well_enable [i915]] enabling DC off
>[  378.783826] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  378.783936] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  378.784011] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  378.784291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  378.784385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  378.784461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  378.784534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  378.784606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  378.784678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  378.784748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  378.784818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  378.784897] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  378.784985] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  378.785146] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  378.785230] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  378.785328] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  378.785410] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  378.787356] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  378.787442] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  378.797805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.806774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.815729] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.824674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.833623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.842657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.851663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.860617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.869658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.878637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.887585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.896255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.904860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.913416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.921938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.930436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.938917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.947387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.950135] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  379.009554] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  379.009574] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  379.009604] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  379.010867] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  379.013445] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  379.014787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  379.014803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  379.014818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  379.014834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  379.019964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  379.019993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  379.025124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  379.027608] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  379.028156] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  379.028183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  379.028199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  379.028222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  379.028362] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  379.028378] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  379.044979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  379.045023] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.045067] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.045227] Console: switching to colour frame buffer device 200x56
>[  379.205098] Console: switching to colour dummy device 80x25
>[  379.205209] [IGT] kms_flip: executing
>[  379.216430] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  379.216455] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  379.216467] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  379.216477] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  379.216496] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  379.218143] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  379.218162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  379.220138] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  379.220143] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  379.222136] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  379.222155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  379.224137] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  379.224142] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  379.224145] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  379.224157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  379.224177] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  379.224891] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  379.224913] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  379.225602] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  379.226412] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  379.227910] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  379.227926] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  379.227941] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  379.227956] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  379.228770] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  379.229470] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  379.230316] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  379.230318] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  379.230321] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  379.230323] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  379.230395] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  379.230397] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  379.230401] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  379.230403] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  379.230407] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  379.230408] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  379.230415] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  379.230418] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.230420] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  379.230423] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  379.230425] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  379.230427] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  379.230430] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  379.230432] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  379.230434] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  379.230437] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  379.230439] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  379.230441] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  379.230443] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  379.230446] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  379.230448] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  379.230450] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  379.230453] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  379.230455] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  379.230457] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  379.230459] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  379.230462] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  379.230464] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  379.230466] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  379.230468] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  379.230471] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  379.230656] [IGT] kms_flip: starting subtest basic-flip-vs-modeset
>[  379.231174] [drm:drm_mode_addfb2] [FB:61]
>[  379.231207] [drm:drm_mode_addfb2] [FB:78]
>[  379.270613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.270663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.270731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  379.270752] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  379.270788] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  379.279494] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  379.279510] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  379.279531] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  379.279551] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  379.279569] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  379.279602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  379.279620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  379.279634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  379.279648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  379.279661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  379.279676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  379.279689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  379.279702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  379.279716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  379.279732] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  379.279747] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.279761] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  379.279775] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  379.279795] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  379.279815] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  379.279836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.279853] [drm:intel_power_well_disable [i915]] disabling DC off
>[  379.279867] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  379.279879] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  379.280331] [drm:intel_power_well_disable [i915]] disabling always-on
>[  379.280406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  379.280825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  379.280912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.280925] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  379.281004] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  379.281026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  379.281052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  379.281076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  379.281097] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  379.281120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  379.281141] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  379.281162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  379.281182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  379.281202] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  379.281222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  379.281227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.281245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  379.281250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.281270] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  379.281290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  379.281309] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  379.281329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  379.281348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  379.281370] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  379.281389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  379.281409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  379.281429] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  379.281448] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  379.281470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.281492] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  379.281514] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  379.281764] [drm:intel_power_well_enable [i915]] enabling always-on
>[  379.281776] [drm:intel_power_well_enable [i915]] enabling DC off
>[  379.282075] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  379.282101] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  379.282123] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  379.282164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  379.282188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  379.282209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  379.282230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  379.282251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  379.282271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  379.282291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  379.282311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  379.282333] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  379.282356] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.282377] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  379.282399] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  379.282423] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  379.282444] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  379.284586] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  379.284602] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  379.294185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.302647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.311108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.319567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.328026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.336485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.344943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.353404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.361863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.370322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.378781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.387240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.395697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.404156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.412614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.421072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.429530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.437988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.446446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.447482] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  379.508173] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  379.508191] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  379.508228] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  379.508907] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  379.509707] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  379.510787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  379.510803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  379.510818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  379.510833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  379.517482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  379.517500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  379.522913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  379.525392] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  379.525834] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  379.525868] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  379.525882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  379.525903] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  379.526077] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  379.526102] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  379.542663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  379.542687] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.542724] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.559391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.559400] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  379.576198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.576254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.592774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  379.592809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  379.593136] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  379.609922] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  379.609955] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  379.610147] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  379.610212] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  379.610269] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  379.610344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  379.610384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  379.610417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  379.610450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  379.610481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  379.610514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  379.610543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  379.610571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  379.610601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  379.610635] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  379.610668] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.610699] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  379.610728] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  379.610772] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  379.610813] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  379.610855] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.610890] [drm:intel_power_well_disable [i915]] disabling DC off
>[  379.610919] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  379.610944] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  379.611891] [drm:intel_power_well_disable [i915]] disabling always-on
>[  379.612193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.612218] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  379.612311] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  379.612343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  379.612377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  379.612413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  379.612442] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  379.612474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  379.612505] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  379.612534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  379.612563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  379.612590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  379.612616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  379.612623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.612648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  379.612654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.612680] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  379.612706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  379.612731] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  379.612756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  379.612780] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  379.612812] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  379.612837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  379.612862] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  379.612887] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  379.612912] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  379.612942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.612977] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  379.613181] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  379.613336] [drm:intel_power_well_enable [i915]] enabling always-on
>[  379.613376] [drm:intel_power_well_enable [i915]] enabling DC off
>[  379.613666] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  379.613705] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  379.613740] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  379.613807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  379.613842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  379.613872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  379.613900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  379.613927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  379.613955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  379.613982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  379.614120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  379.614166] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  379.614215] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.614261] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  379.614297] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  379.614335] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  379.614365] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  379.616555] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  379.616588] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  379.626412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.635065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.643814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.652680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.661584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.670472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.679373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.688257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.697137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.706118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.715015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.723981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.732922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.741844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.750465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.759022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.767545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.776785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.777876] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  379.838885] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  379.838905] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  379.838944] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  379.839777] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  379.840546] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  379.843162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  379.843186] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  379.843207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  379.843230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  379.848613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  379.848634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  379.853797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  379.856286] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  379.856813] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  379.856860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  379.856879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  379.856905] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  379.857132] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  379.857162] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  379.873656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  379.873687] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.873736] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.874584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.874636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.890487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  379.890531] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  379.890769] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  379.909183] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  379.909227] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  379.909290] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  379.909347] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  379.909397] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  379.909486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  379.909537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  379.909579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  379.909620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  379.909659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  379.909701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  379.909738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  379.909775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  379.909816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  379.909863] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  379.909907] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.909949] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  379.909989] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  379.910335] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  379.910421] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  379.910511] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.910588] [drm:intel_power_well_disable [i915]] disabling DC off
>[  379.910649] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  379.910686] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  379.911651] [drm:intel_power_well_disable [i915]] disabling always-on
>[  379.911897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  379.911919] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  379.912166] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  379.912234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  379.912293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  379.912346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  379.912390] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  379.912437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  379.912483] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  379.912526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  379.912567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  379.912607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  379.912645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  379.912656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.912692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  379.912701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  379.912740] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  379.912777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  379.912816] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  379.912852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  379.912889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  379.912933] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  379.912971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  379.913212] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  379.913270] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  379.913329] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  379.913396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.913467] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  379.913530] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  379.913684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  379.913720] [drm:intel_power_well_enable [i915]] enabling DC off
>[  379.914163] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  379.914561] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  379.914612] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  379.914733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  379.914782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  379.914824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  379.914864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  379.914903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  379.914942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  379.914980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  379.915166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  379.915230] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  379.915300] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  379.915368] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  379.915414] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  379.915465] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  379.915509] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  379.917740] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  379.917801] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  379.927781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.936695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.945611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.954518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.963417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.972362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.982154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  379.991156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.000127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.008969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.017852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.026638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.035275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.043843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.052378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.060889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.069378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.077851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.080580] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  380.141198] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  380.141219] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  380.141261] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  380.142099] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  380.142785] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  380.144547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  380.144566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  380.144584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  380.144603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  380.150509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  380.150529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  380.155671] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  380.158158] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  380.158664] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.158732] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  380.158750] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  380.158775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  380.158819] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.158838] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.175554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  380.175583] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  380.175628] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.176504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  380.176551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.192246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.192281] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.192337] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.209656] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  380.209689] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  380.209732] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.209773] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  380.209808] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  380.209873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  380.209909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  380.209940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  380.209968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  380.210083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  380.210129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  380.210177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  380.210221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  380.210270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  380.210320] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  380.210366] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.210411] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  380.210454] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  380.210514] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.210570] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.210627] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  380.210678] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.210722] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  380.210761] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  380.211244] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.211475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  380.211499] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  380.211620] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  380.211665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.211710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  380.211759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  380.211802] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  380.211846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.211892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  380.211936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.211979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  380.212058] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  380.212102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.212115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  380.212153] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.212164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  380.212205] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  380.212245] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  380.212286] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.212327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.212368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.212415] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  380.212458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.212499] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  380.212539] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  380.212579] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  380.212625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.212674] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  380.212716] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  380.212875] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.212914] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.213240] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  380.213297] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.213338] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.213456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  380.213503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  380.213546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  380.213587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  380.213628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  380.213670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  380.213709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  380.213749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  380.213792] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  380.213838] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.213882] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  380.213925] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  380.213975] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  380.214052] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  380.216220] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  380.216252] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  380.225881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.234543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.243293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.252076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.260848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.269625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.278402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.287179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.296012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.304844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.313620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.322394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.331088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.339682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.348227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.356741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.365234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.373707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.378136] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  380.438435] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  380.438543] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  380.438742] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  380.440022] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  380.441679] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  380.443653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  380.443760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  380.443857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  380.443957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  380.450679] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  380.450779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  380.456325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  380.459035] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  380.461370] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.461506] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  380.461595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  380.461707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  380.462544] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.462685] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.478450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  380.478580] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  380.478764] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.480291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  380.480500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.495362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.495489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.496591] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.513456] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  380.513547] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  380.513668] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.513781] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  380.513882] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  380.514229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  380.514370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  380.514508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  380.514632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  380.514755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  380.514884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  380.514999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  380.515193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  380.515321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  380.515467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  380.515601] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.515728] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  380.515851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  380.516027] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.516304] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.516468] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  380.516612] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.516735] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  380.516848] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  380.517867] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.518871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  380.518915] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  380.519334] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  380.519466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.519605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  380.519751] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  380.519879] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  380.520011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.520236] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  380.520369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.520501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  380.520626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  380.520748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.520780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  380.520887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.520918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  380.521040] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  380.521247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  380.521364] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.521481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.521598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.521729] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  380.521846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.521964] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  380.522170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  380.522289] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  380.522423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.522565] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  380.522694] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  380.523243] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.523355] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.523718] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  380.524361] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.524481] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.524776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  380.524878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  380.524964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  380.525177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  380.525286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  380.525408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  380.525525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  380.525644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  380.525769] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  380.525908] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.526038] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  380.526260] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  380.526406] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  380.526536] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  380.528956] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  380.529149] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  380.539308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.548239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.557165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.566158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.575147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.584137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.593135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.602130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.611129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.620055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.628756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.637338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.645874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.654381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.662871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.671348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.679812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.688271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.690999] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  380.751874] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  380.751897] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  380.751938] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  380.752573] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  380.753386] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  380.754109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  380.754129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  380.754147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  380.754166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  380.759923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  380.759940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  380.765075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  380.767559] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  380.768092] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.768134] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  380.768150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  380.768173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  380.768215] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.768232] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.784963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  380.785022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  380.785065] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.786036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  380.786106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.801643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.801678] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.801871] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.820182] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  380.820215] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  380.820258] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.820297] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  380.820333] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  380.820399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  380.820435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  380.820464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  380.820493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  380.820520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  380.820550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  380.820576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  380.820602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  380.820632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  380.820665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  380.820696] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.820726] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  380.820754] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  380.820800] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.820839] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.820880] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  380.820915] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.820943] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  380.820968] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  380.821474] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.821698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  380.821723] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  380.821838] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  380.821875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.821920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  380.821968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  380.822039] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  380.822088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.822127] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  380.822169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.822205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  380.822245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  380.822279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.822291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  380.822324] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.822336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  380.822374] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  380.822408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  380.822444] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.822476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.822512] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.822549] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  380.822585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.822617] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  380.822653] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  380.822683] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  380.822725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.822771] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  380.822806] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  380.822962] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.823030] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.823324] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  380.823375] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.823415] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.823527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  380.823573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  380.823608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  380.823646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  380.823678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  380.823715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  380.823747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  380.823785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  380.823821] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  380.823864] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  380.823906] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  380.823948] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  380.824001] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  380.824087] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  380.826254] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  380.826286] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  380.835900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.844544] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.853280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.862104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.870863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.879624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.888382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.897146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.905915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.915022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.923845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.932607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.941291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.949885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.958427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.966938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.975430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.983905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.988328] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  381.049949] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  381.050038] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  381.050217] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  381.051707] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  381.052803] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  381.053766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  381.053855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  381.053936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  381.054021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  381.059653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  381.059734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  381.065276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  381.067954] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  381.069922] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.070249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  381.070328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  381.070427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  381.070980] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.071373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.086969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.087151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.087311] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.088714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.088892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.103735] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.103860] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.104678] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.122604] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  381.122690] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  381.122811] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.122920] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  381.123020] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  381.123443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  381.123595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  381.123725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  381.123853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  381.123957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  381.124156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  381.124253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  381.124353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  381.124456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.124599] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  381.124732] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.124863] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  381.124992] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  381.125263] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.125436] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.125615] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.125764] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.125848] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  381.125920] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  381.126921] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.127840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.127881] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  381.128286] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  381.128422] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.128560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  381.128668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  381.128755] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  381.128850] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.128941] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  381.129036] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.129224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  381.129327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  381.129423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.129455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  381.129547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.129575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  381.129672] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  381.129765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  381.129859] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.129969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.130128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.130235] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  381.130349] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.130462] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  381.130575] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  381.130686] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  381.130818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.130952] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  381.131134] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  381.131568] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.131685] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.132055] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  381.132601] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.132723] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.132937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  381.133153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  381.133267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  381.133367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  381.133487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  381.133601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  381.133716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  381.133830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  381.133927] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  381.134032] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.134231] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  381.134344] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  381.134491] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  381.134617] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  381.137032] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  381.137194] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  381.147403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.156387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.165378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.174316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.183219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.192116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.201120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.210018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.219002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.227953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.236779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.245400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.253959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.262507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.271006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.279484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.287949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.296434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.297319] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  381.358001] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  381.358023] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  381.358076] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  381.358921] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  381.361484] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  381.362819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  381.362837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  381.362853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  381.362870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  381.367995] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  381.368013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  381.373792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  381.376275] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  381.376745] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.376800] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  381.376817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  381.376840] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  381.376977] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.377161] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.393593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.393620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.393661] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.394512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.394555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.410353] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.410386] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.410563] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.429171] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  381.429203] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  381.429247] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.429287] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  381.429323] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  381.429388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  381.429424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  381.429454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  381.429482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  381.429510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  381.429540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  381.429567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  381.429593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  381.429622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.429655] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  381.429686] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.429715] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  381.429744] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  381.429790] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.429829] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.429870] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.429905] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.429933] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  381.429958] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  381.431287] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.431852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.431868] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  381.431949] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  381.431981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.432070] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  381.432124] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  381.432169] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  381.432217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.432265] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  381.432311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.432355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  381.432397] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  381.432438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.432449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  381.432485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.432495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  381.432534] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  381.432576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  381.432616] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.432655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.432695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.432739] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  381.432780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.432822] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  381.432863] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  381.432902] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  381.432948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.432999] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  381.433077] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  381.433209] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.433249] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.433541] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  381.433594] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.433635] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.433706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  381.433754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  381.433796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  381.433837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  381.433877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  381.433917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  381.433956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  381.433996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  381.434078] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  381.434129] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.434174] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  381.434219] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  381.434268] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  381.434311] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  381.436481] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  381.436513] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  381.446214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.454900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.463662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.472436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.481208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.489983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.498812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.507594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.516365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.525133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.533899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.542667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.551363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.559959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.568531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.577046] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.585538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.594014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.596556] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  381.657267] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  381.657289] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  381.657339] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  381.658164] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  381.660711] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  381.662048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  381.662066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  381.662081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  381.662098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  381.667223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  381.667241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  381.672379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  381.674860] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  381.675388] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.675438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  381.675455] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  381.675478] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  381.675526] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.675549] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.692229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.692254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.692293] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.693114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.693157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.708968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.709035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.709098] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.726164] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  381.726197] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  381.726240] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.726282] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  381.726317] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  381.726382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  381.726418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  381.726447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  381.726476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  381.726503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  381.726532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  381.726559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  381.726585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  381.726616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.726648] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  381.726679] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.726709] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  381.726738] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  381.726784] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.726822] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.726864] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.726899] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.726927] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  381.726952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  381.727467] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.728084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.728108] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  381.728229] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  381.728274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.728321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  381.728371] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  381.728413] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  381.728459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.728503] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  381.728545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.728588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  381.728628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  381.728668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.728678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  381.728715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.728724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  381.728762] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  381.728801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  381.728839] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.728878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.728916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.728959] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  381.729037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.729081] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  381.729124] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  381.729165] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  381.729212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.729261] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  381.729305] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  381.729463] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.729502] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.729794] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  381.729847] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.729889] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.729959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  381.730043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  381.730088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  381.730132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  381.730174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  381.730217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  381.730257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  381.730297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  381.730339] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  381.730386] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.730431] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  381.730475] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  381.730525] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  381.730568] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  381.732733] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  381.732765] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  381.742462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.751124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.759879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.768650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.777433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.786261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.795026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.803882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.812650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.821414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.830179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.839001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.847747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.856341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.864882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.873392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.881882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.890374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  381.892914] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  381.953521] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  381.953544] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  381.953593] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  381.954573] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  381.956335] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  381.958194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  381.958211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  381.958227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  381.958244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  381.963382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  381.963400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  381.968525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  381.971004] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  381.971475] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.971533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  381.971549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  381.971572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  381.971708] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.971726] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.988323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  381.988350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  381.988391] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  381.989204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  381.989247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.005045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.005077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.005231] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.022081] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  382.022109] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  382.022146] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.022181] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  382.022211] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  382.022267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.022298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.022324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.022348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.022372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.022397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.022420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.022442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.022468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.022496] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.022522] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.022547] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.022572] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.022612] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.022660] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.022702] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.022738] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.022766] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  382.022791] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  382.024128] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.024289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.024306] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  382.024387] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  382.024421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.024456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  382.024493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  382.024523] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  382.024555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.024587] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  382.024617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.024646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  382.024673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  382.024699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.024706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.024732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.024738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.024764] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  382.024790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  382.024815] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.024841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.024866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.024897] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  382.024923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.024948] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  382.024973] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  382.025048] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  382.025088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.025131] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  382.025167] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  382.025303] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.025334] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.025616] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  382.025653] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.025683] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.025755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.025790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.025819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.025848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.025875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.025903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.025929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.025956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.025987] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.026057] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.026098] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.026136] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.026181] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  382.026217] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  382.028385] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  382.028417] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  382.038107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.046762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.055573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.064351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.073128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.081899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.090680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.099478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.108273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.117104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.125864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.134623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.143303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.151900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.160446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.168956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.178480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.186954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.189749] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  382.250560] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  382.250580] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  382.250622] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  382.251484] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  382.252215] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  382.253974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  382.254011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  382.254030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  382.254049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  382.259900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  382.259918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  382.265036] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  382.267519] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  382.268033] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.268096] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  382.268113] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  382.268136] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  382.268176] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.268193] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.284896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.284921] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.284961] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.285846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.285888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.301666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.301702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.301756] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.319001] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  382.319072] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  382.319117] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.319158] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  382.319194] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  382.319259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.319294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.319323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.319352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.319379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.319408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.319435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.319461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.319492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.319525] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.319557] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.319587] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.319617] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.319662] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.319701] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.319742] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.319777] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.319805] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  382.319830] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  382.320318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.320919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.320944] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  382.321092] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  382.321137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.321184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  382.321233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  382.321275] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  382.321319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.321363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  382.321405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.321449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  382.321489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  382.321528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.321538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.321574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.321583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.321621] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  382.321660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  382.321698] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.321736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.321774] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.321818] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  382.321856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.321894] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  382.321933] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  382.321972] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  382.322056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.322109] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  382.322154] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  382.322313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.322352] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.322646] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  382.322700] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.322740] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.322810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.322859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.322902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.322945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.322987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.323063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.323104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.323145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.323189] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.323238] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.323283] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.323328] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.323378] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  382.323421] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  382.325616] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  382.325649] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  382.335469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.344130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.352889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.361668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.370443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.379282] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.388114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.396882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.405652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.414428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.423205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.432021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.440783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.449379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.457922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.466433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.474925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.483400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.487828] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  382.548526] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  382.548547] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  382.548584] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  382.549420] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  382.550162] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  382.552742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  382.552762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  382.552780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  382.552799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  382.558183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  382.558200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  382.563321] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  382.565806] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  382.566321] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.566380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  382.566397] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  382.566420] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  382.566557] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.566574] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.583175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.583199] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.583237] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.584047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.584090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.599912] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.599944] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.600178] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.617030] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  382.617058] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  382.617096] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.617131] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  382.617161] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  382.617218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.617249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.617273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.617297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.617320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.617345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.617368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.617390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.617415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.617444] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.617470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.617496] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.617520] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.617559] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.617594] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.617629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.617659] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.617683] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  382.617704] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  382.618952] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.619182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.619196] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  382.619266] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  382.619294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.619324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  382.619355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  382.619381] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  382.619407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.619434] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  382.619459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.619484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  382.619507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  382.619528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.619534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.619556] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.619561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.619583] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  382.619605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  382.619626] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.619647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.619667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.619694] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  382.619716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.619737] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  382.619759] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  382.619779] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  382.619806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.619835] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  382.619861] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  382.619949] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.619970] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.620882] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  382.620914] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.620943] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.621121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.621166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.621196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.621221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.621245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.621269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.621292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.621315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.621340] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.621368] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.621394] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.621419] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.621450] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  382.621477] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  382.623638] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  382.623665] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  382.633351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.641945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.650664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.659324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.667981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.676680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.685338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.693989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.702680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.711342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.719997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.728693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.737315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.745871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.754389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.762886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.771366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.780151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.786262] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  382.846525] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  382.846546] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  382.846582] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  382.847418] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  382.848188] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  382.850767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  382.850787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  382.850805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  382.850824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  382.856210] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  382.856228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  382.861352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  382.863825] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  382.864357] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.864411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  382.864427] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  382.864450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  382.864586] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.864604] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.881202] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.881228] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.881269] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.882112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.882157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.897894] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.897923] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.898110] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.915967] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  382.916029] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  382.916068] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.916103] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  382.916133] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  382.916190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.916220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.916246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.916270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.916294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.916319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.916342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.916364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.916390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  382.916418] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.916444] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.916470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.916494] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.916533] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.916567] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.916603] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  382.916632] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.916656] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  382.916678] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  382.917922] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.918141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  382.918162] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  382.918233] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  382.918261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.918291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  382.918323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  382.918348] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  382.918375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.918402] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  382.918427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.918451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  382.918474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  382.918496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.918501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.918523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.918528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  382.918550] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  382.918571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  382.918593] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.918614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.918634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.918661] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  382.918682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.918703] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  382.918725] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  382.918745] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  382.918772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  382.918801] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  382.918826] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  382.918915] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.918936] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.919855] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  382.920194] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.920230] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.920298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  382.920333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  382.920358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  382.920383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  382.920406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  382.920430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  382.920453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  382.920475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  382.920500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  382.920527] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  382.920552] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  382.920577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  382.920607] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  382.920632] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  382.922788] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  382.922815] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  382.932467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.941063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.949719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.958380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.967036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.975696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.984353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  382.993007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.001702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.010359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.019055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.027710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.036322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.044880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.053402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.061898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.070388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.078854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.083068] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  383.143800] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  383.143818] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  383.143850] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  383.144685] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  383.145450] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  383.148030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  383.148050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  383.148068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.148087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  383.153466] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  383.153484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  383.158607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  383.161092] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  383.161561] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.161614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  383.161630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  383.161653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  383.161791] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.161808] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.178405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  383.178432] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.178472] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.179286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.179329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.195170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.195202] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.195377] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.214135] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  383.214163] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  383.214201] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.214235] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  383.214265] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  383.214322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.214353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  383.214378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  383.214402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  383.214426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  383.214452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  383.214474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  383.214496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  383.214522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  383.214550] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  383.214576] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.214601] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  383.214626] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  383.214666] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.214699] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.214736] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.214766] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.214790] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  383.214812] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  383.215770] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.215947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.216031] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  383.216134] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  383.216162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.216191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  383.216223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  383.216249] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  383.216276] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.216304] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  383.216329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.216354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  383.216378] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  383.216401] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.216407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  383.216429] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.216434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  383.216457] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  383.216480] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  383.216502] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.216523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.216544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.216571] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  383.216593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.216615] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  383.216637] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  383.216658] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  383.216684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.216714] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  383.216740] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  383.216829] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.216850] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.217250] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  383.217653] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.217691] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.217760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.217804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  383.217842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  383.217868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  383.217892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  383.217915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  383.217938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  383.217960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  383.218010] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  383.218046] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.218083] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  383.218110] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  383.218143] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  383.218169] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  383.220330] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  383.220362] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  383.229954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.238779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.247475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.256133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.264784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.273480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.282136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.290787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.299482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.308139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.316793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.325490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.334078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.342616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.351130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.359619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.368092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.376774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.381184] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  383.441958] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  383.441978] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  383.442015] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  383.442842] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  383.443529] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  383.445283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  383.445302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  383.445320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.445338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  383.451232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  383.451250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  383.456386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  383.459055] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  383.461809] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.461956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  383.462156] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  383.462330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  383.462597] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.462704] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.478931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  383.479052] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.479466] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.481149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.481357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.495611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.495731] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.495907] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.513878] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  383.513968] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  383.514339] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.514503] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  383.514654] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  383.514882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.514986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  383.515192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  383.515299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  383.515400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  383.515511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  383.515624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  383.515741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  383.515869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  383.516015] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  383.516237] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.516372] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  383.516500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  383.516682] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.516817] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.516940] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.517150] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.517279] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  383.517390] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  383.517923] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.518909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.518960] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  383.519385] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  383.519496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.519625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  383.519763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  383.519863] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  383.519996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.520223] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  383.520332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.520451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  383.520552] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  383.520664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.520695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  383.520804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.520829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  383.520935] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  383.521032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  383.521219] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.521311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.521416] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.521522] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  383.521634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.521729] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  383.521840] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  383.521932] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  383.522069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.522252] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  383.522355] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  383.522785] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.522890] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.523345] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  383.523782] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.523898] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.524199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.524339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  383.524445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  383.524560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  383.524660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  383.524768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  383.524861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  383.524966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  383.525170] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  383.525296] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.525433] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  383.525562] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  383.525704] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  383.525808] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  383.528228] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  383.528321] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  383.538410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.547384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.556351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.565266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.574183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.583156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.592142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.601125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.610055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.619021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.627904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.636557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.645153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.653716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.662224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.670710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.679185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.687649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.690390] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  383.751220] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  383.751243] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  383.751293] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  383.751936] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  383.752743] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  383.753468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  383.753487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  383.753505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.753524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  383.759272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  383.759290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  383.764416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  383.766867] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  383.767388] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.767424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  383.767440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  383.767463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  383.767505] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.767522] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.784214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  383.784240] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.784280] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.785122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.785169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.800941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.800976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.801120] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.818355] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  383.818388] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  383.818431] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.818472] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  383.818507] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  383.818572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.818609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  383.818639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  383.818667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  383.818693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  383.818722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  383.818748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  383.818773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  383.818802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  383.818835] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  383.818867] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.818897] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  383.818927] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  383.818972] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.819077] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.819132] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.819184] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.819228] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  383.819269] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  383.819710] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.819932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.819956] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  383.820108] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  383.820153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.820201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  383.820250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  383.820292] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  383.820337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.820382] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  383.820425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.820468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  383.820509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  383.820548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.820559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  383.820595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.820605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  383.820643] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  383.820683] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  383.820722] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.820761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.820801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.820845] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  383.820887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.820928] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  383.820970] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  383.821042] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  383.821087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.821136] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  383.821182] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  383.821336] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.821377] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.821671] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  383.821725] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.821766] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.821885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.821932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  383.821977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  383.822056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  383.822098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  383.822141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  383.822182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  383.822221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  383.822264] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  383.822314] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  383.822357] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  383.822401] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  383.822451] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  383.822493] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  383.824665] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  383.824697] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  383.834441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.843084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.851825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.860587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.869347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.878104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.886856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.895616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.904377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.913143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.921899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.930662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.939351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.947945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.956613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.965129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.973618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.982096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  383.986539] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  384.046756] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  384.046777] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  384.046828] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  384.047867] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  384.050429] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  384.051765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.051782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.051799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.051815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.056940] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.056957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  384.062156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.064630] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  384.065159] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  384.065215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  384.065232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  384.065254] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.065296] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  384.065312] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  384.082023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.082050] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.082091] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.082898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.082940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.098724] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  384.098752] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.098792] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  384.116045] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  384.116073] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  384.116110] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  384.116145] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  384.116175] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  384.116231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.116261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  384.116287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  384.116311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  384.116334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  384.116359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  384.116381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  384.116402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  384.116428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.116456] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  384.116482] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.116507] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  384.116532] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  384.116571] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.116605] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.116641] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.116671] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.116695] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  384.116716] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  384.117690] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.117886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.117907] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  384.118086] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  384.118124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.118165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  384.118207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  384.118244] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  384.118282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.118319] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  384.118356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  384.118392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  384.118427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  384.118460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.118469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  384.118500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.118509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  384.118541] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  384.118576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  384.118611] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.118646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.118680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.118719] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  384.118768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.118809] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  384.118850] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  384.118890] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  384.118937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.118987] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  384.119218] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  384.119373] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.119411] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.119703] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  384.119756] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.119797] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.119914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.119962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  384.120117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  384.120159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  384.120202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  384.120243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  384.120283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  384.120324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  384.120367] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  384.120413] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.120458] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  384.120502] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  384.120551] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  384.120594] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  384.122793] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  384.122826] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  384.132563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.141199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.149854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.158508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.167207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.175900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.184557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.193208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.201897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.210551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.219208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.227881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.236447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.244970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.253494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.261981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.270469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.278929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.285025] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  384.345745] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  384.345764] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  384.345807] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  384.346631] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  384.347363] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  384.350274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.350291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.350307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.350324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.355447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.355465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  384.360587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.363073] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be2548
>[  384.363541] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  384.363596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  384.363612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  384.363635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.363677] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  384.363693] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  384.380390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.380417] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.380458] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.381271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.381314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.397102] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  384.397131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.397172] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  384.415271] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  384.415300] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  384.415337] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  384.415373] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  384.415404] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  384.415461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.415492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  384.415517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  384.415540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  384.415564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  384.415589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  384.415611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  384.415633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  384.415659] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.415687] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  384.415713] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.415738] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  384.415763] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  384.415802] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.415837] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.415872] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.415902] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.415926] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  384.415947] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  384.416905] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.417156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.417177] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  384.417277] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  384.417315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.417358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  384.417398] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  384.417434] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  384.417472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.417510] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  384.417546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  384.417582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  384.417616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  384.417649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.417657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  384.417688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.417696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  384.417727] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  384.417760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  384.417794] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.417828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.417862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.417901] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  384.417935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.417969] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  384.418165] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  384.418199] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  384.418239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.418281] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  384.418319] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  384.418451] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.418484] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.418769] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  384.418815] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.418850] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.418951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.418995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  384.419144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  384.419181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  384.419217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  384.419252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  384.419286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  384.419320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  384.419359] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  384.419397] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.419435] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  384.419473] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  384.419515] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  384.419551] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  384.421743] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  384.421771] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  384.431442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.440036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.448668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.457325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.465978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.474675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.483327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.491982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.500672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.509326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.517978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.526669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.535286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.543841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.552360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.560853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.569330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.578467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.584564] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  384.644467] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  384.644485] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  384.644529] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  384.645352] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  384.646076] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  384.648650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.648670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.648688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.648707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.654147] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.654165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  384.659289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.661759] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  384.662287] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  384.662349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  384.662366] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  384.662388] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.662430] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  384.662447] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  384.679143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.679170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.679211] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.680075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.680134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.695924] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  384.695960] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.696173] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  384.713409] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  384.713438] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  384.713475] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  384.713511] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  384.713541] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  384.713598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.713630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  384.713655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  384.713679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  384.713703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  384.713728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  384.713751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  384.713774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  384.713799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.713827] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  384.713854] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.713896] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  384.713925] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  384.713971] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.714279] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.714337] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.714389] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.714433] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  384.714472] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  384.714913] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.715240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.715266] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  384.715388] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  384.715433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.715479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  384.715527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  384.715569] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  384.715615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.715660] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  384.715704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  384.715748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  384.715789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  384.715829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.715838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  384.715875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.715885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  384.715924] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  384.715965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  384.716158] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.716246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.716288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.716335] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  384.716376] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.716418] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  384.716458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  384.716498] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  384.716542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.716591] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  384.716635] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  384.716789] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.716828] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.717226] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  384.717622] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.717657] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.717723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.717758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  384.717788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  384.717816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  384.717844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  384.717871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  384.717897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  384.717923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  384.717952] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  384.717984] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.718160] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  384.718205] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  384.718255] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  384.718298] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  384.720464] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  384.720495] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  384.730181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.738832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.747562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.756330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.765089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.773843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.782607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.791365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.800119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.808865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.817631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.826392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.835075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.843662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.852207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.860718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.869208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.877680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  384.881904] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  384.942708] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  384.942726] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  384.942771] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  384.943598] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  384.944336] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  384.946938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.946958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.946977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.947056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.952389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.952406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  384.957530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.960012] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4a88
>[  384.960481] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  384.960538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  384.960554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  384.960576] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.960617] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  384.960634] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  384.977329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  384.977354] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.977395] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  384.978209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.978252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.994090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  384.994122] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.994169] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  385.012311] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  385.012340] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  385.012378] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  385.012413] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  385.012448] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  385.012511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.012542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.012568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.012592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.012615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.012640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.012662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.012684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.012709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.012737] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.012764] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.012790] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.012814] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.012854] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.012889] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.012925] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.012956] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.013172] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  385.013247] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  385.013679] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.013875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.013898] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  385.014085] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  385.014123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.014164] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  385.014205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  385.014242] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  385.014281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.014321] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  385.014357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  385.014394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  385.014428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  385.014463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.014472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.014503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.014512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.014545] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  385.014580] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  385.014614] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.014647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.014680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.014718] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  385.014753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.014787] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  385.014820] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  385.014854] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  385.014892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.014934] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  385.014972] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  385.015267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.015301] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.015588] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  385.015633] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.015667] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.015768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.015808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.015845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.015879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.015913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.015947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.015982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.016123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.016160] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.016199] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.016237] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.016273] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.016315] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  385.016354] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  385.018549] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  385.018578] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  385.028365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.036963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.045652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.054309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.062963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.071657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.080309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.088960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.097646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.106297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.114956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.123647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.132254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.140812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.149330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.157824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.166302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.175093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.179503] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  385.240285] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  385.240304] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  385.240349] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  385.241177] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  385.241873] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  385.243637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  385.243657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  385.243675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  385.243694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  385.249584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  385.249602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  385.254744] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  385.257226] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be12a8
>[  385.257698] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  385.257753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  385.257770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  385.257792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  385.257841] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  385.257865] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  385.274565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.274589] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.274628] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.275507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.275550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.291317] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  385.291348] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.291404] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  385.308712] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  385.308740] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  385.308778] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  385.308813] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  385.308844] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  385.308900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.308930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.308956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.308981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.309056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.309100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.309132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.309167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.309204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.309247] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.309289] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.309328] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.309366] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.309417] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.309464] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.309513] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.309555] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.309591] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  385.309624] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  385.310101] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.310279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.310301] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  385.310396] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  385.310432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.310472] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  385.310512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  385.310543] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  385.310578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.310610] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  385.310644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  385.310673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  385.310706] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  385.310734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.310742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.310772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.310779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.310813] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  385.310841] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  385.310872] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.310899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.310929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.310961] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  385.311022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.311058] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  385.311086] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  385.311119] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  385.311158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.311199] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  385.311231] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  385.311364] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.311396] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.311681] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  385.311724] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.311760] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.311818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.311856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.311885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.311918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.311946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.311981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.312039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.312072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.312103] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.312141] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.312180] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.312217] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.312259] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  385.312290] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  385.314457] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  385.314484] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  385.324145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.332738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.341379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.350076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.358779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.367474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.376892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.385549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.394204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.402895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.411555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.420212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.428863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.437423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.445943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.454570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.463065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.471533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.475944] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  385.535577] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  385.535597] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  385.535650] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  385.536491] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  385.537185] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  385.538950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  385.538970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  385.539022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  385.539046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  385.544863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  385.544880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  385.549999] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  385.552480] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be53d8
>[  385.552952] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  385.553045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  385.553070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  385.553104] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  385.553159] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  385.553183] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  385.569811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.569836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.569876] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.570741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.570784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.586574] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  385.586605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.586661] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  385.603877] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  385.603902] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  385.603935] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  385.603966] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  385.604063] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  385.604126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.604157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.604180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.604203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.604226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.604252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.604274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.604296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.604321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.604348] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.604373] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.604398] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.604421] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.604459] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.604493] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.604526] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.604569] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.604593] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  385.604615] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  385.605087] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.605252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.605267] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  385.605336] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  385.605362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.605391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  385.605422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  385.605447] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  385.605474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.605500] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  385.605525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  385.605549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  385.605572] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  385.605594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.605599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.605621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.605626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.605648] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  385.605670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  385.605691] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.605713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.605733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.605759] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  385.605781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.605802] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  385.605823] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  385.605844] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  385.605870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.605899] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  385.605924] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  385.606068] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.606096] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.606387] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  385.606431] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.606467] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.606528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.606558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.606584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.606609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.606632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.606656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.606678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.606701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.606726] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.606754] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.606779] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.606805] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.606835] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  385.606860] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  385.609043] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  385.609071] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  385.618647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.627232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.635896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.644552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.653202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.661940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.670776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.679439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.688094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.696745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.705394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.714053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.722682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.731244] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.739784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.748289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.756776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.765248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.769657] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  385.830562] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  385.830582] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  385.830639] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  385.831483] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  385.832216] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  385.834003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  385.834023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  385.834041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  385.834059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  385.839924] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  385.839944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  385.845091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  385.847578] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be1bf8
>[  385.848154] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  385.848203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  385.848222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  385.848246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  385.848292] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  385.848310] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  385.865033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.865066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.865118] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.866055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.866141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.881764] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  385.881806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.881869] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  385.899071] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  385.899111] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  385.899164] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  385.899212] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  385.899256] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  385.899334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.899377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.899414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.899449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.899482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.899518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.899551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.899583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.899619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  385.899659] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.899697] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.899732] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.899767] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.899821] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.899867] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.899918] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  385.899960] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.900096] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  385.900138] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  385.900591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.900859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  385.900890] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  385.901073] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  385.901122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.901185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  385.901249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  385.901303] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  385.901356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.901395] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  385.901432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  385.901469] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  385.901504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  385.901537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.901547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.901578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.901586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  385.901620] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  385.901652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  385.901684] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.901715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.901747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.901784] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  385.901816] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.901847] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  385.901878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  385.901909] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  385.901948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.901996] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  385.902077] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  385.902269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.902319] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.902625] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  385.902695] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.902762] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.902929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  385.902986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  385.903090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  385.903150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  385.903202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  385.903255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  385.903305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  385.903356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  385.903413] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  385.903491] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  385.903563] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  385.903634] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  385.903717] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  385.903770] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  385.905978] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  385.906057] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  385.915853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.924712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.933625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.942534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.951428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.960339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.969234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.978765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.987667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  385.996617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.005515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.014433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.023243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.031887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.040457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.048985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.057521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.066006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.067062] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  386.128135] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  386.128159] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  386.128216] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  386.129062] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  386.129803] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  386.132435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  386.132461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  386.132485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.132510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  386.137898] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  386.137921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  386.143077] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  386.145571] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  386.146234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  386.146296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  386.146317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  386.146347] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  386.146409] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  386.146440] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  386.163099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  386.163136] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  386.163191] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.164121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  386.164181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.179823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  386.179868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.179946] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  386.197249] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  386.197295] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  386.197356] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  386.197413] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  386.197463] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  386.197552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.197604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  386.197648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  386.197690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  386.197730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  386.197772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  386.197810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  386.197847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  386.197889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  386.197935] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  386.197979] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.198663] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  386.198707] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  386.198767] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.198821] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.198883] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  386.198931] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.198972] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  386.199328] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  386.199770] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.200232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  386.200264] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  386.200414] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  386.200475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.200540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  386.200609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  386.200666] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  386.200726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.200786] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  386.200842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  386.200896] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  386.200949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  386.201000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.201607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  386.201705] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.201719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  386.201784] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  386.201844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  386.201900] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.201955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.202008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.202164] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  386.202235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.202305] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  386.202370] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  386.202447] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  386.202524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.202621] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  386.202704] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  386.202963] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.203092] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.203424] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  386.203507] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.203573] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.203699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.203766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  386.203823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  386.203876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  386.203929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  386.203980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  386.204107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  386.204170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  386.204241] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  386.204319] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.204406] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  386.204481] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  386.204552] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  386.204611] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  386.206819] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  386.206871] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  386.216983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.226028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.235011] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.243959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.252925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.261999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.270937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.280125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.289015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.297969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.306932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.315919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.324698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.333251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.341788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.350286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.358766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.367232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.368327] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  386.428579] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  386.428597] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  386.428655] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  386.429343] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  386.430155] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  386.430875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  386.430894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  386.430912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.430931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  386.436694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  386.436711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  386.441835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  386.444315] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  386.444785] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  386.444843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  386.444859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  386.444881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  386.444929] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  386.444953] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  386.461635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  386.461661] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  386.461702] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.462513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  386.462556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.478363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  386.478391] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.478442] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  386.495740] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  386.495764] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  386.495797] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  386.495827] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  386.495853] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  386.495903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.495930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  386.495952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  386.495973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  386.496304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  386.496333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  386.496369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  386.496392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  386.496419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  386.496447] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  386.496474] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.496499] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  386.496524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  386.496562] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.496597] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.496633] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  386.496663] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.496687] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  386.496708] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  386.497802] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.498166] [drm:drm_mode_addfb2] [FB:61]
>[  386.498201] [drm:drm_mode_addfb2] [FB:65]
>[  386.543444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  386.544096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  386.544682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  386.545303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  386.545339] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  386.545517] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  386.545592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.545669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  386.545749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  386.545816] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  386.545885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.545955] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  386.546030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.546188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  386.546279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  386.546353] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.546380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  386.546455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.546477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  386.546568] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  386.546641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  386.546724] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.546794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.546872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.546957] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  386.547089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.547158] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  386.547237] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  386.547305] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  386.547394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.547492] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  386.547570] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  386.548856] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.548911] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.549306] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  386.549771] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.549857] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.550166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.550278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  386.550359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  386.550443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  386.550520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  386.550602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  386.550671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  386.550754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  386.550834] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  386.550926] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.551025] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  386.551185] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  386.551297] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  386.551376] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  386.553654] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  386.553722] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  386.563863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.572650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.581430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.590210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.598988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.607812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.616596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.625373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.634088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.642693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.651243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.659801] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.668296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.676773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.685240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.693701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.702159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.710618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.716717] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  386.777658] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  386.777680] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  386.777728] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  386.778364] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  386.779175] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  386.779896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  386.779916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  386.779933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.779952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  386.785713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  386.785730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  386.790862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  386.793347] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be37e8
>[  386.793824] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.793870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  386.793886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  386.793909] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  386.810664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  386.810691] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  386.810733] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.827451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  386.827465] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  386.844242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  386.844306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.860816] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.860863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.860945] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.878468] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  386.878519] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  386.878590] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  386.878649] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  386.878748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.878803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  386.878850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  386.878894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  386.878938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  386.878984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  386.879466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  386.879511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  386.879558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  386.879612] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  386.879661] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.879709] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  386.879755] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  386.879824] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.879884] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.879948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  386.880320] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.880365] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  386.880404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  386.880844] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.881243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  386.881271] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  386.881394] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  386.881442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.881495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  386.881551] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  386.881595] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  386.881642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.881690] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  386.881735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.881779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  386.881822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  386.881862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.881872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  386.881912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.881921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  386.881961] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  386.882531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  386.882574] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.882616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.882656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.882706] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  386.882748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.882789] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  386.882829] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  386.882867] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  386.882915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.882968] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  386.883371] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  386.883531] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.883569] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.883862] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  386.883915] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.883961] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.884309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.884363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  386.884410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  386.884453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  386.884496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  386.884538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  386.884579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  386.884620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  386.884665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  386.884714] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  386.884761] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  386.884806] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  386.884860] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  386.884905] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  386.887209] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  386.887278] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  386.897201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.906108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.915023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.923987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.932968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.941943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.950996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.959940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.968945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.978726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.987552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  386.996369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.005136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.013764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.022333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.030866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.039395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.047883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.048959] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  387.109823] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  387.109843] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  387.109897] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  387.110736] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  387.111493] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  387.114100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.114122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.114143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.114164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.119548] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.119568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  387.124704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.127190] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be6678
>[  387.127708] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  387.127767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  387.127786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  387.127811] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.144566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  387.144597] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  387.144645] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.145492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.145541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.161345] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  387.161388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.161461] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  387.178827] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  387.178869] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  387.178930] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  387.178980] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  387.179360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.179415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  387.179455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  387.179494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  387.179530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  387.179569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  387.179604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  387.179638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  387.179678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  387.179721] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  387.179763] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.179802] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  387.179840] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  387.179899] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.179950] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.180502] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  387.180546] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.180584] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  387.180617] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  387.181549] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.181747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.181769] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  387.181873] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  387.181914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.181959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  387.182257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  387.182298] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  387.182341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.182383] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  387.182423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  387.182461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  387.182498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.182533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.182542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  387.182576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.182585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  387.182620] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  387.182655] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  387.182689] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  387.182723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.182756] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.182797] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  387.182831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.182865] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  387.182899] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  387.182931] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  387.182972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.183078] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  387.183125] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  387.183319] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.183352] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.183638] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  387.183684] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.183718] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.183788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.183831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  387.183868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  387.183904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  387.183939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  387.183974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  387.184055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  387.184098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  387.184145] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  387.184198] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.184249] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  387.184298] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  387.184366] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  387.184415] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  387.186637] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  387.186691] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  387.196783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.205641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.214628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.223633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.232539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.241437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.250333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.259226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.268122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.277012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.285974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.294874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.303559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.312160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.320712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.329228] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.337718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.346195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.347252] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  387.408188] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  387.408208] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  387.408264] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  387.409094] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  387.410210] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  387.412778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.412796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.412813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.412831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.417960] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.417990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  387.423119] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.425590] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be0958
>[  387.426142] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  387.426178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  387.426194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  387.426218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.442971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  387.443017] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  387.443060] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.443870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.443913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.459712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  387.459746] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.459803] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  387.477093] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  387.477122] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  387.477164] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  387.477198] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  387.477258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.477291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  387.477318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  387.477345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  387.477370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  387.477397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  387.477420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  387.477443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  387.477470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  387.477500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  387.477528] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.477554] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  387.477580] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  387.477622] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.477658] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.477696] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  387.477724] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.477750] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  387.477771] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  387.479109] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.479250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.479265] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  387.479336] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  387.479365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.479395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  387.479428] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  387.479455] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  387.479483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.479511] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  387.479537] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  387.479563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  387.479587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.479611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.479617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  387.479640] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.479645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  387.479669] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  387.479692] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  387.479714] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  387.479737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.479758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.479786] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  387.479808] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.479831] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  387.479853] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  387.479875] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  387.479902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.479933] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  387.479960] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  387.480769] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.480792] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.481129] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  387.481178] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.481214] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.481283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.481327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  387.481360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  387.481397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  387.481427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  387.481463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  387.481493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  387.481527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  387.481559] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  387.481598] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.481638] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  387.481677] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  387.481720] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  387.481752] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  387.483923] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  387.483957] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  387.493713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.502373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.511074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.519770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.528514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.537213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.545950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.554732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.563449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.572168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.580866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.589561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.598172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.606724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.615243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.623738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.632217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.640681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.645092] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  387.705824] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  387.705844] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  387.705886] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  387.706504] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  387.707314] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  387.708040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.708058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.708079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.708099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.713865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.713882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  387.719001] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.721448] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258be4138
>[  387.721924] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  387.721959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  387.721975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  387.722034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.738775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  387.738802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  387.738844] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.739701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.739745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.755509] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  387.755541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.755588] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  387.772856] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  387.772885] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  387.772926] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  387.772959] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  387.773107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.773158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  387.773197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  387.773235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  387.773271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  387.773304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  387.773328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  387.773351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  387.773377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  387.773409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  387.773439] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.773467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  387.773497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  387.773539] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.773574] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.773611] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  387.773639] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.773663] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  387.773685] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  387.774150] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.774307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.774322] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  387.774390] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  387.774416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.774445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  387.774475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  387.774501] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  387.774527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.774553] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  387.774578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  387.774603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  387.774626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.774648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.774654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  387.774676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.774681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  387.774703] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  387.774725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  387.774746] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  387.774768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.774789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.774815] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  387.774836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.774858] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  387.774879] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  387.774900] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  387.774926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.774955] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  387.774980] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  387.775146] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.775171] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.775449] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  387.775494] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.775526] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.775595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.775630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  387.775660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  387.775689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  387.775716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  387.775743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  387.775769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  387.775795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  387.775825] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  387.775857] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  387.775888] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  387.775917] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  387.775953] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  387.775984] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  387.778184] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  387.778216] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  387.787844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.796476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.805142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.813826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.822498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.831206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.839908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.848566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.857224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.865921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.874724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.883378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.891966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.900535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.909042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.917528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.926003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.934464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.940559] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  388.001024] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  388.001043] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  388.001101] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  388.001797] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  388.002607] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  388.004436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.004456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.004473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.004492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.010374] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.010392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  388.015518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.018000] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  388.018485] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  388.018525] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  388.018542] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  388.018565] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.035321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.035348] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.035389] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.036218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.036265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.052087] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  388.052123] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.052185] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  388.069107] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  388.069139] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  388.069186] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  388.069225] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  388.069291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.069328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.069358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.069387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.069415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.069445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.069471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.069497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.069526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.069559] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.069589] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.069618] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.069647] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.069694] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.069733] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.069775] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.069806] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.069834] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  388.069859] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  388.071036] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.071262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.071287] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  388.071412] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  388.071452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.071498] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  388.071546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  388.071588] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  388.071633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.071677] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  388.071720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  388.071763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  388.071805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.071845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.071855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.071892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.071902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.071940] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  388.071981] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  388.072380] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  388.072423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.072464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.072510] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  388.072551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.072591] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  388.072631] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  388.072672] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  388.072717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.072766] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  388.072809] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  388.072937] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.072962] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.073506] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  388.073542] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.073568] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.073645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.073681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.073710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.073738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.073765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.073792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.073818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.073844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.073874] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.073905] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.073935] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.073965] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.074335] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  388.074381] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  388.076568] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  388.076606] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  388.086546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.095249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.104021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.112844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.121631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.130399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.139166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.147930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.156812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.165573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.175233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.183996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.192702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.201275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.209804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.218308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.226794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.235265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.239691] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  388.300508] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  388.300527] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  388.300575] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  388.301410] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  388.302117] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  388.304693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.304713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.304731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.304750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.310166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.310184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  388.315308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.317774] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  388.318318] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  388.318367] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  388.318383] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  388.318406] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.335183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.335212] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.335255] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.336112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.336184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.351918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  388.351950] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.352129] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  388.369154] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  388.369182] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  388.369222] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  388.369254] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  388.369312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.369343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.369368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.369392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.369416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.369441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.369463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.369485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.369510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.369538] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.369565] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.369590] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.369614] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.369654] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.369688] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.369725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.369753] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.369777] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  388.369799] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  388.370904] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.371260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.371282] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  388.371387] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  388.371427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.371468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  388.371512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  388.371550] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  388.371588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.371626] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  388.371662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  388.371698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  388.371735] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.371769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.371777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.371808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.371815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.371849] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  388.371883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  388.371917] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  388.371951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.371985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.372273] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  388.372300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.372326] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  388.372350] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  388.372374] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  388.372402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.372432] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  388.372458] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  388.373486] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.373507] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.373780] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  388.373810] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.373839] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.373913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.373948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.373978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.374061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.374107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.374149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.374190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.374231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.374275] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.374321] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.374367] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.374412] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.374461] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  388.374505] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  388.376673] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  388.376705] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  388.386409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.395079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.403778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.412472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.421135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.429789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.438485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.447140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.455791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.464484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.473138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.481788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.490375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.498917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.507425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.515910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.524384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.532846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.538940] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  388.600662] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  388.600683] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  388.600731] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  388.601568] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  388.602284] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  388.604061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.604081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.604100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.604119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.609969] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.609999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  388.615115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.617583] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  388.618091] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  388.618122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  388.618138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  388.618160] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.634943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.634973] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.635071] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.635910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.635957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.651675] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  388.651712] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.651768] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  388.668933] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  388.668966] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  388.669108] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  388.669153] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  388.669226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.669265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.669297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.669330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.669360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.669393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.669423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.669452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.669484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.669520] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.669554] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.669584] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.669615] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.669660] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.669700] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.669742] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.669774] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.669803] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  388.669828] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  388.670317] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.670888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.670905] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  388.670984] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  388.671061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.671110] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  388.671151] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  388.671182] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  388.671214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.671247] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  388.671278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  388.671307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  388.671335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.671362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.671370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.671397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.671403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.671431] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  388.671457] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  388.671484] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  388.671510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.671536] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.671567] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  388.671594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.671621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  388.671646] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  388.671671] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  388.671702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.671737] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  388.671768] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  388.671875] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.671900] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.672217] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  388.672268] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.672304] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.672378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.672420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.672456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.672491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.672525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.672559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.672606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.672646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.672689] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.672738] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.672785] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.672838] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.672894] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  388.672938] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  388.675218] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  388.675258] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  388.685012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.693838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.702610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.711382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.720225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.728991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.737810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.746572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.755336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.764101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.773507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.782243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.790854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.799406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.807923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.816419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.824904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.833372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.837783] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  388.898569] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  388.898601] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  388.898648] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  388.899485] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  388.900198] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  388.902776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.902795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.902814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.902833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.908216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.908234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  388.913356] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.915827] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  388.916359] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  388.916415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  388.916432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  388.916455] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.933211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.933238] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.933280] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.934097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.934141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.949993] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  388.950063] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.950127] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  388.967050] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  388.967078] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  388.967118] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  388.967150] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  388.967208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.967239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.967265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.967289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.967313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.967339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.967361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.967384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.967409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  388.967437] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.967463] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.967488] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.967513] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.967553] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.967586] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.967623] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.967650] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.967675] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  388.967696] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  388.969241] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.969451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.969468] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  388.969550] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  388.969582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.969617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  388.969653] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  388.969683] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  388.969714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.969745] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  388.969774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  388.969803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  388.969830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.969856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.969862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.969887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.969893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  388.969920] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  388.969945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  388.969971] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  388.970675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.970717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.970763] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  388.970805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.970846] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  388.970886] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  388.970925] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  388.970972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.971258] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  388.971289] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  388.971392] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.971418] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.971698] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  388.971733] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.971760] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.971835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.971871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  388.971899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  388.971927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  388.971953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  388.971980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  388.972472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  388.973434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  388.973467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  388.973501] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  388.973532] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  388.973563] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  388.973599] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  388.973630] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  388.975789] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  388.975821] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  388.985510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  388.994210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.003018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.011834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.020609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.029376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.038138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.046903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.055918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.066248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.075225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.084210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.093032] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.101779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.110399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.118979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.127575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.136121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.138944] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  389.199085] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  389.199104] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  389.199142] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  389.199963] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  389.200704] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  389.202517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.202535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.202551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.202568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.208430] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.208445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  389.213561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.216030] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  389.216477] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  389.216516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  389.216531] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  389.216552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.233309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  389.233331] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.233367] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.234201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.234238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.250082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  389.250109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.250156] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  389.266986] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  389.267029] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  389.267059] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  389.267082] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  389.267125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.267147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  389.267165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  389.267182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  389.267198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  389.267216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  389.267231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  389.267247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  389.267264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  389.267284] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  389.267302] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.267320] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  389.267337] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  389.267367] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.267391] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.267417] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.267436] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.267453] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  389.267468] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  389.267883] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.268236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.268248] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  389.268302] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  389.268323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.268346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  389.268370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  389.268390] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  389.268411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.268431] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  389.268451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  389.268470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  389.268489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.268506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.268511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  389.268528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.268532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  389.268550] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  389.268567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  389.268584] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  389.268600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.268617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.268638] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  389.268655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.268672] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  389.268688] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  389.268704] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  389.268725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.268748] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  389.268768] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  389.268838] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.268855] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.269339] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  389.269631] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.269648] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.269700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.269741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  389.269760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  389.269778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  389.269796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  389.269813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  389.269830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  389.269847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  389.269866] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  389.269886] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.269906] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  389.269925] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  389.269948] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  389.269968] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  389.272243] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  389.272264] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  389.281781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.290301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.298828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.307354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.315877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.324405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.332929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.341453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.349976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.358522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.367050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.375572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.384076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.392558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.401026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.409485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.417942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.426401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.434181] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  389.494407] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  389.494510] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  389.494699] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  389.496217] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  389.497720] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  389.500192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.500298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.500395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.500496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.506791] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.506887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  389.512636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.515420] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  389.517643] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  389.517819] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  389.517905] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  389.518019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.534848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  389.534982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.535746] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.537463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.537671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.551487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  389.551614] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.551839] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  389.569660] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  389.569765] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  389.569921] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  389.570051] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  389.570877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.571006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  389.571390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  389.571476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  389.571559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  389.571648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  389.571725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  389.571801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  389.571887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  389.571980] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  389.572780] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.572921] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  389.573061] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  389.573368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.573528] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.573702] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.573835] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.573958] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  389.574155] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  389.574677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.575695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.575746] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  389.575975] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  389.576248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.576397] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  389.576550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  389.576681] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  389.576819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.576958] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  389.577159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  389.577292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  389.577399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.577521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.577556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  389.577671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.577700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  389.577822] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  389.577943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  389.578060] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  389.578272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.578372] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.578513] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  389.578612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.578734] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  389.578850] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  389.578969] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  389.579189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.579337] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  389.579469] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  389.579899] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.580013] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.580484] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  389.581026] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.581255] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.581592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.581744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  389.581877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  389.582004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  389.582220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  389.582345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  389.582470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  389.582588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  389.582719] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  389.582859] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.582995] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  389.583217] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  389.583369] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  389.583501] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  389.585764] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  389.585844] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  389.596172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.605122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.614042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.623058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.632134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.641170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.650156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.659144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.668126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.677107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.685823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.694431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.702982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.711522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.720020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.728499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.736966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.745457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.748183] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  389.809255] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  389.809274] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  389.809336] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  389.810166] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  389.810852] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  389.812616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.812636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.812654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.812673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.818546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.818563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  389.823686] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.826174] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  389.826645] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  389.826694] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  389.826711] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  389.826733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.843486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  389.843513] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.843555] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.844411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.844454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.860213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  389.860241] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.860292] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  389.877589] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  389.877617] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  389.877657] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  389.877689] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  389.877747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.877777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  389.877803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  389.877827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  389.877851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  389.877876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  389.877898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  389.877920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  389.877945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  389.877973] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  389.878207] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.878246] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  389.878282] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  389.878339] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.878385] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.878434] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.878473] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.878509] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  389.878536] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  389.878965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.879606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.879627] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  389.879715] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  389.879743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.879773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  389.879804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  389.879829] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  389.879856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.879883] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  389.879908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  389.879933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  389.879957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.879980] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.880127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  389.880157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.880166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  389.880198] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  389.880226] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  389.880258] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  389.880286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.880317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.880350] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  389.880381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.880408] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  389.880439] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  389.880466] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  389.880501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.880540] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  389.880571] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  389.880703] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.880730] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.881144] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  389.881525] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.881559] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.881657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.881696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  389.881726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  389.881761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  389.881789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  389.881820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  389.881848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  389.881878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  389.881908] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  389.881944] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  389.881983] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  389.882130] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  389.882171] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  389.882202] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  389.884367] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  389.884394] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  389.894027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.902614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.911255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.919909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.928563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.937216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.945912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.954563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.963213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.971898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.980546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.989195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.997802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.006359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.014875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.023372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.031850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.040315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.046411] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  390.107210] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  390.107229] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  390.107268] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  390.108097] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  390.108792] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  390.111388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.111408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.111426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.111445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.116833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.116851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  390.121982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.124473] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  390.124948] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  390.125066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  390.125091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  390.125126] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.141795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  390.141821] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  390.141863] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.142678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.142721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.158520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  390.158552] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.158608] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  390.175937] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  390.175965] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  390.176160] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  390.176212] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  390.176302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.176346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  390.176378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  390.176413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  390.176443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  390.176479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  390.176507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  390.176538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  390.176569] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  390.176608] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  390.176645] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.176682] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  390.176718] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  390.176769] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.176816] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.176862] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  390.176901] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.176937] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  390.176971] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  390.177563] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.177754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.177775] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  390.177876] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  390.177909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.177947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  390.177992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  390.178121] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  390.178162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.178201] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  390.178238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  390.178277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  390.178313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.178348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.178356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  390.178384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.178391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  390.178422] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  390.178449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  390.178480] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.178507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.178537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.178568] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  390.178599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.178626] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  390.178657] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  390.178684] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  390.178719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.178758] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  390.178789] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  390.178916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.178947] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.179261] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  390.179306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.179341] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.179408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.179449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  390.179481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  390.179515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  390.179545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  390.179579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  390.179607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  390.179639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  390.179670] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  390.179708] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.179748] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  390.179786] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  390.179832] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  390.179870] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  390.182087] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  390.182120] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  390.191762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.200366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.209060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.217720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.226417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.235077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.243777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.252474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.261133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.269796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.278498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.287196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.295799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.304354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.312873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.321370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.329850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.338316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.342728] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  390.403771] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  390.403802] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  390.403871] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  390.404561] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  390.405373] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  390.406095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.406115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.406133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.406151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.411900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.411917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  390.417042] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.419486] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  390.420014] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  390.420054] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  390.420071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  390.420094] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.436847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  390.436875] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  390.436917] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.437778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.437822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.453619] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  390.453651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.453707] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  390.470952] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  390.470981] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  390.471090] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  390.471143] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  390.471378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.471413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  390.471440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  390.471465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  390.471489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  390.471515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  390.471537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  390.471560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  390.471585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  390.471612] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  390.471638] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.471663] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  390.471687] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  390.471726] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.471760] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.471795] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  390.471821] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.471845] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  390.471867] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  390.472333] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.472763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.472785] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  390.472887] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  390.472919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.472957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  390.473029] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  390.473068] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  390.473101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.473139] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  390.473171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  390.473207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  390.473237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.473480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.473486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  390.473510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.473515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  390.473538] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  390.473561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  390.473584] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.473606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.473628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.473655] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  390.473677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.473700] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  390.473721] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  390.473743] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  390.473769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.473798] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  390.473824] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  390.473912] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.473934] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.474245] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  390.474291] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.474327] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.474389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.474429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  390.474459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  390.474493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  390.474521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  390.474554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  390.474582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  390.474615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  390.474646] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  390.474685] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.474722] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  390.475091] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  390.475133] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  390.475164] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  390.477334] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  390.477361] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  390.486927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.495519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.504185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.512838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.521498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.530183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.538833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.547485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.556138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.564787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.573481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.582171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.590788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.599349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.607868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.616376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.624858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.633324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.637535] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  390.698271] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  390.698292] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  390.698334] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  390.699170] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  390.699868] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  390.701630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.701650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.701668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.701687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.707585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.707603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  390.712755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.715222] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  390.715700] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  390.715763] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  390.715779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  390.715801] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.732595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  390.732625] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  390.732671] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.733535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.733582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.749328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  390.749364] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.749420] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  390.766719] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  390.766747] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  390.766788] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  390.766821] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  390.766878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.766908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  390.766934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  390.766958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  390.766982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  390.767081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  390.767114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  390.767149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  390.767189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  390.767232] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  390.767286] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.767334] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  390.767722] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  390.767767] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.767806] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.767851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  390.767882] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.767910] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  390.767935] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  390.768407] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.768730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.768747] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  390.768828] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  390.768861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.768895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  390.768931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  390.768961] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  390.769036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.769083] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  390.769121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  390.769163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  390.769197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.769237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.769247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  390.769286] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.769297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  390.769336] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  390.769641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  390.769676] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.769714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.769747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.769791] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  390.769824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.769862] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  390.769894] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  390.769931] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  390.769968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.770051] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  390.770091] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  390.770475] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.770500] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.770778] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  390.770813] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.770838] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.770914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.770949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  390.770979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  390.771050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  390.771094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  390.771129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  390.771169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  390.771203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  390.771245] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  390.771291] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  390.771335] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  390.771654] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  390.771703] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  390.771739] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  390.773476] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  390.773508] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  390.783200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.791842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.800575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.809349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.818113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.826879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.835641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.844400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.853158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.861914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.870833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.879596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.888285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.896876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.905422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.913936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.922430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.930908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.935335] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  390.995500] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  390.995518] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  390.995556] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  390.996384] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  390.997069] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  390.998820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.998838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.998855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.998872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.004723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.004739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  391.009847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.012339] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  391.012788] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  391.012852] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  391.012867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  391.012888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.029696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.029722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.029775] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.030651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.030698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.046396] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  391.046425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.046471] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  391.063738] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  391.063763] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  391.063798] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  391.063826] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  391.063877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.063904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.063927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.063948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.063969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.064065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.064097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.064127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.064160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.064195] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.064223] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.064247] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.064272] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.064311] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  391.064347] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  391.064383] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.064409] [drm:intel_power_well_disable [i915]] disabling DC off
>[  391.064430] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  391.064449] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  391.064870] [drm:intel_power_well_disable [i915]] disabling always-on
>[  391.065038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.065057] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  391.065139] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  391.065163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.065188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  391.065216] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  391.065239] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  391.065263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.065285] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  391.065308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  391.065329] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  391.065350] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.065370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.065376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.065395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.065400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.065420] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  391.065440] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  391.065459] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  391.065478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.065496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  391.065520] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  391.065539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.065558] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  391.065576] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  391.065595] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  391.065618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.065645] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  391.065667] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  391.065747] [drm:intel_power_well_enable [i915]] enabling always-on
>[  391.065766] [drm:intel_power_well_enable [i915]] enabling DC off
>[  391.066074] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  391.066112] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  391.066139] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  391.066193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.066224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.066250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.066275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.066299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.066336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.066363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.066390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.066420] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.066454] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.066486] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.066524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.066568] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  391.066599] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  391.068792] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  391.068820] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  391.078484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.087073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.095704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.104364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.113062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.121719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.130378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.139039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.147693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.156347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.164998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.173691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.182349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.190938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.199634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.208155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.216644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.225120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.231219] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  391.291893] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  391.291911] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  391.291945] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  391.292771] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  391.293476] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  391.295234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.295253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.295271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.295290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.301214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.301232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  391.306357] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.308842] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  391.309351] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  391.309417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  391.309433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  391.309456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.326207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.326233] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.326274] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.327107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.327151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.342968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  391.343036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.343089] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  391.360406] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  391.360439] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  391.360486] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  391.360524] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  391.360590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.360627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.360658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.360687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.360715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.360745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.360771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.360798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.360827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.360861] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.360892] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.360921] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.360951] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.361073] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  391.361133] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  391.361401] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.361434] [drm:intel_power_well_disable [i915]] disabling DC off
>[  391.361463] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  391.361489] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  391.361916] [drm:intel_power_well_disable [i915]] disabling always-on
>[  391.362129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.362146] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  391.362227] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  391.362258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.362292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  391.362328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  391.362357] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  391.362388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.362419] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  391.362448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  391.362476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  391.362503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.362529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.362535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.362561] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.362567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.362593] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  391.362619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  391.362645] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  391.362670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.362694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  391.362725] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  391.362750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.362775] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  391.362800] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  391.362825] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  391.362854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.362889] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  391.362918] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  391.363083] [drm:intel_power_well_enable [i915]] enabling always-on
>[  391.363116] [drm:intel_power_well_enable [i915]] enabling DC off
>[  391.363407] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  391.363464] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  391.363498] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  391.363567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.363602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.363630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.363659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.363686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.363714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.363740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.363766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.363795] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.363827] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.363857] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.363887] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.363922] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  391.363953] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  391.366143] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  391.366175] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  391.375786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.384431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.393165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.401927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.410818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.419581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.428560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.437325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.446086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.454841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.463608] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.472369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.481055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.489643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.498188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.506698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.515188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.523661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.526202] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  391.587017] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  391.587133] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  391.587454] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  391.588874] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  391.590251] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  391.591296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.591432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.591564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.591688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.598149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.598242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  391.603770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.606483] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  391.608686] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  391.608851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  391.608937] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  391.609205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.625824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.625950] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.626687] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.628300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.628505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.642566] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  391.642693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.642883] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  391.660953] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  391.661184] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  391.661341] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  391.661470] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  391.661679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.661799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.661901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.661997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.662253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.662425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.662544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.662681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.662810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.662971] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.663191] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.663341] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.663488] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.663689] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  391.663869] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  391.664070] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.664338] [drm:intel_power_well_disable [i915]] disabling DC off
>[  391.664486] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  391.664619] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  391.665637] [drm:intel_power_well_disable [i915]] disabling always-on
>[  391.666662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.666734] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  391.667050] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  391.667269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.667419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  391.667706] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  391.667824] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  391.667932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.668066] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  391.668255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  391.668379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  391.668482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.668596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.668627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.668735] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.668760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.668870] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  391.668964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  391.669157] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  391.669255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.669364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  391.669474] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  391.669584] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.669678] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  391.669784] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  391.669874] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  391.669994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.670204] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  391.670313] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  391.670754] [drm:intel_power_well_enable [i915]] enabling always-on
>[  391.670844] [drm:intel_power_well_enable [i915]] enabling DC off
>[  391.671297] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  391.671733] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  391.671850] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  391.672050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.672291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.672402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.672523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.672624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.672739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.672834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.672945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.673131] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.673260] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.673385] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.673506] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.673645] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  391.673750] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  391.676178] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  391.676267] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  391.686392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.695381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.704370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.713279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.722370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.731370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.740277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.749179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.758117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.766932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.775764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.784355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.792895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.801407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.809897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.818371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.826836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.835294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.838019] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  391.898786] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  391.898804] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  391.898847] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  391.899671] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  391.900391] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  391.902973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.903007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.903025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.903044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.908410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.908428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  391.913551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.916033] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  391.916507] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  391.916559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  391.916576] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  391.916598] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.933353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.933379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.933421] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.934233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.934275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.950114] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  391.950146] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.950195] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  391.967490] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  391.967518] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  391.967558] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  391.967591] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  391.967648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.967680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.967705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.967730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.967753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.967779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.967802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.967824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.967849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  391.967877] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.967904] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.967929] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.967953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.968208] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  391.968257] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  391.968309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  391.968350] [drm:intel_power_well_disable [i915]] disabling DC off
>[  391.968387] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  391.968420] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  391.968855] [drm:intel_power_well_disable [i915]] disabling always-on
>[  391.969135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.969157] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  391.969262] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  391.969300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.969340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  391.969382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  391.969417] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  391.969454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.969493] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  391.969530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  391.969568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  391.969603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.969637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.969645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.969677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.969685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  391.969720] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  391.969752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  391.969785] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  391.969819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.969853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  391.969891] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  391.969925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.969958] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  391.970135] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  391.970212] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  391.970252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.970293] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  391.970330] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  391.970462] [drm:intel_power_well_enable [i915]] enabling always-on
>[  391.970495] [drm:intel_power_well_enable [i915]] enabling DC off
>[  391.970782] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  391.970826] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  391.970861] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  391.970962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.971097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  391.971124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  391.971148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  391.971172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  391.971196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  391.971218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  391.971241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  391.971266] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  391.971293] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  391.971319] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  391.971344] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  391.971374] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  391.971400] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  391.973454] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  391.973480] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  391.983133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.991725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.000362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.009059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.017712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.026370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.035065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.043723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.052377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.061064] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.069718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.078368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.086984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.095567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.104085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.112578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.121057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.129523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.135617] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  392.196305] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  392.196325] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  392.196364] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  392.197195] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  392.197892] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  392.199654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.199674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.199692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.199712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.205584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.205601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  392.210757] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.213241] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  392.213718] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.213764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  392.213781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.213803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.230625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  392.230657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.230705] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.231604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.231660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.247333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.247368] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.247433] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.264769] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  392.264801] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  392.264849] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  392.264887] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  392.264954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.265072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  392.265116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  392.265156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  392.265201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  392.265252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  392.265291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  392.265332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  392.265372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  392.265420] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  392.265464] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.265507] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  392.265552] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  392.265615] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  392.265669] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  392.265723] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.265768] [drm:intel_power_well_disable [i915]] disabling DC off
>[  392.265810] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  392.265843] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  392.266317] [drm:intel_power_well_disable [i915]] disabling always-on
>[  392.266546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.266572] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  392.266687] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  392.266724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.266769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  392.266818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  392.266854] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  392.266897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.266934] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.266974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.267050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  392.267093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.267127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.267139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  392.267174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.267184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  392.267224] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  392.267258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  392.267299] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  392.267332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.267370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.267408] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  392.267445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.267485] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  392.267519] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  392.267555] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  392.267592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.267637] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  392.267673] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  392.267828] [drm:intel_power_well_enable [i915]] enabling always-on
>[  392.267859] [drm:intel_power_well_enable [i915]] enabling DC off
>[  392.268179] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  392.268230] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  392.268272] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  392.268347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.268393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  392.268427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  392.268465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  392.268498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  392.268535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  392.268567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  392.268603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  392.268639] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  392.268681] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.268724] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  392.268766] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  392.268814] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  392.268850] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  392.271047] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  392.271081] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  392.280795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.289497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.298254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.307019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.315845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.324617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.333383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.342145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.350903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.359999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.368814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.377583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.386273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.394865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.403407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.411917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.420407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.428883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.431623] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  392.492437] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  392.492456] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  392.492494] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  392.493324] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  392.494022] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  392.495782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.495801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.495819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.495838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.501720] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.501740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  392.506874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.509345] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  392.509854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.509885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  392.509902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.509926] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.526679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  392.526708] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.526754] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.527603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.527652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.543422] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.543457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.543510] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.560834] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  392.560867] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  392.560914] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  392.560953] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  392.561129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.561188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  392.561235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  392.561280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  392.561324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  392.561371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  392.561413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  392.561456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  392.561500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  392.561547] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  392.561593] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.561638] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  392.561681] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  392.561741] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  392.561798] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  392.561855] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.561902] [drm:intel_power_well_disable [i915]] disabling DC off
>[  392.561945] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  392.561985] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  392.562464] [drm:intel_power_well_disable [i915]] disabling always-on
>[  392.562656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.562673] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  392.562752] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  392.562784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.562818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  392.562855] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  392.562885] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  392.562916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.562947] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.562976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.563064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  392.563109] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.563152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.563164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  392.563202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.563212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  392.563253] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  392.563295] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  392.563337] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  392.563377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.563417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.563463] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  392.563505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.563545] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  392.563586] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  392.563626] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  392.563671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.563720] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  392.563765] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  392.563924] [drm:intel_power_well_enable [i915]] enabling always-on
>[  392.563957] [drm:intel_power_well_enable [i915]] enabling DC off
>[  392.564289] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  392.564341] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  392.564382] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  392.564454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.564503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  392.564546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  392.564589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  392.564630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  392.564671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  392.564712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  392.564752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  392.564795] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  392.564840] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.564884] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  392.564927] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  392.564981] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  392.565055] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  392.567225] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  392.567256] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  392.576888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.585543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.594278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.603104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.611872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.620643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.629422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.638195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.647009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.655837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.664600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.673364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.682059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.690654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.699199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.707712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.716202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.724677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.729124] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  392.789318] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  392.789339] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  392.789378] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  392.790692] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  392.793248] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  392.794584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.794602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.794619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.794635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.799754] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.799771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  392.804888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.807377] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  392.807854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.807896] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  392.807912] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.807934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.824727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  392.824754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.824795] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.825601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.825643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.841470] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.841506] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.841708] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.860184] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  392.860216] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  392.860263] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  392.860302] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  392.860369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.860405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  392.860434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  392.860462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  392.860489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  392.860518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  392.860545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  392.860571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  392.860601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  392.860634] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  392.860665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.860695] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  392.860724] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  392.860771] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  392.860809] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  392.860851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.860882] [drm:intel_power_well_disable [i915]] disabling DC off
>[  392.860911] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  392.860936] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  392.861874] [drm:intel_power_well_disable [i915]] disabling always-on
>[  392.862078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.862095] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  392.862176] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  392.862208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.862244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  392.862281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  392.862311] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  392.862343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.862375] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.862405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.862435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  392.862463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.862490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.862497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  392.862525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.862531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  392.862557] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  392.862583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  392.862609] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  392.862634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.862660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.862691] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  392.862718] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.862743] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  392.862769] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  392.862794] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  392.862825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.862860] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  392.862890] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  392.863026] [drm:intel_power_well_enable [i915]] enabling always-on
>[  392.863058] [drm:intel_power_well_enable [i915]] enabling DC off
>[  392.863350] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  392.863400] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  392.863437] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  392.863515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.863559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  392.863595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  392.863636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  392.863666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  392.863693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  392.863719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  392.863744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  392.863773] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  392.863805] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  392.863835] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  392.863864] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  392.863899] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  392.863929] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  392.866114] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  392.866147] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  392.875787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.884478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.893261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.902024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.910839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.919589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.928352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.937110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.945861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.954613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.963363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.972130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.980809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.989420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  392.997960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.006494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.015001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.023474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.027702] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  393.088426] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  393.088446] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  393.088483] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  393.089313] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  393.090099] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  393.092679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.092699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.092717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.092736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.098197] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.098215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  393.103339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.105803] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  393.106351] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  393.106397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  393.106414] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  393.106436] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.123193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  393.123220] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  393.123262] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.124139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.124190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.139953] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  393.140060] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.140147] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  393.157467] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  393.157499] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  393.157546] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  393.157584] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  393.157651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.157687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  393.157717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  393.157747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  393.157775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  393.157806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  393.157833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  393.157859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  393.157888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  393.157921] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  393.157953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.157983] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  393.158105] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  393.158170] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  393.158228] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  393.158286] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  393.158332] [drm:intel_power_well_disable [i915]] disabling DC off
>[  393.158376] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  393.158416] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  393.158854] [drm:intel_power_well_disable [i915]] disabling always-on
>[  393.159112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.159137] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  393.159256] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  393.159300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.159348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  393.159397] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  393.159439] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  393.159483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.159527] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  393.159569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  393.159611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  393.159650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.159688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.159698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  393.159735] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.159744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  393.159782] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  393.159822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  393.159863] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  393.159902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.159940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.159986] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  393.160063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.160108] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  393.160150] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  393.160189] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  393.160237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.160285] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  393.160331] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  393.160491] [drm:intel_power_well_enable [i915]] enabling always-on
>[  393.160530] [drm:intel_power_well_enable [i915]] enabling DC off
>[  393.160823] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  393.160875] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  393.160916] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  393.160988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.161071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  393.161116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  393.161158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  393.161199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  393.161241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  393.161280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  393.161321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  393.161363] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  393.161409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.161453] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  393.161495] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  393.161545] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  393.161588] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  393.163778] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  393.163817] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  393.173559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.182267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.191112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.199886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.208664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.217439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.226207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.234987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.243821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.252593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.261365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.270136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.278792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.287372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.295912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.304420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.312906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.321378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.323917] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  393.384829] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  393.384854] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  393.384908] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  393.386385] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  393.388943] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  393.390281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.390299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.390315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.390332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.395446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.395463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  393.400580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.403064] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  393.403538] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  393.403589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  393.403605] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  393.403627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.420384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  393.420411] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  393.420453] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.420587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.420629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.437115] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  393.437147] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.437193] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  393.454056] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  393.454084] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  393.454124] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  393.454157] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  393.454214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.454245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  393.454270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  393.454295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  393.454318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  393.454343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  393.454366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  393.454388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  393.454413] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  393.454441] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  393.454467] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.454492] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  393.454516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  393.454567] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  393.463216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.471758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.480357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.489113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.497821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.506532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.515238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.523941] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.532805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.541517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.550230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.558937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.567810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.576877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.585422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.593917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.602383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.610828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.616632] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  393.616657] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  393.616673] [drm:intel_power_well_disable [i915]] disabling DC off
>[  393.616691] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  393.616706] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  393.617154] [drm:intel_power_well_disable [i915]] disabling always-on
>[  393.617185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.617200] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  393.617263] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  393.617283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.617307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  393.617332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  393.617351] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  393.617373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.617393] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  393.617415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  393.617434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  393.617455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.617472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.617477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  393.617496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.617500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  393.617522] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  393.617539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  393.617559] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  393.617576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.617595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.617615] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  393.617634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.617651] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  393.617671] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  393.617687] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  393.617710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.617735] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  393.617754] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  393.617824] [drm:intel_power_well_enable [i915]] enabling always-on
>[  393.617841] [drm:intel_power_well_enable [i915]] enabling DC off
>[  393.618133] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  393.618160] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  393.618184] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  393.618228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.618253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  393.618275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  393.618293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  393.618313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  393.618331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  393.618350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  393.618367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  393.618389] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  393.618413] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.618435] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  393.618458] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  393.618483] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  393.618503] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  393.620675] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  393.620693] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  393.621780] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  393.677015] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  393.677034] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  393.677104] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  393.677923] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  393.678625] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  393.681267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.681287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.681305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.681324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.687049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.687067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  393.692190] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.694663] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  393.695199] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  393.695249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  393.695265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  393.695288] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.712044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  393.712071] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  393.712113] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.712919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.712962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.728791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  393.728828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.729197] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  393.746003] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  393.746080] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  393.746128] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  393.746167] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  393.746233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.746270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  393.746299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  393.746327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  393.746354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  393.746385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  393.746411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  393.746438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  393.746467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  393.746500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  393.746531] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.746561] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  393.746590] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  393.746636] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  393.746675] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  393.746717] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  393.746748] [drm:intel_power_well_disable [i915]] disabling DC off
>[  393.746776] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  393.746802] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  393.748095] [drm:intel_power_well_disable [i915]] disabling always-on
>[  393.748391] [drm:drm_mode_addfb2] [FB:61]
>[  393.748431] [drm:drm_mode_addfb2] [FB:65]
>[  393.800038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  393.800505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.801233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  393.801664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  393.801688] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  393.801816] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  393.801869] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.801923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  393.801980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  393.802372] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  393.802425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.802474] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  393.802521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  393.802567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  393.802611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.802653] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.802664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  393.802703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.802712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  393.802753] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  393.802793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  393.802833] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  393.802873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.802911] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.802959] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  393.803639] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.803684] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  393.803726] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  393.803765] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  393.803814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.803868] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  393.803915] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  393.804946] [drm:intel_power_well_enable [i915]] enabling always-on
>[  393.804985] [drm:intel_power_well_enable [i915]] enabling DC off
>[  393.805455] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  393.805510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  393.805562] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  393.805671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.805726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  393.805773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  393.805817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  393.805859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  393.805900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  393.805940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  393.805979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  393.806491] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  393.806543] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  393.806591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  393.806636] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  393.806692] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  393.806739] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  393.808948] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  393.808996] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  393.818907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.827572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.836237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.844892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.853545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.862198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.870783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.879321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.887832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.896323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.904796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.913259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.921715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.930174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.938632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.947090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.955547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.964004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  393.971781] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  394.032320] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  394.032340] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  394.032387] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  394.033220] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  394.033912] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  394.035677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.035697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.035715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.035734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.041592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.041610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  394.046824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.049304] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  394.049786] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  394.049832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  394.049849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  394.049871] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.066637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.066662] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.066702] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.083391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.083407] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  394.100243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.100317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.116759] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  394.116807] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  394.116880] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  394.134780] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  394.134829] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  394.134900] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  394.134959] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  394.135218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.135308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  394.135382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  394.135449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  394.135513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  394.135583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  394.135646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  394.135708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  394.135775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.135849] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  394.135920] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.135990] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  394.136122] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  394.136217] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  394.136306] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  394.136392] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.136462] [drm:intel_power_well_disable [i915]] disabling DC off
>[  394.136528] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  394.136590] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  394.137123] [drm:intel_power_well_disable [i915]] disabling always-on
>[  394.137747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.137773] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  394.137895] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  394.137943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  394.137996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  394.138138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  394.138210] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  394.138287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  394.138360] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  394.138432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  394.138500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  394.138566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  394.138627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.138644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  394.138702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.138716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  394.138776] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  394.138840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  394.138903] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  394.138965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.139076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  394.139140] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  394.139203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.139270] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  394.139335] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  394.139400] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  394.139473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.139548] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  394.139615] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  394.139860] [drm:intel_power_well_enable [i915]] enabling always-on
>[  394.139919] [drm:intel_power_well_enable [i915]] enabling DC off
>[  394.140287] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  394.140745] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  394.140809] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  394.140996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.141131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  394.141200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  394.141266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  394.141329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  394.141392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  394.141454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  394.141515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  394.141581] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  394.141653] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.141721] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  394.141788] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  394.141865] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  394.141931] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  394.144248] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  394.144316] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  394.154224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.163141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.172125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.181034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.190018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.198968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.207944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.217006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.226248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.235159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.244138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.253105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.261927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.270656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.279232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.287762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.296270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.304763] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.307516] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  394.366453] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  394.366476] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  394.366517] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  394.367352] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  394.369158] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  394.371042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.371063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.371082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.371101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.377067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.377091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  394.382227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.384714] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258825d28
>[  394.385304] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  394.385340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  394.385359] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  394.385386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.402164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.402197] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.402246] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.403131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.403183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.418892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  394.418932] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  394.419063] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  394.436312] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  394.436358] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  394.436424] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  394.436478] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  394.436570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.436620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  394.436662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  394.436703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  394.436743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  394.436785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  394.436823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  394.436860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  394.436901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.436947] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  394.436991] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.437154] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  394.437223] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  394.437311] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  394.437388] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  394.437469] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.437532] [drm:intel_power_well_disable [i915]] disabling DC off
>[  394.437592] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  394.437638] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  394.438135] [drm:intel_power_well_disable [i915]] disabling always-on
>[  394.438824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.438859] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  394.439072] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  394.439139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  394.439197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  394.439265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  394.439315] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  394.439375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  394.439427] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  394.439485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  394.439535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  394.439589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  394.439635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.439649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  394.439698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.439710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  394.439763] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  394.439809] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  394.439865] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  394.439910] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.439964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  394.440066] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  394.440125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.440182] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  394.440230] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  394.440285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  394.440348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.440418] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  394.440470] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  394.440692] [drm:intel_power_well_enable [i915]] enabling always-on
>[  394.440736] [drm:intel_power_well_enable [i915]] enabling DC off
>[  394.441093] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  394.441552] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  394.441610] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  394.441707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.441771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  394.441820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  394.441875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  394.441922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  394.441976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  394.442076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  394.442136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  394.442188] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  394.442253] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.442316] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  394.442379] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  394.442447] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  394.442498] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  394.444743] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  394.444790] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  394.454903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.464008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.472968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.481944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.490966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.499935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.508958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.517933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.526967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.535942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.544976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.553879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.562534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.571599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.580243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.588776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.597270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.605746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.606810] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  394.667039] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  394.667060] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  394.667110] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  394.667945] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  394.668639] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  394.670435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.670455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.670474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.670493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.676378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.676396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  394.681523] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.684006] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  394.684496] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  394.684532] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  394.684549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  394.684572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.701319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.701348] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.701392] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.702218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.702263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.718043] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  394.718072] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  394.718212] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  394.735018] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  394.735048] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  394.735090] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  394.735125] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  394.735185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.735218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  394.735244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  394.735270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  394.735295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  394.735322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  394.735345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  394.735368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  394.735394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.735424] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  394.735451] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.735477] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  394.735503] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  394.735546] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  394.735581] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  394.735619] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.735646] [drm:intel_power_well_disable [i915]] disabling DC off
>[  394.735671] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  394.735693] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  394.737059] [drm:intel_power_well_disable [i915]] disabling always-on
>[  394.737205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.737220] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  394.737296] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  394.737327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  394.737360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  394.737395] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  394.737424] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  394.737455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  394.737484] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  394.737513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  394.737541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  394.737567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  394.737592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.737598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  394.737622] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.737628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  394.737652] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  394.737677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  394.737701] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  394.737725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.737748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  394.737778] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  394.737802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.737827] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  394.737851] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  394.737875] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  394.737903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.737936] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  394.737964] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  394.738121] [drm:intel_power_well_enable [i915]] enabling always-on
>[  394.738155] [drm:intel_power_well_enable [i915]] enabling DC off
>[  394.738446] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  394.738480] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  394.738505] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  394.738572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.738606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  394.738634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  394.738660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  394.738684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  394.738710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  394.738733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  394.738758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  394.738784] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  394.738813] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.738841] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  394.738867] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  394.738900] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  394.738926] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  394.741087] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  394.741116] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  394.750675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.759288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.767948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.776934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.785841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.794525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.803208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.811940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.820784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.829520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.838203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.846932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.855694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.864258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.872781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.881281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.889761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.898228] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  394.902441] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  394.963235] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  394.963253] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  394.963286] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  394.964110] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  394.964808] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  394.967390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.967410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.967427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.967446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.973438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.973456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  394.978582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.981069] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  394.981552] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  394.981589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  394.981606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  394.981628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.998383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  394.998410] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.998451] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  394.999266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.999309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.015161] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  395.015196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.015391] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  395.033936] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  395.033968] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  395.034239] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  395.034281] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  395.034349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.034386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.034417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.034446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.034475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.034506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.034533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.034559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.034589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.034622] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.034653] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.034684] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.034713] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.034757] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  395.034796] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  395.034837] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.034867] [drm:intel_power_well_disable [i915]] disabling DC off
>[  395.034895] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  395.034920] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  395.036216] [drm:intel_power_well_disable [i915]] disabling always-on
>[  395.036375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.036392] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  395.036471] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  395.036502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.036536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  395.036573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  395.036602] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  395.036633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.036664] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  395.036693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  395.036721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  395.036748] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.036774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.036781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.036806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.036812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.036839] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  395.036865] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  395.036891] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  395.036916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.036941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.036972] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  395.037691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.037727] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  395.037758] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  395.037788] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  395.037821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.037858] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  395.037889] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  395.037982] [drm:intel_power_well_enable [i915]] enabling always-on
>[  395.038054] [drm:intel_power_well_enable [i915]] enabling DC off
>[  395.038352] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  395.038405] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  395.038446] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  395.038536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.038583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.038618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.038657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.038690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.038728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.038760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.038797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.038832] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.038876] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.038921] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.038964] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.039056] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  395.039104] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  395.041255] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  395.041285] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  395.050933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.059785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.068546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.077318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.086085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.094845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.103610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.112372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.121134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.129894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.138667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.147433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.156110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.164693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.173450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.181968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.190478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.198951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.203473] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  395.264201] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  395.264218] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  395.264261] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  395.265101] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  395.265769] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  395.267524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.267544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.267562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.267580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.273465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.273483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  395.278608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.281090] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  395.281573] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  395.281615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  395.281631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  395.281653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.298406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.298433] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.298473] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.299286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.299329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.315129] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  395.315156] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.315208] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  395.332414] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  395.332442] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  395.332483] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  395.332516] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  395.332573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.332604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.332629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.332654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.332677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.332702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.332725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.332747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.332772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.332799] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.332826] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.332851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.332876] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.332917] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  395.332951] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  395.333047] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.333084] [drm:intel_power_well_disable [i915]] disabling DC off
>[  395.333118] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  395.333146] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  395.333580] [drm:intel_power_well_disable [i915]] disabling always-on
>[  395.333770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.333792] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  395.333891] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  395.333918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.333947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  395.333978] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  395.334043] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  395.334077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.334110] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  395.334141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  395.334178] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  395.334213] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.334249] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.334258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.334291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.334299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.334328] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  395.334351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  395.334374] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  395.334395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.334417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.334444] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  395.334467] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.334490] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  395.334512] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  395.334533] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  395.334561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.334591] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  395.334617] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  395.334708] [drm:intel_power_well_enable [i915]] enabling always-on
>[  395.334729] [drm:intel_power_well_enable [i915]] enabling DC off
>[  395.335040] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  395.335085] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  395.335115] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  395.335183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.335226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.335264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.335300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.335335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.335370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.335404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.335435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.335461] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.335490] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.335516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.335542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.335573] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  395.335599] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  395.337791] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  395.337819] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  395.347490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.356082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.364726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.373405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.382073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.390773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.399435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.408094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.416751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.425411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.434073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.442773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.451399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.459961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.468512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.477012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.485492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.493963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.500077] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  395.560843] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  395.560866] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  395.560911] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  395.561563] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  395.562372] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  395.563094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.563113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.563131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.563150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.568899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.568917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  395.574049] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.576435] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  395.576918] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  395.576955] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  395.576971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  395.577029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.593745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.593771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.593812] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.594649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.594698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.610471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  395.610502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.610561] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  395.627824] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  395.627857] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  395.627904] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  395.627942] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  395.628093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.628150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.628190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.628234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.628272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.628321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.628359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.628399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.628437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.628484] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.628529] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.628574] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.628612] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.628679] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  395.628733] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  395.628789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.628834] [drm:intel_power_well_disable [i915]] disabling DC off
>[  395.628877] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  395.628916] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  395.629392] [drm:intel_power_well_disable [i915]] disabling always-on
>[  395.629619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.629644] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  395.629763] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  395.629809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.629860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  395.629910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  395.629940] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  395.629973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.630048] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  395.630093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  395.630130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  395.630170] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.630203] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.630216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.630251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.630261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.630301] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  395.630335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  395.630372] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  395.630404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.630446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.630484] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  395.630522] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.630554] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  395.630593] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  395.630624] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  395.630667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.630713] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  395.630749] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  395.630904] [drm:intel_power_well_enable [i915]] enabling always-on
>[  395.630935] [drm:intel_power_well_enable [i915]] enabling DC off
>[  395.631259] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  395.631310] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  395.631352] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  395.631422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.631468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.631503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.631545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.631578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.631616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.631648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.631684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.631720] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.631764] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.631808] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.631851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.631899] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  395.631935] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  395.634134] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  395.634167] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  395.643879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.652534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.661273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.670098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.678867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.687634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.696399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.705161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.713923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.722923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.731801] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.740570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.749263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.757860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.766403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.775143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.783636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.792112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.796553] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  395.856319] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  395.856423] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  395.856639] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  395.858265] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  395.859613] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  395.862189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.862297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.862393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.862493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.868747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.868850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  395.874632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.877359] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  395.879885] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  395.880023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  395.880423] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  395.880605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.897026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.897252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.897441] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.899078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.899285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.913739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  395.913866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.914582] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  395.932009] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  395.932197] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  395.932329] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  395.932438] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  395.932616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.932716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.932801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.932882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.932961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.933996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.934252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.934381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.934517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  395.934657] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.934755] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.934847] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.934938] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.935176] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  395.935352] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  395.935535] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.935673] [drm:intel_power_well_disable [i915]] disabling DC off
>[  395.935804] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  395.935909] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  395.936909] [drm:intel_power_well_disable [i915]] disabling always-on
>[  395.937844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.937890] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  395.938297] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  395.938436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.938583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  395.938726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  395.938812] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  395.938909] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.939002] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  395.939189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  395.939296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  395.939395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.939489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.939521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.939611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.939639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  395.939734] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  395.939847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  395.939944] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  395.940052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.940237] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.940366] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  395.940479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.940594] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  395.940682] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  395.940753] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  395.940845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.940945] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  395.941029] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  395.941533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  395.941644] [drm:intel_power_well_enable [i915]] enabling DC off
>[  395.942010] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  395.942533] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  395.942634] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  395.942965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.943218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  395.943339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  395.943448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  395.943568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  395.943685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  395.943800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  395.943907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  395.943994] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  395.944193] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  395.944306] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  395.944434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  395.944587] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  395.944718] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  395.947122] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  395.947213] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  395.957469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.966379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.975387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.984384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.993369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.002273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.011177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.020154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.029127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.038024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.046816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.055423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.063981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.072527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.081023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.089503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.097969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.106444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.109169] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  396.169925] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  396.169945] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  396.170004] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  396.170837] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  396.171606] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  396.175030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.175052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.175071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.175092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.180478] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.180497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  396.185630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.188121] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  396.188637] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  396.188692] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  396.188709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  396.188734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.205488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  396.205519] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.205565] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.206425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.206472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.222252] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  396.222292] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.222512] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  396.241144] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  396.241182] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  396.241240] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  396.241286] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.241365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.241409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  396.241446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  396.241480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  396.241514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  396.241551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  396.241583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  396.241615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  396.241651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  396.241691] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  396.241728] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.241764] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  396.241798] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  396.241854] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.241901] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.241951] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.242533] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.242588] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.242637] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.243585] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.243831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.243861] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  396.244012] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  396.244187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.244231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  396.244275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  396.244312] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  396.244352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.244391] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  396.244428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  396.244464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  396.244498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.244530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.244538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  396.244570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.244577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  396.244610] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  396.244642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  396.244673] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  396.244705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.244734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.244772] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  396.244803] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.244834] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  396.244865] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  396.244895] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  396.244932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.244975] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  396.245261] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  396.245438] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.245488] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.245789] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  396.245851] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.245902] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.246174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.246234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  396.246287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  396.246339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  396.246389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  396.246439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  396.246489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  396.246538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  396.246590] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  396.246648] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.246702] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  396.246756] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  396.246816] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  396.246868] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  396.249118] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  396.249169] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  396.258997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.267900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.277116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.286019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.295000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.303947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.313156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.322126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.331008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.339954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.348930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.357908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.366551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.375163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.383697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.392202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.400685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.409158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.411889] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  396.472706] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  396.472725] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  396.472770] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  396.473604] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  396.474308] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  396.476090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.476111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.476129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.476149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.482025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.482043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  396.487182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.489629] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  396.490151] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  396.490191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  396.490207] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  396.490230] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.507027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  396.507055] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.507098] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.507959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.508045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.523730] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  396.523763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.523813] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  396.541044] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  396.541073] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  396.541115] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  396.541149] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.541210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.541242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  396.541269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  396.541295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  396.541320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  396.541346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  396.541370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  396.541394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  396.541420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  396.541450] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  396.541478] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.541505] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  396.541531] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  396.541574] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.541610] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.541647] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.541691] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.541721] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.541747] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.542263] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.542872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.542900] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  396.543059] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  396.543108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.543153] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  396.543205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  396.543250] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  396.543299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.543345] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  396.543390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  396.543434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  396.543477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.543518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.543529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  396.543567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.543577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  396.543616] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  396.543658] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  396.543698] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  396.543740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.543780] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.543827] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  396.543868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.543910] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  396.543952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  396.543993] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  396.544085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.544140] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  396.544187] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  396.544356] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.544398] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.544692] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  396.544746] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.544791] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.544869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.544921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  396.544968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  396.545047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  396.545092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  396.545138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  396.545180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  396.545225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  396.545271] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  396.545323] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.545373] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  396.545418] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  396.545471] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  396.545518] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  396.547696] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  396.547730] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  396.557446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.566116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.575287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.584115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.592936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.602035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.610917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.620045] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.628925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.638039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.646922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.656024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.664790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.673392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.681939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.690549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.699042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.707517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.710277] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  396.771099] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  396.771120] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  396.771157] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  396.772019] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  396.773201] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  396.774976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.775010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.775031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.775052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.780910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.780931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  396.786069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.788549] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258825d28
>[  396.789151] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  396.789181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  396.789199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  396.789224] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.805976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  396.806025] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.806071] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.806904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.806951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.822705] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  396.822737] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.822890] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  396.841153] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  396.841186] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  396.841233] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  396.841271] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.841337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.841373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  396.841403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  396.841432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  396.841460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  396.841490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  396.841516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  396.841542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  396.841571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  396.841604] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  396.841635] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.841665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  396.841693] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  396.841742] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.841781] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.841823] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.841853] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.841881] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.841906] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.843194] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.843413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.843431] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  396.843512] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  396.843544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.843578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  396.843616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  396.843646] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  396.843678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.843709] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  396.843738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  396.843766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  396.843794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.843820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.843826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  396.843852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.843858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  396.843885] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  396.843910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  396.843936] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  396.843961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.844030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.844075] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  396.844110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.844149] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  396.844182] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  396.844221] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  396.844266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.844315] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  396.844352] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  396.844485] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.844516] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.844809] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  396.844859] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.844899] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.844967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.845046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  396.845082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  396.845122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  396.845156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  396.845196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  396.845229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  396.845267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  396.845304] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  396.845348] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  396.845391] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  396.845434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  396.845481] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  396.845517] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  396.847683] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  396.847715] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  396.857455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.866113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.874864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.883633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.892399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.901164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.909925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.918994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.927808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.936577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.945342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.954103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.962789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.971383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.980242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.988775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.997264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.005739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.008480] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  397.068709] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  397.068729] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  397.068766] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  397.069598] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  397.070349] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  397.072947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  397.072967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  397.073068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.073089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  397.078387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  397.078405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  397.083529] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  397.086006] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  397.086489] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  397.086535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  397.086552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  397.086574] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  397.103364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  397.103394] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.103437] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.104285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.104338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.120079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  397.120114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  397.120306] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  397.138282] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  397.138314] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  397.138362] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  397.138400] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  397.138466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.138502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  397.138532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  397.138560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  397.138588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  397.138618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  397.138644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  397.138669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  397.138698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  397.138731] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  397.138762] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.138792] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  397.138821] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  397.138868] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  397.138906] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  397.138947] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.138977] [drm:intel_power_well_disable [i915]] disabling DC off
>[  397.139650] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  397.139677] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  397.140188] [drm:intel_power_well_disable [i915]] disabling always-on
>[  397.140751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.140768] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  397.140850] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  397.140882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.140917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  397.140953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  397.140983] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  397.141281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.141319] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  397.141350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  397.141379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  397.141406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  397.141432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.141439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  397.141465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.141471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  397.141498] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  397.141525] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  397.141550] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  397.141576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.141601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  397.141632] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  397.141659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.141685] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  397.141711] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  397.141736] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  397.141767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.141802] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  397.141831] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  397.141936] [drm:intel_power_well_enable [i915]] enabling always-on
>[  397.141962] [drm:intel_power_well_enable [i915]] enabling DC off
>[  397.142871] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  397.142907] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  397.142938] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  397.143146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.143199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  397.143237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  397.143267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  397.143295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  397.143323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  397.143350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  397.143376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  397.143406] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  397.143439] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.143469] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  397.143498] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  397.143534] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  397.143564] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  397.145722] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  397.145753] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  397.155451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.164107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.173533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.182321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.191096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.199861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.208633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.217399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.226169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.234932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.243825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.252592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.261263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.269848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.278407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.286917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.295405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.303880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.308306] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  397.369087] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  397.369104] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  397.369138] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  397.369964] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  397.370647] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  397.372423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  397.372442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  397.372460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.373105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  397.378680] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  397.378699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  397.383816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  397.386264] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  397.386745] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  397.386772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  397.386788] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  397.386811] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  397.403597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  397.403624] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.403666] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.404519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.404561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.420340] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  397.420375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  397.420431] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  397.438938] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  397.438971] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  397.439100] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  397.439159] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  397.439390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.439429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  397.439460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  397.439489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  397.439517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  397.439547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  397.439574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  397.439599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  397.439629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  397.439662] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  397.439693] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.439722] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  397.439750] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  397.439796] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  397.439835] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  397.439876] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.439907] [drm:intel_power_well_disable [i915]] disabling DC off
>[  397.439935] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  397.439959] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  397.440448] [drm:intel_power_well_disable [i915]] disabling always-on
>[  397.440670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.440695] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  397.440810] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  397.440847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.440891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  397.440940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  397.440976] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  397.441056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.441103] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  397.441141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  397.441186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  397.441221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  397.441260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.441271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  397.441309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.441319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  397.441358] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  397.441389] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  397.441427] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  397.441460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.441496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  397.441533] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  397.441570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.441601] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  397.441638] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  397.441669] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  397.441711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.441757] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  397.441792] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  397.441942] [drm:intel_power_well_enable [i915]] enabling always-on
>[  397.441982] [drm:intel_power_well_enable [i915]] enabling DC off
>[  397.442308] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  397.442359] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  397.442402] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  397.442473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.442518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  397.442553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  397.442592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  397.442625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  397.442663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  397.442695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  397.442732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  397.442768] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  397.442811] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.442854] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  397.442898] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  397.442946] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  397.442984] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  397.445178] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  397.445209] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  397.454856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.463511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.472248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.481012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.489833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.498597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.507359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.516126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.524880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.533641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.542406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.551167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.559851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.568441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.576984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.585519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.594010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.602483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.606710] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  397.667271] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  397.667305] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  397.667351] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  397.668392] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  397.670151] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  397.672020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  397.672038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  397.672054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.672071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  397.677207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  397.677224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  397.682375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  397.684822] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  397.685350] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  397.685382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  397.685398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  397.685421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  397.702195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  397.702222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.702262] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.703115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.703157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.718918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  397.718950] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  397.719127] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  397.736397] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  397.736430] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  397.736477] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  397.736515] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  397.736581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.736618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  397.736648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  397.736677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  397.736705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  397.736735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  397.736762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  397.736789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  397.736818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  397.736851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  397.736882] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.736911] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  397.736941] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  397.737123] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  397.737179] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  397.737237] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.737281] [drm:intel_power_well_disable [i915]] disabling DC off
>[  397.737325] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  397.737357] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  397.737793] [drm:intel_power_well_disable [i915]] disabling always-on
>[  397.738045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.738071] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  397.738183] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  397.738220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.738265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  397.738315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  397.738350] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  397.738394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.738432] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  397.738472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  397.738507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  397.738545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  397.738578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.738587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  397.738622] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.738630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  397.738669] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  397.738701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  397.738738] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  397.738770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.738806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  397.738843] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  397.738879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.738911] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  397.738948] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  397.738981] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  397.739052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.739099] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  397.739134] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  397.739282] [drm:intel_power_well_enable [i915]] enabling always-on
>[  397.739321] [drm:intel_power_well_enable [i915]] enabling DC off
>[  397.739612] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  397.739662] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  397.739701] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  397.739770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.739815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  397.739849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  397.739888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  397.739920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  397.739958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  397.740015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  397.740052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  397.740087] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  397.740129] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  397.740174] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  397.740218] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  397.740266] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  397.740302] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  397.742469] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  397.742501] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  397.752197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.760858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.769604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.778379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.787155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.795926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.804819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.813602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.822380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.831186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.839991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.848820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.857510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.866141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.874682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.883195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.891684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.900158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  397.904583] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  397.964722] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  397.964740] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  397.964800] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  397.966288] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  397.968856] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  397.970193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  397.970211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  397.970227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.970243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  397.976167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  397.976185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  397.981308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  397.983791] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  397.984342] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  397.984418] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  397.984435] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  397.984458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  398.001211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.001238] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.001279] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.002132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.002179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.017990] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  398.018060] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  398.018255] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  398.036555] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  398.036587] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  398.036634] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  398.036672] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  398.036739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.036776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.036806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.036835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.036863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.036892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.036918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.036943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.036973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.037531] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.037564] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.037595] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.037625] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.037681] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  398.037741] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  398.037788] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.037819] [drm:intel_power_well_disable [i915]] disabling DC off
>[  398.037847] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  398.037872] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  398.038877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  398.039128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.039146] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  398.039227] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  398.039259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  398.039294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  398.039330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  398.039359] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  398.039391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  398.039422] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  398.039451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  398.039480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  398.039506] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  398.039532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  398.039538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.039564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  398.039570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.039596] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  398.039622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  398.039647] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  398.039672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  398.039696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  398.039726] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  398.039752] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  398.039778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  398.039803] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  398.039827] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  398.039857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.039892] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  398.039922] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  398.040599] [drm:intel_power_well_enable [i915]] enabling always-on
>[  398.040640] [drm:intel_power_well_enable [i915]] enabling DC off
>[  398.040930] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  398.040982] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  398.041073] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  398.041152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.041202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.041239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.041280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.041315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.041353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.041385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.041423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.041459] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.041503] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.041547] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.041589] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.041638] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  398.041674] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  398.043840] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  398.043872] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  398.053579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.062240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.071004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.079844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.088623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.097398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.106187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.115014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.123846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.132615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.141413] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.150184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.158926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.167714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.176844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.185354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.193844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.202318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.206744] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  398.267558] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  398.267578] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  398.267614] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  398.268466] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  398.269188] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  398.271763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  398.271783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  398.271801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  398.271820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  398.277203] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  398.277220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  398.282343] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  398.284832] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  398.285377] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  398.285417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  398.285434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  398.285457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  398.302212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.302240] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.302281] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.303093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.303135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.318959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  398.319029] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  398.319227] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  398.337206] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  398.337239] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  398.337286] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  398.337324] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  398.337390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.337427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.337457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.337486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.337515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.337544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.337570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.337595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.337625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.337657] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.337688] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.337718] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.337747] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.337795] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  398.337834] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  398.337876] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.337906] [drm:intel_power_well_disable [i915]] disabling DC off
>[  398.337935] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  398.337960] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  398.338583] [drm:intel_power_well_disable [i915]] disabling always-on
>[  398.338804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.338829] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  398.338935] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  398.338968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  398.339107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  398.339160] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  398.339202] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  398.339237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  398.339270] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  398.339301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  398.339331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  398.339359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  398.339386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  398.339394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.339419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  398.339425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.339454] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  398.339479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  398.339505] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  398.339530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  398.339556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  398.339587] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  398.339614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  398.339639] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  398.339665] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  398.339690] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  398.339722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.339759] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  398.339788] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  398.339895] [drm:intel_power_well_enable [i915]] enabling always-on
>[  398.339920] [drm:intel_power_well_enable [i915]] enabling DC off
>[  398.340366] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  398.340727] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  398.340770] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  398.340896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.340944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.340974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.341102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.341144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.341187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.341217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.341245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.341274] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.341308] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.341339] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.341369] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.341406] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  398.341436] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  398.343594] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  398.343626] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  398.353342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.361998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.370847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.380436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.389207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.397974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.406799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.415560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.424321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.433080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.441849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.450612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.459281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.467872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.476412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.484924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.493411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.501886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.506312] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  398.566117] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  398.566136] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  398.566200] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  398.567682] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  398.570237] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  398.571574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  398.571592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  398.571608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  398.571624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  398.577171] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  398.577189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  398.582313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  398.584797] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  398.585372] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  398.585423] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  398.585439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  398.585462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  398.602215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.602243] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.602284] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.603131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.603173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.618985] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  398.619049] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  398.619225] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  398.637936] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  398.637964] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  398.638084] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  398.638132] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  398.638214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.638262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.638299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.638339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.638371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.638412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.638441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.638473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.638504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.638542] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.638580] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.638616] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.638651] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.638710] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  398.638757] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  398.638804] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.638841] [drm:intel_power_well_disable [i915]] disabling DC off
>[  398.638878] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  398.638910] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  398.639386] [drm:intel_power_well_disable [i915]] disabling always-on
>[  398.639564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.639579] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  398.639648] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  398.639675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  398.639706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  398.639737] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  398.639763] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  398.639790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  398.639817] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  398.639842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  398.639867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  398.639889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  398.639912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  398.639918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.639939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  398.639944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.639967] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  398.640027] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  398.640056] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  398.640089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  398.640117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  398.640154] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  398.640181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  398.640213] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  398.640240] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  398.640271] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  398.640302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.640341] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  398.640374] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  398.640509] [drm:intel_power_well_enable [i915]] enabling always-on
>[  398.640535] [drm:intel_power_well_enable [i915]] enabling DC off
>[  398.640822] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  398.640865] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  398.640900] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  398.640961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.641026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.641056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.641091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.641119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.641151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.641179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.641210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.641240] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.641277] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.641314] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.641350] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.641391] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  398.641421] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  398.643583] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  398.643610] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  398.653428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.662053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.670696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.679351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.688014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.696726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.705383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.714042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.722697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.731349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.740009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.748713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.757338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.765898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.775142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.783652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.792134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.800600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.806696] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  398.866827] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  398.866845] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  398.866882] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  398.867711] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  398.868518] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  398.871101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  398.871121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  398.871140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  398.871159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  398.876537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  398.876555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  398.881677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  398.884173] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  398.884656] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  398.884684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  398.884700] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  398.884722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  398.901477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.901504] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.901545] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.902360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.902403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.918228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  398.918265] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  398.918461] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  398.936559] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  398.936592] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  398.936638] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  398.936677] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  398.936743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.936779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.936810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.936839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.936867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.936897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.936923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.936949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.936979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  398.937450] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.937497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.937541] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.937583] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.937643] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  398.937697] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  398.937753] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  398.937797] [drm:intel_power_well_disable [i915]] disabling DC off
>[  398.937841] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  398.937880] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  398.938804] [drm:intel_power_well_disable [i915]] disabling always-on
>[  398.938947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  398.939146] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  398.939230] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  398.939263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  398.939298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  398.939335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  398.939365] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  398.939397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  398.939428] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  398.939457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  398.939487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  398.939514] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  398.939540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  398.939547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.939573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  398.939579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  398.939606] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  398.939632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  398.939657] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  398.939682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  398.939706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  398.939737] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  398.939762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  398.939788] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  398.939813] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  398.939837] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  398.939867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.939978] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  398.940476] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  398.940622] [drm:intel_power_well_enable [i915]] enabling always-on
>[  398.940654] [drm:intel_power_well_enable [i915]] enabling DC off
>[  398.940945] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  398.941214] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  398.941255] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  398.941371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  398.941418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  398.941454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  398.941494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  398.941528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  398.941568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  398.941601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  398.941640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  398.941675] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  398.941719] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  398.941762] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  398.941804] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  398.941852] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  398.941889] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  398.944087] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  398.944119] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  398.953866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.962528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.971291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.980078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.988862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  398.997642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.006420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.015194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.024014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.032837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.041601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.050368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.059043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.067625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.076168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.084697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.093187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.101660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.106089] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  399.166795] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  399.166815] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  399.166880] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  399.167720] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  399.168514] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  399.171097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  399.171116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  399.171135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.171154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  399.177173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  399.177191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  399.182317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  399.184802] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258825d28
>[  399.185381] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  399.185426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  399.185443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  399.185465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  399.202221] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  399.202248] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  399.202291] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.203150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.203212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.219032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  399.219068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  399.219124] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  399.236069] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  399.236097] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  399.236137] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  399.236169] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  399.236227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.236257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  399.236283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  399.236308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  399.236331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  399.236356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  399.236378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  399.236400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  399.236425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  399.236454] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  399.236481] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.236506] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  399.236530] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  399.236571] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  399.236604] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  399.236640] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  399.236666] [drm:intel_power_well_disable [i915]] disabling DC off
>[  399.236691] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  399.236712] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  399.237227] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.237811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.237836] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  399.237949] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  399.237994] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  399.238070] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  399.238119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  399.238156] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  399.238200] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  399.238238] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  399.238278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  399.238314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  399.238352] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  399.238384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  399.238394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  399.238428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  399.238436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  399.238477] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  399.238509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  399.238546] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  399.238577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  399.238613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  399.238650] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  399.238686] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  399.238718] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  399.238755] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  399.238786] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  399.238827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.238873] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  399.238909] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  399.239093] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.239126] [drm:intel_power_well_enable [i915]] enabling DC off
>[  399.239421] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  399.239473] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  399.239513] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  399.239582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.239627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  399.239661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  399.239700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  399.239732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  399.239770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  399.239802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  399.239839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  399.239873] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  399.239917] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.239961] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  399.240032] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  399.240082] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  399.240119] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  399.242286] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  399.242317] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  399.251928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.260649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.269313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.277974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.286675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.295338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.303996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.312694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.321346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.329993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.338683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.347313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.355869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.364392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.373444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.381926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.390393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.398852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.404946] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  399.465419] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  399.465439] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  399.465476] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  399.466307] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  399.467001] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  399.468826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  399.468846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  399.468865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.468884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  399.474758] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  399.474778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  399.479913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  399.482399] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  399.482916] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  399.482974] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  399.483034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  399.483071] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  399.499770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  399.499800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  399.499844] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.500679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.500727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.516473] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  399.516504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  399.516549] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  399.533904] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  399.533937] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  399.533985] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  399.534123] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  399.534203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.534245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  399.534277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  399.534309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  399.534339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  399.534372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  399.534401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  399.534432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  399.534463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  399.534500] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  399.534533] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.534565] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  399.534595] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  399.534642] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  399.534682] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  399.534723] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  399.534754] [drm:intel_power_well_disable [i915]] disabling DC off
>[  399.534784] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  399.534809] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  399.535298] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.535892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.535909] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  399.535989] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  399.536078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  399.536116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  399.536154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  399.536184] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  399.536217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  399.536249] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  399.536280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  399.536309] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  399.536338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  399.536364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  399.536372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  399.536398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  399.536404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  399.536432] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  399.536458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  399.536485] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  399.536510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  399.536537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  399.536568] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  399.536595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  399.536620] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  399.536645] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  399.536671] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  399.536701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.536737] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  399.536767] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  399.536873] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.536898] [drm:intel_power_well_enable [i915]] enabling DC off
>[  399.537219] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  399.537271] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  399.537307] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  399.537378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.537419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  399.537454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  399.537489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  399.537530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  399.537566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  399.537599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  399.537639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  399.537670] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  399.537703] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.537735] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  399.537766] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  399.537802] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  399.537833] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  399.540020] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  399.540051] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  399.549752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.558416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.567153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.575924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.584803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.593563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.602327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.611086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.619843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.628599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.637357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.646126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.654814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.663435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.671979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.680511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.689001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.697473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.701899] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  399.762193] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  399.762309] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  399.762501] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  399.764260] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  399.765301] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  399.766325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  399.766433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  399.766530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.766632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  399.772288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  399.772381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  399.777909] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  399.780633] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  399.782868] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  399.783041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  399.783276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  399.783448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  399.800015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  399.800235] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  399.800419] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.802243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.802454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.816744] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  399.816870] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  399.817303] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  399.835408] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  399.835498] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  399.835652] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  399.835781] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  399.835992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.836373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  399.836502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  399.836651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  399.836776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  399.836902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  399.837000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  399.837209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  399.837319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  399.837456] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  399.837595] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.837752] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  399.837896] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  399.838227] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  399.838414] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  399.838603] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  399.838754] [drm:intel_power_well_disable [i915]] disabling DC off
>[  399.838875] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  399.838968] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  399.839596] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.840663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.840729] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  399.841080] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  399.841333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  399.841466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  399.841608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  399.841726] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  399.841853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  399.841964] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  399.842173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  399.842283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  399.842399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  399.842496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  399.842531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  399.842633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  399.842663] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  399.842774] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  399.842866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  399.842972] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  399.843173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  399.843267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  399.843393] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  399.843488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  399.843599] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  399.843690] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  399.843794] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  399.843899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.844039] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  399.844444] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  399.844866] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.844956] [drm:intel_power_well_enable [i915]] enabling DC off
>[  399.845416] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  399.845949] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  399.846160] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  399.846364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.846498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  399.846600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  399.846714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  399.846809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  399.846919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  399.847017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  399.847208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  399.847317] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  399.847450] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  399.847577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  399.847703] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  399.847842] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  399.847948] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  399.850410] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  399.850500] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  399.860613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.869528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.878435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.887339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.896235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.905097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.913943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.922885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.931713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.940575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.949258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.957848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.966411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.975144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.983632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  399.992107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.000568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.009025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.013434] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  400.074182] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  400.074202] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  400.074246] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  400.075079] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  400.075793] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  400.078385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  400.078404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.078423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.078441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.083820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.083838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  400.088960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.091398] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  400.091882] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  400.091930] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  400.091946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  400.091968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  400.108724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  400.108752] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.108793] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.109603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.109646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.125482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  400.125514] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  400.125562] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  400.142848] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  400.142877] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  400.142918] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  400.142951] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  400.143231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.143266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  400.143293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  400.143319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  400.143343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  400.143370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  400.143394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  400.143417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  400.143444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  400.143472] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  400.143499] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.143524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  400.143549] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  400.143588] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  400.143622] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  400.143657] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.143683] [drm:intel_power_well_disable [i915]] disabling DC off
>[  400.143708] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  400.143729] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  400.144644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.144775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.144789] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  400.144856] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  400.144882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  400.144911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  400.144942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  400.144968] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  400.145168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  400.145196] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  400.145221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  400.145246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  400.145270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  400.145293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  400.145299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  400.145322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  400.145327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  400.145350] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  400.145372] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  400.145395] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  400.145416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  400.145438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  400.145466] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  400.145489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  400.145510] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  400.145532] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  400.145553] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  400.145580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.145610] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  400.145636] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  400.145725] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.145746] [drm:intel_power_well_enable [i915]] enabling DC off
>[  400.146252] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  400.146536] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  400.146564] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  400.146627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.146656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  400.146682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  400.146706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  400.146729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  400.146752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  400.146774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  400.146796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  400.146820] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  400.146847] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.146873] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  400.146898] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  400.146928] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  400.146954] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  400.149349] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  400.149382] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  400.159050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.167670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.176927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.185902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.194560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.203213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.211909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.220561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.229211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.237899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.246555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.255211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.263795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.272332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.280838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.289322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.297794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.306253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.312346] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  400.372594] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  400.372613] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  400.372755] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  400.373596] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  400.374344] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  400.376947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  400.376967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.377047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.377073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.382388] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.382405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  400.387529] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.390013] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  400.390493] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  400.390537] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  400.390553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  400.390576] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  400.407334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  400.407362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.407403] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.408253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.408302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.424100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  400.424135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  400.424188] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  400.441433] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  400.441465] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  400.441513] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  400.441551] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  400.441617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.441653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  400.441683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  400.441712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  400.441739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  400.441769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  400.441796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  400.441822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  400.441853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  400.441889] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  400.441922] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.441953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  400.441982] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  400.442242] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  400.442305] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  400.442368] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.442417] [drm:intel_power_well_disable [i915]] disabling DC off
>[  400.442462] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  400.442496] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  400.443429] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.443652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.443677] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  400.443795] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  400.443834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  400.443878] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  400.443924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  400.443960] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  400.444034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  400.444100] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  400.444146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  400.444196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  400.444238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  400.444284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  400.444297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  400.444343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  400.444356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  400.444406] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  400.444448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  400.444492] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  400.444530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  400.444575] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  400.444621] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  400.444665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  400.444704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  400.444747] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  400.444784] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  400.444834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.444888] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  400.444930] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  400.445155] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.445200] [drm:intel_power_well_enable [i915]] enabling DC off
>[  400.445500] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  400.445561] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  400.445608] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  400.445697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.445753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  400.445795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  400.445841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  400.445881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  400.445925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  400.445964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  400.446042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  400.446088] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  400.446144] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.446198] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  400.446252] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  400.446310] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  400.446354] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  400.448577] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  400.448617] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  400.458514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.467243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.476017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.484844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.493608] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.502369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.511126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.519879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.528638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.537392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.546155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.554856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.563457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.572022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.580540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.589035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.597509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.605975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.610200] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  400.670683] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  400.670705] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  400.670757] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  400.671636] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  400.673443] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  400.675325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  400.675343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.675359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.675375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.680491] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.680508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  400.685623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.688109] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  400.688592] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  400.688632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  400.688648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  400.688671] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  400.705449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  400.705477] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.705519] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.706403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.706452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.722171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  400.722202] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  400.722248] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  400.739435] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  400.739466] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  400.739511] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  400.739550] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  400.739613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.739648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  400.739678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  400.739706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  400.739735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  400.739764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  400.739791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  400.739817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  400.739847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  400.739880] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  400.739911] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.739940] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  400.739969] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  400.740158] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  400.740214] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  400.740271] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.740316] [drm:intel_power_well_disable [i915]] disabling DC off
>[  400.740360] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  400.740400] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  400.740840] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.741096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.741119] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  400.741234] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  400.741279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  400.741325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  400.741374] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  400.741416] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  400.741459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  400.741504] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  400.741546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  400.741588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  400.741629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  400.741669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  400.741679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  400.741717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  400.741726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  400.741765] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  400.741806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  400.741846] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  400.741885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  400.741924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  400.741968] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  400.742047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  400.742092] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  400.742134] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  400.742174] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  400.742221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.742271] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  400.742317] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  400.742461] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.742500] [drm:intel_power_well_enable [i915]] enabling DC off
>[  400.742813] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  400.742869] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  400.742910] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  400.742982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.743068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  400.743114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  400.743156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  400.743199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  400.743240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  400.743280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  400.743319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  400.743362] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  400.743408] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  400.743451] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  400.743494] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  400.743543] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  400.743587] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  400.745801] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  400.745841] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  400.755615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.764337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.773116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.781913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.790819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.799598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.808372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.817145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.825914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.834811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.843595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.852337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.860973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.869591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.878124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.886626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.895109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.903581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  400.907996] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  400.968072] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  400.968091] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  400.968146] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  400.968982] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  400.969695] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  400.971477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  400.971498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.971516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.971535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.978194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.978212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  400.983338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.985781] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  400.986350] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  400.986397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  400.986414] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  400.986436] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  401.003193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  401.003221] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  401.003263] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  401.004111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  401.004156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  401.019962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  401.020026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  401.020201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  401.037054] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  401.037078] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  401.037114] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  401.037143] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  401.037194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  401.037221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  401.037243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  401.037264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  401.037285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  401.037307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  401.037327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  401.037346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  401.037369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  401.037393] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  401.037417] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  401.037439] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  401.037461] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  401.037497] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  401.037527] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  401.037559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  401.037582] [drm:intel_power_well_disable [i915]] disabling DC off
>[  401.037603] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  401.037621] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  401.038719] [drm:intel_power_well_disable [i915]] disabling always-on
>[  401.042320] [IGT] kms_flip: exiting, ret=0
>[  401.067180] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  401.067235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  401.067292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  401.067351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  401.067399] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  401.067448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  401.067499] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  401.067546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  401.067592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  401.067635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  401.067677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  401.067687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  401.067729] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  401.067736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  401.067778] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  401.067819] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  401.067859] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  401.067899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  401.067937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  401.067985] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  401.068059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  401.068101] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  401.068141] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  401.068179] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  401.068228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  401.068282] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  401.068329] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  401.068496] [drm:intel_power_well_enable [i915]] enabling always-on
>[  401.068536] [drm:intel_power_well_enable [i915]] enabling DC off
>[  401.068830] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  401.068890] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  401.068944] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  401.069100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  401.069152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  401.069195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  401.069235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  401.069274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  401.069313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  401.069352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  401.069390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  401.069434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  401.069482] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  401.069527] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  401.069571] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  401.069624] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  401.069669] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  401.071164] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  401.071210] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  401.081145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.090188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.099183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.108131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.117153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.126154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.135093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.143950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.152880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.161746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.170590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.179435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.188199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.196850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.205405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.213927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.222424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.230904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.233667] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  401.294217] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  401.294233] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  401.294266] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  401.294968] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  401.295772] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  401.297585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  401.297604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  401.297622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  401.297640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  401.303520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  401.303536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  401.308666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  401.311150] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  401.311684] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  401.311725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  401.311740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  401.311763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  401.311899] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  401.311916] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  401.328525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  401.328551] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  401.328595] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  401.328748] Console: switching to colour frame buffer device 200x56
>[  401.523752] Console: switching to colour dummy device 80x25
>[  401.524455] [IGT] kms_flip: executing
>[  401.548683] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  401.548752] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  401.548776] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  401.548807] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  401.548864] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  401.550209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  401.550267] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  401.552186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  401.552203] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  401.554200] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  401.554257] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  401.556213] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  401.556229] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  401.556240] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  401.556278] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  401.556337] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  401.557218] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  401.557296] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  401.558286] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  401.559221] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  401.561011] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  401.561099] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  401.561146] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  401.561192] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  401.562126] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  401.562949] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  401.564268] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  401.564276] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  401.564284] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  401.564290] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  401.564505] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  401.564511] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  401.564524] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  401.564529] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  401.564541] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  401.564547] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  401.564567] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  401.564575] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  401.564583] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  401.564590] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  401.564598] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  401.564605] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  401.564612] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  401.564620] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  401.564627] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  401.564634] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  401.564641] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  401.564648] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  401.564655] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  401.564662] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  401.564669] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  401.564676] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  401.564683] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  401.564690] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  401.564697] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  401.564704] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  401.564711] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  401.564718] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  401.564725] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  401.564732] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  401.564739] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  401.565544] [IGT] kms_flip: starting subtest basic-flip-vs-wf_vblank
>[  401.567693] [drm:drm_mode_addfb2] [FB:64]
>[  401.567754] [drm:drm_mode_addfb2] [FB:78]
>[  401.641488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  401.641536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  401.641603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  401.641623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  401.641658] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  401.646246] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  401.646262] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  401.646283] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  401.646303] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  401.646320] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  401.646353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  401.646370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  401.646384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  401.646398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  401.646411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  401.646426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  401.646438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  401.646451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  401.646466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  401.646482] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  401.646498] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  401.646512] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  401.646527] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  401.646547] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  401.646567] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  401.646588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  401.646605] [drm:intel_power_well_disable [i915]] disabling DC off
>[  401.646619] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  401.646631] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  401.647070] [drm:intel_power_well_disable [i915]] disabling always-on
>[  401.647145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  401.647565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  401.647653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  401.647666] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  401.647723] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  401.647744] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  401.647767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  401.647791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  401.647811] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  401.647833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  401.647854] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  401.647874] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  401.647894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  401.647914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  401.647933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  401.647938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  401.647956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  401.647960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  401.648000] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  401.648020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  401.648037] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  401.648058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  401.648078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  401.648100] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  401.648120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  401.648140] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  401.648160] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  401.648180] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  401.648202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  401.648226] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  401.648247] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  401.648510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  401.648522] [drm:intel_power_well_enable [i915]] enabling DC off
>[  401.648787] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  401.648805] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  401.648818] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  401.648856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  401.648874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  401.648888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  401.648901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  401.648914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  401.648927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  401.648939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  401.648952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  401.648965] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  401.649010] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  401.649032] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  401.649055] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  401.649080] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  401.649101] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  401.651250] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  401.651265] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  401.660712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.669173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.677633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.686093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.694551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.703009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.711467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.719926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.728384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.736843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.745300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.753760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.762219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.770677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.779137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.787595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.796054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.804512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  401.812295] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  401.873056] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  401.873077] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  401.873117] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  401.873730] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  401.874537] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  401.875254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  401.875272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  401.875288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  401.875305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  401.881036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  401.881052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  401.886157] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  401.888602] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  401.889078] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  401.889111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  401.889126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  401.889147] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  401.889181] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  401.889197] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  401.905929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  401.905953] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  401.906030] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  405.541466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.541853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.542315] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.543837] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.560227] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  405.560333] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  405.560535] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.560831] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  405.561025] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  405.561571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  405.561666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  405.561699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  405.561731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  405.561762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  405.561797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  405.561827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  405.561857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  405.561890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  405.561925] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  405.561960] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  405.562017] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  405.562048] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  405.562109] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.562185] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.562229] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  405.562267] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.562300] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  405.562329] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  405.562752] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.563039] [drm:drm_mode_addfb2] [FB:64]
>[  405.563073] [drm:drm_mode_addfb2] [FB:65]
>[  405.587465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  405.587807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  405.587872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  405.588410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  405.588422] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  405.588476] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  405.588497] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.588518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  405.588541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  405.588560] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  405.588579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.588599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  405.588617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  405.588635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  405.588651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  405.588667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.588671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  405.588687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.588691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  405.588707] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  405.588723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  405.588739] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.588754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.588769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.588789] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  405.588804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.588820] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  405.588835] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  405.588850] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  405.588869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.588890] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  405.588909] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  405.589204] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.589220] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.589485] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  405.589507] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.589523] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.589571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  405.589596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  405.589615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  405.589632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  405.589649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  405.589667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  405.589683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  405.589699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  405.589717] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  405.589737] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  405.589756] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  405.589775] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  405.589797] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  405.589815] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  405.591956] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  405.591975] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  405.601552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.610037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.618519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.627001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.635482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.643963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.652459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.660939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.669416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.677879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.686337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.694795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.703254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.711711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.720167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.728624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.737090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.745548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.754006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.755045] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  405.814900] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  405.814919] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  405.814957] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  405.815798] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  405.816524] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  405.819107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  405.819127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  405.819144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  405.819163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  405.824542] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  405.824559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  405.829680] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  405.832161] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258825d28
>[  405.832641] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  405.832688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  405.832704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  405.832727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  405.849483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  405.849510] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  405.849552] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  409.484946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.485445] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.485589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.485817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.502960] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  409.503189] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  409.503346] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  409.503474] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  409.503688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.503809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  409.503910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  409.504008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  409.504297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  409.504452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  409.504611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  409.504757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  409.504910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  409.505088] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  409.505343] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  409.505501] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  409.505649] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  409.505810] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.505852] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.505896] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  409.505930] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.505963] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  409.506017] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  409.506443] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.506739] [drm:drm_mode_addfb2] [FB:64]
>[  409.506770] [drm:drm_mode_addfb2] [FB:65]
>[  409.526936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  409.527420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  409.527480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  409.527905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  409.527916] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  409.527968] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  409.528127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.528157] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  409.528189] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  409.528216] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  409.528244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.528272] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  409.528298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  409.528324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  409.528350] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  409.528375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.528381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  409.528404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.528409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  409.528432] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  409.528457] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  409.528480] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  409.528505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.528530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.528557] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  409.528582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.528606] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  409.528630] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  409.528653] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  409.528680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.528709] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  409.528735] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  409.529076] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.529100] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.529375] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  409.529399] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.529415] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.529453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.529475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  409.529494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  409.529512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  409.529529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  409.529546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  409.529562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  409.529578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  409.529596] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  409.529616] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  409.529635] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  409.529654] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  409.529676] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  409.529695] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  409.531856] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  409.531876] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  409.541456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.549943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.558426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.566908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.575390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.583873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.592348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.600811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.609269] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.617727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.626185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.634642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.643099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.651556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.660015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.668471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.676928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.685388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.693847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  409.694884] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  409.755651] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  409.755668] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  409.755728] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  409.756437] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  409.757251] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  409.757970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  409.758025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  409.758043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.758062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  409.763799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  409.763817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  409.768942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  409.771424] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  409.771912] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  409.771950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  409.771967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  409.772067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  409.788780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  409.788810] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  409.788854] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  413.424297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.424649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.424788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.425011] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.441250] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  413.441357] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  413.441516] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  413.441642] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  413.441855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.441973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  413.443376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  413.443487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  413.443590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  413.443701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  413.443798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  413.443893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  413.443997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  413.444289] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  413.444445] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  413.444591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  413.444665] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  413.444711] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.444751] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.444791] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  413.444821] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.444851] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  413.444878] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  413.445318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.448232] [IGT] kms_flip: exiting, ret=0
>[  413.471716] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  413.471749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.471783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  413.471818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  413.471845] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  413.471875] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.471905] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  413.471932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  413.471958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  413.471984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.472058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.472064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  413.472089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.472094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  413.472119] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  413.472143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  413.472166] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  413.472189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.472212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.472240] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  413.472264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.472288] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  413.472311] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  413.472334] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  413.472362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.472394] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  413.472421] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  413.472524] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.472547] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.472818] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  413.472853] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.472884] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.472951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.472982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  413.473027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  413.473050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  413.473073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  413.473095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  413.473117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  413.473139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  413.473164] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  413.473192] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  413.473218] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  413.473243] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  413.473274] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  413.473299] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  413.475117] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  413.475144] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  413.484747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.493329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.501908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.510484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.519055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.527629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.536200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.544771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.553328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.561852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.570356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.578844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.587315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.595777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.604240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.612703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.621165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.629626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.637429] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  413.698309] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  413.698327] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  413.698354] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  413.699180] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  413.699916] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  413.702503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.702522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.702539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.702557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.707949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.707965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  413.713110] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.715593] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258825d28
>[  413.716144] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  413.716220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  413.716236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  413.716258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.716301] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  413.716317] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  413.733031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  413.733057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.733101] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  413.733258] Console: switching to colour frame buffer device 200x56
>[  413.877422] Console: switching to colour dummy device 80x25
>[  413.877517] [IGT] kms_flip: executing
>[  413.898342] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  413.898371] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  413.898385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  413.898411] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  413.898433] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  413.899623] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.899660] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.901884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.901893] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  413.904130] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.904152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.906299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.906307] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.906312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  413.906333] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  413.906357] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  413.907223] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  413.907250] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  413.907941] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  413.908764] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  413.910284] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  413.910304] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  413.910322] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  413.910339] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  413.911138] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  413.911845] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  413.912729] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  413.912733] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  413.912736] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  413.912738] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  413.912821] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.912824] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.912829] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  413.912831] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  413.912835] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.912838] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.912846] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  413.912849] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  413.912852] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.912855] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.912857] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.912860] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.912863] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.912866] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  413.912868] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.912871] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.912874] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  413.912876] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.912879] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.912882] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  413.912884] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  413.912887] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  413.912890] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  413.912892] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  413.912895] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.912898] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.912900] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.912903] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  413.912906] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.912908] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.912911] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  413.913260] [IGT] kms_flip: starting subtest basic-plain-flip
>[  413.914023] [drm:drm_mode_addfb2] [FB:61]
>[  413.914046] [drm:drm_mode_addfb2] [FB:78]
>[  413.955730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  413.955778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.955845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  413.955866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.955902] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  413.968484] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  413.968501] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  413.968524] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  413.968544] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  413.968562] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  413.968597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.968616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  413.968630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  413.968644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  413.968657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  413.968672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  413.968685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  413.968698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  413.968713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  413.968729] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  413.968744] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  413.968758] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  413.968772] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  413.968797] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.968818] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.968839] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.968858] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.968873] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  413.968885] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  413.969325] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.969396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  413.969806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  413.969885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  413.969898] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  413.969956] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  413.969978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.970022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  413.970047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  413.970068] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  413.970090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.970112] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  413.970133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  413.970153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  413.970173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.970192] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.970197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  413.970214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.970219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  413.970237] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  413.970257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  413.970277] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  413.970296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.970316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.970338] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  413.970357] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.970376] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  413.970396] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  413.970415] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  413.970437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.970460] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  413.970482] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  413.970745] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.970758] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.971044] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  413.971072] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.971093] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.971133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.971157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  413.971178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  413.971199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  413.971219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  413.971239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  413.971258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  413.971279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  413.971300] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  413.971323] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  413.971345] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  413.971367] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  413.971391] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  413.971413] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  413.973556] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  413.973571] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  413.983054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.991516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  413.999978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.008451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.016914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.025374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.033835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.042294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.050752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.059211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.067683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.076144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.084602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.093061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.101521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.109994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.118454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.126914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  414.134694] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  414.194326] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  414.194346] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  414.194377] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  414.195684] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  414.198232] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  414.199562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.199578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.199594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.199609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.204745] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.204761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  414.209877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.212359] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  414.212801] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  414.212832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  414.212847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  414.212868] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.212905] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  414.212921] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  414.229625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  414.229649] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  414.229686] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  417.581663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.582015] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  417.582378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  417.582687] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  417.598993] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  417.599046] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  417.599078] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  417.599108] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  417.599133] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  417.599182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.599208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  417.599229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  417.599249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  417.599269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  417.599290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  417.599309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  417.599327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  417.599348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  417.599372] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  417.599395] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  417.599416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  417.599437] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  417.599471] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  417.599500] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  417.599533] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  417.599558] [drm:intel_power_well_disable [i915]] disabling DC off
>[  417.599579] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  417.599597] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  417.600054] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.600390] [drm:drm_mode_addfb2] [FB:61]
>[  417.600438] [drm:drm_mode_addfb2] [FB:65]
>[  417.623905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  417.624280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  417.624343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  417.624757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  417.624767] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  417.624821] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  417.624841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.624861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  417.624884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  417.624901] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  417.624921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.624940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  417.624958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  417.624981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  417.625024] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.625045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.625051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  417.625070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.625076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  417.625096] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  417.625115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  417.625134] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  417.625153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.625172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.625200] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  417.625219] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.625238] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  417.625262] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  417.625278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  417.625297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.625318] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  417.625336] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  417.625593] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.625608] [drm:intel_power_well_enable [i915]] enabling DC off
>[  417.625870] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  417.625891] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  417.625907] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  417.625973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.626022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  417.626044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  417.626065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  417.626085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  417.626105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  417.626129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  417.626148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  417.626169] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  417.626197] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  417.626216] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  417.626234] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  417.626256] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  417.626274] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  417.628416] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  417.628435] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  417.638051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.646535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.655016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.663494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.671973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.680468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.688947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.697462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.705942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.714420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.722896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.731361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.739819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.748278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.756736] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.765198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.773656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.782117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.789702] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  417.850569] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  417.850590] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  417.850619] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  417.852048] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  417.854606] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  417.855944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.855962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.856010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.856036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.861247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.861264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  417.866401] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.868884] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  417.869420] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  417.869461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  417.869477] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  417.869500] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  417.886280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  417.886307] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  417.886348] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  421.238386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  421.238727] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  421.238862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  421.239306] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  421.254894] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  421.255001] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  421.255454] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  421.255636] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  421.255965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  421.256267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  421.256431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  421.256588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  421.256735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  421.256894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  421.257039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  421.257508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  421.257553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  421.257577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  421.257598] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  421.257618] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  421.257638] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  421.257667] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  421.257694] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  421.257724] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  421.257744] [drm:intel_power_well_disable [i915]] disabling DC off
>[  421.257763] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  421.257780] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  421.258223] [drm:intel_power_well_disable [i915]] disabling always-on
>[  421.258465] [drm:drm_mode_addfb2] [FB:61]
>[  421.258493] [drm:drm_mode_addfb2] [FB:65]
>[  421.279328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  421.279660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  421.279718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  421.280200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  421.280216] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  421.280290] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  421.280319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  421.280347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  421.280370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  421.280389] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  421.280409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  421.280428] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  421.280447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  421.280464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  421.280481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  421.280496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  421.280501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  421.280516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  421.280520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  421.280536] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  421.280552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  421.280567] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  421.280581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  421.280597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  421.280615] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  421.280631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  421.280646] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  421.280661] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  421.280676] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  421.280695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  421.280716] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  421.280734] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  421.281023] [drm:intel_power_well_enable [i915]] enabling always-on
>[  421.281043] [drm:intel_power_well_enable [i915]] enabling DC off
>[  421.281310] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  421.281345] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  421.281367] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  421.281427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  421.281449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  421.281467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  421.281483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  421.281500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  421.281515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  421.281531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  421.281547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  421.281564] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  421.281583] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  421.281601] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  421.281618] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  421.281639] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  421.281657] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  421.283797] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  421.283816] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  421.293386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.301868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.310349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.318828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.327307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.335787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.344266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.352762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.361241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.369707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.378197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.386655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.395115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.403574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.412033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.420491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.428950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.437445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.445906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  421.446948] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  421.507842] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  421.507865] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  421.508000] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  421.508549] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  421.509358] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  421.510083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  421.510102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  421.510121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  421.510139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  421.515896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  421.515913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  421.521052] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  421.523497] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258821bf8
>[  421.523978] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  421.524061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  421.524078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  421.524101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  421.540877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  421.540904] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  421.540946] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  424.892823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  424.893459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  424.893659] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  424.893967] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  424.909992] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  424.910222] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  424.910383] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  424.910511] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  424.910725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  424.910845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  424.910947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  424.911048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  424.911323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  424.911468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  424.911587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  424.911703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  424.911830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  424.912006] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  424.912234] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  424.912396] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  424.912555] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  424.912787] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  424.912998] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  424.913217] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  424.913248] [drm:intel_power_well_disable [i915]] disabling DC off
>[  424.913277] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  424.913298] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  424.913707] [drm:intel_power_well_disable [i915]] disabling always-on
>[  424.916637] [IGT] kms_flip: exiting, ret=0
>[  424.939842] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  424.939884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  424.939926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  424.939970] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  424.940044] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  424.940082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  424.940139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  424.940182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  424.940224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  424.940264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  424.940302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  424.940312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  424.940349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  424.940356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  424.940395] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  424.940433] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  424.940470] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  424.940506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  424.940542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  424.940587] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  424.940624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  424.940661] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  424.940697] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  424.940732] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  424.940778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  424.940829] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  424.940873] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  424.941032] [drm:intel_power_well_enable [i915]] enabling always-on
>[  424.941068] [drm:intel_power_well_enable [i915]] enabling DC off
>[  424.941353] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  424.941409] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  424.941457] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  424.941562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  424.941609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  424.941648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  424.941685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  424.941721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  424.941756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  424.941790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  424.941824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  424.941863] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  424.941907] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  424.941949] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  424.942001] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  424.942082] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  424.942122] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  424.944170] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  424.944212] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  424.954080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  424.962824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  424.971562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  424.980297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  424.989097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  424.997831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.006561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.015285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.024020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.032800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.041452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.050034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.058568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.067078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.075566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.084058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.092523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.100999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.107126] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  425.167831] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  425.167847] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  425.167872] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  425.168691] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  425.169430] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  425.172017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  425.172033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  425.172049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  425.172066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  425.177456] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  425.177470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  425.182593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  425.185075] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258821bf8
>[  425.185576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  425.185650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  425.185664] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  425.185685] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  425.185731] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  425.185752] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  425.202444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  425.202467] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  425.202506] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  425.202651] Console: switching to colour frame buffer device 200x56
>[  425.330497] Console: switching to colour dummy device 80x25
>[  425.330592] [IGT] kms_force_connector_basic: executing
>[  425.344576] [IGT] kms_force_connector_basic: exiting, ret=77
>[  425.369286] Console: switching to colour frame buffer device 200x56
>[  425.464769] Console: switching to colour dummy device 80x25
>[  425.464859] [IGT] kms_force_connector_basic: executing
>[  425.476451] [IGT] kms_force_connector_basic: exiting, ret=77
>[  425.502675] Console: switching to colour frame buffer device 200x56
>[  425.591830] Console: switching to colour dummy device 80x25
>[  425.591924] [IGT] kms_force_connector_basic: executing
>[  425.604519] [IGT] kms_force_connector_basic: exiting, ret=77
>[  425.636125] Console: switching to colour frame buffer device 200x56
>[  425.748465] Console: switching to colour dummy device 80x25
>[  425.748551] [IGT] kms_force_connector_basic: executing
>[  425.773366] [IGT] kms_force_connector_basic: exiting, ret=77
>[  425.786109] Console: switching to colour frame buffer device 200x56
>[  425.896771] Console: switching to colour dummy device 80x25
>[  425.896860] [IGT] kms_frontbuffer_tracking: executing
>[  425.910848] [drm:drm_mode_addfb2] [FB:61]
>[  425.910939] [drm:drm_mode_addfb2] [FB:78]
>[  425.911147] [drm:drm_mode_addfb2] [FB:80]
>[  425.912916] [drm:drm_mode_addfb2] [FB:81]
>[  425.921533] [drm:drm_mode_addfb2] [FB:83]
>[  425.921956] [IGT] kms_frontbuffer_tracking: starting subtest basic
>[  425.924549] [drm:drm_mode_addfb2] [FB:61]
>[  425.924632] [drm:drm_mode_addfb2] [FB:78]
>[  425.924713] [drm:drm_mode_addfb2] [FB:80]
>[  425.926480] [drm:drm_mode_addfb2] [FB:81]
>[  425.934616] [drm:drm_mode_addfb2] [FB:83]
>[  425.934639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  425.934687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  425.934756] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  425.934777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  425.934821] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  425.936449] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  425.936464] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  425.936485] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  425.936505] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  425.936522] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  425.936555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  425.936572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  425.936587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  425.936601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  425.936614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  425.936629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  425.936641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  425.936654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  425.936668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  425.936684] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  425.936699] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  425.936714] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  425.936728] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  425.936748] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  425.936768] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  425.936789] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  425.936806] [drm:intel_power_well_disable [i915]] disabling DC off
>[  425.936820] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  425.936832] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  425.937331] [drm:intel_power_well_disable [i915]] disabling always-on
>[  425.937795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  425.938279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  425.941792] [drm:drm_mode_addfb2] [FB:65]
>[  425.944409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  425.944420] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  425.944469] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  425.944485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  425.944503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  425.944522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  425.944537] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  425.944553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  425.944569] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  425.944584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  425.944599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  425.944613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  425.944627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  425.944630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  425.944643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  425.944645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  425.944659] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  425.944672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  425.944685] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  425.944697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  425.944710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  425.944725] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  425.944738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  425.944751] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  425.944763] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  425.944775] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  425.944791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  425.944808] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  425.944823] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  425.945124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  425.945144] [drm:intel_power_well_enable [i915]] enabling DC off
>[  425.945413] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  425.945444] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  425.945466] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  425.945525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  425.945544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  425.945560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  425.945574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  425.945589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  425.945603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  425.945617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  425.945630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  425.945645] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  425.945662] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  425.945679] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  425.945695] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  425.945713] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  425.945729] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  425.947047] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  425.947063] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  425.956509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.964970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.973442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.981903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.990362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  425.998822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.007283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.015741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.024201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.032661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.041123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.049581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.058055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.066513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.074970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.083442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.091901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.100360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.108140] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  426.168047] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  426.168065] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  426.168101] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  426.168924] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  426.169620] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  426.172208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  426.172227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  426.172245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  426.172264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  426.177644] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  426.177661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  426.182823] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  426.185305] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  426.185776] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  426.185831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  426.185847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  426.185869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  426.185918] [drm:intel_fbc_enable [i915]] reserved 11980800 bytes of contiguous stolen space for FBC, threshold: 1
>[  426.185942] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  426.202677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  426.202707] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  426.202750] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  426.236325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.236395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  426.236500] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  426.236532] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  426.236596] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  426.252990] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  426.253054] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  426.253092] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  426.253128] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  426.253159] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  426.253216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  426.253246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  426.253272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  426.253295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  426.253319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  426.253344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  426.253366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  426.253388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  426.253413] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  426.253441] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  426.253468] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  426.253493] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  426.253518] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  426.253557] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  426.253591] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  426.253627] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  426.253656] [drm:intel_power_well_disable [i915]] disabling DC off
>[  426.253680] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  426.253702] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  426.254695] [drm:intel_power_well_disable [i915]] disabling always-on
>[  426.254808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  426.255382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  426.261505] [drm:drm_mode_addfb2] [FB:65]
>[  426.270328] [drm:drm_mode_addfb2] [FB:84]
>[  426.277277] [drm:drm_mode_addfb2] [FB:85]
>[  426.284791] [drm:drm_mode_addfb2] [FB:86]
>[  426.394562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.394571] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  426.394620] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  426.394637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  426.394655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  426.394673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  426.394688] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  426.394704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  426.394719] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  426.394734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  426.394749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  426.394762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  426.394775] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  426.394778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  426.394791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  426.394794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  426.394807] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  426.394820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  426.394833] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  426.394845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  426.394857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  426.394872] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  426.394885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  426.394897] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  426.394909] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  426.394921] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  426.394936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  426.394953] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  426.394967] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  426.395256] [drm:intel_power_well_enable [i915]] enabling always-on
>[  426.395268] [drm:intel_power_well_enable [i915]] enabling DC off
>[  426.395529] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  426.395548] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  426.395561] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  426.395589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  426.395607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  426.395622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  426.395636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  426.395649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  426.395663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  426.395676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  426.395688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  426.395703] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  426.395719] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  426.395734] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  426.395748] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  426.395766] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  426.395780] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  426.397947] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  426.397964] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  426.407542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.416004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.424463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.432921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.441379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.449837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.458294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.466751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.475208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.483679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.492137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.500593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.509050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.517506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.525962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.534434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.542891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.551348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.559127] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  426.619344] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  426.619362] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  426.619403] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  426.620225] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  426.620895] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  426.623463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  426.623481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  426.623497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  426.623514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  426.628891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  426.628907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  426.634023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  426.636463] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  426.636904] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  426.637014] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  426.637030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  426.637051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  426.637096] [drm:intel_fbc_enable [i915]] reserved 11980800 bytes of contiguous stolen space for FBC, threshold: 1
>[  426.637118] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  426.653831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  426.653858] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  426.653898] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  426.687224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.687238] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  426.737289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.737312] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  426.787566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.787616] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  426.837738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.838021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  426.838869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  426.839034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  426.840320] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  426.855804] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  426.855910] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  426.856056] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  426.856481] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  426.857418] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  426.857718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  426.857842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  426.857946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  426.858046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  426.858375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  426.858537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  426.858680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  426.858824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  426.858974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  426.859257] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  426.859416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  426.859565] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  426.859710] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  426.859906] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  426.860243] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  426.860440] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  426.860611] [drm:intel_power_well_disable [i915]] disabling DC off
>[  426.860759] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  426.860895] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  426.861935] [drm:intel_power_well_disable [i915]] disabling always-on
>[  426.862785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  426.863677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  426.868286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  426.868356] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  426.868620] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  426.868734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  426.868854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  426.868979] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  426.869281] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  426.869455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  426.869616] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  426.869773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  426.869924] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  426.870092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  426.870711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  426.870747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  426.870886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  426.870925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  426.871073] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  426.871294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  426.871406] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  426.871540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  426.871671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  426.871832] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  426.871967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  426.873780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  426.873896] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  426.874000] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  426.874315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  426.874441] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  426.874549] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  426.876674] [drm:intel_power_well_enable [i915]] enabling always-on
>[  426.876749] [drm:intel_power_well_enable [i915]] enabling DC off
>[  426.877280] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  426.877695] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  426.877816] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  426.878041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  426.878307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  426.878442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  426.878575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  426.878698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  426.878821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  426.878939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  426.879058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  426.879270] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  426.879407] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  426.879535] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  426.879659] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  426.879801] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  426.879924] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  426.882316] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  426.882407] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  426.892942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.902321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.911498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.920604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.929533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.938468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.947371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.956271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.965158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.974058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.982755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.991334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  426.999869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.008394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.016883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.025373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.033835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.042293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.045018] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  427.105680] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  427.105699] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  427.105733] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  427.106565] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  427.107266] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  427.109848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  427.109868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  427.109886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  427.109904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  427.115290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  427.115307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  427.120431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  427.122902] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  427.123444] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  427.123490] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  427.123506] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  427.123529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  427.123671] [drm:intel_fbc_enable [i915]] reserved 11980800 bytes of contiguous stolen space for FBC, threshold: 1
>[  427.123688] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  427.140310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  427.140337] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  427.140378] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  427.212910] [drm:drm_mode_addfb2] [FB:65]
>[  427.757991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  427.758515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  427.758654] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  427.758883] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  427.774962] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  427.775139] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  427.775288] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  427.775423] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  427.775542] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  427.775751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  427.775871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  427.775974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  427.776270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  427.776389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  427.776523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  427.776637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  427.776774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  427.776907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  427.777086] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  427.777320] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  427.777450] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  427.777606] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  427.777801] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  427.777984] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  427.778308] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  427.778476] [drm:intel_power_well_disable [i915]] disabling DC off
>[  427.778621] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  427.778759] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  427.779801] [drm:intel_power_well_disable [i915]] disabling always-on
>[  427.782099] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  427.829260] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  427.829295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  427.829320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  427.829347] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  427.829369] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  427.829391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  427.829414] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  427.829434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  427.829455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  427.829474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  427.829493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  427.829498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  427.829516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  427.829520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  427.829539] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  427.829557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  427.829575] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  427.829593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  427.829611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  427.829633] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  427.829651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  427.829668] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  427.829686] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  427.829703] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  427.829725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  427.829749] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  427.829770] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  427.829848] [drm:intel_power_well_enable [i915]] enabling always-on
>[  427.829873] [drm:intel_power_well_enable [i915]] enabling DC off
>[  427.830180] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  427.830215] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  427.830239] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  427.830329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  427.830361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  427.830385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  427.830412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  427.830437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  427.830460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  427.830481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  427.830518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  427.830539] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  427.830564] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  427.830589] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  427.830614] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  427.830652] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  427.830684] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  427.832121] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  427.832140] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  427.841664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.850146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.858614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.867075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.875535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.883995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.892454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.900914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.909373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.917877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.926338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.934799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.943258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.951717] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.960177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.968635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.977095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.985553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.994012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  427.995047] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  428.055121] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  428.055142] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  428.055184] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  428.056030] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.056827] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.058590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  428.058610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  428.058628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  428.058647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  428.064557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  428.064574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  428.069718] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  428.072190] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  428.072681] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  428.072726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  428.072743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  428.072772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  428.072930] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  428.072960] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  428.089571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  428.089601] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  428.089647] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  428.106375] Console: switching to colour frame buffer device 200x56
>[  428.264341] Console: switching to colour dummy device 80x25
>[  428.264427] [IGT] kms_pipe_crc_basic: executing
>[  428.275551] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.275580] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.275593] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.275606] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.275628] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.277296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.277320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.279155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.279163] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.281164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.281187] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.283157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.283166] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.283170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.283191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.283214] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.283945] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.283971] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.284907] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.285726] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.287238] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.287258] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.287276] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.287294] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.288108] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.288815] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.289692] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.289696] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.289699] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.289701] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.289785] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.289788] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.289792] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.289795] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.289799] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.289801] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.289810] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.289813] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.289816] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.289818] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.289821] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.289824] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.289827] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.289829] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.289832] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.289835] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.289837] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.289840] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.289843] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.289846] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.289848] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.289851] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.289854] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.289856] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.289859] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.289862] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.289864] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.289867] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.289870] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.289872] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.289875] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.301212] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.301231] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.301242] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.301457] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.301475] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.303715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.303733] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.305993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.306026] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.308263] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.308284] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.310531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.310539] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.310544] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.310821] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.310845] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.311583] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.311609] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.312357] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.313174] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.314683] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.314701] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.314718] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.314734] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.315535] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.316241] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.317183] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.317187] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.317189] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.317191] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.317267] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.317269] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.317274] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.317276] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.317280] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.317281] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.317289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.317292] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.317295] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.317297] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.317300] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.317302] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.317305] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.317307] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.317309] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.317312] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.317314] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.317317] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.317319] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.317322] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.317324] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.317326] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.317329] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.317331] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.317334] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.317336] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.317339] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.317341] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.317343] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.317346] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.317348] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.317630] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-1
>[  428.317698] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  428.317774] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  428.339667] Console: switching to colour frame buffer device 200x56
>[  428.434653] Console: switching to colour dummy device 80x25
>[  428.434754] [IGT] kms_pipe_crc_basic: executing
>[  428.454148] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.454172] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.454184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.454194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.454212] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.456132] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.456150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.458139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.458144] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.460140] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.460158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.462144] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.462149] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.462152] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.462164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.462184] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.462896] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.462918] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.463595] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.464403] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.465898] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.465915] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.465930] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.465944] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.466728] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.467425] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.468271] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.468274] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.468276] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.468278] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.468347] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.468349] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.468353] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.468355] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.468358] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.468360] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.468367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.468369] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.468372] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.468374] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.468376] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.468378] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.468381] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.468383] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.468385] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.468387] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.468390] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.468392] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.468394] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.468396] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.468399] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.468401] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.468403] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.468405] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.468408] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.468410] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.468412] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.468414] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.468416] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.468418] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.468421] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.478228] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.478246] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.478257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.478458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.478474] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.480700] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.480718] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.482968] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.482998] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.485233] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.485254] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.487496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.487503] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.487508] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.487758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.487780] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.488512] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.488535] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.489216] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.490031] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.491530] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.491546] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.491561] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.491576] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.492364] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.493067] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.493914] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.493917] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.493920] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.493922] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.494064] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.494067] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.494074] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.494077] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.494083] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.494086] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.494097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.494101] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.494105] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.494109] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.494113] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.494117] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.494121] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.494125] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.494129] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.494133] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.494137] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.494141] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.494145] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.494149] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.494153] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.494157] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.494161] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.494165] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.494169] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.494172] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.494176] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.494180] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.494184] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.494188] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.494192] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.494599] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-3
>[  428.494683] [drm:display_crc_ctl_write [i915]] too many words, allowed <= 3
>[  428.494703] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  428.494840] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  428.506403] Console: switching to colour frame buffer device 200x56
>[  428.596086] Console: switching to colour dummy device 80x25
>[  428.596178] [IGT] kms_pipe_crc_basic: executing
>[  428.617348] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.617377] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.617391] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.617404] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.617426] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.619180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.619205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.621159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.621167] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.623159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.623184] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.625154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.625163] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.625168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.625189] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.625214] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.625945] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.625972] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.626728] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.627549] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.629063] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.629083] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.629101] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.629118] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.629913] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.630621] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.631539] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.631542] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.631545] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.631548] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.631632] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.631634] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.631639] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.631641] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.631646] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.631648] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.631656] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.631659] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.631662] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.631664] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.631667] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.631670] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.631673] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.631675] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.631678] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.631681] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.631683] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.631686] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.631689] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.631691] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.631694] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.631697] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.631699] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.631702] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.631705] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.631707] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.631710] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.631713] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.631715] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.631718] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.631720] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.643622] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.643644] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.643656] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.643900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.643920] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.646168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.646190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.648414] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.648420] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.650648] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.650669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.652897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.652903] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.652907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.653252] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.653273] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.654022] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.654057] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.654753] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.655576] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.657098] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.657118] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.657136] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.657153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.657948] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.658661] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.659546] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.659549] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.659551] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.659554] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.659635] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.659638] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.659643] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.659645] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.659649] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.659651] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.659659] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.659662] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.659665] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.659668] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.659671] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.659673] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.659676] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.659679] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.659682] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.659684] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.659687] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.659690] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.659692] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.659695] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.659698] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.659700] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.659703] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.659706] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.659708] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.659711] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.659714] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.659717] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.659719] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.659722] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.659724] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.660058] [IGT] kms_pipe_crc_basic: starting subtest bad-pipe
>[  428.660152] [drm:display_crc_ctl_write [i915]] unknown pipe D
>[  428.660323] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  428.690420] Console: switching to colour frame buffer device 200x56
>[  428.833125] Console: switching to colour dummy device 80x25
>[  428.833218] [IGT] kms_pipe_crc_basic: executing
>[  428.854329] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.854358] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.854372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.854385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.854408] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.856160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.856183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.858155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.858163] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.860160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.860183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.862166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.862174] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.862179] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.862199] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.862224] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.862960] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.863084] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 1 ms
>[  428.863796] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.864615] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.866174] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.866193] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.866211] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.866229] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.867029] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.867739] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.868642] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.868646] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.868649] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.868651] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.868735] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.868737] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.868742] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.868744] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.868748] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.868751] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.868759] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.868762] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.868765] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.868768] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.868771] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.868773] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.868776] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.868779] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.868782] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.868784] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.868787] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.868790] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.868792] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.868795] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.868798] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.868800] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.868803] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.868806] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.868808] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.868811] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.868814] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.868816] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.868819] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.868822] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.868824] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.880473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  428.880493] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  428.880504] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  428.880725] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  428.880743] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  428.882993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.883026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.885175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  428.885184] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  428.887421] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.887444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  428.889688] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  428.889713] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  428.889718] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  428.890081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  428.890114] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  428.890847] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.890873] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.891578] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.892398] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.893913] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  428.893933] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.893950] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.893967] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.894782] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  428.895493] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.896369] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  428.896372] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  428.896375] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.896377] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  428.896458] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.896461] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.896465] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  428.896467] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  428.896472] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  428.896474] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  428.896482] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  428.896485] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  428.896488] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.896490] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.896493] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.896496] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  428.896498] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.896501] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  428.896504] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.896506] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.896509] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  428.896512] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.896514] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.896517] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.896519] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  428.896522] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.896525] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  428.896527] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.896530] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.896532] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.896535] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.896538] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  428.896540] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.896543] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.896545] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  428.896834] [IGT] kms_pipe_crc_basic: starting subtest bad-source
>[  428.897026] [drm:intel_crtc_set_crc_source [i915]] unknown source foo
>[  428.897108] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  428.923253] Console: switching to colour frame buffer device 200x56
>[  429.016442] Console: switching to colour dummy device 80x25
>[  429.016534] [IGT] kms_pipe_crc_basic: executing
>[  429.036324] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  429.036353] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  429.036367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  429.036379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  429.036402] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  429.038155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  429.038179] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  429.040152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  429.040161] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  429.042156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  429.042180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  429.044165] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  429.044173] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  429.044178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  429.044198] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  429.044224] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  429.044955] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  429.045009] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 1 ms
>[  429.045788] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  429.046607] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  429.048123] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  429.048144] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  429.048162] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  429.048179] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  429.048971] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  429.049700] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  429.050607] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  429.050611] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  429.050614] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  429.050616] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  429.050701] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  429.050703] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  429.050708] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  429.050710] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  429.050714] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  429.050717] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  429.050725] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  429.050728] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  429.050731] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  429.050734] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  429.050737] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  429.050739] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  429.050742] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  429.050745] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  429.050747] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  429.050750] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  429.050753] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  429.050756] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  429.050758] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  429.050761] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  429.050764] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  429.050766] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  429.050769] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  429.050772] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  429.050774] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  429.050777] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  429.050780] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  429.050782] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  429.050785] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  429.050787] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  429.050790] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  429.062202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  429.062222] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  429.062233] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  429.062452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  429.062471] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  429.064710] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  429.064730] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  429.066964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  429.066978] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  429.069214] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  429.069233] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  429.071457] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  429.071462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  429.071465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  429.071705] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  429.071725] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  429.072459] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  429.072483] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  429.073215] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  429.074097] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  429.075600] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  429.075618] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  429.075634] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  429.075649] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  429.076441] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  429.077144] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  429.078020] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  429.078023] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  429.078025] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  429.078027] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  429.078138] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  429.078140] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  429.078144] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  429.078146] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  429.078150] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  429.078152] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  429.078159] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  429.078162] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  429.078165] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  429.078167] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  429.078169] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  429.078172] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  429.078174] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  429.078177] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  429.078179] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  429.078181] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  429.078184] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  429.078186] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  429.078189] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  429.078191] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  429.078193] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  429.078196] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  429.078198] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  429.078200] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  429.078203] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  429.078205] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  429.078207] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  429.078210] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  429.078212] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  429.078214] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  429.078217] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  429.078459] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-A
>[  429.079053] [drm:drm_mode_addfb2] [FB:65]
>[  429.083137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  429.083148] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  429.106532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  429.106618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  429.173729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.173997] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  429.174320] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  429.174563] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  429.192231] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  429.192316] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  429.192434] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  429.192541] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  429.192641] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  429.192808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  429.192905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  429.192990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  429.193194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  429.193282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  429.193380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  429.193462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  429.193545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  429.193634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  429.193733] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  429.193832] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  429.193952] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  429.194188] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  429.194368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.194543] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.194721] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  429.194835] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.194916] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  429.194987] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  429.195572] [drm:intel_power_well_disable [i915]] disabling always-on
>[  429.199574] [drm:drm_mode_addfb2] [FB:61]
>[  429.219875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  429.219922] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  429.220324] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  429.220422] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  429.220524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  429.220629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  429.220716] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  429.220811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.220901] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  429.220999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  429.221194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  429.221298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  429.221393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.221423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  429.221514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.221541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  429.221634] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  429.221728] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  429.221821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  429.221935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.222049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.222242] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  429.222336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.222431] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  429.222549] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  429.222625] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  429.222712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.222811] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  429.222898] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  429.223928] [drm:intel_power_well_enable [i915]] enabling always-on
>[  429.224001] [drm:intel_power_well_enable [i915]] enabling DC off
>[  429.224454] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  429.224934] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  429.225029] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  429.225329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  429.225431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  429.225515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  429.225599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  429.225680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  429.225757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  429.225833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  429.225908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  429.226004] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  429.226211] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  429.226325] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  429.226434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  429.226559] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  429.226690] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  429.229000] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  429.229142] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  429.239107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.247726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.256243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.264725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.273189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.281648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.290108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.298566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.307026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.315483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.323942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.332401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.340860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.349319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.357777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.366236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.374693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.383149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.390733] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  429.451236] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  429.451259] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  429.451314] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  429.452327] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  429.454914] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  429.456252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  429.456269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  429.456285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  429.456302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  429.461434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  429.461450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  429.466586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  429.469039] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258821bf8
>[  429.469512] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  429.469543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  429.469559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  429.469582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  429.469629] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  429.469652] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  429.486354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  429.486381] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  429.486422] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  429.570346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.570606] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  429.570713] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  429.570934] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  429.588316] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  429.588401] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  429.588517] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  429.588624] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  429.588721] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  429.588885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  429.588982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  429.589265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  429.589372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  429.589488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  429.589617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  429.589712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  429.589816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  429.589921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  429.590070] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  429.590438] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  429.590558] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  429.590675] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  429.590832] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.590980] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.591233] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  429.591370] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.591487] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  429.591595] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  429.592603] [drm:intel_power_well_disable [i915]] disabling always-on
>[  433.700254] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  438.763793] [drm] GPU HANG: ecode 9:0:0xe757fffe, in kms_pipe_crc_ba [8304], reason: Hang on render ring, action: reset
>[  438.763880] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  438.763915] drm/i915: Resetting chip after gpu hang
>[  438.765192] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8304]/0 marked guilty (score 10) banned? no
>[  438.765208] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x2f4d8a
>[  438.765524] [drm] RC6 on
>[  438.782726] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  438.782813] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x2f4d8a, 0x0]
>[  438.782923] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  438.783346] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  438.783647] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  438.783835] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  438.783989] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  438.784155] [drm] GuC firmware load skipped
>[  438.790476] [drm:drm_mode_addfb2] [FB:61]
>[  438.809336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  438.809382] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  438.809614] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  438.809710] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  438.809809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  438.809913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  438.809998] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  438.810244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  438.810360] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  438.810490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  438.810617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  438.810744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  438.810861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.810895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  438.811015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.811108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  438.811230] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  438.811352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  438.811465] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  438.811577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.811690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  438.811826] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  438.811937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.812051] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  438.812254] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  438.812344] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  438.812474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  438.812613] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  438.812740] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  438.813717] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.813759] [drm:intel_power_well_enable [i915]] enabling DC off
>[  438.814144] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  438.814595] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  438.814680] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  438.814796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  438.814877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  438.814949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  438.815023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  438.815153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  438.815229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  438.815297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  438.815367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  438.815440] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  438.815519] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  438.815593] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  438.815666] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  438.815748] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  438.815820] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  438.818053] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  438.818091] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  438.827722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.836236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.844725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.853186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.861644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.870104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.878563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.887032] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.895493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.903954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.912437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.920896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.929370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.937829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.946287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.954746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.963203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.971660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.980120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.981158] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  439.041895] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  439.041914] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  439.041951] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  439.042794] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  439.043516] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  439.046096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.046115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.046133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.046152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.051530] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.051547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.056668] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.059148] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  439.059619] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  439.059677] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  439.059693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  439.059715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  439.059756] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  439.059772] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  439.076466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  439.076492] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  439.076533] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.160172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.160320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  439.160381] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  439.160476] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  439.177155] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  439.177222] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  439.177315] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  439.177399] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  439.177476] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  439.177611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  439.177687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  439.177752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  439.177813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  439.177872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  439.177968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  439.178244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  439.178356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  439.178467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  439.178605] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  439.178739] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.178865] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  439.178988] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  439.179227] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  439.179381] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  439.179541] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  439.179680] [drm:intel_power_well_disable [i915]] disabling DC off
>[  439.179801] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  439.179893] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  439.180884] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.184975] [drm:drm_mode_addfb2] [FB:61]
>[  439.206312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  439.206362] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  439.206607] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  439.206705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  439.206807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  439.206912] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  439.206999] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  439.207223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  439.207338] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  439.207447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  439.207550] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  439.207649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  439.207748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.207779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  439.207874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.207904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  439.208017] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  439.208179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  439.208275] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  439.208371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.208484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.208620] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  439.208732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.208849] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  439.208962] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  439.209157] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  439.209273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.209397] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  439.209503] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  439.211277] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.211351] [drm:intel_power_well_enable [i915]] enabling DC off
>[  439.211680] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  439.211782] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  439.211887] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  439.212193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  439.212327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  439.212451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  439.212575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  439.212697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  439.212818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  439.212937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  439.213053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  439.213251] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  439.213378] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.213512] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  439.213638] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  439.213790] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  439.213921] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  439.216436] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  439.216530] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  439.226974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.236016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.244980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.253968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.262949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.272197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.281159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.290097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.298922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.308100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.316824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.325435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.333992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.342539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.351034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.359511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.367977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.377226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.378059] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  439.438824] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  439.438844] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  439.438900] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  439.439739] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  439.440439] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  439.442206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.442226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.442244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.442263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.448142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.448161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.453284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.455770] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  439.456314] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  439.456344] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  439.456363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  439.456387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  439.456433] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  439.456451] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  439.473144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  439.473173] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  439.473219] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.556995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.557349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  439.557441] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  439.557590] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  439.574186] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  439.574277] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  439.574401] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  439.574514] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  439.574643] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  439.574901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  439.575022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  439.575389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  439.575519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  439.575661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  439.575787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  439.575881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  439.575994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  439.576180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  439.576312] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  439.576439] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.576585] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  439.576730] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  439.576953] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  439.577301] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  439.577494] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  439.577665] [drm:intel_power_well_disable [i915]] disabling DC off
>[  439.577814] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  439.577949] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  439.578571] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.581512] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  439.614869] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  439.614966] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  439.615126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  439.615228] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  439.615309] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  439.615396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  439.615484] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  439.615565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  439.615645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  439.615720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  439.615793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.615811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  439.615882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.615896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  439.615970] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  439.616157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  439.616234] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  439.616304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.616372] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.616458] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  439.616529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.616599] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  439.616667] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  439.616733] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  439.616817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.616912] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  439.616994] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  439.617331] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.617397] [drm:intel_power_well_enable [i915]] enabling DC off
>[  439.617720] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  439.617825] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  439.617928] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  439.618201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  439.618297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  439.618375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  439.618450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  439.618523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  439.618594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  439.618666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  439.618737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  439.618817] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  439.618904] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.618987] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  439.619122] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  439.619222] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  439.619303] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  439.621296] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  439.621381] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  439.631782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.640719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.649646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.658618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.667462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.676313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.685145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.693976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.702900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.711820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.720666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.729457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.738097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.746668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.755207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.763719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.772211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.780687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.783433] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  439.844293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  439.844311] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  439.844338] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  439.845165] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  439.845902] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  439.848496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.848514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.848531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.848549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.853944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.853959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.859103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.861588] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258825d28
>[  439.862140] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  439.862213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  439.862229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  439.862252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  439.862386] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  439.862403] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  439.879029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  439.879055] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  439.879098] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  439.879249] Console: switching to colour frame buffer device 200x56
>[  440.026874] Console: switching to colour dummy device 80x25
>[  440.027013] [IGT] kms_pipe_crc_basic: executing
>[  440.047202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  440.047229] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  440.047242] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  440.047265] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  440.047286] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  440.049151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  440.049171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  440.051147] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  440.051153] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  440.053142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  440.053163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  440.055147] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  440.055153] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  440.055157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  440.055170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  440.055193] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  440.055915] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  440.055939] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  440.056647] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  440.057501] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  440.059022] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  440.059041] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  440.059059] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  440.059075] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  440.059868] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  440.060580] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  440.061456] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  440.061459] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  440.061462] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  440.061464] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  440.061546] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.061549] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.061553] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  440.061556] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  440.061560] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.061562] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.061570] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  440.061573] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  440.061575] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.061578] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.061581] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.061583] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.061586] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  440.061589] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  440.061591] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.061594] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.061596] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  440.061599] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.061602] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.061604] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  440.061607] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  440.061609] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  440.061612] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  440.061615] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  440.061617] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  440.061620] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.061622] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.061625] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  440.061627] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.061630] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.061632] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  440.073002] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  440.073024] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  440.073035] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  440.073279] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  440.073298] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  440.075526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  440.075547] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  440.077771] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  440.077777] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  440.080048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  440.080070] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  440.082301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  440.082310] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  440.082315] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  440.082607] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  440.082632] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  440.083443] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  440.083469] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  440.084181] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  440.085022] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  440.086540] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  440.086560] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  440.086578] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  440.086595] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  440.087393] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  440.088105] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  440.089015] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  440.089022] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  440.089025] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  440.089028] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  440.089151] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.089155] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.089163] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  440.089166] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  440.089173] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.089176] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.089184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  440.089187] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  440.089190] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.089193] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.089195] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.089198] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.089201] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  440.089203] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  440.089206] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.089209] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.089211] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  440.089214] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.089216] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.089219] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  440.089222] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  440.089224] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  440.089227] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  440.089229] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  440.089232] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  440.089234] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.089237] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.089240] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  440.089242] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.089245] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.089247] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  440.089543] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-B
>[  440.090210] [drm:drm_mode_addfb2] [FB:61]
>[  440.094739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  440.094789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.094861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  440.094885] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  440.094926] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  440.097403] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  440.097421] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  440.097445] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  440.097467] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  440.097487] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  440.097525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.097544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  440.097561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  440.097577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  440.097593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  440.097610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  440.097625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  440.097640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  440.097657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  440.097676] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  440.097693] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.097710] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  440.097726] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  440.097750] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  440.097773] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  440.097796] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  440.097816] [drm:intel_power_well_disable [i915]] disabling DC off
>[  440.097832] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  440.097846] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  440.098302] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.098435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  440.098450] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  440.098517] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  440.098543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  440.098570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  440.098598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  440.098622] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  440.098647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  440.098672] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  440.098697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  440.098721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  440.098744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  440.098766] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.098772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  440.098793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.098798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  440.098819] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  440.098842] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  440.098864] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  440.098887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.098908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.098933] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  440.098956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.098979] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  440.099019] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  440.099043] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  440.099070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.099098] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  440.099123] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  440.099429] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.099451] [drm:intel_power_well_enable [i915]] enabling DC off
>[  440.099725] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  440.099755] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  440.099779] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  440.099855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.099882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  440.099906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  440.099930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  440.099952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  440.099976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  440.100017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  440.100043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  440.100069] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  440.100096] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.100122] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  440.100147] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  440.100175] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  440.100200] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  440.102330] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  440.102348] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  440.111888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.120368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.128844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.137315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.145777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.154237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.162707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.171167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.179626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.188083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.196545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.205004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.213460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.221920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.230380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.238838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.247297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.255756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.264215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.265276] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  440.324458] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  440.324478] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  440.324518] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  440.325349] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  440.326067] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  440.328641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  440.328661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  440.328679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  440.328698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  440.334136] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  440.334153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  440.339277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  440.341724] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  440.342262] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  440.342336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  440.342352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  440.342375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  440.359116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  440.359140] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  440.359178] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.375755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  440.442963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.443381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  440.443491] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  440.443660] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  440.459744] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  440.459828] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  440.459954] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  440.460243] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  440.460528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.460683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  440.460816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  440.460904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  440.460988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  440.461215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  440.461312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  440.461411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  440.461543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  440.461690] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  440.461829] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.461963] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  440.462162] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  440.462348] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  440.462519] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  440.462688] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  440.462778] [drm:intel_power_well_disable [i915]] disabling DC off
>[  440.462860] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  440.462931] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  440.463952] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.467545] [drm:drm_mode_addfb2] [FB:61]
>[  440.493710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  440.493754] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  440.493990] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  440.494246] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  440.494369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  440.494517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  440.494618] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  440.494741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  440.494847] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  440.494961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  440.495153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  440.495266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  440.495361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.495393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  440.495494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.495521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  440.495629] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  440.495742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  440.495836] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  440.495947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.496040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.496230] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  440.496326] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.496430] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  440.496520] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  440.496626] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  440.496751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.496880] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  440.496984] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  440.498480] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.498552] [drm:intel_power_well_enable [i915]] enabling DC off
>[  440.498875] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  440.498971] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  440.499170] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  440.499370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.499510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  440.499610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  440.499719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  440.499813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  440.499919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  440.500014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  440.500197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  440.500301] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  440.500434] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.500560] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  440.500682] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  440.500817] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  440.500919] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  440.501241] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  440.501353] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  440.511444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.520277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.529084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.537882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.546688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.555498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.564296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.573098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.581893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.590587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.599184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.607747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.616262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.624756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.633233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.641697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.650156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.658614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.662822] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  440.723484] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  440.723506] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  440.723540] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  440.724383] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  440.726156] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  440.728015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  440.728032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  440.728049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  440.728065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  440.733191] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  440.733209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  440.738333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  440.740427] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  440.740902] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  440.740937] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  440.740953] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  440.740976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  440.757720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  440.757746] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  440.757787] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.841523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.841787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  440.841899] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  440.842213] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  440.859194] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  440.859280] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  440.859407] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  440.859511] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  440.859678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.859776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  440.859862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  440.859945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  440.860025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  440.860201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  440.860278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  440.860353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  440.860438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  440.860530] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  440.860620] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  440.860706] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  440.860789] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  440.860904] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  440.861008] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  440.861173] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  440.861260] [drm:intel_power_well_disable [i915]] disabling DC off
>[  440.861339] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  440.861409] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  440.861885] [drm:intel_power_well_disable [i915]] disabling always-on
>[  444.772260] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  450.732150] [drm] GPU HANG: ecode 9:0:0xe757fffe, in kms_pipe_crc_ba [8307], reason: Hang on render ring, action: reset
>[  450.732254] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  450.732306] drm/i915: Resetting chip after gpu hang
>[  450.732683] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8307]/0 marked guilty (score 10) banned? no
>[  450.732706] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x2f4dab
>[  450.733160] [drm] RC6 on
>[  450.750116] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  450.750140] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x2f4dab, 0x0]
>[  450.750172] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  450.750233] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  450.750293] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  450.750351] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  450.750392] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  450.750399] [drm] GuC firmware load skipped
>[  450.750880] [drm:drm_mode_addfb2] [FB:61]
>[  450.756185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  450.756199] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  450.756265] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  450.756290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  450.756317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  450.756345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  450.756367] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  450.756391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  450.756414] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  450.756437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  450.756458] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  450.756478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  450.756498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  450.756503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  450.756522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  450.756526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  450.756546] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  450.756565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  450.756584] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  450.756602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  450.756620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  450.756643] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  450.756662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  450.756681] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  450.756700] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  450.756718] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  450.756741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  450.756767] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  450.756789] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  450.757187] [drm:intel_power_well_enable [i915]] enabling always-on
>[  450.757218] [drm:intel_power_well_enable [i915]] enabling DC off
>[  450.757504] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  450.757544] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  450.757576] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  450.757632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  450.757669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  450.757701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  450.757733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  450.757764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  450.757795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  450.757827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  450.757858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  450.757892] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  450.757965] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  450.758016] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  450.758046] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  450.758084] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  450.758117] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  450.760089] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  450.760113] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  450.769640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.778152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.786632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.795094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.803554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.812014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.820473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.828932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.837395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.845856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.854315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.862775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.871234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.879693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.888155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.896617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.905076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.913534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.921991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  450.923048] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  450.983688] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  450.983706] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  450.983738] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  450.984567] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  450.985251] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  450.987826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  450.987845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  450.987861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  450.987878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  450.993260] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  450.993276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  450.998392] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.000772] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  451.001283] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  451.001347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  451.001362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  451.001383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  451.018141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  451.018165] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  451.018203] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.101794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.101926] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  451.101977] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  451.102215] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  451.119230] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  451.119297] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  451.119396] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  451.119477] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  451.119615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  451.119692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  451.119756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  451.119819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  451.119879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  451.119944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  451.120001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  451.120226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  451.120311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  451.120410] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  451.120506] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.120600] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  451.120691] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  451.120823] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  451.120938] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  451.121139] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  451.121240] [drm:intel_power_well_disable [i915]] disabling DC off
>[  451.121334] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  451.121418] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  451.121910] [drm:intel_power_well_disable [i915]] disabling always-on
>[  451.124758] [drm:drm_mode_addfb2] [FB:61]
>[  451.146112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  451.146162] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  451.146407] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  451.146503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  451.146604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  451.146712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  451.146798] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  451.146889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  451.146980] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  451.147213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  451.147327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  451.147424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  451.147518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  451.147550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  451.147641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  451.147669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  451.147764] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  451.147859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  451.147974] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  451.148146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.148244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  451.148376] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  451.148456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  451.148530] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  451.148605] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  451.148677] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  451.148768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.148869] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  451.148955] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  451.150694] [drm:intel_power_well_enable [i915]] enabling always-on
>[  451.150771] [drm:intel_power_well_enable [i915]] enabling DC off
>[  451.151335] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  451.151697] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  451.151771] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  451.151977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  451.152190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  451.152294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  451.152395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  451.152516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  451.152620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  451.152699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  451.152773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  451.152859] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  451.152954] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.153130] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  451.153242] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  451.153370] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  451.153497] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  451.155846] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  451.155954] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  451.166268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.175220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.184146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.193109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.202012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.210969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.219949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.229378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.238297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.247201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.256013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.264705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.273278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.281815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.290320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.298804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.307289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.315750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.318477] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  451.379248] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  451.379268] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  451.379314] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  451.380147] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  451.380843] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  451.383450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  451.383472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  451.383491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.383512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  451.388943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  451.388963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  451.394238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.396711] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258821bf8
>[  451.397332] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  451.397402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  451.397420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  451.397444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  451.414189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  451.414219] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  451.414265] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.498052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.498389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  451.498479] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  451.498624] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  451.515335] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  451.515443] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  451.515600] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  451.515727] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  451.515941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  451.516276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  451.516422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  451.516569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  451.516713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  451.516866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  451.517009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  451.517206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  451.517359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  451.517533] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  451.517688] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.517838] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  451.517986] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  451.518314] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  451.518504] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  451.518697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  451.518867] [drm:intel_power_well_disable [i915]] disabling DC off
>[  451.519011] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  451.519234] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  451.519783] [drm:intel_power_well_disable [i915]] disabling always-on
>[  451.524905] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  451.558963] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  451.559118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  451.559218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  451.559322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  451.559405] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  451.559494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  451.559583] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  451.559664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  451.559743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  451.559818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  451.559889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  451.559907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  451.559979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  451.560072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  451.560148] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  451.560220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  451.560289] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  451.560357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.560425] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  451.560510] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  451.560582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  451.560652] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  451.560721] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  451.560788] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  451.560873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.560969] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  451.561100] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  451.561394] [drm:intel_power_well_enable [i915]] enabling always-on
>[  451.561461] [drm:intel_power_well_enable [i915]] enabling DC off
>[  451.561785] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  451.561891] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  451.561985] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  451.562243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  451.562338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  451.562418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  451.562493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  451.562565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  451.562635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  451.562705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  451.562773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  451.562851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  451.562939] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.563021] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  451.563155] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  451.563254] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  451.563335] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  451.565300] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  451.565387] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  451.575687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.584644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.593680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.602620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.611611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.620550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.629480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.638484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.647422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.656414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.665275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.673924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.682502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.691038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.699546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.708035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.716508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.724973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.726045] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  451.786952] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  451.786970] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  451.787029] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  451.787699] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  451.788509] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  451.789239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  451.789257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  451.789274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.789292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  451.795054] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  451.795070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  451.800201] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.802681] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  451.803231] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  451.803260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  451.803275] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  451.803298] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  451.803340] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  451.803357] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  451.820053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  451.820079] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  451.820123] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  451.820253] Console: switching to colour frame buffer device 200x56
>[  451.975901] Console: switching to colour dummy device 80x25
>[  451.976123] [IGT] kms_pipe_crc_basic: executing
>[  451.997325] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  451.997354] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  451.997367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  451.997380] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  451.997403] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  451.999170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  451.999194] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  452.001152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  452.001160] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  452.003152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  452.003176] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  452.005168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  452.005176] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  452.005182] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  452.005202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  452.005228] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  452.005958] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  452.006224] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 1 ms
>[  452.006926] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  452.007747] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  452.009263] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  452.009283] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  452.009302] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  452.009320] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  452.010156] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  452.010864] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  452.011744] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  452.011748] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  452.011751] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  452.011753] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  452.011837] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  452.011839] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  452.011844] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  452.011846] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  452.011851] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  452.011853] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  452.011861] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  452.011864] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  452.011867] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  452.011870] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  452.011873] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  452.011875] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  452.011878] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  452.011881] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  452.011884] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  452.011886] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  452.011889] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  452.011892] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  452.011894] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  452.011897] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  452.011900] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  452.011902] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  452.011905] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  452.011908] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  452.011910] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  452.011913] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  452.011916] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  452.011918] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  452.011921] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  452.011923] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  452.011926] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  452.024102] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  452.024124] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  452.024136] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  452.024373] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  452.024393] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  452.026614] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  452.026636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  452.028862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  452.028867] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  452.031092] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  452.031113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  452.033337] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  452.033343] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  452.033347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  452.033624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  452.033647] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  452.034523] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  452.034550] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  452.035254] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  452.036076] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  452.037594] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  452.037614] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  452.037632] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  452.037650] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  452.038568] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  452.039281] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  452.040195] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  452.040198] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  452.040201] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  452.040203] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  452.040286] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  452.040288] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  452.040293] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  452.040295] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  452.040299] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  452.040301] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  452.040309] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  452.040312] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  452.040315] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  452.040318] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  452.040321] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  452.040324] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  452.040327] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  452.040329] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  452.040332] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  452.040335] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  452.040338] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  452.040340] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  452.040343] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  452.040346] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  452.040348] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  452.040351] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  452.040354] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  452.040356] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  452.040359] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  452.040362] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  452.040364] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  452.040367] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  452.040370] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  452.040372] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  452.040375] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  452.040654] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-C
>[  452.041564] [drm:drm_mode_addfb2] [FB:61]
>[  452.046058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  452.046109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.046183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  452.046207] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  452.046249] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  452.054969] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  452.055005] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  452.055031] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  452.055054] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  452.055075] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  452.055113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  452.055133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  452.055150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  452.055166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  452.055182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  452.055199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  452.055215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  452.055230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  452.055248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  452.055266] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  452.055284] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.055302] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  452.055318] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  452.055342] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  452.055366] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  452.055390] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  452.055410] [drm:intel_power_well_disable [i915]] disabling DC off
>[  452.055427] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  452.055441] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  452.055854] [drm:intel_power_well_disable [i915]] disabling always-on
>[  452.055937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  452.056427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  452.056442] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  452.056511] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  452.056537] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  452.056565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  452.056594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  452.056619] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  452.056646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  452.056672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  452.056697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  452.056722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  452.056746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  452.056770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  452.056776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  452.056797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  452.056802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  452.056825] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  452.056848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  452.056871] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  452.056893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  452.056916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  452.056942] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  452.056965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  452.057006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  452.057026] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  452.057045] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  452.057067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.057092] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  452.057113] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  452.057454] [drm:intel_power_well_enable [i915]] enabling always-on
>[  452.057477] [drm:intel_power_well_enable [i915]] enabling DC off
>[  452.057501] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  452.057914] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  452.057939] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  452.058033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  452.058064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  452.058086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  452.058111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  452.058136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  452.058160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  452.058184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  452.058209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  452.058235] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  452.058263] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.058290] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  452.058315] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  452.058344] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  452.058370] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  452.060500] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  452.060519] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  452.070070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.078550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.087029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.095507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.103984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.112472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.120934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.129393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.137851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.146308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.154778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.163237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.171694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.180151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.188607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.197065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.205520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.213978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.222449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.223484] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  452.282638] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  452.282658] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  452.282698] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  452.283529] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  452.284248] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  452.286825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  452.286844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  452.286862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  452.286880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  452.292265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  452.292282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  452.297405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  452.299846] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  452.300397] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  452.300464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  452.300481] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  452.300503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  452.317247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  452.317275] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  452.317316] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.401200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.401466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  452.401577] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  452.401749] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  452.417894] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  452.417979] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  452.418279] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  452.418438] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  452.418707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  452.418810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  452.418895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  452.418977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  452.419153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  452.419270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  452.419365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  452.419460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  452.419564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  452.419712] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  452.419850] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.419983] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  452.420203] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  452.420372] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  452.420548] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  452.420724] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  452.420847] [drm:intel_power_well_disable [i915]] disabling DC off
>[  452.420928] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  452.420999] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  452.421641] [drm:intel_power_well_disable [i915]] disabling always-on
>[  452.425143] [drm:drm_mode_addfb2] [FB:61]
>[  452.450519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  452.450566] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  452.450804] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  452.450899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  452.450996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  452.451221] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  452.451358] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  452.451471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  452.451597] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  452.451702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  452.451830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  452.451930] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  452.452045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  452.452141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  452.452237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  452.452260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  452.452369] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  452.452462] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  452.452564] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  452.452653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  452.452753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  452.452857] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  452.452958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  452.453138] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  452.453231] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  452.453337] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  452.453464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.453595] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  452.453700] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  452.455183] [drm:intel_power_well_enable [i915]] enabling always-on
>[  452.455259] [drm:intel_power_well_enable [i915]] enabling DC off
>[  452.455583] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  452.455678] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  452.455784] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  452.455959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  452.456188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  452.456293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  452.456395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  452.456494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  452.456611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  452.456712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  452.456826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  452.456940] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  452.457184] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.457313] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  452.457437] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  452.457574] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  452.457696] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  452.459514] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  452.459601] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  452.469899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.479155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.488119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.496978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.505853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.514654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.523451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.532307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.541113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.549915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.558944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.567835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.576428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.584971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.593509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.602001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.610473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.618937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.619775] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  452.680441] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  452.680461] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  452.680509] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  452.681340] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  452.682065] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  452.684642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  452.684662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  452.684679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  452.684698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  452.690142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  452.690159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  452.695283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  452.697726] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826678
>[  452.698262] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  452.698291] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  452.698307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  452.698330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  452.715072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  452.715100] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  452.715141] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.798921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.799475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  452.799636] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  452.799877] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  452.816238] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  452.816324] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  452.816450] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  452.816556] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  452.816724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  452.816822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  452.816907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  452.816987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  452.817272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  452.817406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  452.817524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  452.817638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  452.817765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  452.817901] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  452.818043] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  452.818264] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  452.818389] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  452.818555] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  452.818712] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  452.818870] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  452.819005] [drm:intel_power_well_disable [i915]] disabling DC off
>[  452.819206] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  452.819320] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  452.819836] [drm:intel_power_well_disable [i915]] disabling always-on
>[  456.740591] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  460.716010] [drm] GPU HANG: ecode 9:0:0xe757fffe, in kms_pipe_crc_ba [8311], reason: Hang on render ring, action: reset
>[  460.716100] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  460.716149] drm/i915: Resetting chip after gpu hang
>[  460.717556] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8311]/0 marked guilty (score 10) banned? no
>[  460.717572] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x2f4dcc
>[  460.717896] [drm] RC6 on
>[  460.733608] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  460.733630] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x2f4dcc, 0x0]
>[  460.733659] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  460.733714] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  460.733768] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  460.733821] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  460.733858] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  460.733865] [drm] GuC firmware load skipped
>[  460.734534] [drm:drm_mode_addfb2] [FB:61]
>[  460.739956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  460.740005] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  460.740087] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  460.740113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  460.740143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  460.740175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  460.740199] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  460.740227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  460.740252] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  460.740279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  460.740303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  460.740328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  460.740350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  460.740356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  460.740378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  460.740384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  460.740409] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  460.740430] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  460.740454] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  460.740474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  460.740498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  460.740522] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  460.740548] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  460.740569] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  460.740593] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  460.740614] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  460.740641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  460.740672] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  460.740695] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  460.741064] [drm:intel_power_well_enable [i915]] enabling always-on
>[  460.741082] [drm:intel_power_well_enable [i915]] enabling DC off
>[  460.741355] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  460.741379] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  460.741395] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  460.741443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  460.741467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  460.741486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  460.741505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  460.741523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  460.741541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  460.741558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  460.741575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  460.741594] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  460.741615] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  460.741635] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  460.741654] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  460.741678] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  460.741698] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  460.743076] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  460.743096] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  460.752551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.761048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.769531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.777993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.786451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.794909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.803368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.811826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.820284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.828742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.837199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.845657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.854117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.862575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.871034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.879491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.887948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.896406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.904865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  460.905904] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  460.966675] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  460.966692] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  460.966730] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  460.967556] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  460.968255] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  460.970820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  460.970838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  460.970854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  460.970875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  460.976252] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  460.976268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  460.981383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  460.983832] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  460.984342] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  460.984390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  460.984405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  460.984426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  461.001182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  461.001207] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  461.001245] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.084834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  461.084968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  461.085142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  461.085263] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  461.102154] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  461.102222] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  461.102320] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  461.102401] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  461.102538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  461.102616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  461.102680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  461.102741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  461.102801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  461.102867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  461.102925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  461.102982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  461.103149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  461.103239] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  461.103339] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.103436] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  461.103527] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  461.103675] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  461.103790] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  461.103912] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  461.104014] [drm:intel_power_well_disable [i915]] disabling DC off
>[  461.104155] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  461.104240] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  461.104732] [drm:intel_power_well_disable [i915]] disabling always-on
>[  461.108682] [drm:drm_mode_addfb2] [FB:61]
>[  461.130819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  461.130870] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  461.131313] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  461.131456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  461.131606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  461.131752] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  461.131880] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  461.132021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  461.132212] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  461.132348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  461.132457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  461.132581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  461.132701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.132733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  461.132841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.132876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  461.132992] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  461.133197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  461.133299] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  461.133413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.133526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.133660] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.133779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.133901] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  461.134018] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  461.134181] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  461.134296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  461.134435] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  461.134560] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  461.136339] [drm:intel_power_well_enable [i915]] enabling always-on
>[  461.136414] [drm:intel_power_well_enable [i915]] enabling DC off
>[  461.136742] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  461.136842] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  461.136915] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  461.137330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  461.137472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  461.137578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  461.137692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  461.137788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  461.137899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  461.137995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  461.138196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  461.138324] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  461.138456] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.138586] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  461.138720] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  461.138860] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  461.138963] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  461.141427] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  461.141518] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  461.151674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.160604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.169525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.178435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.187335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.196240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.205141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.214121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.223017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.231986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.240954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.249784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.258407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.266985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.275538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.284036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.292516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.300997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.303727] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  461.364600] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  461.364620] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  461.364667] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  461.365501] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  461.366198] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  461.367959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  461.367979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  461.368026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  461.368050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  461.373903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  461.373922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  461.379071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  461.381559] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  461.382112] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  461.382184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  461.382202] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  461.382227] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  461.399022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  461.399052] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  461.399098] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.482679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  461.482846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  461.482912] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  461.483183] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  461.500162] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  461.500253] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  461.500386] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  461.500493] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  461.500676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  461.500778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  461.500865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  461.500947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  461.501028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  461.501353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  461.501451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  461.501568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  461.501673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  461.501805] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  461.501934] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.502064] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  461.502265] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  461.502441] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  461.502597] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  461.502756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  461.502891] [drm:intel_power_well_disable [i915]] disabling DC off
>[  461.503020] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  461.503228] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  461.503756] [drm:intel_power_well_disable [i915]] disabling always-on
>[  461.506566] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  461.543934] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  461.544035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  461.544198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  461.544306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  461.544394] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  461.544485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  461.544577] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  461.544663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  461.544747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  461.544825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  461.544901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.544920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  461.544996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.545059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  461.545141] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  461.545217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  461.545291] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  461.545365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.545436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.545526] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.545601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.545675] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  461.545747] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  461.545816] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  461.545907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  461.546007] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  461.546178] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  461.546479] [drm:intel_power_well_enable [i915]] enabling always-on
>[  461.546550] [drm:intel_power_well_enable [i915]] enabling DC off
>[  461.546877] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  461.546987] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  461.547149] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  461.547351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  461.547446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  461.547522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  461.547595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  461.547667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  461.547737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  461.547806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  461.547875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  461.547953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  461.548094] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.548177] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  461.548258] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  461.548355] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  461.548436] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  461.550362] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  461.550447] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  461.560753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.569742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.578670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.587668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.596649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.605663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.614646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.623643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.632636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.641679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.650614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.659374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.668040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.676607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.685136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.693638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.702122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.710593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  461.713339] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  461.774439] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  461.774456] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  461.774515] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  461.775171] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  461.775978] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  461.777800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  461.777819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  461.777836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  461.777854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  461.783749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  461.783766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  461.788898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  461.791383] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  461.791917] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  461.791956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  461.791972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  461.792011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  461.792054] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  461.792070] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  461.808755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  461.808781] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  461.808824] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  461.808996] Console: switching to colour frame buffer device 200x56
>[  461.970134] Console: switching to colour dummy device 80x25
>[  461.970265] [IGT] kms_pipe_crc_basic: executing
>[  461.991321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  461.991350] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  461.991364] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  461.991377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  461.991400] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  461.993166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  461.993190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  461.995166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  461.995175] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  461.997162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  461.997186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  461.999150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  461.999158] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  461.999163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  461.999184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  461.999209] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  461.999940] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  461.999966] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  462.000851] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  462.001669] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  462.003195] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  462.003215] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  462.003233] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  462.003251] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  462.004071] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  462.004785] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  462.005684] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  462.005687] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  462.005690] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  462.005692] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  462.005775] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  462.005778] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  462.005782] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  462.005784] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  462.005789] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  462.005791] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  462.005799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  462.005802] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  462.005805] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.005808] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.005811] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  462.005813] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  462.005816] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  462.005819] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  462.005821] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  462.005824] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  462.005827] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  462.005829] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.005832] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.005835] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  462.005837] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  462.005840] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  462.005843] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  462.005845] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  462.005848] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  462.005851] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.005853] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.005856] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  462.005859] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.005861] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.005864] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  462.017595] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  462.017615] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  462.017626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  462.017844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  462.017862] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  462.020113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  462.020141] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  462.022376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  462.022385] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  462.024642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  462.024665] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  462.026914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  462.026923] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  462.026928] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  462.027370] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  462.027395] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  462.028146] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  462.028172] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  462.028859] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  462.029680] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  462.031199] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  462.031218] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  462.031235] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  462.031252] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  462.032054] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  462.032762] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  462.033638] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  462.033641] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  462.033644] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  462.033646] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  462.033726] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  462.033728] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  462.033733] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  462.033735] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  462.033739] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  462.033742] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  462.033750] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  462.033753] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  462.033755] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.033758] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.033761] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  462.033764] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  462.033766] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  462.033769] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  462.033771] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  462.033774] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  462.033777] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  462.033779] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.033782] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.033784] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  462.033787] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  462.033790] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  462.033792] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  462.033795] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  462.033797] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  462.033800] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.033803] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.033805] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  462.033808] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.033810] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.033813] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  462.034333] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A
>[  462.034755] [drm:drm_mode_addfb2] [FB:61]
>[  462.039072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  462.039100] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  462.058833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  462.058921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  462.143023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.143416] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  462.143514] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  462.143671] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  462.160721] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  462.160830] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  462.160977] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  462.161380] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  462.161552] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  462.161860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  462.162040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  462.162256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  462.162373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  462.162506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  462.162660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  462.162773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  462.162901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  462.163028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  462.163252] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  462.163404] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  462.163551] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  462.163694] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  462.163891] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  462.164170] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  462.164363] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  462.164532] [drm:intel_power_well_disable [i915]] disabling DC off
>[  462.164690] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  462.164829] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  462.165879] [drm:intel_power_well_disable [i915]] disabling always-on
>[  462.170296] [drm:drm_mode_addfb2] [FB:61]
>[  462.193165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  462.193194] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  462.193326] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  462.193367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  462.193411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  462.193456] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  462.193493] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  462.193532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  462.193570] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  462.193606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  462.193641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  462.193675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  462.193707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  462.193715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  462.193747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  462.193754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  462.193786] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  462.193817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  462.193848] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  462.193879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  462.193909] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  462.193948] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  462.193988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  462.194087] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  462.194133] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  462.194180] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  462.194230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.194288] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  462.194333] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  462.195048] [drm:intel_power_well_enable [i915]] enabling always-on
>[  462.195095] [drm:intel_power_well_enable [i915]] enabling DC off
>[  462.195395] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  462.195457] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  462.195507] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  462.195592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  462.195648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  462.195692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  462.195739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  462.195779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  462.195825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  462.195865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  462.195909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  462.195953] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  462.196043] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  462.196098] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  462.196156] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  462.196217] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  462.196263] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  462.198429] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  462.198459] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  462.208106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.216598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.225067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.233528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.242001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.250462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.258922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.267382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.275841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.284300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.292760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.301219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.309678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.318137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.326595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.335054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.343512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.351972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.360444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.361482] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  462.422233] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  462.422254] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  462.422299] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  462.422925] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  462.423734] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  462.424456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  462.424475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  462.424493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  462.424512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  462.430259] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  462.430277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  462.435402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  462.437847] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  462.438378] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  462.438410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  462.438426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  462.438449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  462.438489] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  462.438506] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  462.455199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  462.455224] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  462.455264] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  462.556039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.556590] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  462.556728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  462.556954] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  462.574329] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  462.574418] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  462.574540] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  462.574650] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  462.574753] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  462.574930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  462.575031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  462.575345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  462.575455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  462.575570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  462.575704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  462.575802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  462.575910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  462.576018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  462.576245] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  462.576374] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  462.576497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  462.576619] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  462.576782] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  462.576938] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  462.577170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  462.577318] [drm:intel_power_well_disable [i915]] disabling DC off
>[  462.577441] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  462.577552] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  462.578572] [drm:intel_power_well_disable [i915]] disabling always-on
>[  462.581307] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  462.615811] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  462.615906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  462.616003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  462.616161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  462.616245] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  462.616334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  462.616424] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  462.616506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  462.616586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  462.616660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  462.616731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  462.616749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  462.616820] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  462.616833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  462.616904] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  462.616979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  462.617186] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  462.617266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  462.617335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  462.617421] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  462.617490] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  462.617559] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  462.617627] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  462.617694] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  462.617779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.617875] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  462.617955] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  462.618252] [drm:intel_power_well_enable [i915]] enabling always-on
>[  462.618319] [drm:intel_power_well_enable [i915]] enabling DC off
>[  462.618642] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  462.618746] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  462.618839] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  462.619034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  462.619191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  462.619270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  462.619344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  462.619415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  462.619488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  462.619558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  462.619627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  462.619705] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  462.619792] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  462.619873] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  462.619954] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  462.620100] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  462.620182] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  462.622360] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  462.622445] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  462.632670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.641619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.650666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.659656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.668682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.677621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.686556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.695505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.704427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.713345] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.722134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.730774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.739342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.747873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.756381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.764868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.773341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.781805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.784561] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  462.845611] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  462.845629] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  462.845655] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  462.846480] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  462.847219] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  462.849817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  462.849837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  462.849856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  462.849877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  462.855277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  462.855294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  462.860436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  462.862923] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  462.863514] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  462.863546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  462.863563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  462.863588] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  462.863632] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  462.863650] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  462.880347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  462.880376] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  462.880425] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  462.880594] Console: switching to colour frame buffer device 200x56
>[  463.054554] Console: switching to colour dummy device 80x25
>[  463.054646] [IGT] kms_pipe_crc_basic: executing
>[  463.065379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  463.065406] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  463.065418] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  463.065430] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  463.065450] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  463.067065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  463.067084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  463.069137] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  463.069142] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  463.071142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  463.071163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  463.073141] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  463.073146] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  463.073150] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  463.073163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  463.073183] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  463.073902] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  463.073927] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  463.074625] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  463.075472] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  463.076988] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  463.077023] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  463.077040] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  463.077056] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  463.077846] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  463.078555] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  463.079418] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  463.079422] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  463.079424] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  463.079427] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  463.079505] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  463.079508] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  463.079515] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  463.079517] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  463.079521] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  463.079523] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  463.079531] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  463.079533] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  463.079536] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  463.079539] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  463.079541] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  463.079544] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  463.079546] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  463.079549] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  463.079552] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.079554] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.079557] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  463.079559] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  463.079562] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  463.079564] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  463.079567] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  463.079569] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  463.079572] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  463.079574] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  463.079577] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  463.079579] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  463.079582] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  463.079584] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  463.079586] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.079589] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.079591] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  463.090514] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  463.090535] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  463.090546] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  463.090772] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  463.090791] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  463.093039] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  463.093058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  463.095282] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  463.095287] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  463.097514] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  463.097535] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  463.099763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  463.099768] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  463.099772] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  463.100106] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  463.100135] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  463.100854] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  463.100879] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  463.101577] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  463.102395] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  463.103907] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  463.103925] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  463.103942] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  463.103958] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  463.104774] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  463.105483] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  463.106346] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  463.106349] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  463.106352] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  463.106354] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  463.106431] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  463.106433] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  463.106437] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  463.106439] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  463.106443] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  463.106445] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  463.106453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  463.106455] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  463.106458] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  463.106461] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  463.106463] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  463.106466] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  463.106468] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  463.106471] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  463.106473] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.106476] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.106478] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  463.106481] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  463.106483] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  463.106486] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  463.106488] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  463.106491] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  463.106493] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  463.106496] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  463.106498] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  463.106501] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  463.106503] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  463.106505] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  463.106508] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.106510] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.106513] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  463.106775] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[  463.107167] [drm:drm_mode_addfb2] [FB:61]
>[  463.111469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  463.111480] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  463.130501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  463.130950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  463.214704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  463.215002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  463.215266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  463.215469] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  463.232372] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  463.232480] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  463.232625] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  463.232757] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  463.232876] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  463.233219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  463.233353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  463.233455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  463.233560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  463.233660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  463.233770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  463.233895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  463.234038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  463.234277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  463.234456] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  463.234620] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  463.234782] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  463.234909] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  463.235212] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  463.235345] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  463.235493] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  463.235613] [drm:intel_power_well_disable [i915]] disabling DC off
>[  463.235711] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  463.235797] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  463.236392] [drm:intel_power_well_disable [i915]] disabling always-on
>[  463.240888] [drm:drm_mode_addfb2] [FB:61]
>[  463.266058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  463.266080] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  463.266184] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  463.266226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  463.266270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  463.266316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  463.266353] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  463.266392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  463.266431] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  463.266468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  463.266504] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  463.266537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  463.266570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  463.266578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  463.266609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  463.266616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  463.266649] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  463.266680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  463.266711] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  463.266742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  463.266773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  463.266810] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  463.266842] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  463.266872] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  463.266903] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  463.266933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  463.266971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  463.267055] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  463.267091] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  463.267723] [drm:intel_power_well_enable [i915]] enabling always-on
>[  463.267758] [drm:intel_power_well_enable [i915]] enabling DC off
>[  463.268086] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  463.268141] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  463.268192] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  463.268290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  463.268352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  463.268390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  463.268425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  463.268459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  463.268493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  463.268525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  463.268559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  463.268594] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  463.268635] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  463.268673] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  463.268711] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  463.268756] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  463.268795] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  463.270981] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  463.271034] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  463.280591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.289078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.297548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.306013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.314472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.322930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.331388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.339846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.348302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.356761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.365218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.373679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.382138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.390595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.399052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.407508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.415966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.424433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.432891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.433930] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  463.494647] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  463.494679] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  463.494737] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  463.495409] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  463.496223] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  463.496942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  463.496962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  463.496981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  463.497087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  463.502766] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  463.502784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  463.507908] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  463.510390] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  463.510861] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  463.510916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  463.510932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  463.510955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  463.511029] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  463.511053] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  463.527711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  463.527737] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  463.527778] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  463.628617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  463.628914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  463.629033] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  463.629471] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  463.646358] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  463.646465] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  463.646610] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  463.646742] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  463.646864] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  463.647269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  463.647436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  463.647587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  463.647733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  463.647879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  463.648040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  463.648231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  463.648373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  463.648501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  463.648667] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  463.648825] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  463.648979] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  463.649217] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  463.649421] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  463.649612] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  463.649806] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  463.649981] [drm:intel_power_well_disable [i915]] disabling DC off
>[  463.650223] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  463.650359] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  463.650903] [drm:intel_power_well_disable [i915]] disabling always-on
>[  463.654197] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  463.683947] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  463.684048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  463.684352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  463.684462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  463.684550] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  463.684643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  463.684735] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  463.684821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  463.684906] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  463.684987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  463.685195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  463.685213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  463.685291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  463.685304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  463.685383] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  463.685459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  463.685534] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  463.685607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  463.685678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  463.685768] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  463.685841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  463.685913] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  463.685984] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  463.686114] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  463.686205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  463.686306] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  463.686392] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  463.686673] [drm:intel_power_well_enable [i915]] enabling always-on
>[  463.686745] [drm:intel_power_well_enable [i915]] enabling DC off
>[  463.687131] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  463.687607] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  463.687707] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  463.687903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  463.687999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  463.688130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  463.688207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  463.688282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  463.688357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  463.688429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  463.688498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  463.688577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  463.688667] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  463.688750] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  463.688831] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  463.688929] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  463.689011] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  463.691538] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  463.691626] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  463.702155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.711140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.720152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.729240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.738161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.747152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.756149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.765146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.774183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.783118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.791848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.800460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.809017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.817542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.826043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.834525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.842992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.851453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.854197] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  463.914630] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  463.914647] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  463.914671] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  463.915497] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  463.916234] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  463.918820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  463.918838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  463.918855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  463.918872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  463.924270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  463.924286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  463.929416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  463.931903] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  463.932452] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  463.932526] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  463.932542] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  463.932566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  463.932609] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  463.932625] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  463.949324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  463.949350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  463.949394] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  463.949559] Console: switching to colour frame buffer device 200x56
>[  464.104800] Console: switching to colour dummy device 80x25
>[  464.104892] [IGT] kms_pipe_crc_basic: executing
>[  464.118502] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  464.118530] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  464.118543] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  464.118556] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  464.118579] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  464.120292] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  464.120315] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  464.122152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  464.122161] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  464.124154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  464.124178] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  464.126158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  464.126167] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  464.126172] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  464.126192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  464.126218] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  464.126948] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  464.126974] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  464.127773] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  464.128592] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  464.130105] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  464.130127] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  464.130145] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  464.130162] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  464.130953] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  464.131662] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  464.132564] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  464.132567] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  464.132570] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  464.132573] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  464.132658] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  464.132660] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  464.132665] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  464.132667] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  464.132671] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  464.132673] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  464.132682] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  464.132685] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  464.132688] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  464.132690] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  464.132693] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  464.132696] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  464.132699] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  464.132701] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  464.132704] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.132707] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.132709] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  464.132712] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  464.132715] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  464.132717] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  464.132720] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  464.132723] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  464.132725] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  464.132728] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  464.132731] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  464.132733] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  464.132736] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  464.132738] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  464.132741] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.132744] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.132746] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  464.144269] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  464.144289] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  464.144300] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  464.144518] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  464.144537] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  464.146777] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  464.146795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  464.149074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  464.149082] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  464.151319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  464.151341] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  464.153615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  464.153623] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  464.153628] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  464.153908] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  464.153933] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  464.154686] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  464.154713] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  464.155455] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  464.156272] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  464.157781] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  464.157800] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  464.157817] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  464.157834] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  464.158629] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  464.159386] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  464.160256] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  464.160259] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  464.160262] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  464.160264] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  464.160343] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  464.160345] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  464.160349] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  464.160351] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  464.160356] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  464.160358] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  464.160366] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  464.160368] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  464.160371] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  464.160374] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  464.160376] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  464.160379] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  464.160381] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  464.160384] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  464.160386] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.160389] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.160392] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  464.160394] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  464.160396] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  464.160399] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  464.160402] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  464.160404] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  464.160407] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  464.160409] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  464.160411] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  464.160414] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  464.160416] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  464.160419] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  464.160421] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.160424] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.160426] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  464.160727] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B
>[  464.161194] [drm:drm_mode_addfb2] [FB:61]
>[  464.165508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  464.165560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  464.165627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  464.165649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  464.165685] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  464.168183] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  464.168199] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  464.168221] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  464.168241] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  464.168259] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  464.168292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  464.168309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  464.168324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  464.168339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  464.168353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  464.168368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  464.168381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  464.168394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  464.168409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  464.168425] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  464.168441] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.168456] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  464.168470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  464.168491] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  464.168511] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  464.168532] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  464.168549] [drm:intel_power_well_disable [i915]] disabling DC off
>[  464.168563] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  464.168576] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  464.169016] [drm:intel_power_well_disable [i915]] disabling always-on
>[  464.169118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  464.169132] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  464.169194] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  464.169216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  464.169241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  464.169265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  464.169287] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  464.169310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  464.169332] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  464.169354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  464.169375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  464.169395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  464.169415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  464.169420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  464.169438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  464.169443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  464.169462] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  464.169481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  464.169500] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  464.169520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  464.169539] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  464.169561] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  464.169581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  464.169601] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  464.169621] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  464.169641] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  464.169664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  464.169688] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  464.169709] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  464.169981] [drm:intel_power_well_enable [i915]] enabling always-on
>[  464.170019] [drm:intel_power_well_enable [i915]] enabling DC off
>[  464.170291] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  464.170318] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  464.170339] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  464.170420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  464.170444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  464.170465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  464.170487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  464.170507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  464.170527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  464.170547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  464.170566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  464.170587] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  464.170610] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.170632] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  464.170653] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  464.170678] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  464.170699] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  464.172014] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  464.172037] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  464.181547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.190011] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.198472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.206933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.215478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.223939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.232398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.240858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.249317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.257778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.266237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.274698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.283158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.291617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.300076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.308535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.316994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.325452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.333912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.334953] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  464.394471] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  464.394492] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  464.394527] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  464.395356] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  464.396053] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  464.397821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  464.397841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  464.397860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  464.397879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  464.403730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  464.403748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  464.408863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  464.411345] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  464.411818] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  464.411871] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  464.411887] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  464.411909] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  464.428683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  464.428710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  464.428751] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.445386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  464.529417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  464.529649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  464.529738] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  464.529885] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  464.546689] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  464.546781] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  464.546912] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  464.547020] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  464.547469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  464.547621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  464.547753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  464.547859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  464.547942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  464.548039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  464.548226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  464.548327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  464.548435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  464.548561] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  464.548700] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.548831] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  464.548962] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  464.549393] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  464.549573] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  464.549725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  464.549819] [drm:intel_power_well_disable [i915]] disabling DC off
>[  464.549905] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  464.549980] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  464.550600] [drm:intel_power_well_disable [i915]] disabling always-on
>[  464.554333] [drm:drm_mode_addfb2] [FB:61]
>[  464.579765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  464.579813] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  464.580064] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  464.580291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  464.580419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  464.580572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  464.580676] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  464.580800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  464.580910] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  464.581036] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  464.581243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  464.581349] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  464.581465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  464.581497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  464.581607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  464.581637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  464.581748] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  464.581840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  464.581944] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  464.582041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  464.582485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  464.582592] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  464.582709] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  464.582802] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  464.582906] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  464.582998] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  464.583208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  464.583346] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  464.583454] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  464.585353] [drm:intel_power_well_enable [i915]] enabling always-on
>[  464.585435] [drm:intel_power_well_enable [i915]] enabling DC off
>[  464.585765] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  464.585872] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  464.585972] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  464.586385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  464.586540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  464.586658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  464.586787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  464.586908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  464.587030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  464.587252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  464.587372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  464.587497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  464.587633] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.587762] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  464.587888] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  464.588044] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  464.588350] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  464.590714] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  464.590803] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  464.601020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.609981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.618937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.628135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.637026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.645986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.654952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.664127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.673010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.682127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.690756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.699317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.707840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.716337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.724818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.733285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.741744] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.750202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  464.752924] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  464.814883] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  464.814903] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  464.814959] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  464.815660] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  464.816484] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  464.818292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  464.818311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  464.818329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  464.818348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  464.824237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  464.824257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  464.829390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  464.831864] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258821bf8
>[  464.832433] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  464.832503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  464.832521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  464.832545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  464.849298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  464.849328] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  464.849373] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.950286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  464.950594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  464.950714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  464.950909] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  464.967285] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  464.967374] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  464.967505] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  464.967614] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  464.967793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  464.967895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  464.967979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  464.968273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  464.968380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  464.968511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  464.968627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  464.968723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  464.968846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  464.968986] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  464.969218] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  464.969357] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  464.969486] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  464.969657] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  464.969819] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  464.969985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  464.970219] [drm:intel_power_well_disable [i915]] disabling DC off
>[  464.970344] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  464.970460] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  464.970980] [drm:intel_power_well_disable [i915]] disabling always-on
>[  464.973689] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  465.005083] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  465.005440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.005546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  465.005657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  465.005867] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  465.005963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.006186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  465.006274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  465.006359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  465.006439] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  465.006516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.006533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.006607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.006621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.006698] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  465.006772] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  465.006845] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.006918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.006990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.007138] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.007212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.007285] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  465.007356] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  465.007428] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  465.007517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.007617] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  465.007704] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  465.007988] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.008114] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.008443] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  465.008554] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.008656] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.008854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.008948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  465.009026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  465.009154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  465.009227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  465.009299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  465.009369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  465.009438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  465.009516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  465.009607] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.009690] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  465.009771] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  465.009870] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  465.009950] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  465.012426] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  465.012511] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  465.022741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.031682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.040614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.049539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.058464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.067382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.076397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.085381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.094375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.103316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.112053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.120671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.129228] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.137755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.146255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.154754] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.163224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.171685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.174425] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  465.235452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  465.235469] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  465.235496] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  465.236322] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  465.237061] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  465.239650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  465.239668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.239685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.239706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.245111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.245127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  465.250258] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.252740] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  465.253289] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  465.253316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  465.253332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  465.253355] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  465.253491] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  465.253507] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  465.270114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  465.270140] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  465.270184] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.270338] Console: switching to colour frame buffer device 200x56
>[  465.426229] Console: switching to colour dummy device 80x25
>[  465.426327] [IGT] kms_pipe_crc_basic: executing
>[  465.445285] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  465.445314] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  465.445328] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  465.445341] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  465.445364] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  465.447154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  465.447178] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  465.449161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  465.449169] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  465.451154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  465.451178] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  465.453163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  465.453172] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  465.453177] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  465.453197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  465.453224] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  465.453954] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  465.453980] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  465.454773] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  465.455591] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  465.457107] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  465.457127] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  465.457145] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  465.457163] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  465.457956] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  465.458664] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  465.459556] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  465.459559] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  465.459562] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  465.459564] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  465.459649] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  465.459652] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  465.459656] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  465.459658] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  465.459663] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  465.459665] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  465.459673] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  465.459676] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.459679] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  465.459682] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  465.459685] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  465.459688] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  465.459690] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  465.459693] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  465.459696] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  465.459699] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  465.459701] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  465.459704] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  465.459707] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  465.459709] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  465.459712] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  465.459715] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  465.459717] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  465.459720] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  465.459723] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  465.459725] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  465.459728] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  465.459731] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  465.459733] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  465.459736] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  465.459738] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  465.471340] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  465.471362] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  465.471385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  465.471591] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  465.471608] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  465.473850] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  465.473870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  465.475319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  465.475323] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  465.477563] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  465.477583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  465.479831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  465.479840] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  465.479845] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  465.480294] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  465.480320] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  465.481085] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  465.481110] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  465.481789] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  465.482606] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  465.484116] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  465.484134] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  465.484150] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  465.484166] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  465.484962] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  465.485796] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  465.486662] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  465.486665] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  465.486668] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  465.486670] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  465.486746] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  465.486749] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  465.486753] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  465.486755] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  465.486759] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  465.486761] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  465.486769] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  465.486772] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.486774] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  465.486777] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  465.486780] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  465.486782] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  465.486785] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  465.486787] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  465.486789] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  465.486792] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  465.486794] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  465.486797] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  465.486799] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  465.486802] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  465.486804] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  465.486806] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  465.486809] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  465.486811] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  465.486814] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  465.486816] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  465.486818] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  465.486821] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  465.486823] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  465.486826] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  465.486828] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  465.487756] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B-frame-sequence
>[  465.488106] [drm:drm_mode_addfb2] [FB:61]
>[  465.492116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  465.492162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.492230] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  465.492253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  465.492395] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  465.504655] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  465.504671] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  465.504693] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  465.504713] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  465.504731] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  465.504765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.504782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  465.504797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  465.504811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  465.504825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  465.504840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  465.504853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  465.504867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  465.504881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  465.504898] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  465.504914] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.504929] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  465.504943] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  465.504964] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.505329] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.505359] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  465.505384] [drm:intel_power_well_disable [i915]] disabling DC off
>[  465.505406] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  465.505425] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  465.505842] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.505923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  465.505932] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  465.505971] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  465.506124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.506141] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  465.506160] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  465.506175] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  465.506190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.506206] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  465.506221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  465.506236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  465.506249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  465.506262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.506266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.506278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.506281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.506294] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  465.506307] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  465.506319] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.506331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.506343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.506358] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.506371] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.506384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  465.506396] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  465.506408] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  465.506423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.506441] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  465.506456] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  465.506674] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.506686] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.507425] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  465.507701] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.507722] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.507788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.507812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  465.507833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  465.507854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  465.507874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  465.507894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  465.507914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  465.507933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  465.507955] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  465.507979] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.508186] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  465.508202] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  465.508221] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  465.508237] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  465.510378] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  465.510394] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  465.519935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.528400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.536864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.545327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.553787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.562245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.570703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.579163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.587623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.596081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.604538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.612998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.621455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.629913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.638372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.646831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.655288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.663747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.672204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.673236] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  465.733535] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  465.733554] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  465.733597] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  465.734427] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  465.735126] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  465.736874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  465.736892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.736908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.736925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.742792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.742808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  465.747931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.750410] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  465.750859] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  465.750887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  465.750902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  465.750922] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  465.767705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  465.767729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  465.767767] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.784425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  465.868397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.868621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  465.868712] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  465.868863] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  465.886893] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  465.886985] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  465.887377] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  465.887532] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  465.887806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.887950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  465.888181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  465.888306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  465.888431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  465.888563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  465.888678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  465.888791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  465.888916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  465.889065] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  465.889278] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.889410] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  465.889536] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  465.889706] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.889867] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.890045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  465.890265] [drm:intel_power_well_disable [i915]] disabling DC off
>[  465.890394] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  465.890510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  465.891042] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.894769] [drm:drm_mode_addfb2] [FB:61]
>[  465.916942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  465.917133] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  465.917481] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  465.917620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.917771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  465.917913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  465.918042] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  465.918267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.918411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  465.918539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  465.918669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  465.918785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  465.918904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.918934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.919050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.919168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  465.919281] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  465.919403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  465.919523] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.919641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.919758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.919897] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.920017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.920199] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  465.920297] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  465.920412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  465.920544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.920681] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  465.920804] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  465.922592] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.922675] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.923006] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  465.923585] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.923710] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.923950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.924191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  465.924305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  465.924430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  465.924554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  465.924678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  465.924798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  465.924892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  465.924981] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  465.925184] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  465.925299] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  465.925429] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  465.925580] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  465.925713] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  465.928178] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  465.928271] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  465.938441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.947370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.956292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.965220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.974127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.983048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.992117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.001018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.009997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.018984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.027800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.036450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.045010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.053532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.062030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.070509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.078978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.087452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.090178] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  466.150383] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  466.150403] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  466.150441] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  466.151659] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  466.153427] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  466.155277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.155293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.155308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.155324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.160440] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.160455] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.165571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.168054] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  466.168501] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  466.168526] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  466.168541] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  466.168562] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  466.185320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  466.185345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  466.185383] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  466.285962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.286269] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  466.286361] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  466.286510] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  466.303507] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  466.303615] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  466.303772] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  466.303902] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  466.304277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  466.304403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  466.304508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  466.304606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  466.304700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  466.304804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  466.304895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  466.304986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  466.305159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  466.305276] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  466.305385] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  466.305491] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  466.305594] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  466.305746] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  466.305877] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  466.306019] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  466.306191] [drm:intel_power_well_disable [i915]] disabling DC off
>[  466.306290] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  466.306376] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  466.306872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  466.309837] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  466.342954] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  466.343049] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  466.343205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  466.343308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  466.343388] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  466.343474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.343561] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  466.343641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  466.343720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  466.343795] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  466.343867] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.343885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  466.343955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.343969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  466.344122] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  466.344193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  466.344263] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  466.344334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.344401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  466.344486] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  466.344557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.344628] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  466.344696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  466.344764] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  466.344849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.344944] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  466.345023] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  466.345364] [drm:intel_power_well_enable [i915]] enabling always-on
>[  466.345431] [drm:intel_power_well_enable [i915]] enabling DC off
>[  466.345752] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  466.345858] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  466.345957] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  466.346223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  466.346319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  466.346397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  466.346472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  466.346545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  466.346616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  466.346686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  466.346756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  466.346835] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  466.346924] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  466.347007] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  466.347144] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  466.347244] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  466.347326] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  466.349301] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  466.349387] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  466.359680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.368639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.377684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.386629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.395653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.404519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.413369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.422216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.431138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.439995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.448910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.457713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.466332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.474889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.483414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.491915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.500398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.508866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.511612] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  466.572759] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  466.572779] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  466.572810] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  466.573463] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  466.574270] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  466.575011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.575029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.575046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.575064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.580961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.580978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.586124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.588610] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  466.589160] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  466.589233] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  466.589249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  466.589273] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  466.589322] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  466.589345] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  466.606045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  466.606070] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  466.606112] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  466.606263] Console: switching to colour frame buffer device 200x56
>[  466.753499] Console: switching to colour dummy device 80x25
>[  466.753617] [IGT] kms_pipe_crc_basic: executing
>[  466.775363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  466.775392] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  466.775406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  466.775419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  466.775442] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  466.777119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  466.777142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  466.779146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  466.779154] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  466.781149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  466.781171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  466.783158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  466.783165] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  466.783169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  466.783188] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  466.783210] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  466.783932] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  466.783957] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  466.784696] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  466.785517] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  466.787038] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  466.787058] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  466.787075] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  466.787093] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  466.787888] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  466.788601] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  466.789489] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  466.789492] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  466.789495] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  466.789497] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  466.789580] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  466.789582] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  466.789587] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  466.789589] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  466.789593] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  466.789596] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  466.789603] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  466.789607] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  466.789609] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  466.789612] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  466.789615] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  466.789618] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  466.789621] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  466.789623] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  466.789626] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  466.789629] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  466.789631] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  466.789634] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  466.789637] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  466.789640] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  466.789642] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  466.789645] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  466.789648] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  466.789650] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  466.789653] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  466.789656] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  466.789658] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  466.789661] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  466.789664] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  466.789666] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  466.789669] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  466.801325] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  466.801347] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  466.801359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  466.801596] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  466.801616] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  466.803865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  466.803888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  466.806122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  466.806131] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  466.808377] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  466.808400] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  466.810646] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  466.810655] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  466.810661] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  466.810960] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  466.810985] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  466.811779] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  466.811806] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  466.812514] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  466.813339] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  466.814868] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  466.814888] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  466.814906] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  466.814924] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  466.815726] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  466.816441] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  466.817326] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  466.817330] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  466.817333] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  466.817335] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  466.817419] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  466.817422] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  466.817426] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  466.817429] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  466.817433] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  466.817435] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  466.817444] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  466.817447] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  466.817450] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  466.817452] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  466.817455] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  466.817458] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  466.817461] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  466.817463] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  466.817466] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  466.817469] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  466.817471] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  466.817474] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  466.817477] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  466.817480] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  466.817482] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  466.817485] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  466.817488] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  466.817490] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  466.817493] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  466.817496] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  466.817498] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  466.817501] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  466.817503] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  466.817506] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  466.817509] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  466.817813] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[  466.818268] [drm:drm_mode_addfb2] [FB:61]
>[  466.822678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  466.822728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.822802] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  466.822826] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  466.822867] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  466.839967] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  466.840003] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  466.840029] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  466.840052] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  466.840073] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  466.840112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  466.840133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  466.840150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  466.840167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  466.840183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  466.840200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  466.840216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  466.840231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  466.840248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  466.840267] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  466.840286] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  466.840304] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  466.840321] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  466.840345] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  466.840368] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  466.840393] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  466.840413] [drm:intel_power_well_disable [i915]] disabling DC off
>[  466.840429] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  466.840444] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  466.840856] [drm:intel_power_well_disable [i915]] disabling always-on
>[  466.840941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  466.841431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  466.841446] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  466.841512] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  466.841538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  466.841565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  466.841594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  466.841619] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  466.841646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.841672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  466.841697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  466.841722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  466.841746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  466.841769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.841775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  466.841796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.841802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  466.841824] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  466.841847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  466.841870] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  466.841892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.841915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  466.841940] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  466.841963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.842010] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  466.842030] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  466.842055] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  466.842083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.842112] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  466.842139] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  466.842453] [drm:intel_power_well_enable [i915]] enabling always-on
>[  466.842476] [drm:intel_power_well_enable [i915]] enabling DC off
>[  466.842752] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  466.842782] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  466.842806] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  466.842850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  466.842878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  466.842903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  466.842928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  466.842952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  466.842976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  466.843024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  466.843050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  466.843076] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  466.843103] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  466.843130] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  466.843156] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  466.843185] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  466.843210] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  466.845356] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  466.845375] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  466.854922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.863490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.871969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.880466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.888945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.897423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.905901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.914379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.922850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.931312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.939771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.948230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.956687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.965146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.973603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.982276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.990735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.999194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.006776] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  467.067645] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  467.067665] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  467.067708] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  467.069123] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  467.071680] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  467.073018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  467.073035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  467.073051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  467.073068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  467.078180] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  467.078197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  467.083315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  467.085801] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  467.086343] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  467.086374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  467.086390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  467.086412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  467.103165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  467.103192] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  467.103234] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.204320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  467.204670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  467.204811] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  467.205035] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  467.222164] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  467.222252] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  467.222385] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  467.222493] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  467.222672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  467.222773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  467.222858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  467.222939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  467.223018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  467.223268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  467.223364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  467.223459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  467.223564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  467.223711] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  467.223829] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.223946] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  467.224129] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  467.224306] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  467.224468] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  467.224629] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  467.224759] [drm:intel_power_well_disable [i915]] disabling DC off
>[  467.224883] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  467.224998] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  467.225669] [drm:intel_power_well_disable [i915]] disabling always-on
>[  467.229875] [drm:drm_mode_addfb2] [FB:61]
>[  467.258777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  467.258826] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  467.259239] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  467.259365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  467.259513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  467.259655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  467.259759] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  467.259883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  467.259993] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  467.260210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  467.260319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  467.260436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  467.260534] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  467.260568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  467.260675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  467.260707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  467.260819] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  467.260912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  467.261031] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  467.261227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  467.261339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  467.261446] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  467.261560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  467.261678] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  467.261775] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  467.261883] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  467.262021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  467.262213] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  467.262317] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  467.264146] [drm:intel_power_well_enable [i915]] enabling always-on
>[  467.264229] [drm:intel_power_well_enable [i915]] enabling DC off
>[  467.264560] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  467.264665] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  467.264765] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  467.264965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  467.265262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  467.265403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  467.265532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  467.265656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  467.265779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  467.265902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  467.266022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  467.266216] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  467.266365] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.266503] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  467.266636] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  467.266790] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  467.266901] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  467.269258] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  467.269349] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  467.279492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.288458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.297380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.306249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.315119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.324002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.332970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.341940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.351049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.359700] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.368299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.376839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.385357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.393853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.402330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.410796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.419257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.427715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.432126] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  467.492914] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  467.492934] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  467.492976] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  467.493824] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  467.494522] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  467.496286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  467.496306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  467.496324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  467.496343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  467.502217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  467.502235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  467.507353] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  467.509740] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  467.510251] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  467.510310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  467.510327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  467.510349] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  467.527108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  467.527135] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  467.527177] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.627688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  467.627921] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  467.628013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  467.628817] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  467.645328] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  467.645418] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  467.645551] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  467.645660] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  467.645844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  467.645946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  467.646032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  467.647320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  467.647430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  467.647547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  467.647647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  467.647744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  467.647850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  467.647968] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  467.649234] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.649330] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  467.649420] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  467.649547] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  467.649658] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  467.649780] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  467.649868] [drm:intel_power_well_disable [i915]] disabling DC off
>[  467.649948] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  467.650020] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  467.651689] [drm:intel_power_well_disable [i915]] disabling always-on
>[  467.654381] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  467.685865] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  467.685967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  467.686129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  467.686236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  467.686324] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  467.686417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  467.686511] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  467.686598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  467.686682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  467.686762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  467.686839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  467.686857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  467.686933] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  467.686947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  467.687025] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  467.687147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  467.687224] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  467.687297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  467.687370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  467.687459] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  467.687533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  467.687606] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  467.687679] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  467.687751] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  467.687839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  467.687937] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  467.688023] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  467.688365] [drm:intel_power_well_enable [i915]] enabling always-on
>[  467.688437] [drm:intel_power_well_enable [i915]] enabling DC off
>[  467.688764] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  467.688875] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  467.688973] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  467.689235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  467.689328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  467.689405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  467.689480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  467.689552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  467.689622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  467.689692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  467.689760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  467.689839] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  467.689927] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.690011] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  467.690145] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  467.690243] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  467.690323] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  467.692374] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  467.692459] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  467.702807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.711766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.720713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.729656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.738627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.747480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.756344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.765242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.774248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.783097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.791954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.800803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.809434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.818028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.826561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.835084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.843569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.852043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  467.854786] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  467.915026] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  467.915042] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  467.915067] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  467.915885] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  467.916610] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  467.919194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  467.919210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  467.919226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  467.919242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  467.924632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  467.924647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  467.929769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  467.932250] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820958
>[  467.932752] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  467.932826] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  467.932840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  467.932861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  467.933012] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  467.933026] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  467.949622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  467.949645] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  467.949685] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  467.949829] Console: switching to colour frame buffer device 200x56
>[  468.084724] Console: switching to colour dummy device 80x25
>[  468.084879] [IGT] kms_pipe_crc_basic: executing
>[  468.099650] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  468.099688] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  468.099704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  468.099721] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  468.099752] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  468.101166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  468.101196] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  468.103166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  468.103175] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  468.105158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  468.105188] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  468.107156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  468.107165] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  468.107171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  468.107193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  468.107225] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  468.107977] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  468.108042] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  468.108820] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  468.109666] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  468.111232] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  468.111259] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  468.111285] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  468.111309] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  468.112134] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  468.112864] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  468.113807] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  468.113811] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  468.113815] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  468.113818] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  468.113932] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  468.113935] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  468.113942] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  468.113945] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  468.113951] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  468.113954] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  468.113965] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  468.114004] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  468.114010] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  468.114016] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  468.114022] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  468.114028] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  468.114034] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  468.114040] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  468.114046] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  468.114052] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  468.114058] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  468.114064] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  468.114070] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  468.114076] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  468.114082] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  468.114088] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  468.114094] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  468.114099] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  468.114105] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  468.114112] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  468.114118] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  468.114124] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  468.114130] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  468.114136] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  468.114142] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  468.130114] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  468.130144] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  468.130158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  468.130483] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  468.130511] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  468.132748] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  468.132778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  468.135064] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  468.135076] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  468.137324] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  468.137356] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  468.139595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  468.139606] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  468.139612] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  468.140168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  468.140205] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  468.140964] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  468.141100] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  468.141846] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  468.142695] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  468.144259] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  468.144287] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  468.144312] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  468.144336] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  468.145161] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  468.145891] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  468.146849] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  468.146853] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  468.146857] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  468.146860] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  468.147061] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  468.147066] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  468.147077] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  468.147082] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  468.147091] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  468.147096] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  468.147113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  468.147120] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  468.147126] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  468.147132] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  468.147138] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  468.147144] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  468.147150] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  468.147155] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  468.147161] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  468.147167] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  468.147173] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  468.147179] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  468.147185] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  468.147191] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  468.147197] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  468.147202] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  468.147209] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  468.147214] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  468.147220] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  468.147227] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  468.147232] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  468.147238] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  468.147244] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  468.147250] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  468.147256] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  468.147875] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C-frame-sequence
>[  468.148463] [drm:drm_mode_addfb2] [FB:61]
>[  468.154371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  468.154437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  468.154536] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  468.154569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  468.154763] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  468.166674] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  468.166699] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  468.166734] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  468.166766] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  468.166796] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  468.166848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  468.166876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  468.166901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  468.166925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  468.166947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  468.166971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  468.167126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  468.167155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  468.167188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  468.167227] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  468.167263] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.167300] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  468.167334] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  468.167378] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  468.167422] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  468.167467] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  468.167506] [drm:intel_power_well_disable [i915]] disabling DC off
>[  468.167540] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  468.167573] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  468.168497] [drm:intel_power_well_disable [i915]] disabling always-on
>[  468.168669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  468.169108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  468.169122] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  468.169189] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  468.169216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  468.169244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  468.169274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  468.169298] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  468.169324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  468.169350] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  468.169374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  468.169398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  468.169421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  468.169442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.169447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  468.169469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.169474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  468.169495] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  468.169516] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  468.169537] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  468.169558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.169578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.169604] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.169624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.169644] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  468.169665] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  468.169685] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  468.169710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  468.169737] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  468.169761] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  468.170176] [drm:intel_power_well_enable [i915]] enabling always-on
>[  468.170208] [drm:intel_power_well_enable [i915]] enabling DC off
>[  468.170495] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  468.170535] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  468.170567] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  468.170660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  468.170697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  468.170725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  468.170756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  468.170783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  468.170813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  468.170839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  468.170869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  468.170897] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  468.170932] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.170966] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  468.171033] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  468.171074] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  468.171103] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  468.173262] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  468.173288] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  468.182816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.191343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.199863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.208409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.216928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.225445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.233963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.242503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.251007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.259489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.267958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.276494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.284951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.293476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.301935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.310394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.318853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.327311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.335090] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  468.395345] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  468.395367] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  468.395418] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  468.396503] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  468.399051] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  468.400401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  468.400418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  468.400434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  468.400451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  468.405575] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  468.405592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  468.410717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  468.413199] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  468.413686] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  468.413724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  468.413741] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  468.413763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  468.430513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  468.430537] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  468.430574] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.531540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  468.531834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  468.531948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  468.532364] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  468.549439] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  468.549532] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  468.549665] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  468.549771] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  468.549953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  468.550224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  468.550328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  468.550452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  468.550554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  468.550689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  468.550811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  468.550932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  468.551063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  468.551317] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  468.551437] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.551571] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  468.551700] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  468.551897] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  468.552151] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  468.552335] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  468.552472] [drm:intel_power_well_disable [i915]] disabling DC off
>[  468.552605] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  468.552706] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  468.553726] [drm:intel_power_well_disable [i915]] disabling always-on
>[  468.557526] [drm:drm_mode_addfb2] [FB:61]
>[  468.579947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  468.580346] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  468.580619] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  468.580717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  468.580818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  468.580923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  468.581008] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  468.581811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  468.581944] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  468.582070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  468.582648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  468.582733] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  468.582814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.582833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  468.582911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.582928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  468.583007] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  468.583884] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  468.584006] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  468.584456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.584574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.584709] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.584824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.584942] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  468.585057] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  468.585721] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  468.585813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  468.585914] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  468.586000] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  468.588219] [drm:intel_power_well_enable [i915]] enabling always-on
>[  468.588292] [drm:intel_power_well_enable [i915]] enabling DC off
>[  468.588618] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  468.588716] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  468.588790] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  468.588946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  468.589170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  468.589303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  468.589405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  468.589520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  468.589616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  468.589724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  468.589822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  468.589942] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  468.590157] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.590294] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  468.590417] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  468.590555] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  468.590658] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  468.592704] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  468.592783] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  468.603130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.612127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.621121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.630024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.638953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.648107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.656920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.665889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.674731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.683463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.692083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.700639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.709161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.717656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.726138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.734603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.743061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.751519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  468.755928] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  468.816672] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  468.816692] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  468.816752] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  468.817597] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  468.818352] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  468.820980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  468.821010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  468.821028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  468.821047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  468.826418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  468.826436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  468.831560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  468.834044] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258821bf8
>[  468.834532] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  468.834567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  468.834584] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  468.834607] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  468.851363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  468.851390] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  468.851431] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.951966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  468.952272] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  468.952365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  468.952538] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  468.969638] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  468.969730] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  468.969862] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  468.969968] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  468.970402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  468.970554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  468.970681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  468.970801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  468.970921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  468.971054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  468.971228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  468.971347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  468.971455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  468.971593] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  468.971725] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  468.971853] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  468.971978] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  468.972231] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  468.972394] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  468.972562] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  468.972694] [drm:intel_power_well_disable [i915]] disabling DC off
>[  468.972819] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  468.972933] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  468.973937] [drm:intel_power_well_disable [i915]] disabling always-on
>[  468.976772] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  469.009886] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  469.009981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  469.010137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  469.010238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  469.010319] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  469.010407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  469.010496] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  469.010577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  469.010656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  469.010729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  469.010799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  469.010817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  469.010887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  469.010900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  469.010975] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  469.011125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  469.011197] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  469.011265] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.011333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  469.011419] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  469.011489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  469.011557] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  469.011624] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  469.011692] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  469.011774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.011870] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  469.011951] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  469.012277] [drm:intel_power_well_enable [i915]] enabling always-on
>[  469.012344] [drm:intel_power_well_enable [i915]] enabling DC off
>[  469.012668] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  469.012773] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  469.012871] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  469.013138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  469.013235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  469.013311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  469.013384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  469.013455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  469.013525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  469.013593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  469.013662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  469.013742] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  469.013828] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  469.013910] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  469.013991] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  469.014141] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  469.014222] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  469.016298] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  469.016383] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  469.026702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.035651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.044650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.053499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.062339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.071181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.080130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.088979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.097877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.106722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.115563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.124281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.132890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.141441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.149959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.158477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.166957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.175441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.177997] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  469.238617] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  469.238636] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  469.238665] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  469.240109] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  469.242670] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  469.244011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  469.244027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  469.244042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  469.244057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  469.249190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  469.249206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  469.254337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  469.256820] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  469.257371] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  469.257447] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  469.257462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  469.257486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  469.257621] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  469.257637] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  469.274261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  469.274289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  469.274333] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  469.274494] Console: switching to colour frame buffer device 200x56
>[  469.438650] Console: switching to colour dummy device 80x25
>[  469.438740] [IGT] kms_pipe_crc_basic: executing
>[  469.452579] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  469.452607] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  469.452621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  469.452633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  469.452655] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  469.454162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  469.454186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  469.456157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  469.456165] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  469.458160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  469.458183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  469.460180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  469.460189] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  469.460194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  469.460215] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  469.460240] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  469.460971] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  469.461026] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  469.461748] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  469.462566] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  469.464077] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  469.464096] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  469.464114] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  469.464131] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  469.464921] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  469.465627] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  469.466537] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  469.466540] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  469.466543] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  469.466545] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  469.466626] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  469.466628] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  469.466632] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  469.466634] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  469.466639] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  469.466641] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  469.466649] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  469.466652] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  469.466654] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  469.466657] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  469.466660] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  469.466662] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  469.466665] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  469.466668] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  469.466670] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  469.466673] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  469.466675] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  469.466678] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  469.466681] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  469.466683] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  469.466686] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  469.466688] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  469.466691] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  469.466693] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  469.466696] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  469.466698] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  469.466701] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  469.466704] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  469.466706] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  469.466709] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  469.466711] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  469.478086] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  469.478107] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  469.478118] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  469.478349] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  469.478368] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  469.480599] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  469.480621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  469.482857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  469.482865] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  469.485111] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  469.485133] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  469.487354] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  469.487363] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  469.487369] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  469.487659] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  469.487684] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  469.488466] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  469.488492] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  469.489195] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  469.490059] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  469.491579] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  469.491599] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  469.491616] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  469.491634] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  469.492489] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  469.493200] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  469.494154] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  469.494158] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  469.494161] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  469.494163] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  469.494244] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  469.494247] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  469.494251] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  469.494253] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  469.494258] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  469.494260] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  469.494268] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  469.494271] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  469.494274] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  469.494277] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  469.494279] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  469.494282] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  469.494284] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  469.494287] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  469.494290] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  469.494292] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  469.494295] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  469.494297] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  469.494300] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  469.494303] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  469.494305] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  469.494308] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  469.494310] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  469.494313] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  469.494315] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  469.494318] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  469.494321] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  469.494323] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  469.494326] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  469.494328] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  469.494331] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  469.494618] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A
>[  469.494939] [drm:drm_mode_addfb2] [FB:61]
>[  469.499570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  469.499581] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  469.524356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  469.524467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  469.591462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.591664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  469.591747] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  469.591903] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  469.608436] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  469.608529] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  469.608653] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  469.608764] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  469.608863] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  469.609040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  469.609290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  469.609415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  469.609525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  469.609623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  469.609747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  469.609841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  469.609948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  469.610072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  469.610278] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  469.610407] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  469.610531] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  469.610651] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  469.610822] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  469.610977] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  469.611206] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  469.611354] [drm:intel_power_well_disable [i915]] disabling DC off
>[  469.611481] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  469.611595] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  469.612582] [drm:intel_power_well_disable [i915]] disabling always-on
>[  469.616376] [drm:drm_mode_addfb2] [FB:61]
>[  469.638620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  469.638670] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  469.638914] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  469.639013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  469.639263] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  469.639413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  469.639531] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  469.639627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  469.639719] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  469.639805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  469.639889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  469.639971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  469.640145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  469.640175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  469.640278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  469.640308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  469.640406] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  469.640501] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  469.640599] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  469.640713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.640807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  469.640939] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  469.641025] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  469.641202] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  469.641294] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  469.641386] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  469.641517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.641630] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  469.641716] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  469.643346] [drm:intel_power_well_enable [i915]] enabling always-on
>[  469.643422] [drm:intel_power_well_enable [i915]] enabling DC off
>[  469.643750] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  469.643853] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  469.643927] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  469.644237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  469.644355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  469.644442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  469.644523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  469.644599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  469.644677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  469.644760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  469.644835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  469.644923] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  469.645018] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  469.645212] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  469.645321] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  469.645451] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  469.645556] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  469.647895] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  469.647987] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  469.658394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.667403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.676389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.685359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.694147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.702787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.711357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.719886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.728395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.736886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.745376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.753839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.762302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.770761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.779219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.787677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.796138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.804597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.810692] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  469.871517] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  469.871539] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  469.871589] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  469.872438] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  469.873225] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  469.875800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  469.875820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  469.875838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  469.875857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  469.881244] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  469.881262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  469.886385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  469.888855] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  469.889391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  469.889446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  469.889462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  469.889484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  469.889533] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  469.889556] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  469.906238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  469.906264] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  469.906305] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  469.990403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.990805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  469.990974] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  469.991394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  470.008409] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  470.008501] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  470.008626] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  470.008738] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  470.008840] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  470.009020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  470.009284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  470.009377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  470.009467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  470.009552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  470.009645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  470.009725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  470.009827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  470.009962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  470.010183] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  470.010327] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  470.010462] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  470.010595] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  470.010828] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  470.010982] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  470.011263] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  470.011385] [drm:intel_power_well_disable [i915]] disabling DC off
>[  470.011483] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  470.011568] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  470.012151] [drm:intel_power_well_disable [i915]] disabling always-on
>[  470.014936] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  470.052006] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  470.052169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  470.052274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  470.052382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  470.052469] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  470.052561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  470.052654] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  470.052741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  470.052824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  470.052901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  470.052976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  470.053105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  470.053185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  470.053199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  470.053276] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  470.053350] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  470.053423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  470.053495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.053566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  470.053655] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  470.053732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  470.053805] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  470.053876] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  470.053947] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  470.054036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  470.054187] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  470.054274] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  470.054570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  470.054643] [drm:intel_power_well_enable [i915]] enabling DC off
>[  470.054972] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  470.055504] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  470.055605] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  470.055801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  470.055897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  470.055974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  470.056099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  470.056171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  470.056242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  470.056313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  470.056382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  470.056462] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  470.056550] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  470.056633] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  470.056713] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  470.056811] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  470.056892] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  470.058298] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  470.058383] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  470.068720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.077689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.086642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.095688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.104636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.113506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.122363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.131216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.140138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.148990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.157918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.166720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.175334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.183899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.192426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.200927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.209408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.217877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.220621] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  470.281783] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  470.281803] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  470.281832] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  470.282469] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  470.283277] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  470.284006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  470.284025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  470.284042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  470.284061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  470.289809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  470.289825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  470.294950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  470.297436] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  470.297971] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  470.298060] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  470.298076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  470.298099] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  470.298140] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  470.298156] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  470.314880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  470.314906] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  470.314950] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  470.315097] Console: switching to colour frame buffer device 200x56
>[  470.454862] Console: switching to colour dummy device 80x25
>[  470.455090] [IGT] kms_pipe_crc_basic: executing
>[  470.467753] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  470.467799] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  470.467817] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  470.467838] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  470.467875] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  470.469168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  470.469202] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  470.471167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  470.471178] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  470.473174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  470.473211] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  470.475164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  470.475175] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  470.475182] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  470.475210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  470.475249] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  470.476065] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  470.476120] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  470.476996] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  470.477913] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  470.479514] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  470.479549] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  470.479580] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  470.479610] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  470.480491] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  470.481245] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  470.482283] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  470.482288] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  470.482293] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  470.482297] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  470.482437] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  470.482442] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  470.482450] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  470.482454] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  470.482461] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  470.482465] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  470.482478] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  470.482483] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  470.482488] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  470.482492] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  470.482497] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  470.482502] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  470.482507] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  470.482511] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  470.482516] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  470.482520] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  470.482525] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  470.482530] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  470.482534] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  470.482539] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  470.482543] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  470.482548] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  470.482552] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  470.482557] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  470.482561] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  470.482566] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  470.482570] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  470.482575] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  470.482580] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  470.482584] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  470.482589] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  470.503044] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  470.503082] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  470.503097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  470.503504] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  470.503538] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  470.505776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  470.505814] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  470.508066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  470.508075] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  470.510313] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  470.510349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  470.512582] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  470.512591] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  470.512598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  470.513266] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  470.513304] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  470.514170] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  470.514211] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  470.514996] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  470.515972] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  470.517640] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  470.517674] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  470.517705] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  470.517735] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  470.518654] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  470.519473] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  470.520485] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  470.520491] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  470.520496] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  470.520500] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  470.520638] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  470.520642] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  470.520650] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  470.520654] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  470.520661] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  470.520665] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  470.520678] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  470.520683] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  470.520688] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  470.520693] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  470.520697] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  470.520702] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  470.520706] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  470.520711] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  470.520715] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  470.520720] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  470.520725] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  470.520729] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  470.520734] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  470.520738] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  470.520743] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  470.520747] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  470.520752] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  470.520757] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  470.520761] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  470.520766] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  470.520770] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  470.520775] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  470.520779] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  470.520784] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  470.520788] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  470.522086] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence
>[  470.522623] [drm:drm_mode_addfb2] [FB:61]
>[  470.529618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  470.529634] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  470.548440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  470.549109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  470.615763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  470.616407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  470.616591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  470.616909] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  470.632619] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  470.632710] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  470.632833] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  470.632945] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  470.633213] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  470.633486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  470.633625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  470.633730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  470.633844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  470.633941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  470.634150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  470.634252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  470.634365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  470.634474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  470.634610] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  470.634740] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  470.634872] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  470.634997] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  470.635265] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  470.635421] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  470.635584] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  470.635771] [drm:intel_power_well_disable [i915]] disabling DC off
>[  470.635917] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  470.636057] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  470.636715] [drm:intel_power_well_disable [i915]] disabling always-on
>[  470.640432] [drm:drm_mode_addfb2] [FB:61]
>[  470.662642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  470.662692] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  470.662939] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  470.663043] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  470.663837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  470.663948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  470.664035] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  470.664327] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  470.664468] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  470.664600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  470.664723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  470.664839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  470.664920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  470.664944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  470.665046] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  470.665174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  470.665276] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  470.665380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  470.665476] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  470.665574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.665666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  470.665782] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  470.665875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  470.665972] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  470.666144] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  470.666242] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  470.666380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  470.666524] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  470.666651] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  470.668354] [drm:intel_power_well_enable [i915]] enabling always-on
>[  470.668430] [drm:intel_power_well_enable [i915]] enabling DC off
>[  470.668753] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  470.668855] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  470.668956] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  470.669309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  470.669464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  470.669598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  470.669723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  470.669845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  470.669940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  470.670027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  470.670250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  470.670379] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  470.670522] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  470.670656] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  470.670787] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  470.670934] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  470.671035] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  470.673497] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  470.673588] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  470.683996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.693181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.702159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.711145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.720155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.728958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.737651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.746205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.754722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.763219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.771697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.780162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.788620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.797081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.805539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.814000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.822457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.830916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.835128] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  470.897268] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  470.897300] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  470.897336] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  470.898168] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  470.898866] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  470.901446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  470.901466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  470.901484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  470.901503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  470.906921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  470.906938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  470.912065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  470.914543] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824a88
>[  470.915077] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  470.915125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  470.915142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  470.915165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  470.915300] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  470.915317] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  470.931917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  470.931944] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  470.932057] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.015488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  471.015608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  471.015658] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  471.015737] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  471.033842] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  471.033909] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  471.034001] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  471.034214] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  471.034304] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  471.034512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  471.034627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  471.034725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  471.034817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  471.034907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  471.034985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  471.035147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  471.035205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  471.035271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  471.035347] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  471.035416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.035483] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  471.035551] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  471.035644] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  471.035727] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  471.035815] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  471.035891] [drm:intel_power_well_disable [i915]] disabling DC off
>[  471.035952] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  471.036007] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  471.036527] [drm:intel_power_well_disable [i915]] disabling always-on
>[  471.038556] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  471.070344] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  471.070446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  471.070551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  471.070660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  471.070748] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  471.070842] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  471.070936] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  471.071023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  471.071247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  471.071329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  471.071409] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  471.071427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.071502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  471.071516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.071594] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  471.071669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  471.071743] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  471.071817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  471.071890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  471.071980] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  471.072112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  471.072187] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  471.072258] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  471.072331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  471.072421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  471.072522] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  471.072609] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  471.072897] [drm:intel_power_well_enable [i915]] enabling always-on
>[  471.072970] [drm:intel_power_well_enable [i915]] enabling DC off
>[  471.073351] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  471.073463] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  471.073562] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  471.073760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  471.073858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  471.073937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  471.074013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  471.074139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  471.074213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  471.074284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  471.074352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  471.074431] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  471.074521] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.074605] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  471.074685] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  471.074784] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  471.074865] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  471.076323] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  471.076409] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  471.086951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.096012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.105031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.114008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.123001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.132009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.140991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.149997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.158982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.168057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.177006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.185813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.194466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.203025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.211545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.220044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.228525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.236994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.237854] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  471.298521] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  471.298540] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  471.298568] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  471.299823] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  471.302401] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  471.303742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  471.303758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  471.303773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  471.303789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  471.308921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  471.308936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  471.314068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  471.316550] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  471.317099] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  471.317126] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  471.317142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  471.317165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  471.317299] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  471.317316] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  471.333924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  471.333950] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  471.334013] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.334170] Console: switching to colour frame buffer device 200x56
>[  471.476612] Console: switching to colour dummy device 80x25
>[  471.476770] [IGT] kms_pipe_crc_basic: executing
>[  471.489548] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  471.489593] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  471.489609] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  471.489629] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  471.489665] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  471.491173] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  471.491210] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  471.493169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  471.493179] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  471.495119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  471.495156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  471.497169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  471.497179] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  471.497186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  471.497210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  471.497249] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  471.498054] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  471.498111] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  471.498917] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  471.499783] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  471.501383] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  471.501417] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  471.501448] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  471.501478] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  471.502331] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  471.503106] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  471.504203] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  471.504209] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  471.504214] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  471.504218] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  471.504358] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  471.504362] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  471.504370] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  471.504374] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  471.504381] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  471.504385] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  471.504398] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  471.504404] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.504408] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  471.504413] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  471.504418] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  471.504422] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  471.504427] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  471.504432] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  471.504436] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.504441] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.504446] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  471.504450] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  471.504455] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  471.504460] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  471.504464] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  471.504469] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  471.504473] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  471.504478] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  471.504482] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  471.504487] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  471.504491] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  471.504496] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  471.504501] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.504505] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.504510] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  471.524909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  471.524946] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  471.524961] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  471.525475] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  471.525503] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  471.527727] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  471.527753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  471.529983] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  471.530013] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  471.532246] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  471.532275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  471.534507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  471.534515] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  471.534521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  471.534908] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  471.534939] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  471.535698] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  471.535732] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  471.536568] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  471.537420] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  471.538990] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  471.539030] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  471.539055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  471.539078] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  471.539900] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  471.540639] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  471.541603] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  471.541608] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  471.541612] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  471.541615] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  471.541727] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  471.541731] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  471.541737] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  471.541740] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  471.541747] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  471.541750] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  471.541760] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  471.541765] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.541769] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  471.541773] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  471.541776] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  471.541780] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  471.541784] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  471.541788] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  471.541791] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.541795] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.541799] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  471.541803] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  471.541806] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  471.541810] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  471.541814] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  471.541817] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  471.541821] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  471.541825] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  471.541829] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  471.541832] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  471.541836] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  471.541840] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  471.541843] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.541847] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.541851] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  471.542426] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B
>[  471.542880] [drm:drm_mode_addfb2] [FB:61]
>[  471.548134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  471.548191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  471.548276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  471.548304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  471.548352] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  471.552512] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  471.552531] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  471.552556] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  471.552579] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  471.552601] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  471.552639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  471.552660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  471.552677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  471.552694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  471.552711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  471.552728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  471.552744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  471.552760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  471.552777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  471.552797] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  471.552815] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.552832] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  471.552849] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  471.552874] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  471.552897] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  471.552922] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  471.552942] [drm:intel_power_well_disable [i915]] disabling DC off
>[  471.552959] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  471.552974] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  471.553418] [drm:intel_power_well_disable [i915]] disabling always-on
>[  471.553553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  471.553568] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  471.553632] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  471.553651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  471.553671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  471.553693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  471.553710] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  471.553729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  471.553747] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  471.553765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  471.553782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  471.553798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  471.553813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  471.553817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.553832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  471.553835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.553851] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  471.553866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  471.553881] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  471.553896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  471.553910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  471.553928] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  471.553943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  471.553957] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  471.553972] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  471.554010] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  471.554032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  471.554059] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  471.554079] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  471.554378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  471.554393] [drm:intel_power_well_enable [i915]] enabling DC off
>[  471.554660] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  471.554681] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  471.554698] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  471.554741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  471.554762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  471.554779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  471.554796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  471.554813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  471.554829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  471.554845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  471.554860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  471.554878] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  471.554897] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.554914] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  471.554931] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  471.554952] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  471.554970] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  471.557108] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  471.557127] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  471.566583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.575053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.583517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.591975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.600450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.608910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.617370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.625829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.634288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.642747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.651206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.659665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.668124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.676582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.685055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.693512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.701971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.710443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.718904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.719945] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  471.780727] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  471.780746] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  471.780790] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  471.781616] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  471.782315] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  471.784358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  471.784374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  471.784388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  471.784404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  471.791033] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  471.791049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  471.796168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  471.798637] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  471.799131] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  471.799173] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  471.799188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  471.799209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  471.815965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  471.816005] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  471.816044] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.832681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  471.899610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  471.899777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  471.899842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  471.899951] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  471.917173] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  471.917242] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  471.917340] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  471.917422] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  471.917559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  471.917636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  471.917700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  471.917762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  471.917822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  471.917886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  471.917944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  471.918000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  471.918247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  471.918359] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  471.918493] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.918647] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  471.918804] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  471.919014] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  471.919353] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  471.919556] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  471.919716] [drm:intel_power_well_disable [i915]] disabling DC off
>[  471.919865] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  471.920005] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  471.920649] [drm:intel_power_well_disable [i915]] disabling always-on
>[  471.925135] [drm:drm_mode_addfb2] [FB:61]
>[  471.947093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  471.947145] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  471.947396] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  471.947492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  471.947594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  471.947700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  471.947785] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  471.947876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  471.947968] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  471.948209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  471.948313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  471.948413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  471.948514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  471.948544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.948638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  471.948666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  471.948784] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  471.949644] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  471.949724] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  471.949801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  471.949875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  471.949970] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  471.950133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  471.950234] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  471.950328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  471.950423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  471.950538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  471.950677] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  471.950806] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  471.952584] [drm:intel_power_well_enable [i915]] enabling always-on
>[  471.952668] [drm:intel_power_well_enable [i915]] enabling DC off
>[  471.953000] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  471.953581] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  471.953702] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  471.953915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  471.954067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  471.954663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  471.954752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  471.954833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  471.954913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  471.954991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  471.955229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  471.955359] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  471.955497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  471.955625] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  471.955751] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  471.955894] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  471.956024] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  471.958422] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  471.958512] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  471.969002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.977993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.986976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  471.996183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.005151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.014112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.022924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.032048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.040934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.049895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.058634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.067247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.075798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.084316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.092812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.101293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.109759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.118218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.120941] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  472.181553] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  472.181574] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  472.181615] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  472.182707] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  472.183148] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  472.185412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  472.185432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  472.185450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  472.185470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  472.191220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  472.191237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  472.196362] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  472.198834] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  472.199380] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  472.199421] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  472.199438] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  472.199461] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  472.216212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  472.216239] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  472.216281] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  472.299869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  472.300003] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  472.300147] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  472.300249] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  472.316949] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  472.317137] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  472.317258] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  472.317374] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  472.317587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  472.317679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  472.317744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  472.317808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  472.317870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  472.317936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  472.317995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  472.318148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  472.318213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  472.318287] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  472.318355] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  472.318422] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  472.318484] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  472.318580] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  472.318663] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  472.318755] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  472.318823] [drm:intel_power_well_disable [i915]] disabling DC off
>[  472.318886] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  472.318940] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  472.319462] [drm:intel_power_well_disable [i915]] disabling always-on
>[  472.321722] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  472.355987] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  472.356147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  472.356252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  472.356360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  472.356448] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  472.356541] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  472.356635] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  472.356722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  472.356806] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  472.356887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  472.356966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  472.357058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  472.357170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  472.357191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  472.357268] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  472.357339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  472.357409] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  472.357478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  472.357546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  472.357632] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  472.357702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  472.357771] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  472.357840] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  472.357907] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  472.357993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  472.358148] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  472.358229] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  472.358523] [drm:intel_power_well_enable [i915]] enabling always-on
>[  472.358590] [drm:intel_power_well_enable [i915]] enabling DC off
>[  472.358911] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  472.359017] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  472.359171] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  472.359368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  472.359464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  472.359540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  472.359613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  472.359684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  472.359754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  472.359825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  472.359893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  472.359971] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  472.360113] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  472.360196] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  472.360276] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  472.360377] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  472.360458] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  472.362361] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  472.362447] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  472.372752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.381688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.390613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.399548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.408445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.417375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.426259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.435104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.443936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.452860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.461699] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.470531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.479164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.487735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.496263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.504769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.513258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.521749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.524490] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  472.585520] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  472.585538] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  472.585598] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  472.586281] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  472.587093] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  472.587818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  472.587836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  472.587853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  472.587871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  472.593640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  472.593657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  472.598801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  472.601288] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  472.601864] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  472.601912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  472.601930] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  472.601956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  472.602019] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  472.602037] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  472.618710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  472.618739] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  472.618787] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  472.618930] Console: switching to colour frame buffer device 200x56
>[  472.751255] Console: switching to colour dummy device 80x25
>[  472.751353] [IGT] kms_pipe_crc_basic: executing
>[  472.763405] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  472.763433] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  472.763446] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  472.763458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  472.763479] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  472.765150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  472.765172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  472.767149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  472.767155] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  472.769149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  472.769170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  472.771154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  472.771160] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  472.771164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  472.771178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  472.771201] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  472.771924] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  472.771950] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  472.772652] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  472.773477] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  472.775001] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  472.775021] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  472.775039] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  472.775056] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  472.775848] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  472.776557] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  472.777431] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  472.777434] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  472.777437] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  472.777439] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  472.777523] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  472.777526] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  472.777530] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  472.777533] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  472.777537] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  472.777539] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  472.777549] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  472.777552] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  472.777554] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  472.777557] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  472.777560] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  472.777563] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  472.777566] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  472.777568] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  472.777571] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  472.777574] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  472.777577] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  472.777579] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  472.777582] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  472.777585] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  472.777587] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  472.777590] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  472.777593] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  472.777595] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  472.777598] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  472.777600] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  472.777603] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  472.777606] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  472.777608] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  472.777611] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  472.777614] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  472.789162] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  472.789183] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  472.789195] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  472.789427] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  472.789447] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  472.791670] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  472.791691] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  472.793912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  472.793918] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  472.796210] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  472.796232] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  472.797916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  472.797921] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  472.797926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  472.798312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  472.798334] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  472.799110] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  472.799136] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  472.799830] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  472.800654] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  472.802182] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  472.802202] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  472.802220] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  472.802238] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  472.803067] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  472.803778] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  472.804657] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  472.804660] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  472.804663] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  472.804665] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  472.804746] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  472.804749] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  472.804753] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  472.804756] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  472.804760] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  472.804762] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  472.804770] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  472.804773] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  472.804776] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  472.804779] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  472.804781] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  472.804784] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  472.804787] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  472.804790] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  472.804792] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  472.804795] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  472.804798] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  472.804800] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  472.804803] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  472.804806] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  472.804808] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  472.804811] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  472.804814] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  472.804816] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  472.804819] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  472.804822] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  472.804824] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  472.804827] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  472.804830] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  472.804832] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  472.804835] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  472.805317] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B-frame-sequence
>[  472.805805] [drm:drm_mode_addfb2] [FB:61]
>[  472.810220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  472.810270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  472.810344] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  472.810368] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  472.810410] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  472.820713] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  472.820733] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  472.820760] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  472.820784] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  472.820805] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  472.820846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  472.820868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  472.820885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  472.820902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  472.820918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  472.820935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  472.820951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  472.820967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  472.821047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  472.821078] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  472.821110] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  472.821140] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  472.821170] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  472.821210] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  472.821251] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  472.821289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  472.821325] [drm:intel_power_well_disable [i915]] disabling DC off
>[  472.821354] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  472.821380] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  472.821803] [drm:intel_power_well_disable [i915]] disabling always-on
>[  472.821953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  472.821996] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  472.822067] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  472.822092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  472.822121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  472.822150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  472.822174] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  472.822201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  472.822227] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  472.822253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  472.822278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  472.822303] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  472.822327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  472.822333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  472.822357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  472.822363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  472.822384] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  472.822408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  472.822432] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  472.822456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  472.822479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  472.822505] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  472.822529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  472.822552] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  472.822575] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  472.822599] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  472.822626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  472.822654] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  472.822680] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  472.823007] [drm:intel_power_well_enable [i915]] enabling always-on
>[  472.823022] [drm:intel_power_well_enable [i915]] enabling DC off
>[  472.823299] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  472.823334] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  472.823359] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  472.823437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  472.823458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  472.823475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  472.823492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  472.823508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  472.823524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  472.823540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  472.823555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  472.823572] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  472.823591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  472.823609] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  472.823626] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  472.823647] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  472.823665] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  472.825811] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  472.825829] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  472.835389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.843871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.852349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.860826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.869303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.877779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.886255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.894731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.903201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.911660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.920119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.928577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.937036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.945494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.953952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.962462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.970921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.979378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.987837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  472.988876] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  473.049695] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  473.049715] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  473.049768] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  473.050608] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  473.051307] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  473.053084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  473.053104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  473.053122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.053141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  473.059010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  473.059029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  473.064156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  473.066611] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  473.067186] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  473.067217] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  473.067235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  473.067261] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  473.084045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  473.084073] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  473.084118] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.100703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  473.167746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.167910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  473.167976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  473.168277] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  473.185369] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  473.185461] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  473.185594] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  473.185702] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  473.185884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.185985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  473.186301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  473.186410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  473.186529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  473.186661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  473.186758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  473.186908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  473.187015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  473.187244] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  473.187374] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.187497] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  473.187617] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  473.187792] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  473.187947] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  473.188227] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  473.188365] [drm:intel_power_well_disable [i915]] disabling DC off
>[  473.188487] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  473.188598] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  473.189192] [drm:intel_power_well_disable [i915]] disabling always-on
>[  473.192899] [drm:drm_mode_addfb2] [FB:61]
>[  473.215372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  473.215423] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  473.215670] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  473.215765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  473.215864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  473.215970] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  473.216204] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  473.216356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  473.216476] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  473.216602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  473.216708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  473.216826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  473.216923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  473.216951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  473.217065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  473.217162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  473.217259] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  473.217369] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  473.217462] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  473.217565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  473.217654] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  473.217776] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  473.217867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  473.217973] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  473.218170] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  473.218285] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  473.218419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.218571] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated DPLL 1
>[  473.218679] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  473.220549] [drm:intel_power_well_enable [i915]] enabling always-on
>[  473.220631] [drm:intel_power_well_enable [i915]] enabling DC off
>[  473.220963] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  473.221541] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  473.221666] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  473.221905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.222029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  473.222246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  473.222358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  473.222457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  473.222558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  473.222654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  473.222771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  473.222902] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  473.223045] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.223275] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  473.223392] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  473.223550] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 39
>[  473.223679] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  473.226039] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  473.226207] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  473.236409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.245387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.254379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.263238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.272131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.280960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.289837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.298661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.307504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.316336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.325121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.333781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.342377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.350922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.359434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.367925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.376401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.384864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.389276] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  473.449195] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  473.449220] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  473.449260] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  473.449962] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  473.450775] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  473.451499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  473.451518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  473.451536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.451555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  473.457304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  473.457321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  473.462438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  473.464906] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  473.465411] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  473.465446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  473.465462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  473.465484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  473.482259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  473.482285] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  473.482327] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.566295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.566515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  473.566601] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  473.566742] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  473.583473] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  473.583565] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  473.583700] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 39
>[  473.583809] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  473.583992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.584316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  473.584460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  473.584590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  473.584715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  473.584847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  473.584967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  473.585184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  473.585313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  473.585457] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  473.585589] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.585717] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  473.585844] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  473.586022] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  473.586281] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  473.586447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  473.586581] [drm:intel_power_well_disable [i915]] disabling DC off
>[  473.586706] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  473.586820] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  473.587847] [drm:intel_power_well_disable [i915]] disabling always-on
>[  473.590463] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  473.625823] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  473.625923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  473.626026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  473.626192] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  473.626280] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  473.626373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  473.626465] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  473.626552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  473.626638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  473.626719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  473.626796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  473.626814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  473.626892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  473.626906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  473.626985] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  473.627143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  473.627220] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  473.627296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  473.627370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  473.627461] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  473.627537] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  473.627612] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  473.627686] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  473.627758] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  473.627847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.627949] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  473.628035] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  473.628397] [drm:intel_power_well_enable [i915]] enabling always-on
>[  473.628470] [drm:intel_power_well_enable [i915]] enabling DC off
>[  473.628796] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  473.628905] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  473.628980] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  473.629268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.629366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  473.629446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  473.629524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  473.629600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  473.629675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  473.629748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  473.629822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  473.629904] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  473.629998] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.630138] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  473.630225] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  473.630328] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  473.630413] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  473.632307] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  473.632391] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  473.642693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.651657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.660684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.669621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.678566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.687496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.696374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.705265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.714118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.722974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.731901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.740769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.749452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.758029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.766576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.775088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.783580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.792058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.794801] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  473.855198] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  473.855214] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  473.855239] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  473.856062] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  473.856782] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  473.858834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  473.858851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  473.858866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.858882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  473.865542] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  473.865559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  473.870690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  473.873176] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826fc8
>[  473.873709] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  473.873747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  473.873763] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  473.873786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  473.873920] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  473.873936] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  473.890545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  473.890572] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  473.890616] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  473.890769] Console: switching to colour frame buffer device 200x56
>[  474.056206] Console: switching to colour dummy device 80x25
>[  474.056295] [IGT] kms_pipe_crc_basic: executing
>[  474.077317] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  474.077345] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  474.077360] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  474.077377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  474.077399] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  474.079152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  474.079173] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  474.081149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  474.081156] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  474.083151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  474.083174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  474.085157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  474.085164] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  474.085169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  474.085184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  474.085210] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  474.085946] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  474.085975] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  474.086805] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  474.087636] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  474.089188] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  474.089211] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  474.089232] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  474.089252] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  474.090071] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  474.090794] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  474.091702] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  474.091705] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  474.091709] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  474.091712] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  474.091806] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  474.091809] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  474.091814] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  474.091817] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  474.091822] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  474.091825] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  474.091834] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  474.091837] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.091841] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  474.091844] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  474.091847] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  474.091851] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  474.091854] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  474.091857] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  474.091860] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  474.091863] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  474.091866] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  474.091869] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  474.091872] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  474.091876] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  474.091879] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  474.091882] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  474.091885] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  474.091888] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  474.091891] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  474.091894] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  474.091897] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  474.091900] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  474.091903] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  474.091906] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  474.091909] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  474.105417] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  474.105442] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  474.105454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  474.105735] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  474.105758] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  474.107988] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  474.108032] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  474.110260] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  474.110267] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  474.112496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  474.112520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  474.114745] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  474.114752] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  474.114756] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  474.115160] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  474.115185] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  474.115920] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  474.115949] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  474.116682] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  474.117529] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  474.119073] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  474.119096] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  474.119117] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  474.119137] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  474.119943] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  474.120668] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  474.121590] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  474.121594] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  474.121597] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  474.121600] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  474.121695] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  474.121698] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  474.121703] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  474.121706] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  474.121711] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  474.121714] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  474.121722] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  474.121726] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.121729] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  474.121733] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  474.121736] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  474.121739] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  474.121742] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  474.121745] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  474.121748] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  474.121751] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  474.121754] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  474.121757] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  474.121761] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  474.121764] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  474.121767] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  474.121770] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  474.121773] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  474.121776] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  474.121779] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  474.121782] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  474.121785] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  474.121788] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  474.121791] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  474.121794] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  474.121797] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  474.122244] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C
>[  474.122812] [drm:drm_mode_addfb2] [FB:61]
>[  474.127911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  474.127967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.128113] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  474.128141] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  474.128190] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  474.140901] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  474.140921] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  474.140947] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  474.140971] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  474.141051] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  474.141125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  474.141160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  474.141187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  474.141218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  474.141245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  474.141275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  474.141300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  474.141327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  474.141355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  474.141386] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  474.141416] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.141443] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  474.141470] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  474.141508] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.141547] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.141587] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  474.141618] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.141644] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.141667] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.142116] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.142245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  474.142621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  474.142632] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  474.142676] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  474.142695] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  474.142715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  474.142737] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  474.142755] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  474.142773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  474.142792] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  474.142809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  474.142826] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  474.142842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  474.142858] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  474.142862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.142877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  474.142880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.142896] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  474.142911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  474.142925] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  474.142940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  474.142955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  474.142973] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  474.143020] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  474.143041] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  474.143066] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  474.143090] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  474.143117] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.143146] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  474.143173] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  474.143497] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.143520] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.143795] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.143825] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.143849] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.143895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  474.143924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  474.143949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  474.143974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  474.144024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  474.144050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  474.144075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  474.144098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  474.144124] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  474.144152] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.144178] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  474.144203] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  474.144232] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  474.144258] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  474.146409] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  474.146428] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  474.156008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.164489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.172968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.181464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.189942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.198421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.206888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.215348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.223808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.232265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.240738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.249197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.257655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.266113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.274570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.283028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.291485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.299943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.308401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.309439] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  474.370278] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  474.370300] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  474.370344] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  474.370962] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  474.371772] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  474.372490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  474.372510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  474.372528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  474.372547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  474.378285] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  474.378303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  474.383415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  474.385880] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258826678
>[  474.386390] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  474.386422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  474.386438] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  474.386461] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  474.403266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  474.403297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  474.403340] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.486969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.487219] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  474.487287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  474.487395] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  474.504393] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  474.504485] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  474.504617] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  474.504725] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  474.504908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  474.505008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  474.505347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  474.505478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  474.505603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  474.505740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  474.505857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  474.505978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  474.506175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  474.506310] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  474.506445] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.506574] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  474.506699] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  474.506874] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.507047] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.507323] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  474.507457] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.507585] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.507699] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.508714] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.512669] [drm:drm_mode_addfb2] [FB:61]
>[  474.534809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  474.534858] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  474.535282] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  474.535420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  474.535562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  474.535714] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  474.535844] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  474.535980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  474.536208] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  474.536322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  474.536454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  474.536573] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  474.536695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  474.536728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.536843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  474.536874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.536984] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  474.537159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  474.537264] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  474.537377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  474.537490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  474.537621] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  474.537744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  474.537867] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  474.537989] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  474.538160] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  474.538298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.538439] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  474.538564] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  474.540330] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.540404] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.540728] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.540827] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.540902] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.541290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  474.541433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  474.541536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  474.541649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  474.541744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  474.541854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  474.541948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  474.542060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  474.542264] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  474.542398] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.542529] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  474.542663] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  474.542804] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  474.542909] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  474.545365] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  474.545456] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  474.555766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.569284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.578187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.587110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.596005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.604962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.613851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.622675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.631504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.640268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.648899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.657462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.665985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.674501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.683003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.691474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.699932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.707715] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  474.768352] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  474.768371] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  474.768411] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  474.769244] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  474.769923] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  474.771692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  474.771711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  474.771729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  474.771747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  474.777623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  474.777641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  474.782806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  474.785460] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  474.787712] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  474.787876] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  474.787962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  474.788442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  474.804860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  474.804991] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  474.805570] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.888634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.888934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  474.889255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  474.889448] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  474.906179] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  474.906271] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  474.906405] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  474.906516] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  474.906700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  474.906802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  474.906887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  474.906969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  474.907157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  474.907247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  474.907322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  474.907396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  474.907482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  474.907577] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  474.907668] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.907754] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  474.907838] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  474.907969] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.908130] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.908250] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  474.908338] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.908419] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.908490] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.908965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.913520] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  474.944982] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  474.945279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  474.945383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  474.945491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  474.945580] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  474.945674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  474.945767] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  474.945854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  474.945939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  474.946021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  474.946230] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  474.946249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.946327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  474.946341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  474.946421] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  474.946497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  474.946572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  474.946645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  474.946718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  474.946807] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  474.946879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  474.946952] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  474.947024] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  474.947154] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  474.947245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.947347] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  474.947435] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  474.947712] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.947783] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.948163] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.948640] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.948735] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.948934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  474.949032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  474.949164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  474.949238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  474.949310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  474.949383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  474.949456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  474.949526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  474.949606] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  474.949695] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  474.949778] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  474.949859] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  474.949959] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  474.950039] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  474.952567] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  474.952654] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  474.963042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.972144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.981162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.990144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.999140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.008155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.017161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.026140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.035123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.043938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.052654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.061234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.069795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.078305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.086793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.095265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.103744] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.112207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.114949] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  475.175166] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  475.175183] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  475.175211] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  475.176036] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  475.176797] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  475.179387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  475.179406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  475.179424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  475.179442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  475.184834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  475.184850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  475.189984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  475.192385] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258822e98
>[  475.192919] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  475.192952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  475.192968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  475.193007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  475.193050] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  475.193066] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  475.209750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  475.209776] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  475.209820] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  475.210007] Console: switching to colour frame buffer device 200x56
>[  475.358679] Console: switching to colour dummy device 80x25
>[  475.358772] [IGT] kms_pipe_crc_basic: executing
>[  475.371498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  475.371524] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  475.371537] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  475.371548] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  475.371568] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  475.373167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  475.373190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  475.375163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  475.375172] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  475.377106] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  475.377128] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  475.379146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  475.379154] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  475.379159] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  475.379177] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  475.379199] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  475.379919] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  475.379943] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  475.380635] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  475.381472] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  475.382982] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  475.383010] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  475.383027] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  475.383043] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  475.383832] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  475.384535] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  475.385399] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  475.385402] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  475.385404] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  475.385407] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  475.385484] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  475.385487] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  475.385491] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  475.385493] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  475.385498] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  475.385500] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  475.385512] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  475.385516] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  475.385518] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  475.385521] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  475.385524] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  475.385526] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  475.385529] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  475.385531] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  475.385534] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  475.385536] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  475.385539] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  475.385541] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  475.385544] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  475.385546] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  475.385549] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  475.385551] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  475.385554] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  475.385556] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  475.385559] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  475.385561] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  475.385564] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  475.385566] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  475.385568] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  475.385571] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  475.385573] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  475.396245] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  475.396265] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  475.396276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  475.396510] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  475.396529] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  475.398753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  475.398773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  475.401042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  475.401051] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  475.403285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  475.403307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  475.405554] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  475.405563] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  475.405568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  475.405847] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  475.405870] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  475.406613] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  475.406638] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  475.407337] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  475.408158] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  475.409670] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  475.409689] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  475.409705] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  475.409722] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  475.410521] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  475.411230] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  475.412154] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  475.412158] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  475.412161] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  475.412163] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  475.412241] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  475.412244] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  475.412248] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  475.412250] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  475.412254] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  475.412256] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  475.412264] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  475.412267] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  475.412269] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  475.412272] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  475.412274] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  475.412277] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  475.412279] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  475.412282] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  475.412284] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  475.412287] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  475.412289] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  475.412292] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  475.412294] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  475.412297] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  475.412299] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  475.412302] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  475.412304] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  475.412307] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  475.412309] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  475.412312] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  475.412314] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  475.412317] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  475.412319] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  475.412322] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  475.412324] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  475.412614] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C-frame-sequence
>[  475.412910] [drm:drm_mode_addfb2] [FB:61]
>[  475.417133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  475.417181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  475.417251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  475.417273] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  475.417313] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  475.428193] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  475.428210] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  475.428234] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  475.428256] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  475.428275] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  475.428311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  475.428330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  475.428347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  475.428362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  475.428377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  475.428394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  475.428408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  475.428422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  475.428439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  475.428457] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  475.428474] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  475.428490] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  475.428506] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  475.428529] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  475.428551] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  475.428573] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  475.428592] [drm:intel_power_well_disable [i915]] disabling DC off
>[  475.428608] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  475.428621] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  475.429066] [drm:intel_power_well_disable [i915]] disabling always-on
>[  475.429195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  475.429568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  475.429578] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  475.429623] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  475.429641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  475.429659] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  475.429680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  475.429696] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  475.429713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  475.429731] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  475.429747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  475.429763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  475.429778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  475.429793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  475.429796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  475.429810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  475.429814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  475.429829] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  475.429843] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  475.429857] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  475.429871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  475.429884] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  475.429901] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  475.429915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  475.429929] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  475.429942] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  475.429956] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  475.429972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  475.430020] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  475.430041] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  475.430321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  475.430335] [drm:intel_power_well_enable [i915]] enabling DC off
>[  475.430600] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  475.430620] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  475.430636] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  475.430677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  475.430697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  475.430713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  475.430729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  475.430744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  475.430759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  475.430773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  475.430787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  475.430804] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  475.430822] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  475.430839] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  475.430855] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  475.430875] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  475.430891] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  475.433028] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  475.433045] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  475.442550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.451026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.459498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.467971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.476538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.485010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.493480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.501947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.510408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.518869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.527329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.535789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.544248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.552707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.561166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.569624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.578085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.586543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.594327] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  475.653933] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  475.653953] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  475.654004] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  475.655482] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  475.657226] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  475.659389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  475.659407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  475.659423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  475.659439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  475.664567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  475.664585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  475.669721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  475.672202] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  475.672685] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  475.672729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  475.672745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  475.672768] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  475.689524] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  475.689551] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  475.689592] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  475.773325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  475.773494] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  475.773560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  475.773670] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  475.790362] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  475.790453] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  475.790585] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  475.790692] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  475.790872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  475.790976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  475.791305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  475.791408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  475.791529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  475.791661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  475.791779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  475.791894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  475.792023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  475.792253] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  475.792387] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  475.792515] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  475.792641] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  475.792816] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  475.792978] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  475.793233] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  475.793399] [drm:intel_power_well_disable [i915]] disabling DC off
>[  475.793524] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  475.793638] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  475.794666] [drm:intel_power_well_disable [i915]] disabling always-on
>[  475.798949] [drm:drm_mode_addfb2] [FB:61]
>[  475.826736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  475.826785] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  475.827037] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  475.827269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  475.827402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  475.827554] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  475.827659] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  475.827794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  475.827903] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  475.828030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  475.828224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  475.828329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  475.828442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  475.828474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  475.828586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  475.828616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  475.828730] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  475.828824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  475.828930] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  475.829025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  475.829205] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  475.829321] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  475.829432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  475.829552] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  475.829648] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  475.829756] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  475.829880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  475.830025] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe C] allocated DPLL 1
>[  475.830217] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  475.832012] [drm:intel_power_well_enable [i915]] enabling always-on
>[  475.832220] [drm:intel_power_well_enable [i915]] enabling DC off
>[  475.832553] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  475.832660] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  475.832739] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  475.832943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  475.833054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  475.833470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  475.833599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  475.833724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  475.833846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  475.833939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  475.834020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  475.834218] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  475.834346] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  475.834479] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  475.834591] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  475.834747] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 46
>[  475.834878] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  475.837237] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  475.837328] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  475.847479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.856410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.865381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.874363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.883287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.892176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.901110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.909971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.918789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.927450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.936009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.944528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.953027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.961506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.969972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.978450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.986909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.995368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  475.999779] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  476.060611] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  476.060643] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  476.060691] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  476.061524] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  476.062247] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  476.064831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  476.064851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  476.064869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  476.064888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  476.070271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  476.070289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  476.075414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  476.077884] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  476.078444] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  476.078473] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  476.078490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  476.078512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  476.095267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  476.095294] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  476.095335] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  476.178997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  476.179267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  476.179336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  476.179444] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  476.195898] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  476.195992] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  476.196327] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 46
>[  476.196483] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  476.196759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  476.196906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  476.197036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  476.197305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  476.197427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  476.197560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  476.197674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  476.197791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  476.197914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  476.198061] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  476.198295] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  476.198433] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  476.198554] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  476.198729] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  476.198889] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  476.199072] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  476.199294] [drm:intel_power_well_disable [i915]] disabling DC off
>[  476.199419] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  476.199535] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  476.200525] [drm:intel_power_well_disable [i915]] disabling always-on
>[  476.203347] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  476.234057] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  476.234221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  476.234325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  476.234433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  476.234522] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  476.234615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  476.234710] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  476.234795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  476.234880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  476.234961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  476.235089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  476.235108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  476.235185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  476.235199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  476.235277] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  476.235352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  476.235426] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  476.235500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  476.235571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  476.235660] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  476.235734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  476.235807] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  476.235878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  476.235949] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  476.236037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  476.236192] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  476.236277] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  476.236579] [drm:intel_power_well_enable [i915]] enabling always-on
>[  476.236650] [drm:intel_power_well_enable [i915]] enabling DC off
>[  476.236976] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  476.237511] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  476.237615] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  476.237810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  476.237906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  476.237982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  476.238108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  476.238181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  476.238251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  476.238321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  476.238389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  476.238469] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  476.238557] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  476.238640] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  476.238722] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  476.238821] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  476.238901] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  476.240368] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  476.240454] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  476.250765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.259705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.268630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.277554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.286472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.295391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.304389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.313384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.322373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.331417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.340318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.348984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.357603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.366151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.374673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.383179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.391657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.400126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.401187] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  476.462238] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  476.462254] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  476.462318] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  476.462967] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  476.463777] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  476.464506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  476.464523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  476.464540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  476.464558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  476.470319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  476.470335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  476.475465] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  476.477951] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  476.478501] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  476.478575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  476.478591] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  476.478614] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  476.478748] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  476.478765] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  476.495373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  476.495399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  476.495443] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  476.495571] Console: switching to colour frame buffer device 200x56
>[  476.646734] Console: switching to colour dummy device 80x25
>[  476.646824] [IGT] kms_pipe_crc_basic: executing
>[  476.657335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  476.657362] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  476.657374] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  476.657385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  476.657405] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  476.659146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  476.659166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  476.661141] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  476.661147] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  476.663141] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  476.663161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  476.665139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  476.665144] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  476.665148] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  476.665161] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  476.665182] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  476.665898] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  476.665922] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  476.666671] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  476.667543] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  476.669048] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  476.669066] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  476.669083] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  476.669099] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  476.669886] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  476.670589] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  476.671451] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  476.671454] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  476.671457] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  476.671459] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  476.671540] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  476.671542] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  476.671546] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  476.671548] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  476.671552] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  476.671555] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  476.671562] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  476.671565] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  476.671567] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  476.671570] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  476.671572] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  476.671575] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  476.671577] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  476.671580] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  476.671582] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  476.671585] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  476.671587] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  476.671589] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  476.671592] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  476.671594] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  476.671597] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  476.671599] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  476.671601] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  476.671604] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  476.671606] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  476.671609] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  476.671611] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  476.671613] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  476.671616] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  476.671618] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  476.671621] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  476.682311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  476.682331] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  476.682342] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  476.682571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  476.682589] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  476.684816] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  476.684835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  476.687083] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  476.687091] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  476.689331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  476.689352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  476.691597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  476.691604] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  476.691609] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  476.691880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  476.691905] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  476.692641] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  476.692666] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  476.693353] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  476.694169] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  476.695674] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  476.695692] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  476.695709] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  476.695725] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  476.696523] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  476.697227] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  476.698144] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  476.698147] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  476.698150] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  476.698152] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  476.698235] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  476.698237] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  476.698241] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  476.698243] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  476.698247] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  476.698249] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  476.698257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  476.698260] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  476.698262] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  476.698265] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  476.698268] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  476.698270] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  476.698272] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  476.698275] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  476.698277] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  476.698280] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  476.698282] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  476.698285] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  476.698287] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  476.698290] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  476.698292] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  476.698294] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  476.698297] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  476.698299] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  476.698302] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  476.698304] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  476.698306] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  476.698309] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  476.698311] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  476.698314] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  476.698316] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  476.698597] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
>[  476.738903] PM: Syncing filesystems ... done.
>[  476.739065] PM: Preparing system for sleep (mem)
>[  476.741112] Freezing user space processes ... 
>[  496.742115] Freezing of tasks failed after 20.000 seconds (1 tasks refusing to freeze, wq_busy=0):
>[  496.742182] systemd-udevd   D    0   319    281 0x00000004
>[  496.742211] Call Trace:
>[  496.742246]  __schedule+0x30e/0xbd0
>[  496.742275]  schedule+0x3b/0x90
>[  496.742294]  schedule_timeout+0x23b/0x490
>[  496.742314]  ? _raw_spin_unlock_irq+0x27/0x50
>[  496.742331]  ? __this_cpu_preempt_check+0x13/0x20
>[  496.742351]  ? trace_hardirqs_on_caller+0xe7/0x200
>[  496.742375]  wait_for_common+0x11a/0x1d0
>[  496.742397]  ? wake_up_q+0x70/0x70
>[  496.742421]  wait_for_completion+0x18/0x20
>[  496.742439]  cpuhp_issue_call+0x9b/0xd0
>[  496.742458]  __cpuhp_setup_state+0xe9/0x170
>[  496.742480]  ? coretemp_remove+0x60/0x60 [coretemp]
>[  496.742496]  ? 0xffffffffa0275000
>[  496.742518]  coretemp_init+0x8b/0x1000 [coretemp]
>[  496.742539]  do_one_initcall+0x3f/0x170
>[  496.742558]  ? rcu_read_lock_sched_held+0x75/0x80
>[  496.742577]  ? kmem_cache_alloc_trace+0x274/0x2e0
>[  496.742592]  ? do_init_module+0x22/0x1fb
>[  496.742612]  do_init_module+0x5a/0x1fb
>[  496.742633]  load_module+0x2091/0x2410
>[  496.742648]  ? symbol_put_addr+0x60/0x60
>[  496.742679]  ? kernel_read_file+0x105/0x190
>[  496.742711]  SyS_finit_module+0xbc/0xf0
>[  496.742746]  entry_SYSCALL_64_fastpath+0x1c/0xb1
>[  496.742758] RIP: 0033:0x7f52a15708e9
>[  496.742770] RSP: 002b:00007ffedc0bbc38 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[  496.742793] RAX: ffffffffffffffda RBX: ffffffff81482393 RCX: 00007f52a15708e9
>[  496.742804] RDX: 0000000000000000 RSI: 00007f52a1a66e2a RDI: 0000000000000010
>[  496.742815] RBP: ffffc9000062ff88 R08: 0000000000000000 R09: 000055de625810a0
>[  496.742826] R10: 0000000000000010 R11: 0000000000000246 R12: 0000000000020000
>[  496.742836] R13: 000055de6253ea80 R14: 0000000000000000 R15: 000055de625810a0
>[  496.742855]  ? __this_cpu_preempt_check+0x13/0x20
>[  496.742929] Restarting tasks ... done.
>[  496.754458] [IGT] kms_pipe_crc_basic: exiting, ret=99
>[  496.786610] Console: switching to colour frame buffer device 200x56
>[  496.929180] Console: switching to colour dummy device 80x25
>[  496.929265] [IGT] kms_pipe_crc_basic: executing
>[  496.943341] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  496.943366] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  496.943378] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  496.943390] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  496.943409] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  496.945151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  496.945171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  496.947309] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  496.947315] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  496.949541] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  496.949561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  496.951784] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  496.951790] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  496.951793] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  496.951806] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  496.951828] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  496.952562] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  496.952588] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  496.953384] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  496.954202] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  496.955709] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  496.955728] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  496.955745] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  496.955761] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  496.956563] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  496.957272] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  496.958195] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  496.958198] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  496.958201] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  496.958203] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  496.958281] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  496.958284] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  496.958288] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  496.958290] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  496.958294] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  496.958296] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  496.958304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  496.958306] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  496.958309] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  496.958312] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  496.958314] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  496.958317] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  496.958319] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  496.958322] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  496.958324] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  496.958327] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  496.958329] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  496.958332] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  496.958334] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  496.958337] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  496.958339] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  496.958342] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  496.958344] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  496.958347] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  496.958349] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  496.958352] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  496.958354] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  496.958357] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  496.958359] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  496.958362] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  496.958364] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  496.969335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  496.969356] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  496.969367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  496.969604] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  496.969623] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  496.971149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  496.971169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  496.973389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  496.973394] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  496.975619] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  496.975640] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  496.977867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  496.977872] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  496.977876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  496.978280] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  496.978302] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  496.979122] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  496.979147] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  496.979830] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  496.980650] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  496.982239] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  496.982258] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  496.982274] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  496.982291] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  496.983171] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  496.983874] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  496.984739] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  496.984742] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  496.984745] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  496.984747] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  496.984824] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  496.984826] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  496.984830] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  496.984832] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  496.984837] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  496.984839] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  496.984846] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  496.984849] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  496.984852] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  496.984854] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  496.984857] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  496.984859] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  496.984862] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  496.984864] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  496.984867] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  496.984869] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  496.984872] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  496.984874] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  496.984877] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  496.984879] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  496.984882] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  496.984884] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  496.984887] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  496.984889] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  496.984892] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  496.984894] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  496.984897] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  496.984899] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  496.984902] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  496.984904] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  496.984906] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  496.985680] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
>[  497.016785] PM: Syncing filesystems ... done.
>[  497.016923] PM: Preparing system for sleep (mem)
>[  497.017458] Freezing user space processes ... 
>[  517.021933] Freezing of tasks failed after 20.004 seconds (1 tasks refusing to freeze, wq_busy=0):
>[  517.022108] systemd-udevd   D    0   319    281 0x00000004
>[  517.022138] Call Trace:
>[  517.022172]  __schedule+0x30e/0xbd0
>[  517.022201]  schedule+0x3b/0x90
>[  517.022220]  schedule_timeout+0x23b/0x490
>[  517.022239]  ? _raw_spin_unlock_irq+0x27/0x50
>[  517.022257]  ? __this_cpu_preempt_check+0x13/0x20
>[  517.022277]  ? trace_hardirqs_on_caller+0xe7/0x200
>[  517.022301]  wait_for_common+0x11a/0x1d0
>[  517.022323]  ? wake_up_q+0x70/0x70
>[  517.022347]  wait_for_completion+0x18/0x20
>[  517.022365]  cpuhp_issue_call+0x9b/0xd0
>[  517.022384]  __cpuhp_setup_state+0xe9/0x170
>[  517.022406]  ? coretemp_remove+0x60/0x60 [coretemp]
>[  517.022422]  ? 0xffffffffa0275000
>[  517.022445]  coretemp_init+0x8b/0x1000 [coretemp]
>[  517.022466]  do_one_initcall+0x3f/0x170
>[  517.022485]  ? rcu_read_lock_sched_held+0x75/0x80
>[  517.022505]  ? kmem_cache_alloc_trace+0x274/0x2e0
>[  517.022519]  ? do_init_module+0x22/0x1fb
>[  517.022540]  do_init_module+0x5a/0x1fb
>[  517.022561]  load_module+0x2091/0x2410
>[  517.022577]  ? symbol_put_addr+0x60/0x60
>[  517.022607]  ? kernel_read_file+0x105/0x190
>[  517.022640]  SyS_finit_module+0xbc/0xf0
>[  517.022675]  entry_SYSCALL_64_fastpath+0x1c/0xb1
>[  517.022687] RIP: 0033:0x7f52a15708e9
>[  517.022699] RSP: 002b:00007ffedc0bbc38 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[  517.022722] RAX: ffffffffffffffda RBX: ffffffff81482393 RCX: 00007f52a15708e9
>[  517.022733] RDX: 0000000000000000 RSI: 00007f52a1a66e2a RDI: 0000000000000010
>[  517.022744] RBP: ffffc9000062ff88 R08: 0000000000000000 R09: 000055de625810a0
>[  517.022755] R10: 0000000000000010 R11: 0000000000000246 R12: 0000000000020000
>[  517.022766] R13: 000055de6253ea80 R14: 0000000000000000 R15: 000055de625810a0
>[  517.022786]  ? __this_cpu_preempt_check+0x13/0x20
>[  517.022860] Restarting tasks ... done.
>[  517.033025] [IGT] kms_pipe_crc_basic: exiting, ret=99
>[  517.060443] Console: switching to colour frame buffer device 200x56
>[  517.153854] Console: switching to colour dummy device 80x25
>[  517.153943] [IGT] kms_pipe_crc_basic: executing
>[  517.162521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  517.162550] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  517.162563] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  517.162576] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  517.162598] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  517.164845] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  517.164869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  517.166177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  517.166185] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  517.168334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  517.168357] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  517.170171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  517.170179] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  517.170184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  517.170204] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  517.170228] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  517.170957] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  517.170989] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  517.171774] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  517.172598] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  517.174112] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  517.174133] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  517.174151] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  517.174169] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  517.174959] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  517.175671] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  517.176577] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  517.176580] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  517.176583] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  517.176586] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  517.176668] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  517.176670] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  517.176675] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  517.176678] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  517.176682] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  517.176684] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  517.176693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  517.176696] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  517.176699] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  517.176701] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  517.176704] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  517.176707] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  517.176710] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  517.176712] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  517.176715] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  517.176718] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  517.176720] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  517.176723] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  517.176726] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  517.176728] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  517.176731] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  517.176734] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  517.176736] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  517.176739] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  517.176742] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  517.176744] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  517.176747] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  517.176750] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  517.176752] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  517.176755] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  517.176758] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  517.188814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  517.188836] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  517.188848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  517.189168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  517.189188] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  517.191161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  517.191182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  517.193406] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  517.193412] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  517.195636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  517.195657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  517.197880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  517.197885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  517.197889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  517.198280] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  517.198303] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  517.199076] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  517.199102] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  517.199794] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  517.200616] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  517.202195] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  517.202215] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  517.202233] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  517.202250] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  517.203117] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  517.203823] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  517.204700] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  517.204703] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  517.204706] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  517.204709] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  517.204791] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  517.204793] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  517.204798] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  517.204800] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  517.204805] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  517.204807] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  517.204815] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  517.204818] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  517.204821] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  517.204823] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  517.204826] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  517.204829] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  517.204832] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  517.204834] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  517.204837] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  517.204840] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  517.204843] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  517.204845] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  517.204848] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  517.204851] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  517.204853] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  517.204856] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  517.204859] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  517.204861] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  517.204864] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  517.204867] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  517.204869] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  517.204872] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  517.204875] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  517.204877] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  517.204880] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  517.205755] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C
>[  517.238748] PM: Syncing filesystems ... done.
>[  517.239463] PM: Preparing system for sleep (mem)
>[  517.239810] Freezing user space processes ... 
>[  537.245717] Freezing of tasks failed after 20.005 seconds (1 tasks refusing to freeze, wq_busy=0):
>[  537.245781] systemd-udevd   D    0   319    281 0x00000004
>[  537.245811] Call Trace:
>[  537.245846]  __schedule+0x30e/0xbd0
>[  537.245874]  schedule+0x3b/0x90
>[  537.245893]  schedule_timeout+0x23b/0x490
>[  537.245913]  ? _raw_spin_unlock_irq+0x27/0x50
>[  537.245931]  ? __this_cpu_preempt_check+0x13/0x20
>[  537.245950]  ? trace_hardirqs_on_caller+0xe7/0x200
>[  537.246101]  wait_for_common+0x11a/0x1d0
>[  537.246124]  ? wake_up_q+0x70/0x70
>[  537.246148]  wait_for_completion+0x18/0x20
>[  537.246167]  cpuhp_issue_call+0x9b/0xd0
>[  537.246186]  __cpuhp_setup_state+0xe9/0x170
>[  537.246208]  ? coretemp_remove+0x60/0x60 [coretemp]
>[  537.246224]  ? 0xffffffffa0275000
>[  537.246246]  coretemp_init+0x8b/0x1000 [coretemp]
>[  537.246268]  do_one_initcall+0x3f/0x170
>[  537.246286]  ? rcu_read_lock_sched_held+0x75/0x80
>[  537.246305]  ? kmem_cache_alloc_trace+0x274/0x2e0
>[  537.246320]  ? do_init_module+0x22/0x1fb
>[  537.246341]  do_init_module+0x5a/0x1fb
>[  537.246362]  load_module+0x2091/0x2410
>[  537.246378]  ? symbol_put_addr+0x60/0x60
>[  537.246408]  ? kernel_read_file+0x105/0x190
>[  537.246440]  SyS_finit_module+0xbc/0xf0
>[  537.246475]  entry_SYSCALL_64_fastpath+0x1c/0xb1
>[  537.246487] RIP: 0033:0x7f52a15708e9
>[  537.246499] RSP: 002b:00007ffedc0bbc38 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[  537.246522] RAX: ffffffffffffffda RBX: ffffffff81482393 RCX: 00007f52a15708e9
>[  537.246533] RDX: 0000000000000000 RSI: 00007f52a1a66e2a RDI: 0000000000000010
>[  537.246544] RBP: ffffc9000062ff88 R08: 0000000000000000 R09: 000055de625810a0
>[  537.246555] R10: 0000000000000010 R11: 0000000000000246 R12: 0000000000020000
>[  537.246566] R13: 000055de6253ea80 R14: 0000000000000000 R15: 000055de625810a0
>[  537.246586]  ? __this_cpu_preempt_check+0x13/0x20
>[  537.246661] Restarting tasks ... done.
>[  537.257578] [IGT] kms_pipe_crc_basic: exiting, ret=99
>[  537.284748] Console: switching to colour frame buffer device 200x56
>[  537.426911] Console: switching to colour dummy device 80x25
>[  537.427036] [IGT] kms_setmode: executing
>[  537.440338] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
>[  537.440430] [IGT] kms_setmode: exiting, ret=0
>[  537.484572] Console: switching to colour frame buffer device 200x56
>[  537.622826] Console: switching to colour dummy device 80x25
>[  537.622917] [IGT] kms_sink_crc_basic: executing
>[  537.646224] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  537.646249] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  537.646261] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  537.646489] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  537.646509] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  537.648735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  537.648756] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  537.650931] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  537.650937] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  537.653156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  537.653176] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  537.655399] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  537.655405] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  537.655409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  537.655678] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  537.655701] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  537.656435] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  537.656460] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  537.657157] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  537.657972] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  537.659505] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  537.659524] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  537.659542] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  537.659559] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  537.660355] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  537.661076] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  537.661940] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  537.661943] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  537.661946] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  537.661948] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  537.662074] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  537.662078] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  537.662085] [drm:drm_mode_debug_printmodeline] Modeline 106:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  537.662088] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  537.662092] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  537.662094] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  537.662102] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  537.662105] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  537.662108] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  537.662110] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  537.662113] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  537.662115] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  537.662118] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  537.662121] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  537.662123] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  537.662126] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  537.662128] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  537.662131] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  537.662134] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  537.662136] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  537.662139] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  537.662141] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  537.662144] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  537.662146] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  537.662149] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  537.662151] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  537.662154] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  537.662157] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  537.662159] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  537.662162] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  537.662164] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  537.662431] [IGT] kms_sink_crc_basic: exiting, ret=77
>[  537.684531] Console: switching to colour frame buffer device 200x56
>[  537.776127] Console: switching to colour dummy device 80x25
>[  537.776222] [IGT] pm_backlight: executing
>[  537.776361] [IGT] pm_backlight: exiting, ret=77
>[  537.784570] Console: switching to colour frame buffer device 200x56
>[  537.881124] Console: switching to colour dummy device 80x25
>[  537.881215] [IGT] pm_rpm: executing
>[  537.895768] [drm:drm_mode_addfb2] [FB:64]
>[  538.931341] [IGT] pm_rpm: starting subtest basic-pci-d3-state
>[  538.931526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  538.931761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  538.932357] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  538.932557] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  538.932873] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  538.936900] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  538.937027] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  538.937375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  538.937552] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  538.937715] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  538.938036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  538.938287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  538.938393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  538.938492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  538.938589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  538.938693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  538.938787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  538.938878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  538.938983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  538.939268] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  538.939422] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  538.939569] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  538.939713] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  538.939905] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  538.940156] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  538.940349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  538.940518] [drm:intel_power_well_disable [i915]] disabling DC off
>[  538.940660] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  538.940768] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  538.941686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  538.941958] [drm:intel_runtime_suspend [i915]] Suspending device
>[  538.942786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  538.943306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  538.944049] [drm:intel_runtime_suspend [i915]] Device suspended
>[  539.046623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  539.046642] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  539.046741] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  539.046777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  539.046815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  539.046855] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  539.046887] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  539.046922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  539.046956] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  539.046988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  539.047195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  539.047242] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  539.047288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  539.047299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  539.047341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  539.047351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  539.047393] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  539.047437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  539.047478] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  539.047520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  539.047564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  539.047613] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  539.047655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  539.047698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  539.047740] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  539.047783] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  539.047832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  539.047884] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  539.047931] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  539.060508] [drm:intel_runtime_resume [i915]] Resuming device
>[  539.069690] [drm:intel_runtime_resume [i915]] Device resumed
>[  539.071994] [drm:intel_power_well_enable [i915]] enabling always-on
>[  539.072019] [drm:intel_power_well_enable [i915]] enabling DC off
>[  539.072281] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  539.072303] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  539.072319] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  539.072369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  539.072393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  539.072412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  539.072429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  539.072446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  539.072462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  539.072478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  539.072493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  539.072511] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  539.072530] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  539.072548] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  539.072565] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  539.072587] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  539.072605] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  539.074762] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  539.074783] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  539.084363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.092856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.101340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.109807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.118266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.126724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.135182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.143638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.152098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.160556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.169013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.177472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.185929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.194386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.202842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.211299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.219756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.228213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.236004] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  539.295515] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  539.295535] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  539.295576] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  539.296471] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  539.298209] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  539.300093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  539.300109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  539.300123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  539.300139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  539.305254] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  539.305270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  539.310385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  539.312848] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  539.313341] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  539.313391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  539.313406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  539.313426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  539.313470] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  539.313491] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  539.330182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  539.330204] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  539.330239] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  539.330335] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  539.330362] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  539.330380] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  539.332071] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  539.332095] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  539.332798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  539.333020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  539.333069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  539.333286] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  539.334189] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  539.334195] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  539.336157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  539.336176] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  539.338147] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  539.338153] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  539.338157] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  539.338177] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  539.338923] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  539.338949] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  539.339713] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  539.340530] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  539.342059] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  539.342080] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  539.342099] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  539.342117] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  539.342921] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  539.343640] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  539.347764] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  539.347802] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  539.347837] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  539.347890] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  539.347923] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  539.347970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  539.348031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  539.348053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  539.348076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  539.348096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  539.348121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  539.348140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  539.348162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  539.348183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  539.348210] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  539.348236] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  539.348261] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  539.348286] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  539.348347] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  539.348616] [IGT] pm_rpm: exiting, ret=0
>[  539.358541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.367008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.375457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.383905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.392372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.400819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.409267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.417731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.426178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.434626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.443066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.451495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.459913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.468331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.476748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.485164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.493579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.501995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.510410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  539.511168] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  539.511223] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  539.511237] [drm:intel_power_well_disable [i915]] disabling DC off
>[  539.511251] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  539.511264] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  539.511667] [drm:intel_power_well_disable [i915]] disabling always-on
>[  539.511696] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  539.511788] [drm:intel_runtime_suspend [i915]] Suspending device
>[  539.511891] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  539.511909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  539.511928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  539.511947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  539.511963] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  539.511985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  539.512037] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  539.512055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  539.512073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  539.512090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  539.512110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  539.512116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  539.512131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  539.512136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  539.512152] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  539.512172] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  539.512186] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  539.512199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  539.512211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  539.512230] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  539.512243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  539.512255] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  539.512650] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  539.512667] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  539.512684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  539.512701] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  539.512716] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  539.514725] [drm:intel_runtime_suspend [i915]] Device suspended
>[  539.538591] [drm:intel_runtime_resume [i915]] Resuming device
>[  539.550452] [drm:intel_runtime_resume [i915]] Device resumed
>[  539.551378] [drm:intel_runtime_suspend [i915]] Suspending device
>[  539.558913] [drm:intel_runtime_suspend [i915]] Device suspended
>[  539.583550] [drm:intel_runtime_resume [i915]] Resuming device
>[  539.596217] [drm:intel_runtime_resume [i915]] Device resumed
>[  539.596313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  539.596391] [drm:intel_power_well_enable [i915]] enabling DC off
>[  539.596718] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  539.596831] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  539.596909] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  539.597394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  539.597543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  539.597650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  539.597768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  539.597866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  539.597980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  539.598179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  539.598295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  539.598409] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  539.598544] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  539.598673] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  539.598805] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  539.598949] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  539.599059] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  539.601528] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  539.601619] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  539.603892] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  539.605620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  539.605717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  539.605802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  539.605890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  539.611474] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  539.611567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  539.617212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  539.620005] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588253d8
>[  539.622629] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  539.622803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  539.622893] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  539.623010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  539.623849] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  539.623985] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  539.639790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  539.639920] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  539.640569] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  539.641054] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  539.641185] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  539.641292] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  539.643629] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  539.643718] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  539.646102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  539.646263] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  539.648630] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  539.648729] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  539.651563] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  539.651587] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  539.651605] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  539.651709] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  539.652758] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  539.652855] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  539.654228] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  539.655342] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  539.657349] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  539.657442] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  539.657526] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  539.657606] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  539.658689] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  539.659675] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  539.660650] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  539.660780] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  539.660808] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  539.660892] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  539.663270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  539.663369] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  539.665733] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  539.665757] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  539.668179] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  539.668278] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  539.670641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  539.670665] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  539.670682] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  539.670784] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  539.671831] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  539.671927] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  539.673185] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  539.674294] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  539.676301] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  539.676389] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  539.676471] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  539.676554] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  539.677707] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  539.678695] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  539.679666] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  539.690264] Console: switching to colour frame buffer device 200x56
>[  539.861334] Console: switching to colour dummy device 80x25
>[  539.861430] [IGT] pm_rpm: executing
>[  539.882610] [drm:drm_mode_addfb2] [FB:64]
>[  540.917870] [IGT] pm_rpm: starting subtest basic-rte
>[  540.918229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  540.918535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  540.918939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  540.919095] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  540.919319] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  540.925530] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  540.925559] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  540.925596] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  540.925631] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  540.925661] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  540.925718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  540.925748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  540.925773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  540.925797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  540.925820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  540.925845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  540.925867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  540.925889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  540.925914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  540.925942] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  540.925968] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  540.926052] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  540.926090] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  540.926152] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  540.926201] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  540.926255] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  540.926303] [drm:intel_power_well_disable [i915]] disabling DC off
>[  540.926342] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  540.926376] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  540.926805] [drm:intel_power_well_disable [i915]] disabling always-on
>[  540.926849] [drm:intel_runtime_suspend [i915]] Suspending device
>[  540.928404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  540.928864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  540.931535] [drm:intel_runtime_suspend [i915]] Device suspended
>[  541.029903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  541.029963] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  541.030678] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  541.030849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  541.030998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  541.031295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  541.031423] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  541.031587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  541.031747] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  541.031902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  541.032055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  541.032288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  541.032409] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  541.032448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  541.032560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  541.032593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  541.032739] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  541.032878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  541.033018] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  541.033478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  541.033617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  541.033762] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  541.033856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  541.033951] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  541.034051] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  541.034267] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  541.034405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  541.034550] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  541.034701] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  541.046210] [drm:intel_runtime_resume [i915]] Resuming device
>[  541.049669] [drm:intel_runtime_resume [i915]] Device resumed
>[  541.049966] [drm:intel_runtime_suspend [i915]] Suspending device
>[  541.052472] [drm:intel_runtime_suspend [i915]] Device suspended
>[  541.076250] [drm:intel_runtime_resume [i915]] Resuming device
>[  541.081579] [drm:intel_runtime_resume [i915]] Device resumed
>[  541.081631] [drm:intel_power_well_enable [i915]] enabling always-on
>[  541.081674] [drm:intel_power_well_enable [i915]] enabling DC off
>[  541.081963] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  541.082498] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  541.082555] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  541.082669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  541.082748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  541.082816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  541.082882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  541.082945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  541.083011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  541.083150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  541.083215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  541.083283] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  541.083355] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  541.083423] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  541.083494] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  541.083571] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  541.083640] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  541.085895] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  541.085945] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  541.096188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.105165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.114023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.122672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.131197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.139692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.148164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.156623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.165083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.173540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.181997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.190456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.198913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.207370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.215827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.224284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.232740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.241197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.248975] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  541.308322] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  541.308340] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  541.308374] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  541.309203] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  541.309882] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  541.312446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  541.312464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  541.312481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  541.312498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  541.317875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  541.317891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  541.323009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  541.325490] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588237e8
>[  541.325933] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  541.325964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  541.325979] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  541.326086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  541.326132] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  541.326154] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  541.342757] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  541.342781] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  541.342819] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  541.342928] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  541.342944] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  541.342968] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  541.343710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  541.343764] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  541.343785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  541.343827] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  541.345155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.345174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.347148] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.347155] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  541.349163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.349185] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.351324] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.351330] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  541.351335] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  541.351356] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  541.352143] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  541.352170] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  541.352877] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  541.353708] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  541.355247] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  541.355268] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  541.355286] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  541.355304] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  541.356137] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  541.356850] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  541.360575] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  541.360595] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  541.360624] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  541.360649] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  541.360672] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  541.360716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  541.360739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  541.360758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  541.360777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  541.360795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  541.360815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  541.360833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  541.360850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  541.360869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  541.360891] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  541.360911] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  541.360931] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  541.360950] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  541.361027] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  541.361493] [IGT] pm_rpm: exiting, ret=0
>[  541.369915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.378403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.386864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.395323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.403790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.412256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.420722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.429187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.437651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.446116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.454582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.463049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.471482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.479904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.488321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.496739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.505156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.513573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.522004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  541.522357] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  541.522378] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  541.522392] [drm:intel_power_well_disable [i915]] disabling DC off
>[  541.522406] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  541.522418] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  541.522822] [drm:intel_power_well_disable [i915]] disabling always-on
>[  541.522828] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  541.522855] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  541.522870] [drm:intel_power_well_enable [i915]] enabling always-on
>[  541.522884] [drm:intel_power_well_enable [i915]] enabling DC off
>[  541.522898] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  541.522918] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  541.522934] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  541.523017] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  541.523042] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  541.523058] [drm:intel_power_well_disable [i915]] disabling DC off
>[  541.523075] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  541.523091] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  541.523502] [drm:intel_power_well_disable [i915]] disabling always-on
>[  541.523508] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  541.523532] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  541.523551] [drm:intel_power_well_enable [i915]] enabling always-on
>[  541.525773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.525791] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.528027] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.528033] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  541.530261] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.530279] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.532505] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.532510] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  541.532524] [drm:intel_power_well_disable [i915]] disabling always-on
>[  541.532529] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  541.532548] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  541.532561] [drm:intel_power_well_enable [i915]] enabling always-on
>[  541.532574] [drm:intel_power_well_enable [i915]] enabling DC off
>[  541.532834] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  541.532852] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  541.532868] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  541.533600] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  541.533624] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  541.534321] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  541.583979] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  541.584014] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  541.584055] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  541.584739] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  541.585547] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  541.586357] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  541.589375] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  541.589396] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  541.589415] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  541.589433] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  541.590875] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  541.592377] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  541.593127] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  541.593150] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  541.593165] [drm:intel_power_well_disable [i915]] disabling DC off
>[  541.593180] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  541.593193] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  541.593598] [drm:intel_power_well_disable [i915]] disabling always-on
>[  541.593603] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  541.593621] [drm:intel_runtime_suspend [i915]] Suspending device
>[  541.593728] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  541.593747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  541.593766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  541.593787] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  541.593803] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  541.593820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  541.593837] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  541.593853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  541.593868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  541.593883] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  541.593897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  541.593901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  541.593915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  541.593919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  541.593933] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  541.593947] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  541.593961] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  541.593974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  541.594025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  541.594046] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  541.594063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  541.594080] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  541.594097] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  541.594116] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  541.594137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  541.594160] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  541.594180] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  541.596199] [drm:intel_runtime_suspend [i915]] Device suspended
>[  541.620148] [drm:intel_runtime_resume [i915]] Resuming device
>[  541.623132] [drm:intel_runtime_resume [i915]] Device resumed
>[  541.623174] [drm:intel_power_well_enable [i915]] enabling always-on
>[  541.623192] [drm:intel_power_well_enable [i915]] enabling DC off
>[  541.623491] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  541.623516] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  541.623537] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  541.623593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  541.623618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  541.623639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  541.623658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  541.623676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  541.623694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  541.623712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  541.623729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  541.623748] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  541.623769] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  541.623789] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  541.623809] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  541.623833] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  541.623853] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  541.626007] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  541.626029] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  541.627272] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  541.628645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  541.628669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  541.628692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  541.628715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  541.633911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  541.633940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  541.639127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  541.641643] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258824138
>[  541.642564] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  541.642662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  541.642694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  541.642735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  541.642824] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  541.642870] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  541.659496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  541.659552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  541.659634] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  541.659856] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  541.659882] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  541.659941] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  541.662228] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.662279] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.664539] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.664552] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  541.666820] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.666873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.669146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.669159] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  541.669186] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  541.669258] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  541.670208] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  541.670281] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  541.671387] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  541.672405] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  541.674266] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  541.674332] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  541.674393] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  541.674452] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  541.675449] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  541.676351] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  541.677255] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  541.677366] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  541.677390] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  541.677461] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  541.679822] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.679923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.682371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  541.682396] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  541.684770] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.684871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  541.687233] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  541.687257] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  541.687274] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  541.687377] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  541.688434] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  541.688530] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  541.689900] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  541.691008] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  541.693162] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  541.693254] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  541.693338] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  541.693417] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  541.694507] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  541.695547] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  541.696568] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  541.710170] Console: switching to colour frame buffer device 200x56
>[  541.900620] Console: switching to colour dummy device 80x25
>[  541.900709] [IGT] pm_rps: executing
>[  541.923205] [IGT] pm_rps: starting subtest basic-api
>[  541.924715] [IGT] pm_rps: exiting, ret=0
>[  541.976676] Console: switching to colour frame buffer device 200x56
>[  542.113583] Console: switching to colour dummy device 80x25
>[  542.113670] [IGT] prime_busy: executing
>[  542.214662] [IGT] prime_busy: starting subtest basic-after-default
>[  543.150316] [IGT] prime_busy: exiting, ret=0
>[  543.193882] Console: switching to colour frame buffer device 200x56
>[  543.299279] Console: switching to colour dummy device 80x25
>[  543.299365] [IGT] prime_busy: executing
>[  543.327700] [IGT] prime_busy: starting subtest basic-before-default
>[  544.300432] [IGT] prime_busy: exiting, ret=0
>[  544.344288] Console: switching to colour frame buffer device 200x56
>[  544.447299] Console: switching to colour dummy device 80x25
>[  544.447386] [IGT] prime_busy: executing
>[  544.570455] [IGT] prime_busy: starting subtest basic-wait-after-default
>[  545.464444] [IGT] prime_busy: exiting, ret=0
>[  545.511477] Console: switching to colour frame buffer device 200x56
>[  545.614358] Console: switching to colour dummy device 80x25
>[  545.614447] [IGT] prime_busy: executing
>[  545.673953] [IGT] prime_busy: starting subtest basic-wait-before-default
>[  546.689384] [IGT] prime_busy: exiting, ret=0
>[  546.745264] Console: switching to colour frame buffer device 200x56
>[  546.880956] Console: switching to colour dummy device 80x25
>[  546.881103] [IGT] prime_self_import: executing
>[  546.881214] [IGT] prime_self_import: starting subtest basic-llseek-bad
>[  546.894354] [IGT] prime_self_import: exiting, ret=0
>[  546.944856] Console: switching to colour frame buffer device 200x56
>[  547.082590] Console: switching to colour dummy device 80x25
>[  547.082678] [IGT] prime_self_import: executing
>[  547.082774] [IGT] prime_self_import: starting subtest basic-llseek-size
>[  547.092702] [IGT] prime_self_import: exiting, ret=0
>[  547.144902] Console: switching to colour frame buffer device 200x56
>[  547.277756] Console: switching to colour dummy device 80x25
>[  547.277843] [IGT] prime_self_import: executing
>[  547.277935] [IGT] prime_self_import: starting subtest basic-with_fd_dup
>[  547.298854] [IGT] prime_self_import: exiting, ret=0
>[  547.345042] Console: switching to colour frame buffer device 200x56
>[  547.499714] Console: switching to colour dummy device 80x25
>[  547.499802] [IGT] prime_self_import: executing
>[  547.499897] [IGT] prime_self_import: starting subtest basic-with_one_bo
>[  547.535041] [IGT] prime_self_import: exiting, ret=0
>[  547.561656] Console: switching to colour frame buffer device 200x56
>[  547.683530] Console: switching to colour dummy device 80x25
>[  547.683619] [IGT] prime_self_import: executing
>[  547.683715] [IGT] prime_self_import: starting subtest basic-with_one_bo_two_files
>[  547.692447] [IGT] prime_self_import: exiting, ret=0
>[  547.745263] Console: switching to colour frame buffer device 200x56
>[  547.883399] Console: switching to colour dummy device 80x25
>[  547.883490] [IGT] prime_self_import: executing
>[  547.883605] [IGT] prime_self_import: starting subtest basic-with_two_bos
>[  547.904376] [IGT] prime_self_import: exiting, ret=0
>[  547.945692] Console: switching to colour frame buffer device 200x56
>[  548.069827] Console: switching to colour dummy device 80x25
>[  548.069918] [IGT] prime_vgem: executing
>[  548.099178] [IGT] prime_vgem: starting subtest basic-busy-default
>[  548.111094] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  548.112312] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  548.112420] [IGT] prime_vgem: exiting, ret=0
>[  548.162771] Console: switching to colour frame buffer device 200x56
>[  548.300271] Console: switching to colour dummy device 80x25
>[  548.300727] [IGT] prime_vgem: executing
>[  548.345851] [IGT] prime_vgem: starting subtest basic-fence-flip
>[  548.345925] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  548.349823] [drm:drm_mode_addfb2] [FB:61]
>[  548.349863] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  548.353618] [drm:drm_mode_addfb2] [FB:78]
>[  548.353687] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  548.353735] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  548.353754] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  548.353765] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  548.353805] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  548.355197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  548.355242] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  548.357187] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  548.357199] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  548.359186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  548.359231] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  548.361247] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  548.361259] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  548.361267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  548.361282] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  548.361329] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  548.362317] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  548.362365] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  548.363256] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  548.364186] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  548.365824] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  548.365869] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  548.365908] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  548.365945] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  548.366819] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  548.367593] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  548.368744] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  548.368750] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  548.368756] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  548.368761] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  548.368931] [drm:drm_mode_debug_printmodeline] Modeline 107:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  548.368937] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  548.368946] [drm:drm_mode_debug_printmodeline] Modeline 108:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  548.368951] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  548.368960] [drm:drm_mode_debug_printmodeline] Modeline 131:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  548.368965] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  548.369041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  548.369051] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  548.369060] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  548.369068] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  548.369078] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  548.369087] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  548.369095] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  548.369105] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  548.369114] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  548.369123] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  548.369132] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  548.369141] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  548.369150] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  548.369159] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  548.369168] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  548.369177] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  548.369187] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  548.369196] [drm:drm_mode_debug_printmodeline] Modeline 70:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  548.369204] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  548.369213] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  548.369222] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  548.369232] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  548.369240] [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  548.369249] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  548.369259] [drm:drm_mode_debug_printmodeline] Modeline 73:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  548.369381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  548.369410] [drm:drm_mode_setcrtc] [CONNECTOR:57:DP-2]
>[  548.369574] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  548.369621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  548.369676] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 78750KHz
>[  548.369736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  548.369779] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000
>[  548.369831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  548.369876] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  548.369926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  548.369969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64
>[  548.370046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  548.370086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  548.370099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  548.370141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  548.370151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  548.370198] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  548.370238] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750
>[  548.370283] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  548.370322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  548.370367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  548.370412] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  548.370460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  548.370502] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:79, fb = 1600x900 format = XR24 little-endian (0x34325258)
>[  548.370548] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1600+900 dst 0x0+1600+900
>[  548.370586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  548.370631] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  548.370676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  548.370731] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  548.370775] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  548.372527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  548.372576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  548.372673] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  548.380532] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  548.380569] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  548.380621] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  548.380668] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  548.380711] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  548.380759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  548.380801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  548.380837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  548.380872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  548.380905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  548.380939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  548.380972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  548.381189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  548.381233] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  548.381288] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  548.381345] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  548.381397] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  548.381455] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  548.381499] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  548.383694] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  548.383733] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  548.393448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.402031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.410552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.419040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.427502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.435960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.444536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.453072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.461531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.470003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.478459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.486917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.495374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.503831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.512287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.520745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.529202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.537658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  548.545240] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  548.605865] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  548.605885] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  548.605924] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  548.606764] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  548.607467] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  548.609235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  548.609255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  548.609273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  548.609292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  548.615165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  548.615183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  548.620307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  548.622757] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880258820008
>[  548.623274] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  548.623301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  548.623317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  548.623339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  548.623385] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  548.623410] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  548.636786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  548.636813] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  548.636851] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  548.957718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  548.958054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  548.958406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  548.958703] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  548.970825] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  548.970929] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  548.971074] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  548.971443] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  548.971604] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  548.971915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  548.972094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  548.972356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  548.972478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  548.972613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  548.972762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  548.972877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  548.973009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  548.973217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  548.973375] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  548.973529] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  548.973676] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  548.973821] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  548.974018] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  548.974282] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  548.974473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  548.974643] [drm:intel_power_well_disable [i915]] disabling DC off
>[  548.974800] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  548.974936] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  548.975965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  548.977374] [drm:intel_runtime_suspend [i915]] Suspending device
>[  548.978290] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  548.979689] [IGT] prime_vgem: exiting, ret=0
>[  548.987209] [drm:intel_runtime_suspend [i915]] Device suspended
>[  549.011655] [drm:intel_runtime_resume [i915]] Resuming device
>[  549.022133] [drm:intel_runtime_resume [i915]] Device resumed
>[  549.022996] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  549.023269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  549.023383] [drm:intel_power_well_enable [i915]] enabling DC off
>[  549.023748] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  549.024412] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  549.024541] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  549.024726] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  549.024920] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  549.025041] [drm:intel_power_well_disable [i915]] disabling DC off
>[  549.025285] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  549.025392] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  549.025916] [drm:intel_power_well_disable [i915]] disabling always-on
>[  549.025949] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  549.026094] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  549.026281] [drm:intel_power_well_enable [i915]] enabling always-on
>[  549.028364] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  549.028504] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  549.038239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  549.038277] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  549.040281] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  549.040420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  549.042478] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  549.042509] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  549.042587] [drm:intel_power_well_disable [i915]] disabling always-on
>[  549.042607] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  549.042708] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  549.042783] [drm:intel_power_well_enable [i915]] enabling always-on
>[  549.042852] [drm:intel_power_well_enable [i915]] enabling DC off
>[  549.043334] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  549.043739] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  549.043861] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  549.055550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.064427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.073349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.082206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.091064] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.100056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.108982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.117919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.126878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.135488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.144017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.152504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.160972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.169442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.177875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.186295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.194712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.203127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  549.205117] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  549.205140] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  549.205821] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  549.266559] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[  549.266582] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[  549.266619] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[  549.267242] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  549.268053] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  549.268897] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  549.271918] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  549.271939] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  549.271958] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  549.271977] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  549.273399] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  549.274825] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  549.275577] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  549.275600] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  549.275616] [drm:intel_power_well_disable [i915]] disabling DC off
>[  549.275631] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  549.275645] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  549.276540] [drm:intel_power_well_disable [i915]] disabling always-on
>[  549.276549] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  549.276574] [drm:intel_runtime_suspend [i915]] Suspending device
>[  549.277097] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  549.277123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  549.277148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  549.277175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  549.277199] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  549.277224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  549.277248] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  549.277271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  549.277294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  549.277315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  549.277337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  549.277343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  549.277363] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  549.277368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  549.277389] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  549.277410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  549.277431] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  549.277452] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  549.277473] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  549.277498] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  549.277519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  549.277540] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  549.277562] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  549.277583] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  549.277607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  549.277634] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  549.277657] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  549.279894] [drm:intel_runtime_suspend [i915]] Device suspended
>[  549.303159] [drm:intel_runtime_resume [i915]] Resuming device
>[  549.306146] [drm:intel_runtime_resume [i915]] Device resumed
>[  549.306186] [drm:intel_power_well_enable [i915]] enabling always-on
>[  549.306203] [drm:intel_power_well_enable [i915]] enabling DC off
>[  549.306505] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  549.306529] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  549.306546] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  549.306605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  549.306630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  549.306650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  549.306669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  549.306688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  549.306706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  549.306724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  549.306741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  549.306761] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  549.306782] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  549.306803] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  549.306822] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  549.306846] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  549.306867] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  549.309027] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  549.309048] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  549.310174] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  549.311529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  549.311551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  549.311571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  549.311591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  549.316808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  549.316832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  549.322034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  549.324547] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802588212a8
>[  549.325358] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  549.325409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  549.325436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  549.325471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  549.325534] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  549.325561] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  549.342254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  549.342310] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  549.342392] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  549.342603] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  549.342629] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  549.342689] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  549.344941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  549.344989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  549.347194] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  549.347204] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  549.349474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  549.349529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  549.351790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  549.351803] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  549.351812] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  549.351867] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  549.352733] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  549.352788] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  549.353782] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  549.354730] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  549.356463] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  549.356512] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  549.356556] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  549.356599] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  549.357607] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  549.358508] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  549.359407] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  549.359519] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  549.359544] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:DP-1] status updated from disconnected to disconnected
>[  549.359616] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  549.361927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  549.362003] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  549.364369] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  549.364387] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  549.366753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  549.366851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  549.369213] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  549.369237] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  549.369254] [drm:drm_helper_hpd_irq_event] [CONNECTOR:54:HDMI-A-1] status updated from disconnected to disconnected
>[  549.369357] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  549.370414] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  549.370513] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  549.371894] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  549.373009] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  549.375177] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  549.375269] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  549.375352] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  549.375433] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  549.376519] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  549.377573] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  549.378588] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:DP-2] status updated from connected to connected
>[  549.392829] Console: switching to colour frame buffer device 200x56
>[  549.571242] Console: switching to colour dummy device 80x25
>[  549.571345] [IGT] prime_vgem: executing
>[  549.611347] [IGT] prime_vgem: starting subtest basic-fence-mmap
>[  549.611412] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  549.619020] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  549.619107] [IGT] prime_vgem: exiting, ret=0
>[  549.676159] Console: switching to colour frame buffer device 200x56
>[  549.812355] Console: switching to colour dummy device 80x25
>[  549.812443] [IGT] prime_vgem: executing
>[  549.840508] [IGT] prime_vgem: starting subtest basic-fence-read
>[  549.840572] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  549.853519] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  549.853610] [IGT] prime_vgem: exiting, ret=0
>[  549.909312] Console: switching to colour frame buffer device 200x56
>[  550.042044] Console: switching to colour dummy device 80x25
>[  550.042130] [IGT] prime_vgem: executing
>[  550.078287] [IGT] prime_vgem: starting subtest basic-fence-wait-default
>[  550.090188] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  551.093634] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  551.094356] [IGT] prime_vgem: exiting, ret=0
>[  551.143765] Console: switching to colour frame buffer device 200x56
>[  551.254727] Console: switching to colour dummy device 80x25
>[  551.254820] [IGT] prime_vgem: executing
>[  551.283320] [IGT] prime_vgem: starting subtest basic-gtt
>[  551.283360] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  551.292315] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  551.292410] [IGT] prime_vgem: exiting, ret=0
>[  551.343394] Console: switching to colour frame buffer device 200x56
>[  551.483989] Console: switching to colour dummy device 80x25
>[  551.484084] [IGT] prime_vgem: executing
>[  551.504452] [IGT] prime_vgem: starting subtest basic-read
>[  551.504488] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  551.512719] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  551.512796] [IGT] prime_vgem: exiting, ret=0
>[  551.559960] Console: switching to colour frame buffer device 200x56
>[  551.689243] Console: switching to colour dummy device 80x25
>[  551.689330] [IGT] prime_vgem: executing
>[  551.718335] [IGT] prime_vgem: starting subtest basic-sync-default
>[  551.734029] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  551.735247] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  551.735351] [IGT] prime_vgem: exiting, ret=0
>[  551.777266] Console: switching to colour frame buffer device 200x56
>[  551.912660] Console: switching to colour dummy device 80x25
>[  551.912752] [IGT] prime_vgem: executing
>[  551.937285] [IGT] prime_vgem: starting subtest basic-wait-default
>[  551.953006] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  551.953773] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  551.953834] [IGT] prime_vgem: exiting, ret=0
>[  552.010643] Console: switching to colour frame buffer device 200x56
>[  552.149883] Console: switching to colour dummy device 80x25
>[  552.150006] [IGT] prime_vgem: executing
>[  552.177298] [IGT] prime_vgem: starting subtest basic-write
>[  552.177333] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  552.184661] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  552.184736] [IGT] prime_vgem: exiting, ret=0
>[  552.226920] Console: switching to colour frame buffer device 200x56
>[  552.374040] Console: switching to colour dummy device 80x25
>[  552.374132] [IGT] vgem_basic: executing
>[  552.393457] [IGT] vgem_basic: starting subtest create
>[  552.393504] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  552.393540] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1048576
>[  552.393569] [drm:vgem_gem_dumb_create [vgem]] Created object of size 2147483648
>[  552.393648] [IGT] vgem_basic: exiting, ret=0
>[  552.410172] Console: switching to colour frame buffer device 200x56
>[  552.530558] Console: switching to colour dummy device 80x25
>[  552.530660] [IGT] vgem_basic: executing
>[  552.543488] [IGT] vgem_basic: starting subtest debugfs
>[  552.543741] [IGT] vgem_basic: exiting, ret=0
>[  552.560195] Console: switching to colour frame buffer device 200x56
>[  552.695091] Console: switching to colour dummy device 80x25
>[  552.695185] [IGT] vgem_basic: executing
>[  552.710220] [IGT] vgem_basic: starting subtest dmabuf-export
>[  552.718416] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  552.718578] [IGT] vgem_basic: exiting, ret=0
>[  552.760366] Console: switching to colour frame buffer device 200x56
>[  552.885392] Console: switching to colour dummy device 80x25
>[  552.885480] [IGT] vgem_basic: executing
>[  552.893595] [IGT] vgem_basic: starting subtest dmabuf-fence
>[  552.893631] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  552.893760] [IGT] vgem_basic: exiting, ret=0
>[  552.910292] Console: switching to colour frame buffer device 200x56
>[  553.010453] Console: switching to colour dummy device 80x25
>[  553.010543] [IGT] vgem_basic: executing
>[  553.027105] [IGT] vgem_basic: starting subtest dmabuf-fence-before
>[  553.027147] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  553.027236] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  553.027356] [IGT] vgem_basic: exiting, ret=0
>[  553.043741] Console: switching to colour frame buffer device 200x56
>[  553.153704] Console: switching to colour dummy device 80x25
>[  553.153795] [IGT] vgem_basic: executing
>[  553.160326] [IGT] vgem_basic: starting subtest dmabuf-mmap
>[  553.160362] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  553.160568] [IGT] vgem_basic: exiting, ret=0
>[  553.177098] Console: switching to colour frame buffer device 200x56
>[  553.271101] Console: switching to colour dummy device 80x25
>[  553.271195] [IGT] vgem_basic: executing
>[  553.277089] [IGT] vgem_basic: starting subtest mmap
>[  553.277126] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  553.277248] [IGT] vgem_basic: exiting, ret=0
>[  553.293782] Console: switching to colour frame buffer device 200x56
>[  553.395407] Console: switching to colour dummy device 80x25
>[  553.395496] [IGT] vgem_basic: executing
>[  553.410426] [IGT] vgem_basic: starting subtest second-client
>[  553.443886] [IGT] vgem_basic: exiting, ret=0
>[  553.460552] Console: switching to colour frame buffer device 200x56
>[  553.589108] Console: switching to colour dummy device 80x25
>[  553.589196] [IGT] vgem_basic: executing
>[  553.593839] [IGT] vgem_basic: starting subtest sysfs
>[  553.594264] [IGT] vgem_basic: exiting, ret=0
>[  553.610528] Console: switching to colour frame buffer device 200x56
>[  553.708380] Console: switching to colour dummy device 80x25
>[  553.708469] [IGT] vgem_basic: executing
>[  553.708563] [IGT] vgem_basic: starting subtest unload
>[  553.729993] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  553.748619] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  553.768350] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  553.777212] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  553.799411] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  553.810578] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  553.830387] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  553.844072] [IGT] vgem_basic: exiting, ret=0
>[  553.860720] Console: switching to colour frame buffer device 200x56
>[  553.981057] Console: switching to colour dummy device 80x25
>[  553.981145] [IGT] drv_module_reload: executing
>[  553.981497] [IGT] drv_module_reload: starting subtest basic-reload
>[  554.040608] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  554.040639] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  554.040658] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  554.040681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  554.040697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  554.040713] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  554.040729] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  554.040744] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  554.078245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  554.078756] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  554.078856] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  554.096345] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  554.096400] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  554.096446] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  554.096519] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  554.096562] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  554.096621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  554.096648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  554.096670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  554.096692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  554.096713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  554.096735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  554.096755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  554.096775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  554.096797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  554.096821] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  554.096845] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  554.096867] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  554.096889] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  554.096931] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  554.097049] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  554.097106] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  554.097148] [drm:intel_power_well_disable [i915]] disabling DC off
>[  554.097181] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  554.097211] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  554.097636] [drm:intel_power_well_disable [i915]] disabling always-on
>[  554.113975] [drm:intel_power_well_enable [i915]] enabling always-on
>[  554.114032] [drm:intel_power_well_enable [i915]] enabling DC off
>[  554.114314] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  554.114378] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  554.114421] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  554.114569] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  554.114611] [drm:skl_set_power_well [i915]] Enabling DDI A/E IO power well
>[  554.114650] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  554.114691] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  554.114729] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  554.114769] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  554.114807] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  554.114847] [drm:skl_set_power_well [i915]] Enabling DDI D IO power well
>[  554.334070] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  554.334098] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  554.336524] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  554.336546] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  554.336565] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  554.336593] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  554.336621] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  554.336648] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  554.336675] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  554.336701] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  554.336727] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  554.336753] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  554.336779] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  554.336804] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  554.336830] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  554.336855] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  554.336880] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  554.336905] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  554.336930] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  554.336954] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  554.336979] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  554.337186] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  554.337213] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  554.337240] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  554.337266] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  554.337292] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  554.337317] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  554.337342] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  554.337368] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  554.337394] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  554.337419] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  554.337444] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  554.337469] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  554.337494] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  554.337518] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  554.337543] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  554.337568] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  554.339093] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  554.339115] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  554.339134] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  554.339153] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  554.339171] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  554.339188] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[  554.339206] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  554.339222] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  554.339239] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  554.339255] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  554.339274] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  554.339292] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  554.339314] [drm] Memory usable by graphics device = 4096M
>[  554.339336] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  554.339358] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  554.339365] [drm] Replacing VGA console driver
>[  554.339417] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  554.339504] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ab63018
>[  554.339545] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  554.339568] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  554.345091] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  554.345119] [drm:intel_opregion_setup [i915]] ASLE supported
>[  554.345143] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  554.345168] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  554.345345] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  554.345351] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  554.345353] [drm] Driver supports precise vblank timestamp query.
>[  554.345379] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  554.345404] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[  554.345428] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  554.345451] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  554.347116] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  554.347145] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  554.347170] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  554.347213] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  554.347218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  554.347240] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  554.347263] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  554.347284] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  554.347305] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  554.347329] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  554.347350] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  554.347371] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  554.347392] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  554.347412] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 10
>[  554.347432] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  554.347451] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 10
>[  554.347682] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  554.347718] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  554.347742] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  554.347797] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  554.347828] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  554.347857] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  554.347882] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  554.347905] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  554.347938] [drm:intel_power_well_enable [i915]] enabling always-on
>[  554.347958] [drm:intel_power_well_enable [i915]] enabling DC off
>[  554.347977] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  554.348453] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  554.348473] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  554.348492] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  554.348511] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  554.348530] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  554.348559] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[  554.349668] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[  554.351445] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  554.351481] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  554.351510] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  554.351536] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  554.351562] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  554.351587] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  554.351612] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  554.351635] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  554.351651] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  554.351677] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  554.351878] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  554.352226] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  554.352287] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  554.352397] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  554.352425] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  554.352446] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  554.352467] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  554.352533] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af05
>[  554.352590] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  554.352621] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  554.860405] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[  554.860572] [drm:wait_panel_status [i915]] Wait complete
>[  554.860752] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  554.860897] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  555.077321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.085773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.094220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.102665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.111112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.119557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.128004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.136448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.144894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.153341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.161787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.170232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.178677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.187122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.195566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.204010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.212454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.220901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.229359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.237806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.246251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.254705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.263153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.271597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.280041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.288485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.296927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.305370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.313812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.322255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.330711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.339154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  555.339164] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  555.339167] [drm] failed to retrieve link info, disabling eDP
>[  555.339226] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  555.339285] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[  555.339351] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  555.339390] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  555.339459] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  555.339497] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  555.339529] [drm:intel_ddi_init [i915]] VBT says port C has lspcon
>[  555.339560] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  555.339597] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  555.349109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.357535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.365958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.374409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.382830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.391251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.399684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.408105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.416524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.424944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.433362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.441781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.450199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.458620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.467041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.475460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.483880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.492299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.500718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  555.501435] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  555.502219] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  555.502875] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  555.502902] [drm:lspcon_init [i915]] LSPCON detected
>[  555.503598] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  555.565425] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  555.566579] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  555.567830] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  555.567969] [drm:lspcon_init [i915]] Success: LSPCON init
>[  555.568221] [drm:intel_ddi_init [i915]] LSPCON init success on port C
>[  555.568538] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  555.568694] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  555.568844] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  555.568988] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  555.569236] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  555.569413] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  555.569549] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  555.569682] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  555.569802] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:49:DP-MST A] hw state readout: disabled, pipe A
>[  555.569922] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DP-MST B] hw state readout: disabled, pipe B
>[  555.570045] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DP-MST C] hw state readout: disabled, pipe C
>[  555.570308] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI C] hw state readout: disabled, pipe A
>[  555.570471] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[  555.570586] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[  555.570700] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST C] hw state readout: disabled, pipe C
>[  555.570828] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:DP-1] hw state readout: disabled
>[  555.570953] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:54:HDMI-A-1] hw state readout: disabled
>[  555.571178] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-2] hw state readout: disabled
>[  555.571398] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  555.571581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  555.571760] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  555.571933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  555.571968] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  555.572435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  555.572467] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  555.572636] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  555.572760] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  555.572880] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  555.572996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  555.573404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  555.573595] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  555.573733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  555.573854] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  555.573973] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  555.574361] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  555.574544] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  555.574709] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  555.574825] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  555.574938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  555.574957] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  555.575094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  555.575349] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  555.575516] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  555.575682] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  555.575840] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  555.575955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  555.576089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  555.576493] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  555.576666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  555.576789] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  555.576908] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  555.577033] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  555.577435] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  555.577600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  555.577720] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  555.577831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  555.577852] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  555.577962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  555.578216] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  555.578385] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  555.578548] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  555.578668] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  555.578780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  555.578894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  555.579035] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  555.579446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  555.579617] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  555.579742] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  555.579858] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  555.579988] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  555.580713] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[  555.580883] [drm:skl_set_power_well [i915]] Disabling DDI D IO power well
>[  555.581002] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  555.581418] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  555.581592] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  555.581755] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  555.581867] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  555.581975] [drm:skl_set_power_well [i915]] Disabling DDI A/E IO power well
>[  555.582397] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  555.582661] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  555.582771] [drm:intel_power_well_disable [i915]] disabling DC off
>[  555.582886] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  555.582990] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  555.583772] [drm:intel_power_well_disable [i915]] disabling always-on
>[  555.584846] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/kbl_huc_ver02_00_1810.bin
>[  555.585002] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  555.586325] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/kbl_huc_ver02_00_1810.bin succeeded, fw ffff8802642b9148
>[  555.586462] [drm:intel_uc_fw_fetch [i915]] firmware version 2.0 OK (minimum 2.0)
>[  555.588292] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff88025bd08040
>[  555.588973] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  555.589707] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  555.590474] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  555.595765] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  555.595943] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  555.596634] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  555.596912] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  555.597484] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  555.597709] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  555.597736] [drm] GuC firmware load skipped
>[  555.599309] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  555.599490] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  555.599628] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  555.599757] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  555.608694] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  555.616795] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  555.620346] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  555.624549] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  555.671500] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  555.673267] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input10
>[  555.674515] [drm:drm_setup_crtcs] 
>[  555.674527] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  555.674600] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  555.674683] [drm:intel_power_well_enable [i915]] enabling always-on
>[  555.674755] [drm:intel_power_well_enable [i915]] enabling DC off
>[  555.675112] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  555.675567] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  555.675625] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  555.675760] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  555.675840] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  555.675898] [drm:intel_power_well_disable [i915]] disabling DC off
>[  555.675901] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  555.675904] [drm] DRM_I915_DEBUG enabled
>[  555.675909] [drm] DRM_I915_DEBUG_GEM enabled
>[  555.675961] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  555.676014] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  555.676503] [drm:intel_power_well_disable [i915]] disabling always-on
>[  555.676514] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to disconnected
>[  555.676538] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  555.676546] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  555.676614] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  555.676670] [drm:intel_power_well_enable [i915]] enabling always-on
>[  555.680264] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  555.680325] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  555.682186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  555.682196] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  555.684113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  555.684168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  555.686301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  555.686314] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  555.686366] [drm:intel_power_well_disable [i915]] disabling always-on
>[  555.686375] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] status updated from unknown to disconnected
>[  555.686382] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  555.686389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  555.686446] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  555.686497] [drm:intel_power_well_enable [i915]] enabling always-on
>[  555.686543] [drm:intel_power_well_enable [i915]] enabling DC off
>[  555.686834] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  555.686890] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  555.686934] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  555.688516] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  555.688578] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  555.689543] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  555.690445] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  555.692078] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  555.692128] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  555.692173] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  555.692208] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  555.693165] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  555.693929] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  555.696251] [drm:drm_dp_i2c_do_msg] native defer
>[  555.697305] [drm:drm_dp_i2c_do_msg] native defer
>[  555.698706] [drm:drm_dp_i2c_do_msg] native defer
>[  555.699763] [drm:drm_dp_i2c_do_msg] native defer
>[  555.701142] [drm:drm_dp_i2c_do_msg] native defer
>[  555.702269] [drm:drm_dp_i2c_do_msg] native defer
>[  555.703660] [drm:drm_dp_i2c_do_msg] native defer
>[  555.704714] [drm:drm_dp_i2c_do_msg] native defer
>[  555.706027] [drm:drm_dp_i2c_do_msg] native defer
>[  555.707157] [drm:drm_dp_i2c_do_msg] native defer
>[  555.708550] [drm:drm_dp_i2c_do_msg] native defer
>[  555.709649] [drm:drm_dp_i2c_do_msg] native defer
>[  555.711034] [drm:drm_dp_i2c_do_msg] native defer
>[  555.712162] [drm:drm_dp_i2c_do_msg] native defer
>[  555.713555] [drm:drm_dp_i2c_do_msg] native defer
>[  555.714613] [drm:drm_dp_i2c_do_msg] native defer
>[  555.716815] [drm:drm_dp_i2c_do_msg] native defer
>[  555.717927] [drm:drm_dp_i2c_do_msg] native defer
>[  555.719310] [drm:drm_dp_i2c_do_msg] native defer
>[  555.721040] [drm:drm_dp_i2c_do_msg] native defer
>[  555.722168] [drm:drm_dp_i2c_do_msg] native defer
>[  555.723563] [drm:drm_dp_i2c_do_msg] native defer
>[  555.724621] [drm:drm_dp_i2c_do_msg] native defer
>[  555.725944] [drm:drm_dp_i2c_do_msg] native defer
>[  555.727075] [drm:drm_dp_i2c_do_msg] native defer
>[  555.728480] [drm:drm_dp_i2c_do_msg] native defer
>[  555.729499] [drm:drm_dp_i2c_do_msg] native defer
>[  555.730788] [drm:drm_dp_i2c_do_msg] native defer
>[  555.731911] [drm:drm_dp_i2c_do_msg] native defer
>[  555.733308] [drm:drm_dp_i2c_do_msg] native defer
>[  555.734454] [drm:drm_dp_i2c_do_msg] native defer
>[  555.735493] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  555.736218] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  555.736252] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  555.736277] [drm:intel_power_well_disable [i915]] disabling DC off
>[  555.736302] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  555.736324] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  555.736737] [drm:intel_power_well_disable [i915]] disabling always-on
>[  555.736741] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] status updated from unknown to connected
>[  555.736893] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  555.736896] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  555.736900] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  555.736902] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  555.736951] [drm:drm_mode_debug_printmodeline] Modeline 82:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  555.736953] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  555.736958] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  555.736961] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  555.736966] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  555.736968] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  555.737000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  555.737005] [drm:drm_mode_debug_printmodeline] Modeline 62:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  555.737010] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  555.737015] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  555.737020] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  555.737025] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  555.737032] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  555.737038] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  555.737044] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  555.737049] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  555.737055] [drm:drm_mode_debug_printmodeline] Modeline 67:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  555.737060] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  555.737066] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  555.737072] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  555.737077] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  555.737083] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  555.737089] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  555.737094] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  555.737100] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  555.737105] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  555.737111] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  555.737117] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  555.737122] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  555.737127] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  555.737133] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  555.737150] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  555.737154] [drm:drm_setup_crtcs] connector 54 enabled? no
>[  555.737394] [drm:drm_setup_crtcs] connector 57 enabled? yes
>[  555.737435] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  555.737443] [drm:drm_setup_crtcs] looking for cmdline mode on connector 57
>[  555.737447] [drm:drm_setup_crtcs] looking for preferred mode on connector 57 0
>[  555.737450] [drm:drm_setup_crtcs] found mode 1600x900
>[  555.737454] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  555.737465] [drm:drm_setup_crtcs] desired mode 1600x900 set on crtc 32 (0,0)
>[  555.737518] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  555.737935] [drm:intelfb_create [i915]] allocated 1600x900 fb: 0x00040000
>[  555.738550] fbcon: inteldrmfb (fb0) is primary device
>[  555.738949] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  555.738979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  555.739041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  555.739071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  555.739096] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  555.739124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  555.739151] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  555.739176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  555.739201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  555.739224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  555.739247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  555.739250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  555.739273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  555.739276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  555.739299] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  555.739321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  555.739343] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  555.739364] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  555.739385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  555.739411] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  555.739433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  555.739455] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  555.739476] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  555.739498] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  555.739523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  555.739552] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  555.739577] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  555.739600] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  555.739767] [drm:intel_power_well_enable [i915]] enabling always-on
>[  555.739792] [drm:intel_power_well_enable [i915]] enabling DC off
>[  555.740084] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  555.740116] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  555.740149] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  555.740215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  555.740248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  555.740275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  555.740300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  555.740325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  555.740349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  555.740376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  555.740409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  555.740435] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  555.740462] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  555.740488] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  555.740514] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  555.740572] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  555.740600] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  555.742767] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  555.742793] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  555.743933] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  555.745291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  555.745318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  555.745343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  555.745369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  555.750514] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  555.750541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  555.755686] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  555.758168] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880261ca53d8
>[  555.758808] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  555.758864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  555.758890] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  555.758955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  555.759031] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  555.759061] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  555.775724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  555.775759] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  555.775811] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  555.775840] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  555.775988] Console: switching to colour frame buffer device 200x56
>[  555.795556] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  555.808526] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  555.834517] [drm] RC6 on
>[  555.834568] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  555.834597] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  555.834607] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  555.834616] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  555.834624] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  556.092752] [IGT] drv_module_reload: exiting, ret=0
>[  556.186795] Console: switching to colour dummy device 80x25
>[  556.186881] [IGT] drv_module_reload: executing
>[  556.187258] [IGT] drv_module_reload: starting subtest basic-no-display
>[  557.866203] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  557.866234] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  557.866255] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  557.866285] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  557.866304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  557.866322] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  557.866340] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  557.866358] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  557.874664] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input11
>[  557.876166] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input12
>[  557.876819] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input13
>[  557.877568] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input14
>[  557.878228] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input15
>[  557.878791] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input16
>[  557.965220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  557.965308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  557.965356] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  557.977975] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  557.978036] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  557.978075] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  557.978190] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  557.978233] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  557.978287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  557.978312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  557.978331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  557.978350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  557.978369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  557.978389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  557.978406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  557.978423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  557.978443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  557.978465] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  557.978486] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  557.978505] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  557.978524] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  557.978556] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  557.978602] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  557.978632] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  557.978655] [drm:intel_power_well_disable [i915]] disabling DC off
>[  557.978674] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  557.978691] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  557.979907] [drm:intel_power_well_disable [i915]] disabling always-on
>[  557.995586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  557.995607] [drm:intel_power_well_enable [i915]] enabling DC off
>[  557.995875] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  557.995901] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  557.995921] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  557.995974] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  557.996235] [drm:skl_set_power_well [i915]] Enabling DDI A/E IO power well
>[  557.996253] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  557.996271] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  557.996289] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  557.996307] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  557.996324] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  557.996342] [drm:skl_set_power_well [i915]] Enabling DDI D IO power well
>[  558.128818] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  558.128849] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  558.130305] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  558.130337] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  558.130367] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  558.130396] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  558.130424] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  558.130451] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  558.130479] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  558.130506] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  558.130534] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  558.130561] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  558.130588] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  558.130615] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  558.130642] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  558.130668] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  558.130694] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  558.130720] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  558.130746] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  558.130772] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  558.130798] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  558.130824] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  558.130850] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  558.130877] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  558.130903] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  558.130929] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  558.130955] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  558.130981] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  558.131038] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  558.131065] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  558.131091] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  558.131117] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  558.131143] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  558.131169] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  558.131196] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  558.131222] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  558.131247] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  558.133612] [drm] Display disabled (module parameter)
>[  558.133642] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  558.133665] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  558.133686] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  558.133706] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  558.133725] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  558.133744] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[  558.133763] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  558.133782] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  558.133800] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  558.133818] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  558.133839] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  558.133858] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  558.133886] [drm] Memory usable by graphics device = 4096M
>[  558.133910] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  558.133934] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  558.133941] [drm] Replacing VGA console driver
>[  558.134030] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  558.134155] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ab63018
>[  558.134211] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  558.134236] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  558.140156] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  558.140185] [drm:intel_opregion_setup [i915]] ASLE supported
>[  558.140211] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  558.140251] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  558.140427] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  558.140455] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  558.140480] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[  558.140505] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  558.140528] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  558.142650] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  558.142679] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  558.142705] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  558.142735] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  558.142739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  558.142763] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  558.142786] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  558.142809] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  558.142831] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  558.142857] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  558.142879] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  558.142901] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  558.142922] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  558.142943] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 10
>[  558.142964] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  558.142985] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 10
>[  558.143314] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  558.143352] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  558.143375] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  558.143438] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  558.143469] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  558.143498] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  558.143523] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  558.143546] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  558.143580] [drm:intel_power_well_enable [i915]] enabling always-on
>[  558.143600] [drm:intel_power_well_enable [i915]] enabling DC off
>[  558.143620] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  558.143644] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  558.143664] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  558.143683] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  558.143702] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  558.143720] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  558.143750] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[  558.145036] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[  558.145749] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  558.145787] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  558.145817] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  558.145845] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  558.145872] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  558.145899] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  558.145925] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  558.145951] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  558.145977] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  558.146069] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/kbl_huc_ver02_00_1810.bin
>[  558.146101] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  558.146326] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/kbl_huc_ver02_00_1810.bin succeeded, fw ffff880256faf2b8
>[  558.146356] [drm:intel_uc_fw_fetch [i915]] firmware version 2.0 OK (minimum 2.0)
>[  558.146731] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff8802608c8040
>[  558.146831] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  558.146929] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  558.147076] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  558.148056] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  558.148091] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  558.148149] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  558.148206] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  558.148261] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  558.148306] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  558.148312] [drm] GuC firmware load skipped
>[  558.149097] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  558.150135] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  558.150138] [drm] DRM_I915_DEBUG enabled
>[  558.150140] [drm] DRM_I915_DEBUG_GEM enabled
>[  558.154636] [IGT] drv_module_reload: exiting, ret=0
>[  558.156084] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  558.165683] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  558.165692] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  558.165696] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  558.165700] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  558.165703] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  558.174415] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  558.178223] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  558.189826] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input17
>[  558.190914] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input18
>[  558.240066] [IGT] drv_module_reload: executing
>[  558.240372] [IGT] drv_module_reload: starting subtest basic-reload-inject
>[  558.365897] Setting dangerous option inject_load_failure - tainting kernel
>[  558.376997] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  558.377054] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  558.378770] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  558.378804] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  558.378835] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  558.378865] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  558.378895] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  558.378924] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  558.378953] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  558.378981] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  558.379247] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  558.379276] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  558.379305] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  558.379333] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  558.379361] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  558.379388] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  558.379415] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  558.379442] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  558.379468] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  558.379495] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  558.379522] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  558.379548] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  558.379574] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  558.379601] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  558.379627] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  558.379653] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  558.379679] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  558.379705] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  558.379731] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  558.379757] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  558.379782] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  558.379808] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  558.379834] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  558.379859] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  558.379885] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  558.379911] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  558.379936] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  558.382824] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  558.382849] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  558.382871] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  558.382893] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  558.382913] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  558.382934] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[  558.382954] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  558.382975] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  558.383228] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  558.383248] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  558.383268] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  558.383287] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  558.383312] [drm] Memory usable by graphics device = 4096M
>[  558.383336] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  558.383359] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  558.383366] [drm] Replacing VGA console driver
>[  558.383421] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  558.383512] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ab63018
>[  558.383555] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  558.383580] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  558.389867] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  558.389896] [drm:intel_opregion_setup [i915]] ASLE supported
>[  558.389922] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  558.389947] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  558.390257] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  558.390263] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  558.390265] [drm] Driver supports precise vblank timestamp query.
>[  558.390292] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  558.390318] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[  558.390342] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  558.390365] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  558.392465] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  558.392494] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  558.392521] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  558.392551] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  558.392556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  558.392581] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  558.392605] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  558.392628] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  558.392651] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  558.392677] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  558.392701] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  558.392723] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  558.392745] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  558.392767] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 10
>[  558.392788] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  558.392809] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 10
>[  558.393302] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  558.393342] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  558.393366] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  558.393425] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  558.393455] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  558.393484] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  558.393511] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  558.393534] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  558.393569] [drm:intel_power_well_enable [i915]] enabling always-on
>[  558.393589] [drm:intel_power_well_enable [i915]] enabling DC off
>[  558.393609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  558.393632] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  558.393652] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  558.393671] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  558.393690] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  558.393708] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  558.393738] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[  558.395068] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[  558.396233] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  558.396273] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  558.396304] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  558.396334] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  558.396362] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  558.396389] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  558.396416] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  558.396443] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  558.396470] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  558.396508] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  558.396810] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  558.397171] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  558.397270] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  558.397394] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  558.397424] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  558.397449] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  558.397472] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  558.397539] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af05
>[  558.397600] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  558.397634] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  558.900403] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[  558.900569] [drm:wait_panel_status [i915]] Wait complete
>[  558.900754] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  558.900899] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  559.117240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.125689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.134136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.142579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.151036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.159478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.167922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.176363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.184809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.193252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.201695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.210138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.218579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.227035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.235477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.243919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.252362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.260804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.269246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.277686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.286129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.294571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.303014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.311455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.319897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.328339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.336784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.345226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.353668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.362109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.370550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.378992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  559.379015] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  559.379019] [drm] failed to retrieve link info, disabling eDP
>[  559.379076] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  559.379135] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[  559.379202] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  559.379241] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  559.379311] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  559.379350] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  559.379383] [drm:intel_ddi_init [i915]] VBT says port C has lspcon
>[  559.379413] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  559.379447] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  559.388903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.397326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.405747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.414168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.422588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.431009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.439430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.447850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.456270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.464689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.473109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.481530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.489951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.498371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.506792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.515212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.523632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.532052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.540470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  559.541186] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  559.541964] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  559.542655] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  559.542681] [drm:lspcon_init [i915]] LSPCON detected
>[  559.543367] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  559.604220] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  559.605072] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  559.605874] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  559.605900] [drm:lspcon_init [i915]] Success: LSPCON init
>[  559.605926] [drm:intel_ddi_init [i915]] LSPCON init success on port C
>[  559.605989] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  559.606052] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  559.606088] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  559.606121] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  559.606153] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  559.606184] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  559.606214] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  559.606245] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  559.606270] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:49:DP-MST A] hw state readout: disabled, pipe A
>[  559.606299] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DP-MST B] hw state readout: disabled, pipe B
>[  559.606324] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DP-MST C] hw state readout: disabled, pipe C
>[  559.606353] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI C] hw state readout: disabled, pipe A
>[  559.606377] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[  559.606403] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[  559.606427] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST C] hw state readout: disabled, pipe C
>[  559.606457] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:DP-1] hw state readout: disabled
>[  559.606486] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:54:HDMI-A-1] hw state readout: disabled
>[  559.606516] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-2] hw state readout: disabled
>[  559.606552] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  559.606579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  559.606608] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  559.606634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  559.606639] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  559.606666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  559.606671] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  559.606698] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  559.606723] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  559.606749] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  559.606774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  559.606800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  559.606831] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  559.606856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  559.606883] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  559.606907] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  559.606934] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  559.606962] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  559.606986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  559.607029] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  559.607053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  559.607060] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  559.607086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  559.607091] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  559.607118] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  559.607142] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  559.607168] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  559.607192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  559.607218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  559.607249] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  559.607274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  559.607301] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  559.607325] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  559.607352] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  559.607379] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  559.607403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  559.607428] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  559.607451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  559.607456] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  559.607481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  559.607486] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  559.607511] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  559.607534] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  559.607562] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  559.607585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  559.607611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  559.607638] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  559.607665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  559.607689] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  559.607715] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  559.607738] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  559.607766] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  559.607871] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[  559.607915] [drm:skl_set_power_well [i915]] Disabling DDI D IO power well
>[  559.607945] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  559.607974] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  559.608017] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  559.608046] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  559.608074] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  559.608101] [drm:skl_set_power_well [i915]] Disabling DDI A/E IO power well
>[  559.608128] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  559.608183] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  559.608210] [drm:intel_power_well_disable [i915]] disabling DC off
>[  559.608239] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  559.608265] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  559.608683] [drm:intel_power_well_disable [i915]] disabling always-on
>[  559.608727] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/kbl_huc_ver02_00_1810.bin
>[  559.608759] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  559.608978] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/kbl_huc_ver02_00_1810.bin succeeded, fw ffff8802584bc5c8
>[  559.609025] [drm:intel_uc_fw_fetch [i915]] firmware version 2.0 OK (minimum 2.0)
>[  559.609398] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff88025be70040
>[  559.609739] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  559.609819] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  559.609899] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  559.610840] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  559.610875] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  559.610934] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  559.611029] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  559.611105] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  559.611151] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  559.611157] [drm] GuC firmware load skipped
>[  559.613117] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  559.613145] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  559.613171] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  559.613195] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  559.615594] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  559.617977] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  559.618447] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  559.619239] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  559.630152] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  559.631378] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input19
>[  559.632138] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  559.632141] [drm] DRM_I915_DEBUG enabled
>[  559.632143] [drm] DRM_I915_DEBUG_GEM enabled
>[  559.632149] [drm:drm_setup_crtcs] 
>[  559.632156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  559.632200] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  559.632254] [drm:intel_power_well_enable [i915]] enabling always-on
>[  559.632296] [drm:intel_power_well_enable [i915]] enabling DC off
>[  559.632578] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  559.632616] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  559.632648] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  559.632729] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  559.632770] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  559.632799] [drm:intel_power_well_disable [i915]] disabling DC off
>[  559.632829] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  559.632856] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  559.633301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  559.633307] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to disconnected
>[  559.633321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  559.633326] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  559.633358] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  559.633385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  559.635122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  559.635170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  559.637086] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  559.637096] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  559.639259] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  559.639287] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  559.641108] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  559.641116] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  559.641149] [drm:intel_power_well_disable [i915]] disabling always-on
>[  559.641155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] status updated from unknown to disconnected
>[  559.641160] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  559.641165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  559.641203] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  559.641234] [drm:intel_power_well_enable [i915]] enabling always-on
>[  559.641256] [drm:intel_power_well_enable [i915]] enabling DC off
>[  559.641524] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  559.641549] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  559.641570] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  559.642377] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  559.642411] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  559.643122] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  559.643949] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  559.645671] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  559.645700] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  559.645725] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  559.645750] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  559.646575] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  559.647301] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  559.649665] [drm:drm_dp_i2c_do_msg] native defer
>[  559.650782] [drm:drm_dp_i2c_do_msg] native defer
>[  559.652094] [drm:drm_dp_i2c_do_msg] native defer
>[  559.653222] [drm:drm_dp_i2c_do_msg] native defer
>[  559.654606] [drm:drm_dp_i2c_do_msg] native defer
>[  559.655655] [drm:drm_dp_i2c_do_msg] native defer
>[  559.656968] [drm:drm_dp_i2c_do_msg] native defer
>[  559.658038] [drm:drm_dp_i2c_do_msg] native defer
>[  559.659351] [drm:drm_dp_i2c_do_msg] native defer
>[  559.660507] [drm:drm_dp_i2c_do_msg] native defer
>[  559.661762] [drm:drm_dp_i2c_do_msg] native defer
>[  559.662889] [drm:drm_dp_i2c_do_msg] native defer
>[  559.664276] [drm:drm_dp_i2c_do_msg] native defer
>[  559.666003] [drm:drm_dp_i2c_do_msg] native defer
>[  559.667127] [drm:drm_dp_i2c_do_msg] native defer
>[  559.669388] [drm:drm_dp_i2c_do_msg] native defer
>[  559.670498] [drm:drm_dp_i2c_do_msg] native defer
>[  559.671778] [drm:drm_dp_i2c_do_msg] native defer
>[  559.672892] [drm:drm_dp_i2c_do_msg] native defer
>[  559.674276] [drm:drm_dp_i2c_do_msg] native defer
>[  559.675402] [drm:drm_dp_i2c_do_msg] native defer
>[  559.676769] [drm:drm_dp_i2c_do_msg] native defer
>[  559.677885] [drm:drm_dp_i2c_do_msg] native defer
>[  559.679263] [drm:drm_dp_i2c_do_msg] native defer
>[  559.680393] [drm:drm_dp_i2c_do_msg] native defer
>[  559.681761] [drm:drm_dp_i2c_do_msg] native defer
>[  559.682883] [drm:drm_dp_i2c_do_msg] native defer
>[  559.684278] [drm:drm_dp_i2c_do_msg] native defer
>[  559.685428] [drm:drm_dp_i2c_do_msg] native defer
>[  559.686776] [drm:drm_dp_i2c_do_msg] native defer
>[  559.687905] [drm:drm_dp_i2c_do_msg] native defer
>[  559.689016] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  559.689732] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  559.689764] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  559.689787] [drm:intel_power_well_disable [i915]] disabling DC off
>[  559.689810] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  559.689830] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  559.690266] [drm:intel_power_well_disable [i915]] disabling always-on
>[  559.690273] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] status updated from unknown to connected
>[  559.690521] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  559.690525] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  559.690527] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  559.690530] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  559.690574] [drm:drm_mode_debug_printmodeline] Modeline 82:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  559.690576] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  559.690581] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  559.690583] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  559.690588] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  559.690590] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  559.690596] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  559.690599] [drm:drm_mode_debug_printmodeline] Modeline 62:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  559.690602] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  559.690604] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  559.690607] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  559.690610] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  559.690613] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  559.690615] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  559.690618] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  559.690620] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  559.690623] [drm:drm_mode_debug_printmodeline] Modeline 67:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  559.690626] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  559.690628] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  559.690631] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  559.690634] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  559.690636] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  559.690639] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  559.690642] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  559.690644] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  559.690647] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  559.690649] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  559.690652] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  559.690655] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  559.690657] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  559.690660] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  559.690670] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  559.690672] [drm:drm_setup_crtcs] connector 54 enabled? no
>[  559.690675] [drm:drm_setup_crtcs] connector 57 enabled? yes
>[  559.690705] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  559.690710] [drm:drm_setup_crtcs] looking for cmdline mode on connector 57
>[  559.690712] [drm:drm_setup_crtcs] looking for preferred mode on connector 57 0
>[  559.690714] [drm:drm_setup_crtcs] found mode 1600x900
>[  559.690716] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  559.690723] [drm:drm_setup_crtcs] desired mode 1600x900 set on crtc 32 (0,0)
>[  559.690757] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  559.691128] [drm:intelfb_create [i915]] allocated 1600x900 fb: 0x00040000
>[  559.691805] fbcon: inteldrmfb (fb0) is primary device
>[  559.692452] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  559.692489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  559.692526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  559.692564] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  559.692596] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  559.692632] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  559.692668] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  559.692701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  559.692734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  559.692766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  559.692797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  559.692801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  559.692831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  559.692835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  559.692865] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  559.692896] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  559.692926] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  559.692956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  559.692985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  559.693037] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  559.693068] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  559.693098] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  559.693129] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  559.693159] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  559.693193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  559.693231] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  559.693264] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  559.693298] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  559.693522] [drm:intel_power_well_enable [i915]] enabling always-on
>[  559.693557] [drm:intel_power_well_enable [i915]] enabling DC off
>[  559.693839] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  559.693882] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  559.693914] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  559.693999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  559.694051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  559.694081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  559.694112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  559.694138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  559.694168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  559.694194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  559.694221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  559.694247] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  559.694278] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  559.694308] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  559.694339] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  559.694408] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  559.694443] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  559.696124] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  559.696148] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  559.697264] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  559.698616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  559.698641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  559.698665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  559.698689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  559.703834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  559.703859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  559.709016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  559.711492] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880257465d28
>[  559.712114] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  559.712187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  559.712211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  559.712272] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  559.712317] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  559.712344] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  559.729109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  559.729143] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  559.729193] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  559.729222] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  559.729350] Console: switching to colour frame buffer device 200x56
>[  559.748466] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  559.759373] Console: switching to colour dummy device 80x25
>[  559.764218] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  559.788102] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  559.788129] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  559.788137] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  559.788144] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  559.788152] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  559.816890] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  559.816974] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  559.817159] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  559.817279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  559.817343] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  559.817414] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  559.817486] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  559.817555] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  559.851761] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input20
>[  559.855914] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input21
>[  559.858409] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input22
>[  559.860906] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input23
>[  559.863437] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input24
>[  559.865893] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input25
>[  559.944221] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  559.944271] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  559.944313] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  559.944351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  559.944382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  559.944413] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  559.944444] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  559.944474] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  559.976161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  559.976248] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  559.976295] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  559.980329] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  559.980352] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  559.980383] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  559.980451] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  559.980481] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  559.980521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  559.980539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  559.980555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  559.980569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  559.980583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  559.980598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  559.980612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  559.980625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  559.980640] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  559.980657] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  559.980673] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  559.980687] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  559.980702] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  559.980723] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  559.980756] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  559.980778] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  559.980795] [drm:intel_power_well_disable [i915]] disabling DC off
>[  559.980810] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  559.980822] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  559.981254] [drm:intel_power_well_disable [i915]] disabling always-on
>[  559.989935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  559.989950] [drm:intel_power_well_enable [i915]] enabling DC off
>[  559.989963] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  559.990013] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  559.990034] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  559.990084] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  559.990103] [drm:skl_set_power_well [i915]] Enabling DDI A/E IO power well
>[  559.990118] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  559.990137] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  559.990152] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  559.990170] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  559.990185] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  559.990203] [drm:skl_set_power_well [i915]] Enabling DDI D IO power well
>[  560.132776] Setting dangerous option inject_load_failure - tainting kernel
>[  560.148754] [drm] Injecting failure at checkpoint 1 [i915_driver_init_early:812]
>[  560.148795] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  560.156365] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  560.165702] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  560.165708] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  560.165710] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  560.165712] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  560.165714] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  560.176303] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  560.179001] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  560.191222] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input26
>[  560.192282] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input27
>[  560.264814] Setting dangerous option inject_load_failure - tainting kernel
>[  560.275484] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  560.275514] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  560.277296] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  560.277332] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  560.277365] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  560.277396] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  560.277426] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  560.277456] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  560.277486] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  560.277515] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  560.277545] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  560.277574] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  560.277603] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  560.277632] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  560.277661] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  560.277689] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  560.277717] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  560.277745] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  560.277772] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  560.277800] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  560.277829] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  560.277857] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  560.277885] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  560.277912] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  560.277940] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  560.277968] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  560.278557] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  560.278588] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  560.278618] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  560.278648] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  560.278677] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  560.278707] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  560.278735] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  560.278763] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  560.278791] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  560.278819] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  560.278847] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  560.278852] [drm] Injecting failure at checkpoint 2 [i915_driver_init_mmio:945]
>[  560.303182] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  560.309190] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  560.318609] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  560.318614] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  560.318617] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  560.318618] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  560.318620] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  560.327573] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  560.329961] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  560.338896] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input28
>[  560.340256] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input29
>[  560.414722] Setting dangerous option inject_load_failure - tainting kernel
>[  560.425373] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  560.425402] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  560.426857] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  560.426889] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  560.426920] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  560.426949] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  560.426977] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  560.427029] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  560.427056] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  560.427079] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  560.427104] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  560.427127] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  560.427151] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  560.427189] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  560.427214] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  560.427236] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  560.427261] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  560.427283] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  560.427307] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  560.427329] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  560.427353] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  560.427375] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  560.427399] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  560.427420] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  560.427444] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  560.427465] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  560.427490] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  560.427512] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  560.427536] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  560.427557] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  560.427581] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  560.427603] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  560.427627] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  560.427647] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  560.427671] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  560.427692] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  560.427716] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  560.430063] [drm] Injecting failure at checkpoint 3 [i915_driver_init_hw:1009]
>[  560.448198] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  560.451884] [IGT] drv_module_reload: exiting, ret=0
>[  560.453949] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  560.464013] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  560.464021] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  560.464024] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  560.464027] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  560.464030] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  560.475680] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  560.479633] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  560.492742] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input30
>[  560.494436] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input31
>[  560.537623] [IGT] drv_module_reload: executing
>[  560.537926] [IGT] drv_module_reload: starting subtest basic-reload-final
>[  560.633749] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  560.633779] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  560.635513] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  560.635547] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  560.635579] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  560.635608] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  560.635638] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  560.635668] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  560.635698] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  560.635726] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  560.635755] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  560.635776] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  560.635794] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  560.635813] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  560.635831] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  560.635849] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  560.635867] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  560.635885] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  560.635902] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  560.635920] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  560.635937] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  560.635955] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  560.635974] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  560.636025] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  560.636048] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  560.636071] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  560.636093] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  560.636115] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  560.636138] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  560.636160] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  560.636183] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  560.636205] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  560.636227] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  560.636249] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  560.636271] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  560.636294] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  560.636315] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  560.638096] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  560.638120] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  560.638142] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  560.638162] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  560.638182] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  560.638201] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[  560.638219] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  560.638238] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  560.638256] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  560.638275] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  560.638295] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  560.638315] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  560.638339] [drm] Memory usable by graphics device = 4096M
>[  560.638364] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  560.638388] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  560.638395] [drm] Replacing VGA console driver
>[  560.638452] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  560.638551] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ab63018
>[  560.638592] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  560.638618] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  560.644082] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  560.644111] [drm:intel_opregion_setup [i915]] ASLE supported
>[  560.644136] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  560.644161] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  560.644346] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  560.644353] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  560.644354] [drm] Driver supports precise vblank timestamp query.
>[  560.644382] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  560.644407] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[  560.644432] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  560.644455] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  560.646081] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  560.646108] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  560.646133] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  560.646161] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  560.646181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  560.646205] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  560.646228] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  560.646251] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  560.646273] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  560.646298] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  560.646320] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  560.646341] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  560.646362] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  560.646384] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 10
>[  560.646405] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  560.646425] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 10
>[  560.646666] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  560.646704] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  560.646729] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  560.646787] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  560.646819] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  560.646850] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  560.646876] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  560.646900] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  560.646935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  560.646956] [drm:intel_power_well_enable [i915]] enabling DC off
>[  560.646981] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  560.647037] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  560.647069] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  560.647098] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  560.647127] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  560.647155] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  560.647215] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[  560.648745] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[  560.649691] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  560.649730] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  560.649760] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  560.649789] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  560.649817] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  560.649844] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  560.649871] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  560.649897] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  560.649924] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  560.649962] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  560.650329] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  560.650697] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  560.650796] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  560.650923] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  560.650964] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  560.650998] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  560.651137] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  560.651217] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af05
>[  560.651302] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  560.651350] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  561.156413] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[  561.156579] [drm:wait_panel_status [i915]] Wait complete
>[  561.156761] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  561.156905] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  561.373246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.381694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.390139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.398581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.407039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.415482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.423926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.432369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.440812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.449255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.457698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.466141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.474584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.483028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.491470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.499913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.508356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.516799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.525241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.533682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.542124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.550565] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.559008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.567450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.575892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.584336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.592779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.601221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.609663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.618105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.626546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.634989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  561.635013] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  561.635016] [drm] failed to retrieve link info, disabling eDP
>[  561.635071] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  561.635130] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[  561.635197] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  561.635236] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  561.635304] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  561.635343] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  561.635374] [drm:intel_ddi_init [i915]] VBT says port C has lspcon
>[  561.635405] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  561.635441] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  561.644909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.653335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.661758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.670181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.678602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.687038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.695460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.703882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.712303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.720724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.729145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.737565] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.745985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.754419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.762840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.771260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.779680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.788102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.796522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  561.797239] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  561.798021] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  561.798680] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  561.798706] [drm:lspcon_init [i915]] LSPCON detected
>[  561.799417] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  561.860177] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  561.861031] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  561.861835] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  561.861861] [drm:lspcon_init [i915]] Success: LSPCON init
>[  561.861886] [drm:intel_ddi_init [i915]] LSPCON init success on port C
>[  561.861947] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  561.861977] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  561.862039] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  561.862074] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  561.862108] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  561.862139] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  561.862172] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  561.862203] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  561.862229] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:49:DP-MST A] hw state readout: disabled, pipe A
>[  561.862257] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DP-MST B] hw state readout: disabled, pipe B
>[  561.862282] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DP-MST C] hw state readout: disabled, pipe C
>[  561.862312] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI C] hw state readout: disabled, pipe A
>[  561.862337] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[  561.862366] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[  561.862390] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST C] hw state readout: disabled, pipe C
>[  561.862421] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:DP-1] hw state readout: disabled
>[  561.862451] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:54:HDMI-A-1] hw state readout: disabled
>[  561.862481] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-2] hw state readout: disabled
>[  561.862518] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  561.862545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  561.862573] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  561.862599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.862605] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  561.862631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.862636] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  561.862664] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  561.862689] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  561.862715] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  561.862740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.862766] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.862794] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  561.862820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.862845] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  561.862871] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  561.862895] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  561.862923] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  561.862947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  561.862974] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  561.863020] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.863026] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  561.863052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.863057] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  561.863084] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  561.863109] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  561.863135] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  561.863159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.863186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.863214] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  561.863241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.863266] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  561.863293] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  561.863318] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  561.863346] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  561.863370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  561.863396] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  561.863420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.863426] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  561.863450] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.863455] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  561.863481] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  561.863505] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  561.863531] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  561.863554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.863581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.863609] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  561.863636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.863661] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  561.863688] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  561.863712] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  561.863742] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  561.863847] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[  561.863892] [drm:skl_set_power_well [i915]] Disabling DDI D IO power well
>[  561.863922] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  561.863951] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  561.863980] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  561.864071] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  561.864101] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  561.864129] [drm:skl_set_power_well [i915]] Disabling DDI A/E IO power well
>[  561.864157] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  561.864208] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  561.864234] [drm:intel_power_well_disable [i915]] disabling DC off
>[  561.864263] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  561.864289] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  561.864710] [drm:intel_power_well_disable [i915]] disabling always-on
>[  561.864754] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/kbl_huc_ver02_00_1810.bin
>[  561.864786] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  561.865037] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/kbl_huc_ver02_00_1810.bin succeeded, fw ffff880256e3fe38
>[  561.865071] [drm:intel_uc_fw_fetch [i915]] firmware version 2.0 OK (minimum 2.0)
>[  561.865425] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff88025c4d0040
>[  561.865769] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  561.865850] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  561.865929] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  561.866914] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  561.866950] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  561.867052] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  561.867121] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  561.867178] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  561.867224] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  561.867230] [drm] GuC firmware load skipped
>[  561.867469] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  561.867496] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  561.867520] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  561.867543] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  561.868711] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  561.869733] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  561.870223] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  561.870892] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  561.881117] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  561.882227] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input32
>[  561.882915] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  561.882917] [drm] DRM_I915_DEBUG enabled
>[  561.882920] [drm] DRM_I915_DEBUG_GEM enabled
>[  561.882924] [drm:drm_setup_crtcs] 
>[  561.882931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  561.882976] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  561.883390] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.883431] [drm:intel_power_well_enable [i915]] enabling DC off
>[  561.883715] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  561.883753] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  561.883785] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  561.883869] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  561.883915] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  561.883947] [drm:intel_power_well_disable [i915]] disabling DC off
>[  561.883979] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  561.884043] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  561.884466] [drm:intel_power_well_disable [i915]] disabling always-on
>[  561.884473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to disconnected
>[  561.884487] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  561.884492] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  561.884530] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  561.884562] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.886111] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  561.886147] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  561.888131] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  561.888139] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  561.890312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  561.890340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  561.892074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  561.892081] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  561.892106] [drm:intel_power_well_disable [i915]] disabling always-on
>[  561.892111] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] status updated from unknown to disconnected
>[  561.892114] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  561.892117] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  561.892146] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  561.892170] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.892191] [drm:intel_power_well_enable [i915]] enabling DC off
>[  561.892459] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  561.892484] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  561.892505] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  561.893292] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  561.893327] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  561.894156] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  561.895039] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  561.896614] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  561.896654] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  561.896690] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  561.896724] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  561.897601] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  561.898347] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  561.900604] [drm:drm_dp_i2c_do_msg] native defer
>[  561.901664] [drm:drm_dp_i2c_do_msg] native defer
>[  561.903038] [drm:drm_dp_i2c_do_msg] native defer
>[  561.904168] [drm:drm_dp_i2c_do_msg] native defer
>[  561.905557] [drm:drm_dp_i2c_do_msg] native defer
>[  561.906603] [drm:drm_dp_i2c_do_msg] native defer
>[  561.907908] [drm:drm_dp_i2c_do_msg] native defer
>[  561.909032] [drm:drm_dp_i2c_do_msg] native defer
>[  561.910449] [drm:drm_dp_i2c_do_msg] native defer
>[  561.911490] [drm:drm_dp_i2c_do_msg] native defer
>[  561.912823] [drm:drm_dp_i2c_do_msg] native defer
>[  561.913948] [drm:drm_dp_i2c_do_msg] native defer
>[  561.915334] [drm:drm_dp_i2c_do_msg] native defer
>[  561.916481] [drm:drm_dp_i2c_do_msg] native defer
>[  561.917778] [drm:drm_dp_i2c_do_msg] native defer
>[  561.918906] [drm:drm_dp_i2c_do_msg] native defer
>[  561.921171] [drm:drm_dp_i2c_do_msg] native defer
>[  561.922291] [drm:drm_dp_i2c_do_msg] native defer
>[  561.923706] [drm:drm_dp_i2c_do_msg] native defer
>[  561.924758] [drm:drm_dp_i2c_do_msg] native defer
>[  561.926073] [drm:drm_dp_i2c_do_msg] native defer
>[  561.927202] [drm:drm_dp_i2c_do_msg] native defer
>[  561.928595] [drm:drm_dp_i2c_do_msg] native defer
>[  561.929652] [drm:drm_dp_i2c_do_msg] native defer
>[  561.930984] [drm:drm_dp_i2c_do_msg] native defer
>[  561.932112] [drm:drm_dp_i2c_do_msg] native defer
>[  561.933511] [drm:drm_dp_i2c_do_msg] native defer
>[  561.934511] [drm:drm_dp_i2c_do_msg] native defer
>[  561.935775] [drm:drm_dp_i2c_do_msg] native defer
>[  561.936907] [drm:drm_dp_i2c_do_msg] native defer
>[  561.938297] [drm:drm_dp_i2c_do_msg] native defer
>[  561.939443] [drm:drm_dp_i2c_do_msg] native defer
>[  561.940497] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  561.941218] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  561.941251] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  561.941274] [drm:intel_power_well_disable [i915]] disabling DC off
>[  561.941298] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  561.941318] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  561.941731] [drm:intel_power_well_disable [i915]] disabling always-on
>[  561.941735] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] status updated from unknown to connected
>[  561.941874] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  561.941876] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  561.941879] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  561.941882] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  561.941926] [drm:drm_mode_debug_printmodeline] Modeline 82:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  561.941928] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  561.941933] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  561.941935] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  561.941940] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  561.941942] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  561.941948] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  561.941951] [drm:drm_mode_debug_printmodeline] Modeline 62:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  561.941953] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  561.941956] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  561.941959] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  561.941961] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  561.941964] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  561.941967] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  561.941969] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  561.941994] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  561.941998] [drm:drm_mode_debug_printmodeline] Modeline 67:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  561.942002] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  561.942006] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  561.942010] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  561.942014] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  561.942018] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  561.942024] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  561.942029] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  561.942034] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  561.942039] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  561.942044] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  561.942049] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  561.942054] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  561.942060] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  561.942065] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  561.942081] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  561.942085] [drm:drm_setup_crtcs] connector 54 enabled? no
>[  561.942090] [drm:drm_setup_crtcs] connector 57 enabled? yes
>[  561.942129] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  561.942137] [drm:drm_setup_crtcs] looking for cmdline mode on connector 57
>[  561.942141] [drm:drm_setup_crtcs] looking for preferred mode on connector 57 0
>[  561.942145] [drm:drm_setup_crtcs] found mode 1600x900
>[  561.942150] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  561.942161] [drm:drm_setup_crtcs] desired mode 1600x900 set on crtc 32 (0,0)
>[  561.942205] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  561.942614] [drm:intelfb_create [i915]] allocated 1600x900 fb: 0x00040000
>[  561.943100] fbcon: inteldrmfb (fb0) is primary device
>[  561.943496] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  561.943534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  561.943571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  561.943609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  561.943642] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  561.943678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  561.943712] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  561.943746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  561.943778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  561.943810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  561.943839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.943844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  561.943874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.943878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  561.943908] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  561.943938] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  561.943967] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  561.944013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.944042] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.944077] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  561.944107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.944137] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  561.944167] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  561.944197] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  561.944230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  561.944266] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  561.944299] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  561.944331] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  561.944566] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.944601] [drm:intel_power_well_enable [i915]] enabling DC off
>[  561.944881] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  561.944910] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  561.944931] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  561.944996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  561.945041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  561.945066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  561.945091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  561.945114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  561.945137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  561.945159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  561.945181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  561.945204] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  561.945229] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  561.945253] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  561.945276] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  561.945331] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  561.945358] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  561.947522] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  561.947547] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  561.948664] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  561.950016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  561.950042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  561.950066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  561.950091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  561.955228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  561.955253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  561.960404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  561.962884] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802574cc138
>[  561.963515] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  561.963574] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  561.963599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  561.963658] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  561.963704] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  561.963732] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  561.980434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  561.980467] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  561.980516] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  561.980544] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  561.980671] Console: switching to colour frame buffer device 200x56
>[  562.010509] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  562.031676] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  562.056418] [drm] RC6 on
>[  562.080277] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  562.080316] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  562.080328] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  562.080337] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  562.080345] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  562.347893] [IGT] drv_module_reload: exiting, ret=0
>[  562.462422] Console: switching to colour dummy device 80x25
>[  562.462511] [IGT] gvt_basic: executing
>[  563.097960] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  563.097993] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  563.098008] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  563.098032] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  563.098046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  563.098060] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  563.098074] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  563.098087] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  563.107374] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input33
>[  563.108598] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input34
>[  563.109648] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input35
>[  563.110393] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input36
>[  563.111108] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input37
>[  563.111807] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input38
>[  563.170081] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  563.170137] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  563.170172] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  563.170205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  563.170233] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  563.170261] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  563.170289] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  563.170317] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  563.202185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  563.202291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  563.202348] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  563.215533] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  563.215568] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  563.215611] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  563.215725] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  563.215771] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  563.215828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  563.215854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  563.215875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  563.215896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  563.215916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  563.215937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  563.215956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  563.215975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  563.216073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  563.216107] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  563.216142] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  563.216175] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  563.216208] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  563.216496] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  563.216574] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  563.216618] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  563.216656] [drm:intel_power_well_disable [i915]] disabling DC off
>[  563.216687] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  563.216715] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  563.217170] [drm:intel_power_well_disable [i915]] disabling always-on
>[  563.230134] [drm:intel_power_well_enable [i915]] enabling always-on
>[  563.230167] [drm:intel_power_well_enable [i915]] enabling DC off
>[  563.230447] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  563.230486] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  563.230516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  563.230595] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  563.230625] [drm:skl_set_power_well [i915]] Enabling DDI A/E IO power well
>[  563.230653] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  563.230683] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  563.230711] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  563.230740] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  563.230767] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  563.230796] [drm:skl_set_power_well [i915]] Enabling DDI D IO power well
>[  563.385324] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[  563.385354] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  563.387412] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[  563.387448] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  563.387481] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  563.387511] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  563.387541] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  563.387572] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  563.387602] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  563.387632] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  563.387662] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  563.387690] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  563.387719] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  563.387748] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  563.387777] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  563.387806] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  563.387834] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  563.387863] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  563.387891] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  563.387919] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  563.387948] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  563.387977] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  563.388457] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  563.388479] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  563.388499] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  563.388519] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  563.388539] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  563.388559] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  563.388578] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  563.388597] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  563.388616] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  563.388635] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  563.388653] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  563.388671] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  563.388691] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  563.388718] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  563.388742] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  563.391088] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  563.391112] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  563.391134] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  563.391155] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  563.391175] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  563.391195] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[  563.391214] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  563.391234] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  563.391253] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  563.391272] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  563.391293] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  563.391313] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  563.391339] [drm] Memory usable by graphics device = 4096M
>[  563.391365] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  563.391389] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  563.391397] [drm] Replacing VGA console driver
>[  563.391456] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  563.391553] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ab63018
>[  563.391595] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  563.391622] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  563.397303] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  563.397333] [drm:intel_opregion_setup [i915]] ASLE supported
>[  563.397360] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  563.397386] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  563.397573] [drm:intel_gvt_init [i915]] Unsupported device. GVT-g is disabled
>[  563.397579] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  563.397581] [drm] Driver supports precise vblank timestamp query.
>[  563.397610] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  563.397637] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[  563.397663] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  563.397687] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  563.401115] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  563.401146] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  563.401174] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  563.401206] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  563.401210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  563.401235] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  563.401260] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  563.401283] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  563.401307] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  563.401334] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  563.401357] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  563.401379] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  563.401402] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  563.401423] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 10
>[  563.401445] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  563.401467] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 10
>[  563.401713] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  563.401753] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  563.401779] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  563.401842] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  563.401875] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  563.401906] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  563.401934] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  563.401959] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  563.402019] [drm:intel_power_well_enable [i915]] enabling always-on
>[  563.402046] [drm:intel_power_well_enable [i915]] enabling DC off
>[  563.402073] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  563.402105] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  563.402132] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  563.402158] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  563.402184] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  563.402209] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[  563.402256] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[  563.403704] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  563.403733] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  563.403755] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  563.403775] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  563.403794] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  563.403813] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  563.403831] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  563.403850] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  563.403868] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  563.403896] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  563.404166] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  563.404537] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  563.404641] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  563.404776] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  563.404820] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  563.404855] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  563.404890] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  563.404969] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af05
>[  563.405091] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  563.405143] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  563.406475] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[  563.908467] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>[  563.908631] [drm:wait_panel_status [i915]] Wait complete
>[  563.908814] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  563.908957] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  564.125252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.133709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.142155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.150598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.159043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.167487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.175930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.184373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.192817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.201261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.209717] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.218159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.226603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.235046] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.243488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.251931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.260375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.268818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.277260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.285714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.294158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.302600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.311042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.319484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.327927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.336370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.344812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.353253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.361694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.370137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.378578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.387020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  564.387030] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  564.387034] [drm] failed to retrieve link info, disabling eDP
>[  564.387089] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  564.387148] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[  564.387216] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  564.387254] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  564.387323] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  564.387361] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  564.387393] [drm:intel_ddi_init [i915]] VBT says port C has lspcon
>[  564.387423] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  564.387459] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  564.396928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.405367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.413790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.422212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.430632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.439052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.447473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.455894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.464315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.472735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.481156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.489575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.498011] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.506431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.514852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.523272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.531691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.540111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.548531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  564.549247] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  564.550038] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  564.550702] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  564.550727] [drm:lspcon_init [i915]] LSPCON detected
>[  564.551435] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  564.612252] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  564.613079] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  564.613878] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  564.613904] [drm:lspcon_init [i915]] Success: LSPCON init
>[  564.613929] [drm:intel_ddi_init [i915]] LSPCON init success on port C
>[  564.613982] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  564.614046] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  564.614085] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  564.614119] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  564.614151] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  564.614182] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  564.614212] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  564.614243] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  564.614268] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:49:DP-MST A] hw state readout: disabled, pipe A
>[  564.614295] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DP-MST B] hw state readout: disabled, pipe B
>[  564.614320] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DP-MST C] hw state readout: disabled, pipe C
>[  564.614348] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI C] hw state readout: disabled, pipe A
>[  564.614373] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[  564.614399] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[  564.614423] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST C] hw state readout: disabled, pipe C
>[  564.614453] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:DP-1] hw state readout: disabled
>[  564.614484] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:54:HDMI-A-1] hw state readout: disabled
>[  564.614514] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-2] hw state readout: disabled
>[  564.614550] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  564.614577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  564.614606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  564.614632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  564.614637] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  564.614664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  564.614669] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  564.614697] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  564.614721] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  564.614749] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  564.614773] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  564.614799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  564.614828] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  564.614855] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  564.614879] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  564.614906] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  564.614930] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  564.614958] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  564.614983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  564.615028] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  564.615053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  564.615059] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  564.615084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  564.615089] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  564.615117] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  564.615141] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  564.615168] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  564.615192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  564.615218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  564.615246] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  564.615273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  564.615298] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[  564.615325] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[  564.615349] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[  564.615378] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  564.615402] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  564.615428] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  564.615451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  564.615457] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  564.615482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  564.615487] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  564.615513] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  564.615537] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  564.615563] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  564.615587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  564.615613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  564.615641] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  564.615669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  564.615694] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[  564.615722] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[  564.615747] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[  564.615776] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  564.615881] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[  564.615925] [drm:skl_set_power_well [i915]] Disabling DDI D IO power well
>[  564.615956] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  564.615986] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  564.616035] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  564.616064] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  564.616092] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  564.616120] [drm:skl_set_power_well [i915]] Disabling DDI A/E IO power well
>[  564.616147] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  564.616198] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  564.616225] [drm:intel_power_well_disable [i915]] disabling DC off
>[  564.616254] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  564.616280] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  564.616699] [drm:intel_power_well_disable [i915]] disabling always-on
>[  564.616743] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/kbl_huc_ver02_00_1810.bin
>[  564.616774] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  564.616997] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/kbl_huc_ver02_00_1810.bin succeeded, fw ffff880258f7acf8
>[  564.617054] [drm:intel_uc_fw_fetch [i915]] firmware version 2.0 OK (minimum 2.0)
>[  564.617420] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880230ca0040
>[  564.617763] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  564.617843] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  564.617924] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  564.618921] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  564.618957] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 17
>[  564.619067] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  564.619145] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  564.619203] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  564.619250] [drm:intel_guc_setup [i915]] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[  564.619256] [drm] GuC firmware load skipped
>[  564.619492] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  564.619519] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  564.619543] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  564.619567] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  564.620868] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  564.622229] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  564.622839] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  564.623767] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  564.634050] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  564.634741] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input39
>[  564.635415] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  564.635418] [drm] DRM_I915_DEBUG enabled
>[  564.635421] [drm] DRM_I915_DEBUG_GEM enabled
>[  564.635425] [drm:drm_setup_crtcs] 
>[  564.635432] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[  564.635479] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[  564.635533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  564.635573] [drm:intel_power_well_enable [i915]] enabling DC off
>[  564.635855] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  564.635894] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  564.635924] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  564.636046] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  564.636093] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  564.636125] [drm:intel_power_well_disable [i915]] disabling DC off
>[  564.636157] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  564.636186] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  564.636608] [drm:intel_power_well_disable [i915]] disabling always-on
>[  564.636614] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to disconnected
>[  564.636628] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] disconnected
>[  564.636633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[  564.636671] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[  564.636701] [drm:intel_power_well_enable [i915]] enabling always-on
>[  564.638097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  564.638132] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  564.640169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  564.640176] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  564.642338] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  564.642376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  564.644519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  564.644528] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  564.644563] [drm:intel_power_well_disable [i915]] disabling always-on
>[  564.644570] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] status updated from unknown to disconnected
>[  564.644574] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[  564.644579] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2]
>[  564.644608] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-2]
>[  564.644632] [drm:intel_power_well_enable [i915]] enabling always-on
>[  564.644653] [drm:intel_power_well_enable [i915]] enabling DC off
>[  564.644922] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  564.644948] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  564.644969] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  564.645786] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  564.645820] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  564.646553] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  564.647403] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  564.648957] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  564.648991] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  564.649074] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  564.649108] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  564.649914] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  564.650633] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  564.652869] [drm:drm_dp_i2c_do_msg] native defer
>[  564.654003] [drm:drm_dp_i2c_do_msg] native defer
>[  564.655394] [drm:drm_dp_i2c_do_msg] native defer
>[  564.657117] [drm:drm_dp_i2c_do_msg] native defer
>[  564.658248] [drm:drm_dp_i2c_do_msg] native defer
>[  564.659643] [drm:drm_dp_i2c_do_msg] native defer
>[  564.660695] [drm:drm_dp_i2c_do_msg] native defer
>[  564.662010] [drm:drm_dp_i2c_do_msg] native defer
>[  564.663135] [drm:drm_dp_i2c_do_msg] native defer
>[  564.664527] [drm:drm_dp_i2c_do_msg] native defer
>[  564.665511] [drm:drm_dp_i2c_do_msg] native defer
>[  564.666772] [drm:drm_dp_i2c_do_msg] native defer
>[  564.667895] [drm:drm_dp_i2c_do_msg] native defer
>[  564.669291] [drm:drm_dp_i2c_do_msg] native defer
>[  564.670436] [drm:drm_dp_i2c_do_msg] native defer
>[  564.672658] [drm:drm_dp_i2c_do_msg] native defer
>[  564.673710] [drm:drm_dp_i2c_do_msg] native defer
>[  564.675025] [drm:drm_dp_i2c_do_msg] native defer
>[  564.676150] [drm:drm_dp_i2c_do_msg] native defer
>[  564.677541] [drm:drm_dp_i2c_do_msg] native defer
>[  564.678606] [drm:drm_dp_i2c_do_msg] native defer
>[  564.679925] [drm:drm_dp_i2c_do_msg] native defer
>[  564.681043] [drm:drm_dp_i2c_do_msg] native defer
>[  564.682491] [drm:drm_dp_i2c_do_msg] native defer
>[  564.683505] [drm:drm_dp_i2c_do_msg] native defer
>[  564.684815] [drm:drm_dp_i2c_do_msg] native defer
>[  564.685945] [drm:drm_dp_i2c_do_msg] native defer
>[  564.687339] [drm:drm_dp_i2c_do_msg] native defer
>[  564.689066] [drm:drm_dp_i2c_do_msg] native defer
>[  564.690195] [drm:drm_dp_i2c_do_msg] native defer
>[  564.691306] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  564.692029] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  564.692061] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  564.692084] [drm:intel_power_well_disable [i915]] disabling DC off
>[  564.692108] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  564.692129] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  564.692618] [drm:intel_power_well_disable [i915]] disabling always-on
>[  564.692623] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] status updated from unknown to connected
>[  564.692764] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  564.692767] [drm:drm_edid_to_eld] ELD monitor DELL E2014T
>[  564.692770] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  564.692772] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  564.692817] [drm:drm_mode_debug_printmodeline] Modeline 82:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  564.692820] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  564.692824] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  564.692826] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  564.692831] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  564.692833] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  564.692839] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-2] probed modes :
>[  564.692842] [drm:drm_mode_debug_printmodeline] Modeline 62:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  564.692845] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  564.692848] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  564.692850] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  564.692853] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  564.692856] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  564.692858] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  564.692861] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  564.692863] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  564.692866] [drm:drm_mode_debug_printmodeline] Modeline 67:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  564.692869] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  564.692871] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  564.692874] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  564.692876] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  564.692879] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  564.692882] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  564.692884] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  564.692887] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  564.692889] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  564.692892] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  564.692895] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  564.692897] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  564.692900] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  564.692902] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  564.692912] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  564.692914] [drm:drm_setup_crtcs] connector 54 enabled? no
>[  564.692917] [drm:drm_setup_crtcs] connector 57 enabled? yes
>[  564.692947] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  564.692952] [drm:drm_setup_crtcs] looking for cmdline mode on connector 57
>[  564.692954] [drm:drm_setup_crtcs] looking for preferred mode on connector 57 0
>[  564.692957] [drm:drm_setup_crtcs] found mode 1600x900
>[  564.692959] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  564.692966] [drm:drm_setup_crtcs] desired mode 1600x900 set on crtc 32 (0,0)
>[  564.693034] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  564.693694] [drm:intelfb_create [i915]] allocated 1600x900 fb: 0x00040000
>[  564.694096] fbcon: inteldrmfb (fb0) is primary device
>[  564.694487] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-2] checking for sink bpp constrains
>[  564.694524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  564.694562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 97750KHz
>[  564.694600] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  564.694633] [drm:intel_dp_compute_config [i915]] DP link bw required 293250 available 324000
>[  564.694668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  564.694703] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  564.694736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  564.694769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3796233, gmch_n: 4194304, link_m: 158176, link_n: 262144, tu: 64
>[  564.694801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  564.694832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  564.694837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  564.694867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  564.694872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 97750 1600 1648 1680 1760 900 903 908 926 0x48 0x5
>[  564.694902] [drm:intel_dump_pipe_config [i915]] crtc timings: 97750 1600 1648 1680 1760 900 903 908 926, type: 0x48 flags: 0x5
>[  564.694932] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x900, pixel rate 97750
>[  564.694962] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  564.694991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  564.695041] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  564.695075] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  564.695106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  564.695136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  564.695166] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  564.695195] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  564.695229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  564.695265] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  564.695297] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  564.695330] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  564.695563] [drm:intel_power_well_enable [i915]] enabling always-on
>[  564.695599] [drm:intel_power_well_enable [i915]] enabling DC off
>[  564.695881] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  564.695926] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  564.695957] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  564.696043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  564.696075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  564.696100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  564.696124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  564.696147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  564.696170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  564.696192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  564.696214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST C]
>[  564.696237] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 0
>[  564.696262] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  564.696285] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 2
>[  564.696309] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 3
>[  564.696364] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  564.696391] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  564.698555] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  564.698580] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  564.699717] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  564.701068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  564.701094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  564.701117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  564.701142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  564.706297] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  564.706322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  564.711478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  564.713958] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8802574cc138
>[  564.714582] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  564.714647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:57:DP-2], [ENCODER:56:DDI C]
>[  564.714672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  564.714733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  564.714787] [drm:intel_fbc_enable [i915]] reserved 11520000 bytes of contiguous stolen space for FBC, threshold: 1
>[  564.714816] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  564.731525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:DP-2]
>[  564.731562] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  564.731618] [drm:verify_single_dpll_state.isra.69 [i915]] DPLL 1
>[  564.731649] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  564.731790] Console: switching to colour frame buffer device 200x56
>[  564.751490] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  564.762071] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  564.764873] [IGT] gvt_basic: exiting, ret=77
>[  564.786052] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC255: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  564.786070] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  564.786075] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  564.786079] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  564.786082] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  564.804381] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  564.804431] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  564.804464] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  564.804521] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  564.804550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  564.804580] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  564.804608] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  564.804636] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  564.823828] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input40
>[  564.825846] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input41
>[  564.827020] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input42
>[  564.828245] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input43
>[  564.829390] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input44
>[  564.830531] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input45
>[  565.735447] [drm] RC6 on

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